1--------------------------------------------------------------------------------
2--
3-- FIFO Generator Core Demo Testbench
4--
5--------------------------------------------------------------------------------
6--
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52--------------------------------------------------------------------------------
53--
54-- Filename: fifo_4k_2clk_dgen.vhd
55--
56-- Description:
57--   Used for write interface stimulus generation
58--
59--------------------------------------------------------------------------------
60-- Library Declarations
61--------------------------------------------------------------------------------
62LIBRARY ieee;
63USE ieee.std_logic_1164.ALL;
64USE ieee.std_logic_unsigned.all;
65USE IEEE.std_logic_arith.all;
66USE IEEE.std_logic_misc.all;
67
68LIBRARY work;
69USE work.fifo_4k_2clk_pkg.ALL;
70
71ENTITY fifo_4k_2clk_dgen IS
72  GENERIC (
73	    C_DIN_WIDTH   : INTEGER := 32;
74	    C_DOUT_WIDTH  : INTEGER := 32;
75	    C_CH_TYPE     : INTEGER := 0;
76	    TB_SEED       : INTEGER := 2
77	 );
78  PORT (
79        RESET     : IN STD_LOGIC;
80        WR_CLK    : IN STD_LOGIC;
81        PRC_WR_EN : IN STD_LOGIC;
82        FULL      : IN STD_LOGIC;
83        WR_EN     : OUT STD_LOGIC;
84        WR_DATA   : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
85       );
86END ENTITY;
87
88
89ARCHITECTURE fg_dg_arch OF fifo_4k_2clk_dgen IS
90
91  CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
92  CONSTANT LOOP_COUNT   : INTEGER := divroundup(C_DATA_WIDTH,8);
93
94  SIGNAL pr_w_en        : STD_LOGIC := '0';
95  SIGNAL rand_num       : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
96  SIGNAL wr_data_i      : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
97 BEGIN
98
99   WR_EN   <= PRC_WR_EN ;
100   WR_DATA <= wr_data_i AFTER 100 ns;
101
102  ----------------------------------------------
103  -- Generation of DATA
104  ----------------------------------------------
105  gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
106    rd_gen_inst1:fifo_4k_2clk_rng
107    GENERIC MAP(
108    	       WIDTH => 8,
109               SEED  => TB_SEED+N
110               )
111    PORT MAP(
112              CLK        => WR_CLK,
113	      RESET      => RESET,
114              RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
115              ENABLE     => pr_w_en
116            );
117  END GENERATE;
118
119     pr_w_en <= PRC_WR_EN AND NOT FULL;
120     wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
121
122
123END ARCHITECTURE;
124