1-------------------------------------------------------------------------------- 2-- 3-- FIFO Generator Core Demo Testbench 4-- 5-------------------------------------------------------------------------------- 6-- 7-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. 8-- 9-- This file contains confidential and proprietary information 10-- of Xilinx, Inc. and is protected under U.S. and 11-- international copyright and other intellectual property 12-- laws. 13-- 14-- DISCLAIMER 15-- This disclaimer is not a license and does not grant any 16-- rights to the materials distributed herewith. Except as 17-- otherwise provided in a valid license issued to you by 18-- Xilinx, and to the maximum extent permitted by applicable 19-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 20-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 21-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 22-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 23-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 24-- (2) Xilinx shall not be liable (whether in contract or tort, 25-- including negligence, or under any other theory of 26-- liability) for any loss or damage of any kind or nature 27-- related to, arising under or in connection with these 28-- materials, including for any direct, or any indirect, 29-- special, incidental, or consequential loss or damage 30-- (including loss of data, profits, goodwill, or any type of 31-- loss or damage suffered as a result of any action brought 32-- by a third party) even if such damage or loss was 33-- reasonably foreseeable or Xilinx had been advised of the 34-- possibility of the same. 35-- 36-- CRITICAL APPLICATIONS 37-- Xilinx products are not designed or intended to be fail- 38-- safe, or for use in any application requiring fail-safe 39-- performance, such as life-support or safety devices or 40-- systems, Class III medical devices, nuclear facilities, 41-- applications related to the deployment of airbags, or any 42-- other applications that could lead to death, personal 43-- injury, or severe property or environmental damage 44-- (individually and collectively, "Critical 45-- Applications"). Customer assumes the sole risk and 46-- liability of any use of Xilinx products in Critical 47-- Applications, subject only to applicable laws and 48-- regulations governing limitations on product liability. 49-- 50-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 51-- PART OF THIS FILE AT ALL TIMES. 52-------------------------------------------------------------------------------- 53-- 54-- Filename: fifo_short_2clk_dgen.vhd 55-- 56-- Description: 57-- Used for write interface stimulus generation 58-- 59-------------------------------------------------------------------------------- 60-- Library Declarations 61-------------------------------------------------------------------------------- 62LIBRARY ieee; 63USE ieee.std_logic_1164.ALL; 64USE ieee.std_logic_unsigned.all; 65USE IEEE.std_logic_arith.all; 66USE IEEE.std_logic_misc.all; 67 68LIBRARY work; 69USE work.fifo_short_2clk_pkg.ALL; 70 71ENTITY fifo_short_2clk_dgen IS 72 GENERIC ( 73 C_DIN_WIDTH : INTEGER := 32; 74 C_DOUT_WIDTH : INTEGER := 32; 75 C_CH_TYPE : INTEGER := 0; 76 TB_SEED : INTEGER := 2 77 ); 78 PORT ( 79 RESET : IN STD_LOGIC; 80 WR_CLK : IN STD_LOGIC; 81 PRC_WR_EN : IN STD_LOGIC; 82 FULL : IN STD_LOGIC; 83 WR_EN : OUT STD_LOGIC; 84 WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) 85 ); 86END ENTITY; 87 88 89ARCHITECTURE fg_dg_arch OF fifo_short_2clk_dgen IS 90 91 CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); 92 CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); 93 94 SIGNAL pr_w_en : STD_LOGIC := '0'; 95 SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); 96 SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); 97 BEGIN 98 99 WR_EN <= PRC_WR_EN ; 100 WR_DATA <= wr_data_i AFTER 100 ns; 101 102 ---------------------------------------------- 103 -- Generation of DATA 104 ---------------------------------------------- 105 gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE 106 rd_gen_inst1:fifo_short_2clk_rng 107 GENERIC MAP( 108 WIDTH => 8, 109 SEED => TB_SEED+N 110 ) 111 PORT MAP( 112 CLK => WR_CLK, 113 RESET => RESET, 114 RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), 115 ENABLE => pr_w_en 116 ); 117 END GENERATE; 118 119 pr_w_en <= PRC_WR_EN AND NOT FULL; 120 wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); 121 122 123END ARCHITECTURE; 124