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48
49//  Generated from component ID: xilinx.com:ip:fir_compiler:5.0
50
51
52// The following must be inserted into your Verilog file for this
53// core to be instantiated. Change the instance name and port connections
54// (in parentheses) to your own signal names.
55
56//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
57hbdec1 YourInstanceName (
58	.sclr(sclr), // input sclr
59	.clk(clk), // input clk
60	.ce(ce), // input ce
61	.nd(nd), // input nd
62	.coef_ld(coef_ld), // input coef_ld
63	.coef_we(coef_we), // input coef_we
64	.coef_din(coef_din), // input [17 : 0] coef_din
65	.rfd(rfd), // output rfd
66	.rdy(rdy), // output rdy
67	.data_valid(data_valid), // output data_valid
68	.din_1(din_1), // input [23 : 0] din_1
69	.din_2(din_2), // input [23 : 0] din_2
70	.dout_1(dout_1), // output [46 : 0] dout_1
71	.dout_2(dout_2)); // output [46 : 0] dout_2
72
73// INST_TAG_END ------ End INSTANTIATION Template ---------
74
75// You must compile the wrapper file hbdec1.v when simulating
76// the core, hbdec1. When compiling the wrapper file, be sure to
77// reference the XilinxCoreLib Verilog simulation library. For detailed
78// instructions, please refer to the "CORE Generator Help".
79
80