1/******************************************************************************* 2* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * 3* * 4* This file contains confidential and proprietary information * 5* of Xilinx, Inc. and is protected under U.S. and * 6* international copyright and other intellectual property * 7* laws. * 8* * 9* DISCLAIMER * 10* This disclaimer is not a license and does not grant any * 11* rights to the materials distributed herewith. Except as * 12* otherwise provided in a valid license issued to you by * 13* Xilinx, and to the maximum extent permitted by applicable * 14* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * 15* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * 16* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * 17* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * 18* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * 19* (2) Xilinx shall not be liable (whether in contract or tort, * 20* including negligence, or under any other theory of * 21* liability) for any loss or damage of any kind or nature * 22* related to, arising under or in connection with these * 23* materials, including for any direct, or any indirect, * 24* special, incidental, or consequential loss or damage * 25* (including loss of data, profits, goodwill, or any type of * 26* loss or damage suffered as a result of any action brought * 27* by a third party) even if such damage or loss was * 28* reasonably foreseeable or Xilinx had been advised of the * 29* possibility of the same. * 30* * 31* CRITICAL APPLICATIONS * 32* Xilinx products are not designed or intended to be fail- * 33* safe, or for use in any application requiring fail-safe * 34* performance, such as life-support or safety devices or * 35* systems, Class III medical devices, nuclear facilities, * 36* applications related to the deployment of airbags, or any * 37* other applications that could lead to death, personal * 38* injury, or severe property or environmental damage * 39* (individually and collectively, "Critical * 40* Applications"). Customer assumes the sole risk and * 41* liability of any use of Xilinx products in Critical * 42* Applications, subject only to applicable laws and * 43* regulations governing limitations on product liability. * 44* * 45* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * 46* PART OF THIS FILE AT ALL TIMES. * 47*******************************************************************************/ 48 49// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 50 51 52// The following must be inserted into your Verilog file for this 53// core to be instantiated. Change the instance name and port connections 54// (in parentheses) to your own signal names. 55 56//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57hbdec1 YourInstanceName ( 58 .sclr(sclr), // input sclr 59 .clk(clk), // input clk 60 .ce(ce), // input ce 61 .nd(nd), // input nd 62 .coef_ld(coef_ld), // input coef_ld 63 .coef_we(coef_we), // input coef_we 64 .coef_din(coef_din), // input [17 : 0] coef_din 65 .rfd(rfd), // output rfd 66 .rdy(rdy), // output rdy 67 .data_valid(data_valid), // output data_valid 68 .din_1(din_1), // input [23 : 0] din_1 69 .din_2(din_2), // input [23 : 0] din_2 70 .dout_1(dout_1), // output [46 : 0] dout_1 71 .dout_2(dout_2)); // output [46 : 0] dout_2 72 73// INST_TAG_END ------ End INSTANTIATION Template --------- 74 75// You must compile the wrapper file hbdec1.v when simulating 76// the core, hbdec1. When compiling the wrapper file, be sure to 77// reference the XilinxCoreLib Verilog simulation library. For detailed 78// instructions, please refer to the "CORE Generator Help". 79 80