1## (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. 2## 3## This file contains confidential and proprietary information 4## of Xilinx, Inc. and is protected under U.S. and 5## international copyright and other intellectual property 6## laws. 7## 8## DISCLAIMER 9## This disclaimer is not a license and does not grant any 10## rights to the materials distributed herewith. Except as 11## otherwise provided in a valid license issued to you by 12## Xilinx, and to the maximum extent permitted by applicable 13## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18## (2) Xilinx shall not be liable (whether in contract or tort, 19## including negligence, or under any other theory of 20## liability) for any loss or damage of any kind or nature 21## related to, arising under or in connection with these 22## materials, including for any direct, or any indirect, 23## special, incidental, or consequential loss or damage 24## (including loss of data, profits, goodwill, or any type of 25## loss or damage suffered as a result of any action brought 26## by a third party) even if such damage or loss was 27## reasonably foreseeable or Xilinx had been advised of the 28## possibility of the same. 29## 30## CRITICAL APPLICATIONS 31## Xilinx products are not designed or intended to be fail- 32## safe, or for use in any application requiring fail-safe 33## performance, such as life-support or safety devices or 34## systems, Class III medical devices, nuclear facilities, 35## applications related to the deployment of airbags, or any 36## other applications that could lead to death, personal 37## injury, or severe property or environmental damage 38## (individually and collectively, "Critical 39## Applications"). Customer assumes the sole risk and 40## liability of any use of Xilinx products in Critical 41## Applications, subject only to applicable laws and 42## regulations governing limitations on product liability. 43## 44## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45## PART OF THIS FILE AT ALL TIMES. 46 47create_clock -period 6.400 [get_ports {dclk}] 48 49create_clock -period 6.400 [get_ports refclk_p] 50 51create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_ports xgmii_rx_clk] 52set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] 53set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] 54set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] 55set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] 56 57# False paths for async reset removal synchronizers 58set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *PRE}] 59set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *CLR}] 60 61 62## Sample constraint for GT location 63#set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/*/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i] 64#set_property LOC GTXE2_COMMON_X0Y4 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i] 65 66set_property IOSTANDARD HSTL_I [get_ports {xgmii_txc[*]}] 67set_property IOSTANDARD HSTL_I [get_ports {xgmii_txd[*]}] 68 69set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxc[*]}] 70set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxd[*]}] 71 72set_property IOB TRUE [get_cells {xgmii_rxc_reg[*]}] 73set_property IOB TRUE [get_cells {xgmii_rxd_reg[*]}] 74 75set_property IOSTANDARD HSTL_I [get_ports xgmii_rx_clk] 76 77 78################################################################## 79# MDIO-related constraints # 80################################################################## 81set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_out*reg*}] 82set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_tri*reg*}] 83################################################################### 84 85################################################################## 86# MDIO-related constraints # 87################################################################## 88set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdc_reg_reg}] 89set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdio_in_reg_reg}] 90################################################################### 91 92