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46
47create_clock -period 6.400 [get_ports {dclk}]
48
49create_clock -period 6.400 [get_ports refclk_p]
50
51create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_ports xgmii_rx_clk]
52set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}]
53set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}]
54set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}]
55set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}]
56
57# False paths for async reset removal synchronizers
58set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *PRE}]
59set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *CLR}]
60
61
62## Sample constraint for GT location
63#set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/*/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i]
64#set_property LOC GTXE2_COMMON_X0Y4 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i]
65
66set_property IOSTANDARD HSTL_I [get_ports {xgmii_txc[*]}]
67set_property IOSTANDARD HSTL_I [get_ports {xgmii_txd[*]}]
68
69set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxc[*]}]
70set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxd[*]}]
71
72set_property IOB TRUE [get_cells {xgmii_rxc_reg[*]}]
73set_property IOB TRUE [get_cells {xgmii_rxd_reg[*]}]
74
75set_property IOSTANDARD HSTL_I [get_ports xgmii_rx_clk]
76
77
78##################################################################
79# MDIO-related constraints                                       #
80##################################################################
81set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_out*reg*}]
82set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_tri*reg*}]
83###################################################################
84
85##################################################################
86# MDIO-related constraints                                       #
87##################################################################
88set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdc_reg_reg}]
89set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdio_in_reg_reg}]
90###################################################################
91
92