1// 2// Copyright 2017 Ettus Research, a National Instruments Company 3// 4// SPDX-License-Identifier: LGPL-3.0-or-later 5// 6 7module n3xx_db_fe_core #( 8 // Drive SPI core with input spi_clk instead of ce_clk. This is useful if ce_clk is very slow which 9 // would cause spi transactions to take a long time. WARNING: This adds a clock crossing FIFO! 10 parameter USE_SPI_CLK = 0, 11 parameter [7:0] SR_DB_FE_BASE = 160, 12 parameter [7:0] RB_DB_FE_BASE = 16, 13 parameter WIDTH = 32, 14 parameter NUM_SPI_SEN = 8, 15 parameter USE_CORRECTION = 0 16)( 17 input clk, input reset, 18 // Commands from Radio Core 19 input set_stb, input [7:0] set_addr, input [31:0] set_data, 20 output rb_stb, input [7:0] rb_addr, output [63:0] rb_data, 21 // Radio datapath 22 input tx_stb, input [WIDTH-1:0] tx_data_in, output [WIDTH-1:0] tx_data_out, input tx_running, 23 input rx_stb, input [WIDTH-1:0] rx_data_in, output [WIDTH-1:0] rx_data_out, input rx_running, 24 // Frontend / Daughterboard I/O 25 input [31:0] misc_ins, output [31:0] misc_outs, 26 input [31:0] fp_gpio_in, output [31:0] fp_gpio_out, output [31:0] fp_gpio_ddr, input [31:0] fp_gpio_fab, 27 input [31:0] db_gpio_in, output [31:0] db_gpio_out, output [31:0] db_gpio_ddr, input [31:0] db_gpio_fab, 28 output [31:0] leds, 29 input spi_clk, input spi_rst, output [NUM_SPI_SEN-1:0] sen, output sclk, output mosi, input miso 30); 31 32 localparam [7:0] SR_TX_FE_BASE = SR_DB_FE_BASE + 8'd48; 33 localparam [7:0] SR_RX_FE_BASE = SR_DB_FE_BASE + 8'd64; 34 35 db_control #( 36 .USE_SPI_CLK(USE_SPI_CLK), .SR_BASE(SR_DB_FE_BASE), .RB_BASE(RB_DB_FE_BASE), 37 .NUM_SPI_SEN(NUM_SPI_SEN) 38 ) db_control_i ( 39 .clk(clk), .reset(reset), 40 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 41 .rb_stb(rb_stb), .rb_addr(rb_addr), .rb_data(rb_data), 42 .run_rx(rx_running), .run_tx(tx_running), 43 .misc_ins(misc_ins), .misc_outs(misc_outs), 44 .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), .fp_gpio_fab(fp_gpio_fab), 45 .db_gpio_in(db_gpio_in), .db_gpio_out(db_gpio_out), .db_gpio_ddr(db_gpio_ddr), .db_gpio_fab(db_gpio_fab), 46 .leds(leds), 47 .spi_clk(spi_clk), .spi_rst(spi_rst), .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso) 48 ); 49 50 generate 51 if (USE_CORRECTION == 1) begin 52 tx_frontend_gen3 #( 53 .SR_OFFSET_I(SR_TX_FE_BASE + 0), .SR_OFFSET_Q(SR_TX_FE_BASE + 1),.SR_MAG_CORRECTION(SR_TX_FE_BASE + 2), 54 .SR_PHASE_CORRECTION(SR_TX_FE_BASE + 3), .SR_MUX(SR_TX_FE_BASE + 4), 55 .BYPASS_DC_OFFSET_CORR(0), .BYPASS_IQ_COMP(0), 56 .DEVICE("7SERIES") 57 ) tx_fe_corr_i ( 58 .clk(clk), .reset(reset), 59 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 60 .tx_stb(tx_stb), .tx_i(tx_data_in[31:16]), .tx_q(tx_data_in[15:0]), 61 .dac_stb(), .dac_i(tx_data_out[31:16]), .dac_q(tx_data_out[15:0]) 62 ); 63 64 rx_frontend_gen3 #( 65 .SR_MAG_CORRECTION(SR_RX_FE_BASE + 0), .SR_PHASE_CORRECTION(SR_RX_FE_BASE + 1), .SR_OFFSET_I(SR_RX_FE_BASE + 2), 66 .SR_OFFSET_Q(SR_RX_FE_BASE + 3), .SR_IQ_MAPPING(SR_RX_FE_BASE + 4), .SR_HET_PHASE_INCR(SR_RX_FE_BASE + 5), 67 .BYPASS_DC_OFFSET_CORR(0), .BYPASS_IQ_COMP(0), .BYPASS_REALMODE_DSP(1), 68 .DEVICE("7SERIES") 69 ) rx_fe_corr_i ( 70 .clk(clk), .reset(reset), .sync_in(), 71 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 72 .adc_stb(rx_stb), .adc_i(rx_data_in[31:16]), .adc_q(rx_data_in[15:0]), 73 .rx_stb(), .rx_i(rx_data_out[31:16]), .rx_q(rx_data_out[15:0]) 74 ); 75 end else begin 76 //TODO: Flesh out this module 77 assign tx_data_out = tx_data_in; 78 assign rx_data_out = rx_data_in; 79 end 80 endgenerate 81 82endmodule 83