1/*! \page page_usrp_x3x0 USRP X3x0 Series 2 3\tableofcontents 4 5More information: 6\li \subpage page_gpsdo_x3x0 7\li \subpage page_gpio_api 8\li \subpage page_usrp_x3x0_config 9\li \subpage page_ni_rio_kernel 10 11\section x3x0_feature_list Comparative features list 12 13- Hardware Capabilities: 14 - 2 transceiver card slots (can do 2x2 MIMO out of the box) 15 - Dual SFP+ Transceivers (can be used with 1 GigE, 10 GigE) 16 - PCI Express over cable (MXI) gen1 x4 17 - External PPS input & output 18 - External reference (10 MHz, 11.52 MHz, 23.04 MHz, or 30.72 MHz) input & output 19 - Expandable via 2nd SFP+ interface 20 - Supported master clock rates: 200 MHz and 184.32 MHz 21 - Variable daughterboard clock rates 22 - External GPIO Connector with UHD API control 23 - External USB Connection for built-in JTAG debugger 24 - Internal GPSDO option 25 - Kintex-7 FPGA (X310: XC7K410T, X300: XC7K325T) 26- FPGA Capabilities: 27 - 2 RX DDC chains in FPGA 28 - 2 TX DUC chain in FPGA 29 - Timed commands in FPGA 30 - Timed sampling in FPGA 31 - Up to 120 MHz of RF bandwidth with 16-bit samples 32 33\section x3x0_getting_started Getting started 34 35This will run you through the first steps relevant to get your USRP X300/X310 36up and running. Here, we assume you will connect your USRP using Gigabit Ethernet (1GigE), 37as this interface is readily available in most computers. For 10 Gigabit Ethernet (10GigE) or 38PCI Express (PCIe), see the corresponding sections in this manual page. 39 40\subsection x3x0_getting_started_assembling Assembling the X300/X310 kit 41 42Before you can start using your USRP, you might have to assemble the hardware, 43if this has not yet happened. Make sure you are grounded (e.g. by touching a radiator) 44in order not to damage sensitive electronics through static discharge! 45 461. Unscrew the top of your X300/X310 (there are 2 screws which can be easily loosened 47 using a small Phillips screwdriver). 482. Insert the daughterboards by inserting them into the slots and optionally screwing 49 them onto the motherboard. 503. Connect the RF connectors on the daughterboards to the front panel. In order to avoid 51 confusion, make sure the internal connections match the labels on the front panel (i.e. 52 TX/RX is connected to TX/RX). 534. If you have purchased an internal GPSDO, follow the instructions on 54 \ref page_gpsdo_x3x0 to insert the GPSDO. Note that you 55 will need an external GPS antenna connected to the rear GPS ANT connector in order to 56 make use of GPS, although your USRP will still be usable without. 575. Connect the 1 GigE SFP+ transceiver into the Ethernet port 0 and connect the X300/X310 with 58 your computer. 596. Connect the power supply and switch on the USRP. 60 61\subsection x3x0_getting_started_connectivity Network Connectivity 62 63The next step is to make sure your computer can talk to the USRP. An otherwise unconfigured 64USRP device will have the IP address 192.168.10.2 when using 1GigE. 65It is recommended to directly connect your USRP to the computer at first, 66and to set the IP address on your machine to 192.168.10.1. 67See \ref x3x0_setup_network_host_interface on details how to change your machine's IP address. 68 69<b>Note</b>: If you are running an automatic IP configuration service such as Network Manager, make 70sure it is either deactivated or configured to not change the network device! This can, in extreme cases, 71lead to you bricking the USRP! 72 73If your network configuration is correct, running `uhd_find_devices` will find your USRP 74and print some information about it. You will also be able to ping the USRP by running: 75 76 ping 192.168.10.2 77 78on the command line. At this point, you should also run: 79 80 uhd_usrp_probe --args addr=192.168.10.2 81 82to make sure all of your components (daughterboards, GPSDO) are correctly detected and usable. 83 84\subsection x3x0_getting_started_fpga_update Updating the FPGA 85 86If the output from `uhd_find_devices` and `uhd_usrp_probe` didn't show any warnings, you 87can skip this step. However, if there were errors regarding the FPGA version compatibility 88number, you will have to update the FPGA image before you can start using your USRP. 89 901. Download the current UHD images. You can use the `uhd_images_downloader` script provided 91 with UHD (see also \ref page_images). 922. Use the `uhd_image_loader` utility to update the FPGA image. On the command line, run: 93 94 uhd_image_loader --args="type=x300,addr=192.168.10.2,fpga=HG" 95 96 If you have installed the images to a non-standard location, you might need to run (change the filename according to your device): 97 98 uhd_image_loader --args="type=x300,addr=192.168.10.2" --fpga-path="<path_to_images>/usrp_x310_fpga_HG.bit" 99 100 The process of updating the FPGA image will take several minutes. Make sure the process of flashing the image does not get interrupted. 101 102See \ref x3x0_flash for more details. 103 104When your FPGA is up to date, power-cycle the device and re-run `uhd_usrp_probe`. There should 105be no more warnings at this point, and all components should be correctly detected. Your USRP is now 106ready for development! 107 108\section x3x0_hw Hardware Setup 109 110\subsection x3x0_hw_1gige Gigabit Ethernet (1 GigE) 111 112- Prior to installing the module, the host PC can remain powered on. 113- Plug a 1 Gigabit SFP Transceiver into Ethernet Port 0 on the USRP X300/X310 device. 114- Use the Ethernet cable to connect the SFP+ transceiver on the device to the host computer. For maximum throughput, Ettus Research recommends that you connect each device to its own dedicated Gigabit Ethernet interface on the host computer. 115- Connect the AC/DC power supply to the device and plug the supply into a wall outlet. 116- The OS will automatically recognize the device (e.g. when running `uhd_find_devices`). 117 118\subsection x3x0_hw_10gige Ten Gigabit Ethernet (10 GigE) 119 120### Installing the Host Ethernet Interface 121 122Ettus Research recommends the Intel Ethernet Converged Network Adapter X520-DA2 interface for communication with the USRP X300/X310 device. 123Installation instructions for this interface are available on the official Intel website. 124 125### Installing the USRP X300/X310 126 127- Prior to installing the module, the host PC can remain powered on. 128- Use a 10 Gigabit SFP+ cable to connect Ethernet Port 1 on the USRP X300/X310 device to the host computer. For maximum throughput, Ettus Research recommends that you connect the device to its own dedicated Ten Gigabit, Ettus Research recommended Ethernet interface on the host computer. 129- Connect the AC/DC power supply to the device and plug the supply into a wall outlet. 130- The OS will automatically recognize the device (e.g. when running `uhd_find_devices`). 131 132The LEDs on the front panel can be useful in debugging hardware and software issues (see \ref x3x0_hw_fpanel) 133 134### Dual 10 Gigabit Ethernet 135 136In order to utilize the X-series USRP over dual 10 Gigabit Ethernet interfaces, ensure 137either the XG image is installed (see \ref x3x0_load_fpga_imgs_fpga_flavours). 138In addition to burning the prerequisite FPGA image, it may also be necessary 139to tune the network interface card (NIC) to eliminate drops (Ds) and reduce overflows (Os). 140This is done by increasing the number of RX descriptors (see \ref transport_udp_linux). 141 142The benchmark_rate tool can be used to test this capability. 143Run the following commands to test the X-series USRP over both 10 Gigabit 144Ethernet interfaces with the maximum rate of 200 Msps per channel: 145 146 cd <install-path>/lib/uhd/examples 147 ./benchmark_rate --args="type=x300,addr=<Primary IP>,second_addr=<secondary IP>" --channels="0,1" --rx_rate 200e6 148 149The second interface is specified by the extra argument <b>second_addr</b>. 150 151### DPDK Support 152 153To enable the highest streaming rates over the network, X310 supports using 154transports based on the \ref page_dpdk "Data Plane Development Kit (DPDK)". 155See the DPDK page for details on how it can improve streaming and how to use 156it. 157 158\subsection x3x0_hw_pcie PCI Express (Desktop) 159 160<b>Important Note: The USRP X-Series provides PCIe connectivity over MXI cable. 161We will use the 'MXI' nomenclature for the rest of this manual.</b> 162 163### Installing the PCIe Kernel Drivers 164 165In order to use the USRP X-Series on a PCIe-over-MXI connection, you need to 166install the NI RIO drivers on your system. Please follow the instructions here: 167\ref page_ni_rio_kernel 168 169### Installing the PCI Express Interface Kit 170 171Follow the instructions listed in the <a href="http://www.ni.com/pdf/manuals/371976c.pdf">Set Up Your MXI-Express x4 System</a> 172document to setup the NI PCIe-8371 module. 173 174### Installing the USRP X300/X310 175 176- Prior to installing the module, make sure that the PC is powered off. 177- Using a MXI-Express Cable connect the USRP X300/X310 to the NI PCIe-8371. 178- Connect the AC/DC power supply to the device and plug the supply into a wall outlet. 179- Power on the USRP X300/X310 device using the power switch located in the bottom-right corner of the front panel. 180- Power on the PC (The OS automatically recognizes the new device) 181 182<b>Note:</b> The USRP device is not hot-pluggable over PCI Express. Any connection changes with only be detected by your 183computer after a successful reboot. 184 185### Troubleshooting 186 187Two possible failure modes are your computer not booting when connected to your 188USRP device through MXI-Express, and Windows not properly discovering your 189devices (for example, there is a yellow exclamation point on a PCI to PCI 190bridge in Windows Device Manager, despite drivers for all devices being 191installed). These situations often are due to programming errors in PCI Express 192device configuration of the BIOS. To use this software, you need a MXI-Express 193device that supports Mode 1 operation. 194Refer to <a href="http://download.ni.com/support/softlib//PXI/MXIe%20Compatibility%20Software/1.5.0/readme.html#SupportedHardware">NI MXI-Express BIOS Compatibility Software Readme</a> 195for more information. 196 197The BIOS Compatibility Software can be downloaded for Windows from the <a href="http://www.ni.com/download/mxi-express-bios-compatibility-software-1.5/3764/en/"> MXI-Express BIOS Compatibility Software page</a>. 198 199\subsection x3x0_hw_pcie_laptop PCI Express (Laptop) 200 201<b>Important Note: The USRP X-Series provides PCIe connectivity over MXI cable 202We will use the 'MXI' nomenclature for the rest of this manual.</b> 203 204### Installing the PCIe Kernel Drivers 205 206In order to use the USRP X-Series on a PCIe-over-MXI connection, you need to 207install the NI RIO drivers on your system. Please follow the instructions here: 208\ref page_ni_rio_kernel 209 210### Installing the PCI Express Card 211 212Follow the instructions listed in the “Installing an NI ExpressCard-8360 Host Card” section of the 213<a href="http://www.ni.com/pdf/manuals/373259d.pdf#page=10">Set Up Your MXI-Express x1 System</a> 214document to setup the NI ExpressCard-8360B module. 215 216### Installing the USRP X300/X310 217 218Because a laptop computer is not grounded, follow this procedure to safely connect a laptop 219computer to your USRP device. 220 221- Connect the AC/DC power supply to the device and plug the supply into a wall outlet. Ensure that the USRP device is powered off. 222- Touch the NI ExpressCard-8360B and a metal part of the USRP device simultaneously. Do not install the NI ExpressCard-8360B into the laptop computer yet. 223- Connect the cable to the NI ExpressCard-8360B and USRP. 224- Plug the NI ExpressCard-8360B into an available ExpressCard slot. If your laptop computer is already running (or hibernating, suspended, etc.) when you install an NI ExpressCard-8360B, you must reboot to detect the USRP. Otherwise, the USRP is detected when you start your computer. 225 226\b Note: The USRP device is not hot-pluggable over PCI Express. Any connection changes will only be detected by your computer after a successful reboot. 227 228\section x3x0_jtag On-Board JTAG Programmer 229 230The USRP X3x0 includes an on-board JTAG programmer, built into the motherboard. 231To connect to this JTAG device, simply connect your computer to the USB JTAG 232port on the front of the X3x0 device. You may now use the JTAG programmer in 233the same way you would use any other, including: 234 235- Vivado (standard workflow, see below) 236- <a href="http://www.xilinx.com/support/download/index.htm">Xilinx Programming Tools (ISE, iMPACT)</a> 237- <a href="http://www.xilinx.com/tools/cspro.htm">Xilinx Chipscope</a> 238- <a href="https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2">Digilent ADEPT</a> 239 240In order to use the JTAG programmer with the Xilinx tools, the Digilent drivers and plugin have to be installed first. Although recent versions of Vivado ship with the driver, it has to still be manually installed. 241 242To install first locate your Vivado installation path on a Linux system (default is `/opt/Xilinx/Vivado/<Version>`): 243 244 sudo `find /opt/Xilinx/Vivado/<Version> -name install_digilent.sh` 245 246The USRP-X series device should now be usable with all the tools mentioned above. 247 248\section x3x0_load_fpga_imgs Load FPGA Images onto the Device 249 250The USRP-X Series device ships with a bitstream pre-programmed in the flash, 251which is automatically loaded onto the FPGA during device power-up. However, 252a new FPGA image can be configured over the PCI Express interface or the 253on-board USB-JTAG programmer. This process can be seen as a "one-time load", in 254that if you power-cycle the device, it will not retain the FPGA image. 255 256Please note that this process is *different* than replacing the FPGA image 257stored in the flash, which will then be automatically loaded the next time the 258device is reset. 259 260\subsection x3x0_load_fpga_imgs_fpga_flavours FPGA Image Flavors 261 262The USRP-X Series devices contains two SFP+ ports for the two Ethernet channels. 263Because the SFP+ ports support both 1 Gigabit (SFP) and 10 Gigabit (SFP+) 264transceivers, several FPGA images are shipped with UHD to determine the 265behavior of the above interfaces. 266 267| FPGA Image Flavor | SFP+ Port 0 Interface | SFP+ Port 1 Interface | 268|---------------------|------------------------|------------------------| 269| HG (Default) | 1 Gigabit Ethernet | 10 Gigabit Ethernet | 270| XG | 10 Gigabit Ethernet | 10 Gigabit Ethernet | 271| HA | 1 Gigabit Ethernet | Aurora | 272| XA | 10 Gigabit Ethernet | Aurora | 273 274Note: The Aurora images need to be built manually from the FPGA source code. 275 276FPGA images are shipped in 2 formats: 277 278- **LVBITX**: LabVIEW FPGA configuration bitstream format (for use over PCI Express and Ethernet) 279- **BIT**: Xilinx configuration bitstream format (for use over Ethernet and JTAG) 280 281To get the latest images, simply use the uhd_images_downloader script. On Unix systems, use this command: 282 283 $ [sudo] uhd_images_downloader 284 285On Windows, use: 286 287 <path_to_python.exe> <install-path>/bin/uhd_images_downloader.py 288 289 290\subsection x3x0_load_fpga_imgs_pcie Use PCI Express to load FPGA images 291 292UHD requires a valid LabVIEW FPGA configuration bitstream file (LVBITX) to use the USRP-X Series 293device over the PCI Express bus. LabVIEW FPGA is \b not required to use UHD with a USRP-X Series device. 294Because FPGA configuration is a part of normal operation over PCI Express, there is no setup required 295before running UHD. 296 297The \e fpga tag can be set in the optional device args passed to indicate the FPGA image flavor to UHD. 298If the above tag is specified, UHD will attempt to load the FPGA image with the requested flavor from the 299UHD images directory. If the tag is not specified, UHD will automatically detect the flavor of the image 300and attempt to load the corresponding configuration bitstream onto the device. Note that if UHD detects 301that the requested image is already loaded onto the FPGA then it will not reload it. 302 303\subsection x3x0_load_fpga_imgs_jtag Use JTAG to load FPGA images 304 305The USRP-X Series device features an on-board USB-JTAG programmer that can be accessed on the front-panel 306of the device. There are multiple tools available to access the FPGA through the JTAG connector (see \ref x3x0_jtag). 307 308If you have Vivado installed, we provide a command-line script to flash images. Make sure your X3x0 is powered on and connected to your computer using the front panel USB JTAG connector (USB 2.0 is fine for this). Head to the X3x0 FPGA directory, then run the following commands: 309 310 $ cd uhd/fpga/usrp3/top/x300 # Assuming this is where the FPGA code is checked out 311 $ source ./setupenv.sh 312 $ viv_jtag_program /path/to/bitfile.bit 313 314 315If you have iMPACT installed, you can use the `impact_jtag_programmer.sh` tool to install images. Then run the tool: 316 317 <path_to_uhd_tools>/impact_jtag_programmer.sh --fpga-path=<fpga_image_path> 318 319\section x3x0_flash Load the Images onto the On-board Flash 320 321To change the FPGA image stored in the on-board flash, the USRP-X Series device 322can be reprogrammed over the network or PCI Express. Once you have programmed an 323image into the flash, that image will be automatically loaded on the FPGA 324during the device boot-up sequence. 325 326\b Note: 327Different hardware revisions require different FPGA images. 328Determine the revision number from the sticker on the rear of the device. 329If you are manually specifying an FPGA path, the utility will not try to 330detect your device information, and you will need to use this number to 331select which image to burn. 332 333\b Note: 334The image loader utility will default to using the appropriate BIT file if no custom 335FPGA image path is specified, but it is compatible with BIN, BIT, and LVBITX 336images. 337 338\subsection uhd_image_loader_tool Use the image loader over Ethernet 339 340 Automatic FPGA path, detect image type: 341 uhd_image_loader --args="type=x300,addr=<IP address>" 342 343 Automatic FPGA path, select image type: 344 uhd_image_loader --args="type=x300,addr=<IP address>,fpga=<HG or XG>" 345 346 Manual FPGA path: 347 uhd_image_loader --args="type=x300,addr=<IP address>" --fpga-path="<path to FPGA image>" 348 349\subsection uhd_image_loader_tool_pcie Use the image loader over PCI Express 350 351 Automatic FPGA path, detect image type: 352 uhd_image_loader --args="type=x300,resource=<NI-RIO resource>" 353 354 Automatic FPGA path, select image type: 355 uhd_image_loader --args="type=x300,resource=<NI-RIO resource>,fpga=<HG or XG>" 356 357 Manual FPGA path: 358 uhd_image_loader --args="type=x300,resource=<NI-RIO resource>" --fpga-path="<path to FPGA image>" 359 360\subsection x3x0_flash_bricking Device recovery and bricking 361It is possible to put the device into an unusable state by loading bad images ("bricking"). 362Fortunately, the USRP-X Series device can be loaded with a good image temporarily using the USB-JTAG interface. 363Once booted into the safe image, the user can once again load images onto the device over Ethernet or PCI Express. 364 365See Section \ref x3x0_load_fpga_imgs_jtag on how to load the FPGA image onto the device using a JTAG interface. 366After running the JTAG process, a new image can be flashed onto the device using the usual procedure 367to permently recover the device. 368 369\section x3x0_setup_network Setup Networking 370The USRP-X Series only supports Gigabit and Ten Gigabit Ethernet and will not work with a 10/100 Mbps interface. 371 372<b>Please note that 10 Gigabit Ethernet defines the protocol, not necessary the 373medium. For example, you may use 10GigE over optical with optical SFP+ 374transceiver modules.</b> 375 376\subsection x3x0_setup_network_host_interface Setup the host interface 377 378The USRP-X Series communicates at the IP/UDP layer over the Gigabit and Ten Gigabit Ethernet. 379The default IP address for the USRP X300/X310 device depends on the Ethernet Port and interface used. 380You must configure the host Ethernet interface with a static IP address on the same subnet as the connected 381device to enable communication, as shown in the following table: 382 383 Ethernet Interface | USRP Ethernet Port | Default USRP IP Address | Host Static IP Address | Host Static Subnet Mask | Address EEPROM key 384---------------------|-------------------------|--------------------------|-------------------------|-------------------------|------------------- 385 Gigabit | Port 0 (HG Image) | 192.168.10.2 | 192.168.10.1 | 255.255.255.0 | `ip-addr0` 386 Ten Gigabit | Port 0 (XG Image) | 192.168.30.2 | 192.168.30.1 | 255.255.255.0 | `ip-addr2` 387 Ten Gigabit | Port 1 (HG/XG Image) | 192.168.40.2 | 192.168.40.1 | 255.255.255.0 | `ip-addr3` 388 389As you can see, the X300/X310 actually stores different IP addresses, which all address the device differently: Each combination of Ethernet port and interface type (i.e., Gigabit or Ten Gigabit) has its own IP address. As an example, when addressing the device through 1 Gigabit Ethernet on its first port (Port 0), the relevant IP address is the one stored in the EEPROM with key `ip-addr0`, or 192.168.10.2 by default. 390 391See \ref x3x0cfg_hostpc_netcfg_ip on details how to change your machine's IP address and MTU size to work well with the X300. 392 393\subsection x3x0_setup_network_multidevs Multiple devices per host 394 395For maximum throughput, one Ethernet interface per USRP is recommended, 396although multiple devices may be connected via an Ethernet switch. 397In any case, each Ethernet interface should have its own subnet, 398and the corresponding USRP device should be assigned an address in that subnet. 399Example: 400 401### Configuration for USRP-X Series device 0: 402 403- Ethernet interface IPv4 address: `192.168.10.1` 404- Ethernet interface subnet mask: `255.255.255.0` 405- USRP-X Series device IPv4 address: `192.168.10.2` 406 407### Configuration for USRP-X Series device 1: 408 409- Ethernet interface IPv4 address: `192.168.110.1` 410- Ethernet interface subnet mask: `255.255.255.0` 411- USRP-X Series device IPv4 address: `192.168.110.2` 412 413If all devices are to be used in a compound, see also \ref page_multiple. 414 415\subsection x3x0_setup_change_ip Change the USRP's IP address 416 417You may need to change the USRP's IP address for several reasons: 418- to satisfy your particular network configuration 419- to use multiple USRP-X Series devices on the same host computer 420- to set a known IP address into USRP (in case you forgot) 421 422To change the USRP's IP address, 423you must know the current address of the USRP, 424and the network must be setup properly as described above. 425You must also know which IP address of the X300 you want to change, as identified by their address EEPROM key (e.g. `ip-addr0`, see the table above). 426Run the following commands: 427 428\b UNIX: 429 430 cd <install-path>/lib/uhd/utils 431 ./usrp_burn_mb_eeprom --args=<optional device args> --values="ip-addr0=192.168.10.3" 432 433\b Windows: 434 435 cd <install-path>\lib\uhd\utils 436 usrp_burn_mb_eeprom.exe --args=<optional device args> --values="ip-addr0=192.168.10.3" 437 438You must power-cycle the device before you can use this new address. 439 440\section x3x0_setup_clocking Setup Clocking 441 442\subsection x3x0_set_clocking_mboard Motherboard clock 443 444The X300 series generates a master clock on the motherboard, which is then used 445to drive the ADCs, DACs, and the radio blocks. This clock rate is referred to as 446the "master clock rate". There is always a single master clock rate per 447motherboard. This rate is also the base sample rate of the radio blocks. By 448using DDC and DUC blocks (these are part of the default X300/X310 FPGA image), 449the actual sampling rate available to your application can be an integer divisor 450of the master clock rate, so for a 200 MHz master clock rate, the sampling rate 451available to the application can be 200 Msps, 100 Msps, 66.6 Msps, 50 Msps, and 452so on. 453 454The X300 series support a 200 MHz and a 184.32 MHz master clock rate, with 455200 MHz being the default. To specify a master clock rate, use the 456`master_clock_rate` device arg at initialization time. Example: 457~~~{.cpp} 458auto usrp = uhd::usrp::multi_usrp::make("type=x300,master_clock_rate=184.32e6"); 459usrp->set_rx_rate(30e6); // This will coerce to the next possible value 460// The next possible value is 30.72e6, which is 184.32e6 / 6 461std::cout << usrp->get_rx_rate() << std::endl; // Prints 30.72e6 462~~~ 463 464\b Note: The X300 series does not support the 465`uhd::usrp::multi_usrp::set_master_clock_rate()` API call, because it can only 466configure the clock at initialization time, but not afterwards. To switch the 467master clock rate, destroy your USRP object, and recreate a new one. Example: 468~~~{.cpp} 469// 1. Create USRP object with 184.32 MHz master clock rate 470auto usrp = uhd::usrp::multi_usrp::make("type=x300,master_clock_rate=184.32e6"); 471// 2. Destroy the reference 472usrp.reset(); 473// 3. Recreate the object with a 200 MHz master clock rate 474usrp = uhd::usrp::multi_usrp::make("type=x300,master_clock_rate=200e6"); 475~~~ 476Due to the contract of `uhd::usrp::multi_usrp::set_master_clock_rate()`, the 477call will not throw an exception, but will coerce to the previously set master 478clock rate. Effectively, it will do nothing but print a warning (but it won't 479terminate your application). Also note that the return value of said API call 480as well as the associated getter will always return accurate values. Example: 481~~~{.cpp} 482auto usrp = uhd::usrp::multi_usrp::make("type=x300,master_clock_rate=200e6"); 483double desired_rate = 184.32e6; 484// This call does nothing: 485usrp->set_master_clock_rate(desired_rate); 486// At this point, desired_rate does not actually store the correct rate! 487// This prints the correct rate: 488std::cout << usrp->get_master_clock_rate() << std::endl; // Prints 200e6 489~~~ 490 491 492\subsection x3x0_set_clocking_dboard Daughterboard clock 493 494The X3x0 provides a clock signal to the daughterboards which is used as a 495reference clock for synthesizers and other components that require clocks. 496There are daughterboards that require non-default clock values. See 497Section \ref config_devaddr on how to change the clock value, and \ref page_dboards 498for information specific to certain daughterboards. 499 500Not all combinations of daughterboards work within the same device, if 501daughterboard clock requirements conflict. Note that some daughterboards 502will try and set the daughterboard clock rate themselves. Refer to the 503<a href="https://kb.ettus.com/X300/X310#Choosing_an_RF_Daughterboard">Ettus Research 504Knowledge Base article on the X300/X310</a> for more information on daughterboard 505compatibilty. 506 507\section x3x0_addressing Addressing the Device 508 509\subsection x3x0_addressing_singledev Single device configuration 510 511In a single-device configuration, 512the USRP device must have a unique IPv4 address on the host computer. 513The USRP can be identified through its IPv4 address, resolvable hostname, NI-RIO resource name or by other means. 514See the application notes on \ref page_identification. 515Use this addressing scheme with the uhd::usrp::multi_usrp interface (not a typo!). 516 517Example device address string representation for a USRP-X Series device with IPv4 address 192.168.10.2: 518 519 addr=192.168.10.2 520 521Example device address string representation for a USRP-X Series device with RIO resource name `RIO0` over PCI Express: 522 523 resource=RIO0 524 525\subsection x3x0_addressing_multidevcfg Multiple device configuration 526 527In a multi-device configuration, 528each USRP device must have a unique IPv4 address on the host computer. 529The device address parameter keys must be suffixed with the device index. 530Each parameter key should be of the format \<key\>\<index\>. 531Use this addressing scheme with the uhd::usrp::multi_usrp interface. 532 533- The order in which devices are indexed corresponds to the indexing of the transmit and receive channels. 534- The key indexing provides the same granularity of device identification as in the single device case. 535 536Example device address string representation for 2 USRPs with IPv4 addresses **192.168.10.2** and **192.168.20.2**: 537 538 addr0=192.168.10.2, addr1=192.168.20.2 539 540See also \ref page_multiple. 541 542\section x3x0_troubleshooting Troubleshooting 543\subsection x3x0_comm_issues Communication Issues 544 545When setting up a development machine for the first time, 546you may have various difficulties communicating with the USRP device. 547The following tips are designed to help narrow down and diagnose the problem. 548 549\subsection x3x0_comm_issues_runtimeerr RuntimeError: no control response 550 551This is a common error that occurs when you have set the subnet of your network 552interface to a different subnet than the network interface of the USRP device. For 553example, if your network interface is set to **192.168.20.1**, and the USRP device is **192.168.10.2** 554(note the difference in the third numbers of the IP addresses), you 555will likely see a 'no control response' error message. 556 557Fixing this is simple - just set the your host PC's IP address to the same 558subnet as that of your USRP device. Instructions for setting your IP address are in the 559previous section of this documentation. 560 561\subsection x3x0_comm_issues_firewall Firewall Issues 562 563When the IP address is not specified, 564the device discovery broadcasts UDP packets from each Ethernet interface. 565Many firewalls will block the replies to these broadcast packets. 566If disabling your system's firewall 567or specifying the IP address yields a discovered device, 568then your firewall may be blocking replies to UDP broadcast packets. 569If this is the case, we recommend that you disable the firewall 570or create a rule to allow all incoming packets with UDP source port **49152**. 571 572\subsection x3x0_comm_issues_ping Ping the device 573The USRP device will reply to ICMP echo requests ("ping"). 574A successful ping response means that the device has booted properly 575and that it is using the expected IP address. 576 577 ping 192.168.10.2 578 579\subsection x3x0_comm_issues_not_enumerated Device not enumerated over PCI-Express (Linux) 580 581UHD requires the RIO device manager service to be running in order to 582communicate with an X-Series USRP over PCIe. This service is installed as 583a part of the USRP RIO (or NI-USRP) installer. On Linux, the service is not 584started at system boot time, and is left to the user to control. To start it, 585run the following command: 586 587 sudo niusrprio_pcie start 588 589If the device still does not enumerate after starting the device manager, make sure that the host computer 590has successfully detected it. You can do so by running the following command: 591 592 lspci -k -d 1093:c4c4 593 594A device similar to the following should be detected: 595 596 $ lspci -k -d 1093:c4c4 597 04:00.0 Signal processing controller: National Instruments ... 598 Subsystem: National Instruments Device 76ca 599 Kernel driver in use: niusrpriok_shipped 600 601- All USRP X-Series devices should appear with 'Subsystem: National Instruments Device' 602- The device ID following can be: 603 - USRP X300: 7736 or 7861 604 - USRP X310: 76CA or 7862 605 - NI-USRP 294xR: 772B, 77FB, 772C, 77FC, 772D, 77FD, 772E, 7853, 785B, 7854, 785C, 7855, 785D or 7856 606 - NI-USRP 295xR: 772F, 77FE, 7730, 77FF, 7731, 7800, 7732, 7857, 785E, 7858, 785F, 7859, 7860 or 785A 607 608 609\subsection x3x0_comm_issues_not_enumerated_win Device not enumerated over PCI-Express (Windows) 610 611UHD requires the RIO device manager service to be running in order to 612communicate with an X-Series USRP over PCIe. 613This service is installed as a part of the USRP RIO (or NI-USRP) installer. On Windows, it can be found in 614the **Services** section in the Control Panel and it is started at system boot time. To ensure that the 615service is indeed started, navigate to the Services tag in the Windows Task Manager and ensure that the 616status of **niusrpriorpc** is "Running". 617 618If the device still does not enumerate after starting the device manager, make sure that the host computer 619has successfully detected it. You can do so by checking if your device shows up in the Windows Device Manager. 620 621\subsection x3x0_comm_issues_monitor Monitor the host network traffic 622Use Wireshark to monitor packets sent to and received from the device. 623 624\subsection x3x0_comm_problems_leds Observe Ethernet port LEDs 625When there is network traffic arriving at the Ethernet port, LEDs will light up. 626You can use this to make sure the network connection is correctly set up, e.g. 627by pinging the USRP and making sure the LEDs start to blink. 628 629\subsection x3x0_corrupt_eeprom Corrupt EEPROM 630 631This is a rare bug in which the X-Series device's on-board EEPROM becomes corrupt and reports an incorrect 632firmware and FPGA version. In this situation, UHD cannot properly use the device. To fix this bug, use 633the **usrp_burn_mb_eeprom** utility as follows: 634 635 usrp_burn_mb_eeprom --args="type=x300,recover_mb_eeprom,disable_adc_self_test" --values="revision=(NUM HERE)" 636 637Afterward, power-cycle your X-Series device for the changes to take effect. 638 639\section x3x0_hw_notes Hardware Notes 640 641\subsection x3x0_hw_fpanel Front Panel 642 643\image html x3x0_fp_overlay.png "X3x0" 644 645- **JTAG**: USB connector for the on-board USB-JTAG programmer 646- **RF A Group** 647 + **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on daughterboard A 648 + **RX2 LED**: Indicates that data is streaming on the RX2 channel on daughterboard A 649- **REF**: Indicates that the external Reference Clock is locked 650- **PPS**: Indicates a valid PPS signal by pulsing once per second 651- **AUX I/O**: Front panel GPIO connector. 652- **GPS**: Indicates that GPS reference is locked 653- **LINK**: Indicates that the host computer is communicating with the device (Activity) 654 655- **RF B Group** 656 + **TX/RX LED**: Indicates that data is streaming on the TX/RX channel on daughterboard B 657 + **RX2 LED**: Indicates that data is streaming on the RX2 channel on daughterboard B 658- **PWR**: Power switch 659 660\subsection x3x0_hw_rear_panel Rear Panel 661 662\image html x3x0_rp_overlay.png "X3x0 Rear Panel" 663 664- **PWR**: Connector for the USRP-X Series power supply 665- **1G/10G ETH**: SFP+ ports for Ethernet interfaces 666- **REF OUT**: Output port for the exported reference clock 667- **REF IN**: Reference clock input 668- **PCIe x4**: Connector for Cabled PCI Express link 669- **PPS/TRIG OUT**: Output port for the PPS signal 670- **PPS/TRIG IN**: Input port for the PPS signal 671- **GPS**: Connection for the GPS antenna 672 673\subsection x3x0_hw_x3x0_hw_ref10M Ref Clock (10 MHz or other frequency) 674 675Using an external 10 MHz reference clock, a square wave will offer the best phase 676noise performance, but a sinusoid is acceptable. 677The power level of the reference clock must exceed +15 dBm. 678 679The following reference frequencies are supported: 680- 10 MHz 681- 11.52 MHz 682- 23.04 MHz 683- 30.72 MHz 684 685If the external reference clock is not 10 MHz, the `system_ref_rate` device arg 686must be provided. 687 688To use the external reference in your UHD session, make sure to either call 689uhd::usrp::multi_usrp::set_clock_source() or specify `clock_source=external` in 690your device args. 691 692\subsection x3x0_hw_pps PPS - Pulse Per Second 693 694Using a PPS signal for timestamp synchronization requires a square wave signal 695with a 5Vpp amplitude. 696 697To test the PPS input, you can use the following tool from the UHD examples: 698 699- `<args>` are device address arguments (optional if only one USRP device is on your machine) 700 701 cd <install-path>/lib/uhd/examples 702 ./test_pps_input --args=\<args\> 703 704To use the external time source in your UHD session, make sure to either call 705uhd::usrp::multi_usrp::set_time_source() or specify `time_source=external` in 706your device args. 707 708\subsection x3x0_hw_gpsdo Internal GPSDO 709 710Please see \ref page_gpsdo_x3x0 for information on configuring and using the internal GPSDO. 711 712\subsection x3x0_hw_gpio Front Panel GPIO 713 714### Connector 715 716\image html x3x0_gpio_conn.png "X3x0 GPIO Connector" 717 718The GPIO port is not meant to drive big loads. You should not try to source more than 5mA per pin. 719 720The +3.3V is for ESD clamping purposes only and not designed to deliver high currents. 721 722### Pin Mapping 723 724- Pin 1: +3.3V 725- Pin 2: Data[0] 726- Pin 3: Data[1] 727- Pin 4: Data[2] 728- Pin 5: Data[3] 729- Pin 6: Data[4] 730- Pin 7: Data[5] 731- Pin 8: Data[6] 732- Pin 9: Data[7] 733- Pin 10: Data[8] 734- Pin 11: Data[9] 735- Pin 12: Data[10] 736- Pin 13: Data[11] 737- Pin 14: 0V 738- Pin 15: 0V 739 740 741Please see the \ref page_gpio_api for information on configuring and using the GPIO bus. 742 743\subsection x3x0_hw_on_board_leds On-Board LEDs 744 745|LED | | Description | 746|-------|---------------|-------------------------------| 747|DS1 |1.2V |power | 748|DS2 |TXRX1 |Red: TX, Green: RX | 749|DS3 |RX1 |Green: RX | 750|DS4 |REF |reference lock | 751|DS5 |PPS |flashes on edge | 752|DS6 |GPS |GPS lock | 753|DS7 |SFP0 |link | 754|DS8 |SFP0 |link activity | 755|DS10 |TXRX2 |Red: TX Green: RX | 756|DS11 |RX2 |Green: RX | 757|DS12 |6V |daughterboard power | 758|DS13 |3.8V |power | 759|DS14 |3.3V |management power | 760|DS15 |3.3V |auxiliary management power | 761|DS16 |1.8V |FPGA power | 762|DS16 |3.3V |FPGA power | 763|DS19 |SFP1 |link | 764|DS20 |SFP1 |link active | 765|DS21 |LINK |link activity | 766 767\subsection x3x0_hw_chipscope Debugging custom FPGA designs with Xilinx Chipscope 768 769Xilinx chipscope allows for debugging custom FPGA designs similar to a logic analyzer. 770USRP-X series devices can be used with Xilinx chipscope using the onboard USB JTAG connector. 771 772Further information on how to use Chipscope can be found in the Xilinx Chipscope Pro Software and Cores User Guide (UG029). 773 774\section x3x0_misc Miscellaneous 775 776\subsection x3x0_misc_power Power API 777 778The X300 series support the UHD power calibration API (see: \ref page_power). 779Calibration data is daughterboard-specific, i.e., the daughterboard serial is 780used to map calibration data to a serial. 781 782Daughterboards have to be manually calibrated using a calibrated power meter or 783signal generator. 784 785\subsection x3x0_misc_settings Configuring the device in an application 786 787During runtime, the device can be configured in several different ways. 788 789The following pages may shed some light: 790 791- \ref page_configuration 792- uhd::stream_args_t 793- \ref multiple_channumbers 794 795\subsection x3x0_misc_multirx Multiple RX channels 796 797There are two complete DDC and DUC DSP chains in the FPGA. In the single channel case, 798only one chain is ever used. To receive from both channels, the user must set the **RX** or **TX** 799subdevice specification. 800 801In the following example, a TVRX2 is installed. 802Channel 0 is sourced from subdevice **RX1**, 803and channel 1 is sourced from subdevice **RX2** (**RX1** and **RX2** are antenna connectors on the TVRX2 daughterboard). 804 805~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp} 806usrp->set_rx_subdev_spec("A:RX1 A:RX2"); 807~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 808 809\subsection x3x0_misc_sensors Available Sensors 810 811The following sensors are available for the USRP-X Series motherboards; 812they can be queried through the API. 813 814- **ref_locked** - clock reference locked (internal/external) 815- Other sensors are added when the GPSDO is enabled 816 817\subsection x3x0_misc_timed_cmds_lockup Multiple Timed Command Advisory 818 819When issuing multiple timed commands to an x3xx device, it is important to ensure that the device is streaming data in some capacity. In the HG and XG images, the DDC & DUC derive their sense of time from the header of passing packets. This sense of time is necessary to execute timed commands. Repeatedly issuing timed commands without streaming will result in the command queue of the DDC / DUC backing up and overflowing, putting the device in a state where a full restart is required. 820 821 822*/ 823// vim:ft=doxygen: 824