1 //
2 // Copyright 2010-2012 Ettus Research LLC
3 // Copyright 2018 Ettus Research, a National Instruments Company
4 //
5 // SPDX-License-Identifier: GPL-3.0-or-later
6 //
7 
8 #ifndef INCLUDED_USRP2_REGS_HPP
9 #define INCLUDED_USRP2_REGS_HPP
10 
11 ////////////////////////////////////////////////////////////////////////
12 // Define slave bases
13 ////////////////////////////////////////////////////////////////////////
14 #define ROUTER_RAM_BASE 0x4000
15 #define SPI_BASE 0x5000
16 #define I2C_BASE 0x5400
17 #define GPIO_BASE 0x5800
18 #define READBACK_BASE 0x5C00
19 #define ETH_BASE 0x6000
20 #define SETTING_REGS_BASE 0x7000
21 #define PIC_BASE 0x8000
22 #define UART_BASE 0x8800
23 #define ATR_BASE 0x8C00
24 
25 ////////////////////////////////////////////////////////////////////////
26 // Setting register offsets
27 ////////////////////////////////////////////////////////////////////////
28 #define SR_MISC 0 // 7 regs
29 #define SR_USER_REGS 8 // 2
30 #define SR_TIME64 10 // 6
31 #define SR_BUF_POOL 16 // 4
32 #define SR_SPI_CORE 20 // 3
33 #define SR_RX_FRONT 24 // 5
34 #define SR_RX_CTRL0 32 // 9
35 #define SR_RX_DSP0 48 // 7
36 #define SR_RX_CTRL1 80 // 9
37 #define SR_RX_DSP1 96 // 7
38 
39 #define SR_TX_FRONT 128 // ?
40 #define SR_TX_CTRL 144 // 6
41 #define SR_TX_DSP 160 // 5
42 
43 #define SR_GPIO 184
44 #define SR_UDP_SM 192 // 64
45 
46 #define U2_REG_SR_ADDR(sr) (SETTING_REGS_BASE + (4 * (sr)))
47 
48 #define U2_REG_ROUTER_CTRL_PORTS U2_REG_SR_ADDR(SR_BUF_POOL) + 8
49 
50 /////////////////////////////////////////////////
51 // SPI Slave Constants
52 ////////////////////////////////////////////////
53 // Masks for controlling different peripherals
54 #define SPI_SS_AD9510 1
55 #define SPI_SS_AD9777 2
56 #define SPI_SS_RX_DAC 4
57 #define SPI_SS_RX_ADC 8
58 #define SPI_SS_RX_DB 16
59 #define SPI_SS_TX_DAC 32
60 #define SPI_SS_TX_ADC 64
61 #define SPI_SS_TX_DB 128
62 #define SPI_SS_ADS62P44 256 // for usrp2p
63 
64 /////////////////////////////////////////////////
65 // Misc Control
66 ////////////////////////////////////////////////
67 #define U2_REG_MISC_CTRL_CLOCK U2_REG_SR_ADDR(0)
68 #define U2_REG_MISC_CTRL_SERDES U2_REG_SR_ADDR(1)
69 #define U2_REG_MISC_CTRL_ADC U2_REG_SR_ADDR(2)
70 #define U2_REG_MISC_CTRL_LEDS U2_REG_SR_ADDR(3)
71 #define U2_REG_MISC_CTRL_PHY U2_REG_SR_ADDR(4)
72 #define U2_REG_MISC_CTRL_DBG_MUX U2_REG_SR_ADDR(5)
73 #define U2_REG_MISC_CTRL_RAM_PAGE U2_REG_SR_ADDR(6)
74 #define U2_REG_MISC_CTRL_FLUSH_ICACHE U2_REG_SR_ADDR(7)
75 #define U2_REG_MISC_CTRL_LED_SRC U2_REG_SR_ADDR(8)
76 
77 #define U2_FLAG_MISC_CTRL_SERDES_ENABLE 8
78 #define U2_FLAG_MISC_CTRL_SERDES_PRBSEN 4
79 #define U2_FLAG_MISC_CTRL_SERDES_LOOPEN 2
80 #define U2_FLAG_MISC_CTRL_SERDES_RXEN 1
81 
82 #define U2_FLAG_MISC_CTRL_ADC_ON 0x0F
83 #define U2_FLAG_MISC_CTRL_ADC_OFF 0x00
84 
85 /////////////////////////////////////////////////
86 // Readback regs
87 ////////////////////////////////////////////////
88 #define U2_REG_STATUS READBACK_BASE + 4 * 8
89 #define U2_REG_GPIO_RB READBACK_BASE + 4 * 9
90 #define U2_REG_TIME64_HI_RB_IMM READBACK_BASE + 4 * 10
91 #define U2_REG_TIME64_LO_RB_IMM READBACK_BASE + 4 * 11
92 #define U2_REG_COMPAT_NUM_RB READBACK_BASE + 4 * 12
93 #define U2_REG_IRQ_RB READBACK_BASE + 4 * 13
94 #define U2_REG_TIME64_HI_RB_PPS READBACK_BASE + 4 * 14
95 #define U2_REG_TIME64_LO_RB_PPS READBACK_BASE + 4 * 15
96 
97 #endif /* INCLUDED_USRP2_REGS_HPP */
98