1 /** 2 * \file common.h 3 * \brief Contains type definitions and prototype declarations for common.c 4 */ 5 6 /** 7 * \page Disclaimer Legal Disclaimer 8 * Copyright 2015-2017 Analog Devices Inc. 9 * Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. 10 * 11 */ 12 13 #ifndef _COMMON_H_ 14 #define _COMMON_H_ 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* build project settings include the path to the desired platform folder for correct includes */ 21 #include "stdint.h" 22 23 #define THROW_ERROR() 24 25 #define SPIARRAYSIZE 1024 26 27 /* assuming 3 byte SPI message - integer math enforces floor() */ 28 #define SPIARRAYTRIPSIZE ((SPIARRAYSIZE / 3) * 3) 29 30 /*======================================== 31 * Enums and structures 32 *=======================================*/ 33 /* proposed to increase number of error return values to make unique for each return */ 34 typedef enum 35 { 36 ADIERR_OK=0, 37 ADIERR_INV_PARM, 38 ADIERR_FAILED 39 } ADI_ERR; 40 41 /*!< \brief COMMON layer error reporting enumerated types */ 42 typedef enum 43 { 44 COMMONERR_OK=0, 45 COMMONERR_FAILED 46 } commonErr_t; 47 48 /* bit 0 is MESSAGE, bit 1 is WARNING, bit 2 is ERROR */ 49 typedef enum 50 { 51 ADIHAL_LOG_NONE = 0x0, 52 ADIHAL_LOG_MESSAGE = 0x1, 53 ADIHAL_LOG_WARNING = 0x2, 54 ADIHAL_LOG_ERROR = 0x4, 55 ADIHAL_LOG_SPI = 0x8, 56 ADIHAL_LOG_AXI_REG = 0x10, 57 ADIHAL_LOG_AXI_MEM = 0x20, 58 ADIHAL_LOG_ALL = 0x3F 59 } ADI_LOGLEVEL; 60 61 /** 62 * \brief Data structure to hold SPI settings for all system device types 63 */ 64 typedef struct 65 { 66 uint8_t chipSelectIndex; ///< valid 1~8 67 uint8_t writeBitPolarity; ///< the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation 68 uint8_t longInstructionWord; ///< 1 = 16bit instruction word, 0 = 8bit instruction word 69 uint8_t MSBFirst; ///< 1 = MSBFirst, 0 = LSBFirst 70 uint8_t CPHA; ///< clock phase, sets which clock edge the data updates (valid 0 or 1) 71 uint8_t CPOL; ///< clock polarity 0 = clock starts low, 1 = clock starts high 72 uint8_t enSpiStreaming; ///< Not implemented. SW feature to improve SPI throughput. 73 uint8_t autoIncAddrUp; ///< Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1 74 uint8_t fourWireMode; ///< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode. 75 uint32_t spiClkFreq_Hz; ///< SPI Clk frequency in Hz (default 25000000), platform will use next lowest frequency that it's baud rate generator can create */ 76 77 } spiSettings_t; 78 79 /* global variable so application layer can set the log level */ 80 extern ADI_LOGLEVEL CMB_LOGLEVEL; 81 82 /* close hardware pointers */ 83 commonErr_t CMB_closeHardware(void); 84 85 /* GPIO function */ 86 commonErr_t CMB_setGPIO(uint32_t GPIO); 87 88 /* hardware reset function */ 89 commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex); 90 91 /* SPI read/write functions */ 92 commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings); /* allows the platform HAL to work with devices with various SPI settings */ 93 commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex ); /* value of 0 deasserts all chip selects */ 94 commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t data); /* single SPI byte write function */ 95 commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr, uint8_t *data, uint32_t count); 96 commonErr_t CMB_SPIReadByte (spiSettings_t *spiSettings, uint16_t addr, uint8_t *readdata); /* single SPI byte read function */ 97 commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, uint8_t field_val, uint8_t mask, uint8_t start_bit); /* write a field in a single register */ 98 commonErr_t CMB_SPIReadField (spiSettings_t *spiSettings, uint16_t addr, uint8_t *field_val, uint8_t mask, uint8_t start_bit); /* read a field in a single register */ 99 100 /* platform timer functions */ 101 commonErr_t CMB_wait_ms(uint32_t time_ms); 102 commonErr_t CMB_wait_us(uint32_t time_us); 103 commonErr_t CMB_setTimeout_ms(spiSettings_t *spiSettings, uint32_t timeOut_ms); 104 commonErr_t CMB_setTimeout_us(spiSettings_t *spiSettings, uint32_t timeOut_us); 105 commonErr_t CMB_hasTimeoutExpired(spiSettings_t *spiSettings); 106 107 /* platform logging functions */ 108 commonErr_t CMB_openLog(const char *filename); 109 commonErr_t CMB_closeLog(void); 110 commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, uint32_t errorCode, const char *comment); 111 commonErr_t CMB_flushLog(void); 112 113 /* platform FPGA AXI register read/write functions */ 114 commonErr_t CMB_regRead(uint32_t offset, uint32_t *data); 115 commonErr_t CMB_regWrite(uint32_t offset, uint32_t data); 116 117 /* platform DDR3 memory read/write functions */ 118 commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len); 119 commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len); 120 121 #ifdef __cplusplus 122 } 123 #endif 124 #endif 125