1# 2# Copyright 2018 Ettus Research, a National Instruments Company 3# 4# SPDX-License-Identifier: GPL-3.0-or-later 5# 6""" 7White Rabbit Control 8""" 9 10from builtins import object 11from usrp_mpm.sys_utils.uio import UIO 12 13 14class WhiteRabbitRegsControl(object): 15 """ 16 Control and read the FPGA White Rabbit core registers 17 """ 18 # Memory Map 19 # 0x00000000: I/D Memory 20 # 0x00020000: Peripheral interconnect 21 # +0x000: Minic 22 # +0x100: Endpoint 23 # +0x200: Softpll 24 # +0x300: PPS gen 25 # +0x400: Syscon 26 # +0x500: UART 27 # +0x600: OneWire 28 # +0x700: Auxillary space (Etherbone config, etc) 29 # +0x800: WRPC diagnostics registers 30 PERIPH_INTERCON_BASE = 0x20000 31 32 # PPS_GEN Map 33 PPSG_ESCR = 0x31C 34 35 def __init__(self, label, log): 36 self.log = log 37 self.regs = UIO( 38 label=label, 39 read_only=False 40 ) 41 self.periph_peek32 = lambda addr: self.regs.peek32(addr + self.PERIPH_INTERCON_BASE) 42 self.periph_poke32 = lambda addr, data: self.regs.poke32(addr + self.PERIPH_INTERCON_BASE, data) 43 44 def get_time_lock_status(self): 45 """ 46 Retrieves and decodes the lock status for the PPS out of the WR core. 47 """ 48 with self.regs: 49 ext_sync_status = self.periph_peek32(self.PPSG_ESCR) 50 # bit 2: PPS_VALID 51 # bit 3: TM_VALID (timecode) 52 # All other bits MUST be ignored since they are not guaranteed to be zero or 53 # stable! 54 return (ext_sync_status & 0b1100) == 0b1100 55