1;; Code and mode itertator and attribute definitions for the ARM backend 2;; Copyright (C) 2010-2018 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21 22;;---------------------------------------------------------------------------- 23;; Mode iterators 24;;---------------------------------------------------------------------------- 25 26;; A list of modes that are exactly 64 bits in size. This is used to expand 27;; some splits that are the same for all modes when operating on ARM 28;; registers. 29(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) 30 31(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) 32 33;; A list of integer modes that are up to one word long 34(define_mode_iterator QHSI [QI HI SI]) 35 36;; A list of integer modes that are half and one word long 37(define_mode_iterator HSI [HI SI]) 38 39;; A list of integer modes that are less than a word 40(define_mode_iterator NARROW [QI HI]) 41 42;; A list of all the integer modes up to 64bit 43(define_mode_iterator QHSD [QI HI SI DI]) 44 45;; A list of the 32bit and 64bit integer modes 46(define_mode_iterator SIDI [SI DI]) 47 48;; A list of atomic compare and swap success return modes 49(define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")]) 50 51;; A list of modes which the VFP unit can handle 52(define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")]) 53 54;; Integer element sizes implemented by IWMMXT. 55(define_mode_iterator VMMX [V2SI V4HI V8QI]) 56 57(define_mode_iterator VMMX2 [V4HI V2SI]) 58 59;; Integer element sizes for shifts. 60(define_mode_iterator VSHFT [V4HI V2SI DI]) 61 62;; Integer and float modes supported by Neon and IWMMXT. 63(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) 64 65;; Integer and float modes supported by Neon and IWMMXT, except V2DI. 66(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) 67 68;; Integer modes supported by Neon and IWMMXT 69(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) 70 71;; Integer modes supported by Neon and IWMMXT, except V2DI 72(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) 73 74;; Double-width vector modes, on which we support arithmetic (no HF!) 75(define_mode_iterator VD [V8QI V4HI V2SI V2SF]) 76 77;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate. 78(define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI]) 79 80;; Double-width vector modes plus 64-bit elements. 81(define_mode_iterator VDX [V8QI V4HI V4HF V2SI V2SF DI]) 82 83;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane. 84(define_mode_iterator VD_LANE [V8QI V4HI V4HF V2SI V2SF]) 85 86;; Double-width vector modes without floating-point elements. 87(define_mode_iterator VDI [V8QI V4HI V2SI]) 88 89;; Quad-width vector modes supporting arithmetic (no HF!). 90(define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) 91 92;; Quad-width vector modes, including V8HF. 93(define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF]) 94 95;; Quad-width vector modes with 16- or 32-bit elements 96(define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF]) 97 98;; Quad-width vector modes plus 64-bit elements. 99(define_mode_iterator VQX [V16QI V8HI V8HF V4SI V4SF V2DI]) 100 101;; Quad-width vector modes without floating-point elements. 102(define_mode_iterator VQI [V16QI V8HI V4SI]) 103 104;; Quad-width vector modes, with TImode added, for moves. 105(define_mode_iterator VQXMOV [V16QI V8HI V8HF V4SI V4SF V2DI TI]) 106 107;; Opaque structure types wider than TImode. 108(define_mode_iterator VSTRUCT [EI OI CI XI]) 109 110;; Opaque structure types used in table lookups (except vtbl1/vtbx1). 111(define_mode_iterator VTAB [TI EI OI]) 112 113;; Widenable modes. 114(define_mode_iterator VW [V8QI V4HI V2SI]) 115 116;; Narrowable modes. 117(define_mode_iterator VN [V8HI V4SI V2DI]) 118 119;; All supported vector modes (except singleton DImode). 120(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI]) 121 122;; All supported floating-point vector modes (except V2DF). 123(define_mode_iterator VF [(V4HF "TARGET_NEON_FP16INST") 124 (V8HF "TARGET_NEON_FP16INST") V2SF V4SF]) 125 126;; All supported vector modes (except those with 64-bit integer elements). 127(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) 128 129;; All supported vector modes including 16-bit float modes. 130(define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF 131 V8HF V4HF]) 132 133;; Supported integer vector modes (not 64 bit elements). 134(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) 135 136;; Supported integer vector modes (not singleton DI) 137(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) 138 139;; Vector modes, including 64-bit integer elements. 140(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI 141 V4HF V8HF V2SF V4SF DI V2DI]) 142 143;; Vector modes including 64-bit integer elements, but no floats. 144(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) 145 146;; Vector modes for H, S and D types. 147(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) 148 149;; Vector modes for float->int conversions. 150(define_mode_iterator VCVTF [V2SF V4SF]) 151 152;; Vector modes form int->float conversions. 153(define_mode_iterator VCVTI [V2SI V4SI]) 154 155;; Vector modes for int->half conversions. 156(define_mode_iterator VCVTHI [V4HI V8HI]) 157 158;; Vector modes for doubleword multiply-accumulate, etc. insns. 159(define_mode_iterator VMD [V4HI V2SI V2SF]) 160 161;; Vector modes for quadword multiply-accumulate, etc. insns. 162(define_mode_iterator VMQ [V8HI V4SI V4SF]) 163 164;; Above modes combined. 165(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) 166 167;; As VMD, but integer modes only. 168(define_mode_iterator VMDI [V4HI V2SI]) 169 170;; As VMQ, but integer modes only. 171(define_mode_iterator VMQI [V8HI V4SI]) 172 173;; Above modes combined. 174(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) 175 176;; Modes with 8-bit and 16-bit elements. 177(define_mode_iterator VX [V8QI V4HI V16QI V8HI]) 178 179;; Modes with 8-bit elements. 180(define_mode_iterator VE [V8QI V16QI]) 181 182;; Modes with 64-bit elements only. 183(define_mode_iterator V64 [DI V2DI]) 184 185;; Modes with 32-bit elements only. 186(define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) 187 188;; Modes with 8-bit, 16-bit and 32-bit elements. 189(define_mode_iterator VU [V16QI V8HI V4SI]) 190 191;; Vector modes for 16-bit floating-point support. 192(define_mode_iterator VH [V8HF V4HF]) 193 194;; Iterators used for fixed-point support. 195(define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) 196 197(define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) 198 199(define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) 200 201(define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) 202 203(define_mode_iterator QMUL [HQ HA]) 204 205;; Modes for polynomial or float values. 206(define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) 207 208;;---------------------------------------------------------------------------- 209;; Code iterators 210;;---------------------------------------------------------------------------- 211 212;; A list of condition codes used in compare instructions where 213;; the carry flag from the addition is used instead of doing the 214;; compare a second time. 215(define_code_iterator LTUGEU [ltu geu]) 216 217;; The signed gt, ge comparisons 218(define_code_iterator GTGE [gt ge]) 219 220;; The signed gt, ge, lt, le comparisons 221(define_code_iterator GLTE [gt ge lt le]) 222 223;; The unsigned gt, ge comparisons 224(define_code_iterator GTUGEU [gtu geu]) 225 226;; Comparisons for vc<cmp> 227(define_code_iterator COMPARISONS [eq gt ge le lt]) 228 229;; A list of ... 230(define_code_iterator IOR_XOR [ior xor]) 231 232;; Operations on two halves of a quadword vector. 233(define_code_iterator VQH_OPS [plus smin smax umin umax]) 234 235;; Operations on two halves of a quadword vector, 236;; without unsigned variants (for use with *SFmode pattern). 237(define_code_iterator VQHS_OPS [plus smin smax]) 238 239;; A list of widening operators 240(define_code_iterator SE [sign_extend zero_extend]) 241 242;; Right shifts 243(define_code_iterator RSHIFTS [ashiftrt lshiftrt]) 244 245;; Iterator for integer conversions 246(define_code_iterator FIXUORS [fix unsigned_fix]) 247 248;; Binary operators whose second operand can be shifted. 249(define_code_iterator SHIFTABLE_OPS [plus minus ior xor and]) 250 251;; Operations on the sign of a number. 252(define_code_iterator ABSNEG [abs neg]) 253 254;; The PLUS and MINUS operators. 255(define_code_iterator PLUSMINUS [plus minus]) 256 257;; Conversions. 258(define_code_iterator FCVT [unsigned_float float]) 259 260;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows 261;; a stack pointer opoerand. The minus operation is a candidate for an rsub 262;; and hence only plus is supported. 263(define_code_attr t2_binop0 264 [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) 265 266;; The instruction to use when a SHIFTABLE_OPS has a shift operation as 267;; its first operand. 268(define_code_attr arith_shift_insn 269 [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) 270 271(define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le") 272 (gtu "gt") (geu "ge")]) 273 274(define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")]) 275 276(define_code_attr vfml_op [(plus "a") (minus "s")]) 277 278;;---------------------------------------------------------------------------- 279;; Int iterators 280;;---------------------------------------------------------------------------- 281 282(define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM 283 UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) 284 285(define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE 286 UNSPEC_VCLT UNSPEC_VCLE]) 287 288(define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT]) 289 290(define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT 291 UNSPEC_VCALE UNSPEC_VCALT]) 292 293(define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) 294 295(define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM 296 UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) 297 298(define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA]) 299 300(define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U]) 301 302(define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U]) 303 304(define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U 305 UNSPEC_VHADD_S UNSPEC_VHADD_U]) 306 307(define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U]) 308 309(define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN]) 310 311(define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U]) 312 313(define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE]) 314 315(define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U]) 316 317(define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE]) 318 319(define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH]) 320 321(define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE]) 322 323(define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P]) 324 325(define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE]) 326 327(define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U]) 328 329(define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U]) 330 331(define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U]) 332 333(define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U]) 334 335(define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN]) 336 337(define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U]) 338 339(define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U]) 340 341(define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U 342 UNSPEC_VMIN UNSPEC_VMIN_U]) 343 344(define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN]) 345 346(define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM]) 347 348(define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U]) 349 350(define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U]) 351 352(define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U 353 UNSPEC_VPMIN UNSPEC_VPMIN_U]) 354 355(define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN]) 356 357(define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U]) 358 359(define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N]) 360 361(define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N]) 362 363(define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N]) 364 365(define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U 366 UNSPEC_VCVTM_S UNSPEC_VCVTM_U 367 UNSPEC_VCVTN_S UNSPEC_VCVTN_U 368 UNSPEC_VCVTP_S UNSPEC_VCVTP_U]) 369 370(define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U]) 371 372;; Operators for FP16 instructions. 373(define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA 374 UNSPEC_VRNDM UNSPEC_VRNDN 375 UNSPEC_VRNDP UNSPEC_VRNDX]) 376 377(define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U]) 378 379(define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U]) 380 381(define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U 382 UNSPEC_VRSHL_S UNSPEC_VRSHL_U]) 383 384(define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U 385 UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U]) 386 387(define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N 388 UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N]) 389 390(define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N]) 391 392(define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N 393 UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N]) 394 395(define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N]) 396 397(define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N]) 398 399(define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N]) 400 401(define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N 402 UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N]) 403 404(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W 405 UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW]) 406 407(define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC]) 408 409(define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE 410 UNSPEC_SHA1SU1 UNSPEC_SHA256SU0]) 411 412(define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H 413 UNSPEC_SHA256H2 UNSPEC_SHA256SU1]) 414 415(define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M 416 UNSPEC_SHA1P]) 417 418(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH]) 419 420(define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE]) 421 422(define_int_iterator DOTPROD [UNSPEC_DOT_S UNSPEC_DOT_U]) 423 424(define_int_iterator VFMLHALVES [UNSPEC_VFML_LO UNSPEC_VFML_HI]) 425 426;;---------------------------------------------------------------------------- 427;; Mode attributes 428;;---------------------------------------------------------------------------- 429 430;; Determine name of atomic compare and swap from success result mode. This 431;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM. 432(define_mode_attr arch [(CC_Z "32") (SI "t1")]) 433 434;; Determine element size suffix from vector mode. 435(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) 436 437;; vtbl<n> suffix for NEON vector modes. 438(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) 439 440;; (Opposite) mode to convert to/from for NEON mode conversions. 441(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") 442 (V4SI "V4SF") (V4SF "V4SI")]) 443 444;; As above but in lower case. 445(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") 446 (V4SI "v4sf") (V4SF "v4si")]) 447 448;; (Opposite) mode to convert to/from for vector-half mode conversions. 449(define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI") 450 (V8HI "V8HF") (V8HF "V8HI")]) 451 452;; Define element mode for each vector mode. 453(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") 454 (V4HI "HI") (V8HI "HI") 455 (V4HF "HF") (V8HF "HF") 456 (V2SI "SI") (V4SI "SI") 457 (V2SF "SF") (V4SF "SF") 458 (DI "DI") (V2DI "DI")]) 459 460;; As above but in lower case. 461(define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi") 462 (V4HI "hi") (V8HI "hi") 463 (V4HF "hf") (V8HF "hf") 464 (V2SI "si") (V4SI "si") 465 (V2SF "sf") (V4SF "sf") 466 (DI "di") (V2DI "di")]) 467 468;; Element modes for vector extraction, padded up to register size. 469 470(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") 471 (V4HI "SI") (V8HI "SI") 472 (V2SI "SI") (V4SI "SI") 473 (V2SF "SF") (V4SF "SF") 474 (DI "DI") (V2DI "DI")]) 475 476;; Mode of pair of elements for each vector mode, to define transfer 477;; size for structure lane/dup loads and stores. 478(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") 479 (V4HI "SI") (V8HI "SI") 480 (V4HF "SF") (V8HF "SF") 481 (V2SI "V2SI") (V4SI "V2SI") 482 (V2SF "V2SF") (V4SF "V2SF") 483 (DI "V2DI") (V2DI "V2DI")]) 484 485;; Mode mapping for VFM[A,S]L instructions. 486(define_mode_attr VFML [(V2SF "V4HF") (V4SF "V8HF")]) 487 488;; Mode mapping for VFM[A,S]L instructions for the vec_select result. 489(define_mode_attr VFMLSEL [(V2SF "V2HF") (V4SF "V4HF")]) 490 491;; Mode mapping for VFM[A,S]L instructions for some awkward lane-wise forms. 492(define_mode_attr VFMLSEL2 [(V2SF "V8HF") (V4SF "V4HF")]) 493 494;; Same as the above, but lowercase. 495(define_mode_attr vfmlsel2 [(V2SF "v8hf") (V4SF "v4hf")]) 496 497;; Similar, for three elements. 498(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") 499 (V4HI "BLK") (V8HI "BLK") 500 (V4HF "BLK") (V8HF "BLK") 501 (V2SI "BLK") (V4SI "BLK") 502 (V2SF "BLK") (V4SF "BLK") 503 (DI "EI") (V2DI "EI")]) 504 505;; Similar, for four elements. 506(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") 507 (V4HI "V4HI") (V8HI "V4HI") 508 (V4HF "V4HF") (V8HF "V4HF") 509 (V2SI "V4SI") (V4SI "V4SI") 510 (V2SF "V4SF") (V4SF "V4SF") 511 (DI "OI") (V2DI "OI")]) 512 513;; Register width from element mode 514(define_mode_attr V_reg [(V8QI "P") (V16QI "q") 515 (V4HI "P") (V8HI "q") 516 (V4HF "P") (V8HF "q") 517 (V2SI "P") (V4SI "q") 518 (V2SF "P") (V4SF "q") 519 (DI "P") (V2DI "q") 520 (V2HF "") (SF "") 521 (DF "P") (HF "")]) 522 523;; Output template to select the high VFP register of a mult-register value. 524(define_mode_attr V_hi [(V2SF "p") (V4SF "f")]) 525 526;; Output template to select the low VFP register of a mult-register value. 527(define_mode_attr V_lo [(V2SF "") (V4SF "e")]) 528 529;; Helper attribute for printing output templates for awkward forms of 530;; vfmlal/vfmlsl intrinsics. 531(define_mode_attr V_lane_reg [(V2SF "") (V4SF "P")]) 532 533;; Wider modes with the same number of elements. 534(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) 535 536;; Narrower modes with the same number of elements. 537(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) 538 539;; Narrower modes with double the number of elements. 540(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") 541 (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) 542 543;; Modes with half the number of equal-sized elements. 544(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") 545 (V8HF "V4HF") (V4SI "V2SI") 546 (V4SF "V2SF") (V2DF "DF") 547 (V2DI "DI") (V4HF "HF")]) 548 549;; Same, but lower-case. 550(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") 551 (V4SI "v2si") (V4SF "v2sf") 552 (V2DI "di")]) 553 554;; Modes with twice the number of equal-sized elements. 555(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") 556 (V2SI "V4SI") (V4HF "V8HF") 557 (V2SF "V4SF") (DF "V2DF") 558 (DI "V2DI")]) 559 560;; Same, but lower-case. 561(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") 562 (V2SI "v4si") (V2SF "v4sf") 563 (DI "v2di")]) 564 565;; Modes with double-width elements. 566(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") 567 (V4HI "V2SI") (V8HI "V4SI") 568 (V2SI "DI") (V4SI "V2DI")]) 569 570;; Double-sized modes with the same element size. 571;; Used for neon_vdup_lane, where the second operand is double-sized 572;; even when the first one is quad. 573(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") 574 (V4SI "V2SI") (V4SF "V2SF") 575 (V8QI "V8QI") (V4HI "V4HI") 576 (V2SI "V2SI") (V2SF "V2SF") 577 (V8HF "V4HF") (V4HF "V4HF")]) 578 579;; Mode of result of comparison operations (and bit-select operand 1). 580(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") 581 (V4HI "V4HI") (V8HI "V8HI") 582 (V2SI "V2SI") (V4SI "V4SI") 583 (V4HF "V4HI") (V8HF "V8HI") 584 (V2SF "V2SI") (V4SF "V4SI") 585 (DI "DI") (V2DI "V2DI")]) 586 587(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") 588 (V4HI "v4hi") (V8HI "v8hi") 589 (V2SI "v2si") (V4SI "v4si") 590 (DI "di") (V2DI "v2di") 591 (V2SF "v2si") (V4SF "v4si")]) 592 593;; Get element type from double-width mode, for operations where we 594;; don't care about signedness. 595(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") 596 (V4HI "i16") (V8HI "i16") 597 (V2SI "i32") (V4SI "i32") 598 (DI "i64") (V2DI "i64") 599 (V2SF "f32") (V4SF "f32") 600 (SF "f32") (DF "f64") 601 (HF "f16") (V4HF "f16") 602 (V8HF "f16")]) 603 604;; Same, but for operations which work on signed values. 605(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") 606 (V4HI "s16") (V8HI "s16") 607 (V2SI "s32") (V4SI "s32") 608 (DI "s64") (V2DI "s64") 609 (V2SF "f32") (V4SF "f32") 610 (HF "f16") (V4HF "f16") 611 (V8HF "f16")]) 612 613;; Same, but for operations which work on unsigned values. 614(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") 615 (V4HI "u16") (V8HI "u16") 616 (V2SI "u32") (V4SI "u32") 617 (DI "u64") (V2DI "u64") 618 (V2SF "f32") (V4SF "f32")]) 619 620;; Element types for extraction of unsigned scalars. 621(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") 622 (V4HI "u16") (V8HI "u16") 623 (V2SI "32") (V4SI "32") 624 (V4HF "u16") (V8HF "u16") 625 (V2SF "32") (V4SF "32")]) 626 627(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") 628 (V4HI "16") (V8HI "16") 629 (V2SI "32") (V4SI "32") 630 (DI "64") (V2DI "64") 631 (V4HF "16") (V8HF "16") 632 (V2SF "32") (V4SF "32")]) 633 634(define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b") 635 (V4HI "h") (V8HI "h") 636 (V2SI "s") (V4SI "s") 637 (DI "d") (V2DI "d") 638 (V2SF "s") (V4SF "s") 639 (V2SF "s") (V4SF "s")]) 640 641(define_mode_attr VH_elem_ch [(V4HI "s") (V8HI "s") 642 (V4HF "s") (V8HF "s") 643 (HF "s")]) 644 645;; Element sizes for duplicating ARM registers to all elements of a vector. 646(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) 647 648;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) 649(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") 650 (V4HI "TI") (V8HI "OI") 651 (V2SI "TI") (V4SI "OI") 652 (V2SF "TI") (V4SF "OI") 653 (DI "TI") (V2DI "OI")]) 654 655;; Same, but lower-case. 656(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") 657 (V4HI "ti") (V8HI "oi") 658 (V2SI "ti") (V4SI "oi") 659 (V2SF "ti") (V4SF "oi") 660 (DI "ti") (V2DI "oi")]) 661 662;; Extra suffix on some 64-bit insn names (to avoid collision with standard 663;; names which we don't want to define). 664(define_mode_attr V_suf64 [(V8QI "") (V16QI "") 665 (V4HI "") (V8HI "") 666 (V2SI "") (V4SI "") 667 (V2SF "") (V4SF "") 668 (DI "_neon") (V2DI "")]) 669 670 671;; Scalars to be presented to scalar multiplication instructions 672;; must satisfy the following constraints. 673;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. 674;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. 675 676;; This mode attribute is used to obtain the correct register constraints. 677 678(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") 679 (V8HI "x") (V4SI "t") (V4SF "t") 680 (V8HF "x") (V4HF "x")]) 681 682;; Predicates used for setting type for neon instructions 683 684(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") 685 (V4HI "false") (V8HI "false") 686 (V2SI "false") (V4SI "false") 687 (V4HF "true") (V8HF "true") 688 (V2SF "true") (V4SF "true") 689 (DI "false") (V2DI "false")]) 690 691(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") 692 (V4HI "true") (V8HI "true") 693 (V2SI "false") (V4SI "false") 694 (V2SF "false") (V4SF "false") 695 (DI "false") (V2DI "false")]) 696 697(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") 698 (V4HI "true") (V8HI "false") 699 (V2SI "true") (V4SI "false") 700 (V2SF "true") (V4SF "false") 701 (DI "true") (V2DI "false") 702 (V4HF "true") (V8HF "false")]) 703 704(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") 705 (V4HF "4") (V8HF "8") 706 (V4HI "4") (V8HI "8") 707 (V2SI "2") (V4SI "4") 708 (V2SF "2") (V4SF "4") 709 (DI "1") (V2DI "2") 710 (DF "1") (V2DF "2")]) 711 712;; Same as V_widen, but lower-case. 713(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) 714 715;; Widen. Result is half the number of elements, but widened to double-width. 716(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) 717 718;; Conditions to be used in extend<mode>di patterns. 719(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) 720(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") 721 (QI "&& arm_arch6")]) 722(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") 723 (HI "nonimmediate_operand") 724 (QI "nonimmediate_operand")]) 725(define_mode_attr qhs_extenddi_op [(SI "s_register_operand") 726 (HI "nonimmediate_operand") 727 (QI "arm_reg_or_extendqisi_mem_op")]) 728(define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")]) 729(define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")]) 730 731;; Mode attributes used for fixed-point support. 732(define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") 733 (V2UHA "16") (UHA "16") 734 (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") 735 (V2HA "16") (HA "16") (SQ "") (SA "")]) 736 737;; Mode attribute for vshll. 738(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) 739 740;; Mode attributes used for VFP support. 741(define_mode_attr F_constraint [(SF "t") (DF "w")]) 742(define_mode_attr vfp_type [(SF "s") (DF "d")]) 743(define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) 744(define_mode_attr VF_constraint [(V2SF "t") (V4SF "w")]) 745 746;; Mode attribute used to build the "type" attribute. 747(define_mode_attr q [(V8QI "") (V16QI "_q") 748 (V4HI "") (V8HI "_q") 749 (V2SI "") (V4SI "_q") 750 (V4HF "") (V8HF "_q") 751 (V2SF "") (V4SF "_q") 752 (V4HF "") (V8HF "_q") 753 (DI "") (V2DI "_q") 754 (DF "") (V2DF "_q") 755 (HF "")]) 756 757(define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")]) 758 759(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) 760(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) 761 762;;---------------------------------------------------------------------------- 763;; Code attributes 764;;---------------------------------------------------------------------------- 765 766;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. 767(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") 768 (umin "vmin") (umax "vmax")]) 769 770;; Type attributes for vqh_ops and vqhs_ops iterators. 771(define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") 772 (umin "minmax") (umax "minmax")]) 773 774;; Signs of above, where relevant. 775(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") 776 (umax "u")]) 777 778(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) 779(define_code_attr optab [(ltu "ltu") (geu "geu")]) 780 781;; Assembler mnemonics for signedness of widening operations. 782(define_code_attr US [(sign_extend "s") (zero_extend "u")]) 783 784;; Signedness suffix for float->fixed conversions. Empty for signed 785;; conversion. 786(define_code_attr su_optab [(fix "") (unsigned_fix "u")]) 787 788;; Sign prefix to use in instruction type suffixes, i.e. s32, u32. 789(define_code_attr su [(fix "s") (unsigned_fix "u")]) 790 791;; Right shifts 792(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) 793(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) 794 795;; String reprentations of operations on the sign of a number. 796(define_code_attr absneg_str [(abs "abs") (neg "neg")]) 797 798;; Conversions. 799(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")]) 800 801(define_code_attr float_sup [(unsigned_float "u") (float "s")]) 802 803(define_code_attr float_SUP [(unsigned_float "U") (float "S")]) 804 805;;---------------------------------------------------------------------------- 806;; Int attributes 807;;---------------------------------------------------------------------------- 808 809;; Mapping between vector UNSPEC operations and the signed ('s'), 810;; unsigned ('u'), poly ('p') or float ('f') nature of their data type. 811(define_int_attr sup [ 812 (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u") 813 (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u") 814 (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u") 815 (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u") 816 (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u") 817 (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u") 818 (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u") 819 (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u") 820 (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u") 821 (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p") 822 (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u") 823 (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u") 824 (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u") 825 (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u") 826 (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u") 827 (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u") 828 (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u") 829 (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u") 830 (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u") 831 (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u") 832 (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u") 833 (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u") 834 (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u") 835 (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u") 836 (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u") 837 (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u") 838 (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u") 839 (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u") 840 (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u") 841 (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u") 842 (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u") 843 (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u") 844 (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u") 845 (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u") 846 (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u") 847 (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u") 848 (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u") 849 (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u") 850 (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u") 851 (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u") 852 (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u") 853 (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u") 854 (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u") 855 (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u") 856 (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u") 857 (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u") 858 (UNSPEC_DOT_S "s") (UNSPEC_DOT_U "u") 859]) 860 861(define_int_attr vfml_half 862 [(UNSPEC_VFML_HI "high") (UNSPEC_VFML_LO "low")]) 863 864(define_int_attr vfml_half_selector 865 [(UNSPEC_VFML_HI "true") (UNSPEC_VFML_LO "false")]) 866 867(define_int_attr vcvth_op 868 [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a") 869 (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m") 870 (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n") 871 (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")]) 872 873(define_int_attr fp16_rnd_str 874 [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda") 875 (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn") 876 (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")]) 877 878(define_int_attr fp16_rnd_insn 879 [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta") 880 (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn") 881 (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")]) 882 883(define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt") 884 (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le") 885 (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge") 886 (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le") 887 (UNSPEC_VCALT "lt")]) 888 889(define_int_attr r [ 890 (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r") 891 (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "") 892 (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r") 893 (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r") 894 (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r") 895 (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r") 896]) 897 898(define_int_attr maxmin [ 899 (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max") 900 (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min") 901 (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max") 902 (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min") 903]) 904 905(define_int_attr fmaxmin [ 906 (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")]) 907 908(define_int_attr fmaxmin_op [ 909 (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm") 910]) 911 912(define_int_attr shift_op [ 913 (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl") 914 (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl") 915 (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl") 916 (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl") 917 (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr") 918 (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr") 919 (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn") 920 (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn") 921 (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn") 922 (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun") 923 (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra") 924 (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra") 925]) 926 927;; Standard names for floating point to integral rounding instructions. 928(define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") 929 (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") 930 (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) 931 932;; Suffixes for vrint instructions specifying rounding modes. 933(define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") 934 (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") 935 (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) 936 937;; Some of the vrint instuctions are predicable. 938(define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") 939 (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") 940 (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) 941 942(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") 943 (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") 944 (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) 945 946(define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") 947 (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") 948 (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) 949 950(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") 951 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb") 952 (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")]) 953 954(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") 955 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI") 956 (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")]) 957 958(define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc") 959 (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd") 960 (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1") 961 (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c") 962 (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p") 963 (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h") 964 (UNSPEC_SHA256H2 "sha256h2") 965 (UNSPEC_SHA256SU1 "sha256su1")]) 966 967(define_int_attr crypto_type 968 [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") 969 (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") 970 (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") 971 (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") 972 (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") 973 (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast") 974 (UNSPEC_SHA256SU1 "crypto_sha256_slow")]) 975 976(define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8") 977 (UNSPEC_AESIMC "8") (UNSPEC_AESD "8") 978 (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32") 979 (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32") 980 (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32") 981 (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32") 982 (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")]) 983 984(define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI") 985 (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI") 986 (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI") 987 (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI") 988 (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI") 989 (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI") 990 (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) 991 992;; Both kinds of return insn. 993(define_code_iterator RETURNS [return simple_return]) 994(define_code_attr return_str [(return "") (simple_return "simple_")]) 995(define_code_attr return_simple_p [(return "false") (simple_return "true")]) 996(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") 997 (simple_return " && use_simple_return_p ()")]) 998(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") 999 (simple_return " && use_simple_return_p ()")]) 1000 1001;; Attributes for VQRDMLAH/VQRDMLSH 1002(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")]) 1003 1004;; Attributes for VFMA_LANE/ VFMS_LANE 1005(define_int_attr neon_vfm_lane_as 1006 [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")]) 1007 1008;; An iterator for the CDP coprocessor instructions 1009(define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2]) 1010(define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")]) 1011(define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")]) 1012 1013;; An iterator for the LDC coprocessor instruction 1014(define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2 1015 VUNSPEC_LDCL VUNSPEC_LDC2L]) 1016(define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2") 1017 (VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")]) 1018(define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2") 1019 (VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")]) 1020 1021;; An iterator for the STC coprocessor instructions 1022(define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2 1023 VUNSPEC_STCL VUNSPEC_STC2L]) 1024(define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2") 1025 (VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")]) 1026(define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2") 1027 (VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")]) 1028 1029;; An iterator for the MCR coprocessor instructions 1030(define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2]) 1031 1032(define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")]) 1033(define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")]) 1034 1035;; An iterator for the MRC coprocessor instructions 1036(define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2]) 1037 1038(define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")]) 1039(define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")]) 1040 1041;; An iterator for the MCRR coprocessor instructions 1042(define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2]) 1043 1044(define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")]) 1045(define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")]) 1046 1047;; An iterator for the MRRC coprocessor instructions 1048(define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2]) 1049 1050(define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")]) 1051(define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")]) 1052 1053(define_int_attr opsuffix [(UNSPEC_DOT_S "s8") 1054 (UNSPEC_DOT_U "u8")]) 1055