1 /* Intrinsic definitions of Andes NDS32 cpu for GNU compiler 2 Copyright (C) 2012-2018 Free Software Foundation, Inc. 3 Contributed by Andes Technology Corporation. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 Under Section 7 of GPL version 3, you are granted additional 18 permissions described in the GCC Runtime Library Exception, version 19 3.1, as published by the Free Software Foundation. 20 21 You should have received a copy of the GNU General Public License and 22 a copy of the GCC Runtime Library Exception along with this program; 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 <http://www.gnu.org/licenses/>. */ 25 26 #ifndef _NDS32_INTRINSIC_H 27 #define _NDS32_INTRINSIC_H 28 29 /* General instrinsic register names. */ 30 enum nds32_intrinsic_registers 31 { 32 __NDS32_REG_CPU_VER__ = 1024, 33 __NDS32_REG_ICM_CFG__, 34 __NDS32_REG_DCM_CFG__, 35 __NDS32_REG_MMU_CFG__, 36 __NDS32_REG_MSC_CFG__, 37 __NDS32_REG_MSC_CFG2__, 38 __NDS32_REG_CORE_ID__, 39 __NDS32_REG_FUCOP_EXIST__, 40 41 __NDS32_REG_PSW__, 42 __NDS32_REG_IPSW__, 43 __NDS32_REG_P_IPSW__, 44 __NDS32_REG_IVB__, 45 __NDS32_REG_EVA__, 46 __NDS32_REG_P_EVA__, 47 __NDS32_REG_ITYPE__, 48 __NDS32_REG_P_ITYPE__, 49 50 __NDS32_REG_MERR__, 51 __NDS32_REG_IPC__, 52 __NDS32_REG_P_IPC__, 53 __NDS32_REG_OIPC__, 54 __NDS32_REG_P_P0__, 55 __NDS32_REG_P_P1__, 56 57 __NDS32_REG_INT_MASK__, 58 __NDS32_REG_INT_MASK2__, 59 __NDS32_REG_INT_MASK3__, 60 __NDS32_REG_INT_PEND__, 61 __NDS32_REG_INT_PEND2__, 62 __NDS32_REG_INT_PEND3__, 63 __NDS32_REG_SP_USR__, 64 __NDS32_REG_SP_PRIV__, 65 __NDS32_REG_INT_PRI__, 66 __NDS32_REG_INT_PRI2__, 67 __NDS32_REG_INT_PRI3__, 68 __NDS32_REG_INT_PRI4__, 69 __NDS32_REG_INT_CTRL__, 70 __NDS32_REG_INT_TRIGGER__, 71 __NDS32_REG_INT_TRIGGER2__, 72 __NDS32_REG_INT_GPR_PUSH_DIS__, 73 74 __NDS32_REG_MMU_CTL__, 75 __NDS32_REG_L1_PPTB__, 76 __NDS32_REG_TLB_VPN__, 77 __NDS32_REG_TLB_DATA__, 78 __NDS32_REG_TLB_MISC__, 79 __NDS32_REG_VLPT_IDX__, 80 __NDS32_REG_ILMB__, 81 __NDS32_REG_DLMB__, 82 83 __NDS32_REG_CACHE_CTL__, 84 __NDS32_REG_HSMP_SADDR__, 85 __NDS32_REG_HSMP_EADDR__, 86 __NDS32_REG_SDZ_CTL__, 87 __NDS32_REG_N12MISC_CTL__, 88 __NDS32_REG_MISC_CTL__, 89 __NDS32_REG_ECC_MISC__, 90 91 __NDS32_REG_BPC0__, 92 __NDS32_REG_BPC1__, 93 __NDS32_REG_BPC2__, 94 __NDS32_REG_BPC3__, 95 __NDS32_REG_BPC4__, 96 __NDS32_REG_BPC5__, 97 __NDS32_REG_BPC6__, 98 __NDS32_REG_BPC7__, 99 100 __NDS32_REG_BPA0__, 101 __NDS32_REG_BPA1__, 102 __NDS32_REG_BPA2__, 103 __NDS32_REG_BPA3__, 104 __NDS32_REG_BPA4__, 105 __NDS32_REG_BPA5__, 106 __NDS32_REG_BPA6__, 107 __NDS32_REG_BPA7__, 108 109 __NDS32_REG_BPAM0__, 110 __NDS32_REG_BPAM1__, 111 __NDS32_REG_BPAM2__, 112 __NDS32_REG_BPAM3__, 113 __NDS32_REG_BPAM4__, 114 __NDS32_REG_BPAM5__, 115 __NDS32_REG_BPAM6__, 116 __NDS32_REG_BPAM7__, 117 118 __NDS32_REG_BPV0__, 119 __NDS32_REG_BPV1__, 120 __NDS32_REG_BPV2__, 121 __NDS32_REG_BPV3__, 122 __NDS32_REG_BPV4__, 123 __NDS32_REG_BPV5__, 124 __NDS32_REG_BPV6__, 125 __NDS32_REG_BPV7__, 126 127 __NDS32_REG_BPCID0__, 128 __NDS32_REG_BPCID1__, 129 __NDS32_REG_BPCID2__, 130 __NDS32_REG_BPCID3__, 131 __NDS32_REG_BPCID4__, 132 __NDS32_REG_BPCID5__, 133 __NDS32_REG_BPCID6__, 134 __NDS32_REG_BPCID7__, 135 136 __NDS32_REG_EDM_CFG__, 137 __NDS32_REG_EDMSW__, 138 __NDS32_REG_EDM_CTL__, 139 __NDS32_REG_EDM_DTR__, 140 __NDS32_REG_BPMTC__, 141 __NDS32_REG_DIMBR__, 142 143 __NDS32_REG_TECR0__, 144 __NDS32_REG_TECR1__, 145 __NDS32_REG_PFMC0__, 146 __NDS32_REG_PFMC1__, 147 __NDS32_REG_PFMC2__, 148 __NDS32_REG_PFM_CTL__, 149 __NDS32_REG_PFT_CTL__, 150 __NDS32_REG_HSP_CTL__, 151 __NDS32_REG_SP_BOUND__, 152 __NDS32_REG_SP_BOUND_PRIV__, 153 __NDS32_REG_SP_BASE__, 154 __NDS32_REG_SP_BASE_PRIV__, 155 __NDS32_REG_FUCOP_CTL__, 156 __NDS32_REG_PRUSR_ACC_CTL__, 157 158 __NDS32_REG_DMA_CFG__, 159 __NDS32_REG_DMA_GCSW__, 160 __NDS32_REG_DMA_CHNSEL__, 161 __NDS32_REG_DMA_ACT__, 162 __NDS32_REG_DMA_SETUP__, 163 __NDS32_REG_DMA_ISADDR__, 164 __NDS32_REG_DMA_ESADDR__, 165 __NDS32_REG_DMA_TCNT__, 166 __NDS32_REG_DMA_STATUS__, 167 __NDS32_REG_DMA_2DSET__, 168 __NDS32_REG_DMA_2DSCTL__, 169 __NDS32_REG_DMA_RCNT__, 170 __NDS32_REG_DMA_HSTATUS__, 171 172 __NDS32_REG_PC__, 173 __NDS32_REG_SP_USR1__, 174 __NDS32_REG_SP_USR2__, 175 __NDS32_REG_SP_USR3__, 176 __NDS32_REG_SP_PRIV1__, 177 __NDS32_REG_SP_PRIV2__, 178 __NDS32_REG_SP_PRIV3__, 179 __NDS32_REG_BG_REGION__, 180 __NDS32_REG_SFCR__, 181 __NDS32_REG_SIGN__, 182 __NDS32_REG_ISIGN__, 183 __NDS32_REG_P_ISIGN__, 184 __NDS32_REG_IFC_LP__, 185 __NDS32_REG_ITB__ 186 }; 187 188 /* The cctl subtype for intrinsic. */ 189 enum nds32_cctl_valck 190 { 191 __NDS32_CCTL_L1D_VA_FILLCK__, 192 __NDS32_CCTL_L1D_VA_ULCK__, 193 __NDS32_CCTL_L1I_VA_FILLCK__, 194 __NDS32_CCTL_L1I_VA_ULCK__ 195 }; 196 197 enum nds32_cctl_idxwbinv 198 { 199 __NDS32_CCTL_L1D_IX_WBINVAL__, 200 __NDS32_CCTL_L1D_IX_INVAL__, 201 __NDS32_CCTL_L1D_IX_WB__, 202 __NDS32_CCTL_L1I_IX_INVAL__ 203 }; 204 205 enum nds32_cctl_vawbinv 206 { 207 __NDS32_CCTL_L1D_VA_INVAL__, 208 __NDS32_CCTL_L1D_VA_WB__, 209 __NDS32_CCTL_L1D_VA_WBINVAL__, 210 __NDS32_CCTL_L1I_VA_INVAL__ 211 }; 212 213 enum nds32_cctl_idxread 214 { 215 __NDS32_CCTL_L1D_IX_RTAG__, 216 __NDS32_CCTL_L1D_IX_RWD__, 217 __NDS32_CCTL_L1I_IX_RTAG__, 218 __NDS32_CCTL_L1I_IX_RWD__ 219 }; 220 221 enum nds32_cctl_idxwrite 222 { 223 __NDS32_CCTL_L1D_IX_WTAG__, 224 __NDS32_CCTL_L1D_IX_WWD__, 225 __NDS32_CCTL_L1I_IX_WTAG__, 226 __NDS32_CCTL_L1I_IX_WWD__ 227 }; 228 229 enum nds32_dpref 230 { 231 __NDS32_DPREF_SRD__, 232 __NDS32_DPREF_MRD__, 233 __NDS32_DPREF_SWR__, 234 __NDS32_DPREF_MWR__, 235 __NDS32_DPREF_PTE__, 236 __NDS32_DPREF_CLWR__ 237 }; 238 239 /* ------------------------------------------------------------------------ */ 240 241 /* Define interrupt number for intrinsic function. */ 242 #define NDS32_INT_H0 0 243 #define NDS32_INT_H1 1 244 #define NDS32_INT_H2 2 245 #define NDS32_INT_H3 3 246 #define NDS32_INT_H4 4 247 #define NDS32_INT_H5 5 248 #define NDS32_INT_H6 6 249 #define NDS32_INT_H7 7 250 #define NDS32_INT_H8 8 251 #define NDS32_INT_H9 9 252 #define NDS32_INT_H10 10 253 #define NDS32_INT_H11 11 254 #define NDS32_INT_H12 12 255 #define NDS32_INT_H13 13 256 #define NDS32_INT_H14 14 257 #define NDS32_INT_H15 15 258 #define NDS32_INT_H16 16 259 #define NDS32_INT_H17 17 260 #define NDS32_INT_H18 18 261 #define NDS32_INT_H19 19 262 #define NDS32_INT_H20 20 263 #define NDS32_INT_H21 21 264 #define NDS32_INT_H22 22 265 #define NDS32_INT_H23 23 266 #define NDS32_INT_H24 24 267 #define NDS32_INT_H25 25 268 #define NDS32_INT_H26 26 269 #define NDS32_INT_H27 27 270 #define NDS32_INT_H28 28 271 #define NDS32_INT_H29 29 272 #define NDS32_INT_H30 30 273 #define NDS32_INT_H31 31 274 #define NDS32_INT_H32 32 275 #define NDS32_INT_H33 33 276 #define NDS32_INT_H34 34 277 #define NDS32_INT_H35 35 278 #define NDS32_INT_H36 36 279 #define NDS32_INT_H37 37 280 #define NDS32_INT_H38 38 281 #define NDS32_INT_H39 39 282 #define NDS32_INT_H40 40 283 #define NDS32_INT_H41 41 284 #define NDS32_INT_H42 42 285 #define NDS32_INT_H43 43 286 #define NDS32_INT_H44 44 287 #define NDS32_INT_H45 45 288 #define NDS32_INT_H46 46 289 #define NDS32_INT_H47 47 290 #define NDS32_INT_H48 48 291 #define NDS32_INT_H49 49 292 #define NDS32_INT_H50 50 293 #define NDS32_INT_H51 51 294 #define NDS32_INT_H52 52 295 #define NDS32_INT_H53 53 296 #define NDS32_INT_H54 54 297 #define NDS32_INT_H55 55 298 #define NDS32_INT_H56 56 299 #define NDS32_INT_H57 57 300 #define NDS32_INT_H58 58 301 #define NDS32_INT_H59 59 302 #define NDS32_INT_H60 60 303 #define NDS32_INT_H61 61 304 #define NDS32_INT_H62 62 305 #define NDS32_INT_H63 63 306 #define NDS32_INT_SWI 64 307 #define NDS32_INT_ALZ 65 308 #define NDS32_INT_IDIVZE 66 309 #define NDS32_INT_DSSIM 67 310 311 /* ------------------------------------------------------------------------ */ 312 313 /* Define intrinsic register name macro for compatibility. */ 314 #define NDS32_SR_CPU_VER __NDS32_REG_CPU_VER__ 315 #define NDS32_SR_ICM_CFG __NDS32_REG_ICM_CFG__ 316 #define NDS32_SR_DCM_CFG __NDS32_REG_DCM_CFG__ 317 #define NDS32_SR_MMU_CFG __NDS32_REG_MMU_CFG__ 318 #define NDS32_SR_MSC_CFG __NDS32_REG_MSC_CFG__ 319 #define NDS32_SR_MSC_CFG2 __NDS32_REG_MSC_CFG2__ 320 #define NDS32_SR_CORE_ID __NDS32_REG_CORE_ID__ 321 #define NDS32_SR_FUCOP_EXIST __NDS32_REG_FUCOP_EXIST__ 322 #define NDS32_SR_PSW __NDS32_REG_PSW__ 323 #define NDS32_SR_IPSW __NDS32_REG_IPSW__ 324 #define NDS32_SR_P_IPSW __NDS32_REG_P_IPSW__ 325 #define NDS32_SR_IVB __NDS32_REG_IVB__ 326 #define NDS32_SR_EVA __NDS32_REG_EVA__ 327 #define NDS32_SR_P_EVA __NDS32_REG_P_EVA__ 328 #define NDS32_SR_ITYPE __NDS32_REG_ITYPE__ 329 #define NDS32_SR_P_ITYPE __NDS32_REG_P_ITYPE__ 330 #define NDS32_SR_MERR __NDS32_REG_MERR__ 331 #define NDS32_SR_IPC __NDS32_REG_IPC__ 332 #define NDS32_SR_P_IPC __NDS32_REG_P_IPC__ 333 #define NDS32_SR_OIPC __NDS32_REG_OIPC__ 334 #define NDS32_SR_P_P0 __NDS32_REG_P_P0__ 335 #define NDS32_SR_P_P1 __NDS32_REG_P_P1__ 336 #define NDS32_SR_INT_MASK __NDS32_REG_INT_MASK__ 337 #define NDS32_SR_INT_MASK2 __NDS32_REG_INT_MASK2__ 338 #define NDS32_SR_INT_MASK3 __NDS32_REG_INT_MASK3__ 339 #define NDS32_SR_INT_PEND __NDS32_REG_INT_PEND__ 340 #define NDS32_SR_INT_PEND2 __NDS32_REG_INT_PEND2__ 341 #define NDS32_SR_INT_PEND3 __NDS32_REG_INT_PEND3__ 342 #define NDS32_SR_SP_USR __NDS32_REG_SP_USR__ 343 #define NDS32_SR_SP_PRIV __NDS32_REG_SP_PRIV__ 344 #define NDS32_SR_INT_PRI __NDS32_REG_INT_PRI__ 345 #define NDS32_SR_INT_PRI2 __NDS32_REG_INT_PRI2__ 346 #define NDS32_SR_INT_PRI3 __NDS32_REG_INT_PRI3__ 347 #define NDS32_SR_INT_PRI4 __NDS32_REG_INT_PRI4__ 348 #define NDS32_SR_INT_CTRL __NDS32_REG_INT_CTRL__ 349 #define NDS32_SR_INT_TRIGGER __NDS32_REG_INT_TRIGGER__ 350 #define NDS32_SR_INT_TRIGGER2 __NDS32_REG_INT_TRIGGER2__ 351 #define NDS32_SR_INT_GPR_PUSH_DIS __NDS32_REG_INT_GPR_PUSH_DIS__ 352 #define NDS32_SR_MMU_CTL __NDS32_REG_MMU_CTL__ 353 #define NDS32_SR_L1_PPTB __NDS32_REG_L1_PPTB__ 354 #define NDS32_SR_TLB_VPN __NDS32_REG_TLB_VPN__ 355 #define NDS32_SR_TLB_DATA __NDS32_REG_TLB_DATA__ 356 #define NDS32_SR_TLB_MISC __NDS32_REG_TLB_MISC__ 357 #define NDS32_SR_VLPT_IDX __NDS32_REG_VLPT_IDX__ 358 #define NDS32_SR_ILMB __NDS32_REG_ILMB__ 359 #define NDS32_SR_DLMB __NDS32_REG_DLMB__ 360 #define NDS32_SR_CACHE_CTL __NDS32_REG_CACHE_CTL__ 361 #define NDS32_SR_HSMP_SADDR __NDS32_REG_HSMP_SADDR__ 362 #define NDS32_SR_HSMP_EADDR __NDS32_REG_HSMP_EADDR__ 363 #define NDS32_SR_SDZ_CTL __NDS32_REG_SDZ_CTL__ 364 #define NDS32_SR_N12MISC_CTL __NDS32_REG_N12MISC_CTL__ 365 #define NDS32_SR_MISC_CTL __NDS32_REG_MISC_CTL__ 366 #define NDS32_SR_ECC_MISC __NDS32_REG_ECC_MISC__ 367 #define NDS32_SR_BPC0 __NDS32_REG_BPC0__ 368 #define NDS32_SR_BPC1 __NDS32_REG_BPC1__ 369 #define NDS32_SR_BPC2 __NDS32_REG_BPC2__ 370 #define NDS32_SR_BPC3 __NDS32_REG_BPC3__ 371 #define NDS32_SR_BPC4 __NDS32_REG_BPC4__ 372 #define NDS32_SR_BPC5 __NDS32_REG_BPC5__ 373 #define NDS32_SR_BPC6 __NDS32_REG_BPC6__ 374 #define NDS32_SR_BPC7 __NDS32_REG_BPC7__ 375 #define NDS32_SR_BPA0 __NDS32_REG_BPA0__ 376 #define NDS32_SR_BPA1 __NDS32_REG_BPA1__ 377 #define NDS32_SR_BPA2 __NDS32_REG_BPA2__ 378 #define NDS32_SR_BPA3 __NDS32_REG_BPA3__ 379 #define NDS32_SR_BPA4 __NDS32_REG_BPA4__ 380 #define NDS32_SR_BPA5 __NDS32_REG_BPA5__ 381 #define NDS32_SR_BPA6 __NDS32_REG_BPA6__ 382 #define NDS32_SR_BPA7 __NDS32_REG_BPA7__ 383 #define NDS32_SR_BPAM0 __NDS32_REG_BPAM0__ 384 #define NDS32_SR_BPAM1 __NDS32_REG_BPAM1__ 385 #define NDS32_SR_BPAM2 __NDS32_REG_BPAM2__ 386 #define NDS32_SR_BPAM3 __NDS32_REG_BPAM3__ 387 #define NDS32_SR_BPAM4 __NDS32_REG_BPAM4__ 388 #define NDS32_SR_BPAM5 __NDS32_REG_BPAM5__ 389 #define NDS32_SR_BPAM6 __NDS32_REG_BPAM6__ 390 #define NDS32_SR_BPAM7 __NDS32_REG_BPAM7__ 391 #define NDS32_SR_BPV0 __NDS32_REG_BPV0__ 392 #define NDS32_SR_BPV1 __NDS32_REG_BPV1__ 393 #define NDS32_SR_BPV2 __NDS32_REG_BPV2__ 394 #define NDS32_SR_BPV3 __NDS32_REG_BPV3__ 395 #define NDS32_SR_BPV4 __NDS32_REG_BPV4__ 396 #define NDS32_SR_BPV5 __NDS32_REG_BPV5__ 397 #define NDS32_SR_BPV6 __NDS32_REG_BPV6__ 398 #define NDS32_SR_BPV7 __NDS32_REG_BPV7__ 399 #define NDS32_SR_BPCID0 __NDS32_REG_BPCID0__ 400 #define NDS32_SR_BPCID1 __NDS32_REG_BPCID1__ 401 #define NDS32_SR_BPCID2 __NDS32_REG_BPCID2__ 402 #define NDS32_SR_BPCID3 __NDS32_REG_BPCID3__ 403 #define NDS32_SR_BPCID4 __NDS32_REG_BPCID4__ 404 #define NDS32_SR_BPCID5 __NDS32_REG_BPCID5__ 405 #define NDS32_SR_BPCID6 __NDS32_REG_BPCID6__ 406 #define NDS32_SR_BPCID7 __NDS32_REG_BPCID7__ 407 #define NDS32_SR_EDM_CFG __NDS32_REG_EDM_CFG__ 408 #define NDS32_SR_EDMSW __NDS32_REG_EDMSW__ 409 #define NDS32_SR_EDM_CTL __NDS32_REG_EDM_CTL__ 410 #define NDS32_SR_EDM_DTR __NDS32_REG_EDM_DTR__ 411 #define NDS32_SR_BPMTC __NDS32_REG_BPMTC__ 412 #define NDS32_SR_DIMBR __NDS32_REG_DIMBR__ 413 #define NDS32_SR_TECR0 __NDS32_REG_TECR0__ 414 #define NDS32_SR_TECR1 __NDS32_REG_TECR1__ 415 #define NDS32_SR_PFMC0 __NDS32_REG_PFMC0__ 416 #define NDS32_SR_PFMC1 __NDS32_REG_PFMC1__ 417 #define NDS32_SR_PFMC2 __NDS32_REG_PFMC2__ 418 #define NDS32_SR_PFM_CTL __NDS32_REG_PFM_CTL__ 419 #define NDS32_SR_HSP_CTL __NDS32_REG_HSP_CTL__ 420 #define NDS32_SR_SP_BOUND __NDS32_REG_SP_BOUND__ 421 #define NDS32_SR_SP_BOUND_PRIV __NDS32_REG_SP_BOUND_PRIV__ 422 #define NDS32_SR_SP_BASE __NDS32_REG_SP_BASE__ 423 #define NDS32_SR_SP_BASE_PRIV __NDS32_REG_SP_BASE_PRIV__ 424 #define NDS32_SR_FUCOP_CTL __NDS32_REG_FUCOP_CTL__ 425 #define NDS32_SR_PRUSR_ACC_CTL __NDS32_REG_PRUSR_ACC_CTL__ 426 #define NDS32_SR_DMA_CFG __NDS32_REG_DMA_CFG__ 427 #define NDS32_SR_DMA_GCSW __NDS32_REG_DMA_GCSW__ 428 #define NDS32_SR_DMA_CHNSEL __NDS32_REG_DMA_CHNSEL__ 429 #define NDS32_SR_DMA_ACT __NDS32_REG_DMA_ACT__ 430 #define NDS32_SR_DMA_SETUP __NDS32_REG_DMA_SETUP__ 431 #define NDS32_SR_DMA_ISADDR __NDS32_REG_DMA_ISADDR__ 432 #define NDS32_SR_DMA_ESADDR __NDS32_REG_DMA_ESADDR__ 433 #define NDS32_SR_DMA_TCNT __NDS32_REG_DMA_TCNT__ 434 #define NDS32_SR_DMA_STATUS __NDS32_REG_DMA_STATUS__ 435 #define NDS32_SR_DMA_2DSET __NDS32_REG_DMA_2DSET__ 436 #define NDS32_SR_DMA_2DSCTL __NDS32_REG_DMA_2DSCTL__ 437 #define NDS32_SR_DMA_RCNT __NDS32_REG_DMA_RCNT__ 438 #define NDS32_SR_DMA_HSTATUS __NDS32_REG_DMA_HSTATUS__ 439 #define NDS32_SR_SP_USR1 __NDS32_REG_SP_USR1__ 440 #define NDS32_SR_SP_USR2 __NDS32_REG_SP_USR2__ 441 #define NDS32_SR_SP_USR3 __NDS32_REG_SP_USR3__ 442 #define NDS32_SR_SP_PRIV1 __NDS32_REG_SP_PRIV1__ 443 #define NDS32_SR_SP_PRIV2 __NDS32_REG_SP_PRIV2__ 444 #define NDS32_SR_SP_PRIV3 __NDS32_REG_SP_PRIV3__ 445 #define NDS32_SR_BG_REGION __NDS32_REG_BG_REGION__ 446 #define NDS32_SR_SFCR __NDS32_REG_SFCR__ 447 #define NDS32_SR_SIGN __NDS32_REG_SIGN__ 448 #define NDS32_SR_ISIGN __NDS32_REG_ISIGN__ 449 #define NDS32_SR_P_ISIGN __NDS32_REG_P_ISIGN__ 450 451 #define NDS32_USR_PC __NDS32_REG_PC__ 452 #define NDS32_USR_DMA_CFG __NDS32_REG_DMA_CFG__ 453 #define NDS32_USR_DMA_GCSW __NDS32_REG_DMA_GCSW__ 454 #define NDS32_USR_DMA_CHNSEL __NDS32_REG_DMA_CHNSEL__ 455 #define NDS32_USR_DMA_ACT __NDS32_REG_DMA_ACT__ 456 #define NDS32_USR_DMA_SETUP __NDS32_REG_DMA_SETUP__ 457 #define NDS32_USR_DMA_ISADDR __NDS32_REG_DMA_ISADDR__ 458 #define NDS32_USR_DMA_ESADDR __NDS32_REG_DMA_ESADDR__ 459 #define NDS32_USR_DMA_TCNT __NDS32_REG_DMA_TCNT__ 460 #define NDS32_USR_DMA_STATUS __NDS32_REG_DMA_STATUS__ 461 #define NDS32_USR_DMA_2DSET __NDS32_REG_DMA_2DSET__ 462 #define NDS32_USR_DMA_2DSCTL __NDS32_REG_DMA_2DSCTL__ 463 #define NDS32_USR_PFMC0 __NDS32_REG_PFMC0__ 464 #define NDS32_USR_PFMC1 __NDS32_REG_PFMC1__ 465 #define NDS32_USR_PFMC2 __NDS32_REG_PFMC2__ 466 #define NDS32_USR_PFM_CTL __NDS32_REG_PFM_CTL__ 467 #define NDS32_USR_IFC_LP __NDS32_REG_IFC_LP__ 468 #define NDS32_USR_ITB __NDS32_REG_ITB__ 469 470 #define NDS32_CCTL_L1D_VA_FILLCK __NDS32_CCTL_L1D_VA_FILLCK__ 471 #define NDS32_CCTL_L1D_VA_ULCK __NDS32_CCTL_L1D_VA_ULCK__ 472 #define NDS32_CCTL_L1I_VA_FILLCK __NDS32_CCTL_L1I_VA_FILLCK__ 473 #define NDS32_CCTL_L1I_VA_ULCK __NDS32_CCTL_L1I_VA_ULCK__ 474 475 #define NDS32_CCTL_L1D_IX_WBINVAL __NDS32_CCTL_L1D_IX_WBINVAL__ 476 #define NDS32_CCTL_L1D_IX_INVAL __NDS32_CCTL_L1D_IX_INVAL__ 477 #define NDS32_CCTL_L1D_IX_WB __NDS32_CCTL_L1D_IX_WB__ 478 #define NDS32_CCTL_L1I_IX_INVAL __NDS32_CCTL_L1I_IX_INVAL__ 479 480 #define NDS32_CCTL_L1D_VA_INVAL __NDS32_CCTL_L1D_VA_INVAL__ 481 #define NDS32_CCTL_L1D_VA_WB __NDS32_CCTL_L1D_VA_WB__ 482 #define NDS32_CCTL_L1D_VA_WBINVAL __NDS32_CCTL_L1D_VA_WBINVAL__ 483 #define NDS32_CCTL_L1I_VA_INVAL __NDS32_CCTL_L1I_VA_INVAL__ 484 485 #define NDS32_CCTL_L1D_IX_RTAG __NDS32_CCTL_L1D_IX_RTAG__ 486 #define NDS32_CCTL_L1D_IX_RWD __NDS32_CCTL_L1D_IX_RWD__ 487 #define NDS32_CCTL_L1I_IX_RTAG __NDS32_CCTL_L1I_IX_RTAG__ 488 #define NDS32_CCTL_L1I_IX_RWD __NDS32_CCTL_L1I_IX_RWD__ 489 490 #define NDS32_CCTL_L1D_IX_WTAG __NDS32_CCTL_L1D_IX_WTAG__ 491 #define NDS32_CCTL_L1D_IX_WWD __NDS32_CCTL_L1D_IX_WWD__ 492 #define NDS32_CCTL_L1I_IX_WTAG __NDS32_CCTL_L1I_IX_WTAG__ 493 #define NDS32_CCTL_L1I_IX_WWD __NDS32_CCTL_L1I_IX_WWD__ 494 495 #define NDS32_DPREF_SRD __NDS32_DPREF_SRD__ 496 #define NDS32_DPREF_MRD __NDS32_DPREF_MRD__ 497 #define NDS32_DPREF_SWR __NDS32_DPREF_SWR__ 498 #define NDS32_DPREF_MWR __NDS32_DPREF_MWR__ 499 #define NDS32_DPREF_PTE __NDS32_DPREF_PTE__ 500 #define NDS32_DPREF_CLWR __NDS32_DPREF_CLWR__ 501 502 /* ------------------------------------------------------------------------ */ 503 504 505 /* Map __nds32__xxx() to __builtin_xxx() functions for compatibility. */ 506 #define __nds32__llw(a) \ 507 (__builtin_nds32_llw ((a))) 508 #define __nds32__lwup(a) \ 509 (__builtin_nds32_lwup ((a))) 510 #define __nds32__lbup(a) \ 511 (__builtin_nds32_lbup ((a))) 512 #define __nds32__scw(a, b) \ 513 (__builtin_nds32_scw ((a), (b))) 514 #define __nds32__swup(a, b) \ 515 (__builtin_nds32_swup ((a), (b))) 516 #define __nds32__sbup(a, b) \ 517 (__builtin_nds32_sbup ((a), (b))) 518 519 #define __nds32__mfsr(srname) \ 520 (__builtin_nds32_mfsr ((srname))) 521 #define __nds32__mfusr(usrname) \ 522 (__builtin_nds32_mfusr ((usrname))) 523 #define __nds32__mtsr(val, srname) \ 524 (__builtin_nds32_mtsr ((val), (srname))) 525 #define __nds32__mtsr_isb(val, srname) \ 526 (__builtin_nds32_mtsr_isb ((val), (srname))) 527 #define __nds32__mtsr_dsb(val, srname) \ 528 (__builtin_nds32_mtsr_dsb ((val), (srname))) 529 #define __nds32__mtusr(val, usrname) \ 530 (__builtin_nds32_mtusr ((val), (usrname))) 531 532 #define __nds32__break(swid) \ 533 (__builtin_nds32_break(swid)) 534 #define __nds32__cctlva_lck(subtype, va) \ 535 (__builtin_nds32_cctl_va_lck ((subtype), (va))) 536 #define __nds32__cctlidx_wbinval(subtype, idx) \ 537 (__builtin_nds32_cctl_idx_wbinval ((subtype), (idx))) 538 #define __nds32__cctlva_wbinval_alvl(subtype, va) \ 539 (__builtin_nds32_cctl_va_wbinval_la ((subtype), (va))) 540 #define __nds32__cctlva_wbinval_one_lvl(subtype, va) \ 541 (__builtin_nds32_cctl_va_wbinval_l1 ((subtype), (va))) 542 #define __nds32__cctlidx_read(subtype, idx) \ 543 (__builtin_nds32_cctl_idx_read ((subtype), (idx))) 544 #define __nds32__cctlidx_write(subtype, b, idxw) \ 545 (__builtin_nds32_cctl_idx_write ((subtype), (b), (idxw))) 546 #define __nds32__cctl_l1d_invalall() \ 547 (__builtin_nds32_cctl_l1d_invalall()) 548 #define __nds32__cctl_l1d_wball_alvl() \ 549 (__builtin_nds32_cctl_l1d_wball_alvl()) 550 #define __nds32__cctl_l1d_wball_one_lvl() \ 551 (__builtin_nds32_cctl_l1d_wball_one_lvl()) 552 553 #define __nds32__dsb() \ 554 (__builtin_nds32_dsb()) 555 #define __nds32__isb() \ 556 (__builtin_nds32_isb()) 557 #define __nds32__msync_store() \ 558 (__builtin_nds32_msync_store()) 559 #define __nds32__msync_all() \ 560 (__builtin_nds32_msync_all()) 561 #define __nds32__nop() \ 562 (__builtin_nds32_nop()) 563 564 #define __nds32__standby_wait_done() \ 565 (__builtin_nds32_standby_wait_done()) 566 #define __nds32__standby_no_wake_grant() \ 567 (__builtin_nds32_standby_no_wake_grant()) 568 #define __nds32__standby_wake_grant() \ 569 (__builtin_nds32_standby_wake_grant()) 570 #define __nds32__schedule_barrier() \ 571 (__builtin_nds32_schedule_barrier()) 572 #define __nds32__setend_big() \ 573 (__builtin_nds32_setend_big()) 574 #define __nds32__setend_little() \ 575 (__builtin_nds32_setend_little()) 576 #define __nds32__setgie_en() \ 577 (__builtin_nds32_setgie_en()) 578 #define __nds32__setgie_dis() \ 579 (__builtin_nds32_setgie_dis()) 580 581 #define __nds32__jr_itoff(a) \ 582 (__builtin_nds32_jr_itoff ((a))) 583 #define __nds32__jr_toff(a) \ 584 (__builtin_nds32_jr_toff ((a))) 585 #define __nds32__jral_iton(a) \ 586 (__builtin_nds32_jral_iton ((a))) 587 #define __nds32__jral_ton(a) \ 588 (__builtin_nds32_jral_ton ((a))) 589 #define __nds32__ret_itoff(a) \ 590 (__builtin_nds32_ret_itoff ((a))) 591 #define __nds32__ret_toff(a) \ 592 (__builtin_nds32_ret_toff ((a))) 593 #define __nds32__svs(a, b) \ 594 (__builtin_nds32_svs ((a), (b))) 595 #define __nds32__sva(a, b) \ 596 (__builtin_nds32_sva ((a), (b))) 597 #define __nds32__dpref_qw(a, b, subtype) \ 598 (__builtin_nds32_dpref_qw ((a), (b), (subtype))) 599 #define __nds32__dpref_hw(a, b, subtype) \ 600 (__builtin_nds32_dpref_hw ((a), (b), (subtype))) 601 #define __nds32__dpref_w(a, b, subtype) \ 602 (__builtin_nds32_dpref_w ((a), (b), (subtype))) 603 #define __nds32__dpref_dw(a, b, subtype) \ 604 (__builtin_nds32_dpref_dw ((a), (b), (subtype))) 605 606 #define __nds32__teqz(a, swid) \ 607 (__builtin_nds32_teqz ((a), (swid))) 608 #define __nds32__tnez(a, swid) \ 609 ( __builtin_nds32_tnez ((a), (swid))) 610 #define __nds32__trap(swid) \ 611 (__builtin_nds32_trap ((swid))) 612 #define __nds32__isync(a) \ 613 (__builtin_nds32_isync ((a))) 614 #define __nds32__rotr(val, ror) \ 615 (__builtin_nds32_rotr ((val), (ror))) 616 #define __nds32__wsbh(a) \ 617 (__builtin_nds32_wsbh ((a))) 618 #define __nds32__syscall(a) \ 619 (__builtin_nds32_syscall ((a))) 620 #define __nds32__return_address() \ 621 (__builtin_nds32_return_address()) 622 #define __nds32__get_current_sp() \ 623 (__builtin_nds32_get_current_sp()) 624 #define __nds32__set_current_sp(a) \ 625 (__builtin_nds32_set_current_sp ((a))) 626 #define __nds32__abs(a) \ 627 (__builtin_nds32_pe_abs ((a))) 628 #define __nds32__ave(a, b) \ 629 (__builtin_nds32_pe_ave ((a), (b))) 630 #define __nds32__bclr(a, pos) \ 631 (__builtin_nds32_pe_bclr ((a), (pos))) 632 #define __nds32__bset(a, pos) \ 633 (__builtin_nds32_pe_bset ((a), (pos))) 634 #define __nds32__btgl(a, pos) \ 635 (__builtin_nds32_pe_btgl ((a), (pos))) 636 #define __nds32__btst(a, pos) \ 637 (__builtin_nds32_pe_btst ((a), (pos))) 638 639 #define __nds32__clip(a, imm) \ 640 (__builtin_nds32_pe_clip ((a), (imm))) 641 #define __nds32__clips(a, imm) \ 642 (__builtin_nds32_pe_clips ((a), (imm))) 643 #define __nds32__clz(a) \ 644 (__builtin_nds32_pe_clz ((a))) 645 #define __nds32__clo(a) \ 646 (__builtin_nds32_pe_clo ((a))) 647 #define __nds32__bse(r, a, b) \ 648 (__builtin_nds32_pe2_bse ((r), (a), (b))) 649 #define __nds32__bsp(r, a, b) \ 650 (__builtin_nds32_pe2_bsp ((r), (a), (b))) 651 #define __nds32__pbsad(a, b) \ 652 (__builtin_nds32_pe2_pbsad ((a), (b))) 653 #define __nds32__pbsada(acc, a, b) \ 654 (__builtin_nds32_pe2_pbsada ((acc), (a), (b))) 655 656 #define __nds32__ffb(a, b) \ 657 (__builtin_nds32_se_ffb ((a), (b))) 658 #define __nds32__ffmism(a, b) \ 659 (__builtin_nds32_se_ffmism ((a), (b))) 660 #define __nds32__flmism(a, b) \ 661 (__builtin_nds32_se_flmism ((a), (b))) 662 #define __nds32__fcpynsd(a, b) \ 663 (__builtin_nds32_fcpynsd ((a), (b))) 664 #define __nds32__fcpynss(a, b) \ 665 (__builtin_nds32_fcpynss ((a), (b))) 666 #define __nds32__fcpysd(a, b) \ 667 (__builtin_nds32_fcpysd ((a), (b))) 668 #define __nds32__fcpyss(a, b) \ 669 (__builtin_nds32_fcpyss ((a), (b))) 670 #define __nds32__fmfcsr() \ 671 (__builtin_nds32_fmfcsr()) 672 #define __nds32__fmtcsr(fpcsr) \ 673 (__builtin_nds32_fmtcsr ((fpcsr))) 674 #define __nds32__fmfcfg() \ 675 (__builtin_nds32_fmfcfg()) 676 677 #define __nds32__tlbop_trd(a) \ 678 (__builtin_nds32_tlbop_trd ((a))) 679 #define __nds32__tlbop_twr(a) \ 680 (__builtin_nds32_tlbop_twr ((a))) 681 #define __nds32__tlbop_rwr(a) \ 682 (__builtin_nds32_tlbop_rwr ((a))) 683 #define __nds32__tlbop_rwlk(a) \ 684 (__builtin_nds32_tlbop_rwlk ((a))) 685 #define __nds32__tlbop_unlk(a) \ 686 (__builtin_nds32_tlbop_unlk ((a))) 687 #define __nds32__tlbop_pb(a) \ 688 (__builtin_nds32_tlbop_pb ((a))) 689 #define __nds32__tlbop_inv(a) \ 690 (__builtin_nds32_tlbop_inv ((a))) 691 #define __nds32__tlbop_flua() \ 692 (__builtin_nds32_tlbop_flua()) 693 694 #define __nds32__gie_dis() \ 695 (__builtin_nds32_gie_dis()) 696 #define __nds32__gie_en() \ 697 (__builtin_nds32_gie_en()) 698 #define __nds32__enable_int(a) \ 699 (__builtin_nds32_enable_int ((a))) 700 #define __nds32__disable_int(a) \ 701 (__builtin_nds32_disable_int ((a))) 702 #define __nds32__set_pending_swint() \ 703 (__builtin_nds32_set_pending_swint()) 704 #define __nds32__clr_pending_swint() \ 705 (__builtin_nds32_clr_pending_swint()) 706 #define __nds32__clr_pending_hwint(a) \ 707 (__builtin_nds32_clr_pending_hwint(a)) 708 #define __nds32__get_all_pending_int() \ 709 (__builtin_nds32_get_all_pending_int()) 710 #define __nds32__get_pending_int(a) \ 711 (__builtin_nds32_get_pending_int ((a))) 712 #define __nds32__set_int_priority(a, b) \ 713 (__builtin_nds32_set_int_priority ((a), (b))) 714 #define __nds32__get_int_priority(a) \ 715 (__builtin_nds32_get_int_priority ((a))) 716 #define __nds32__set_trig_type_level(a) \ 717 (__builtin_nds32_set_trig_level(a)) 718 #define __nds32__set_trig_type_edge(a) \ 719 (__builtin_nds32_set_trig_edge(a)) 720 #define __nds32__get_trig_type(a) \ 721 (__builtin_nds32_get_trig_type ((a))) 722 723 #define __nds32__unaligned_feature() \ 724 (__builtin_nds32_unaligned_feature()) 725 #define __nds32__enable_unaligned() \ 726 (__builtin_nds32_enable_unaligned()) 727 #define __nds32__disable_unaligned() \ 728 (__builtin_nds32_disable_unaligned()) 729 #endif /* nds32_intrinsic.h */ 730