1 /* Subroutines for the C front end on the PowerPC architecture.
2 Copyright (C) 2002-2018 Free Software Foundation, Inc.
3
4 Contributed by Zack Weinberg <zack@codesourcery.com>
5 and Paolo Bonzini <bonzini@gnu.org>
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #define IN_TARGET_CODE 1
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "target.h"
29 #include "c-family/c-common.h"
30 #include "memmodel.h"
31 #include "tm_p.h"
32 #include "stringpool.h"
33 #include "stor-layout.h"
34 #include "c-family/c-pragma.h"
35 #include "langhooks.h"
36 #include "c/c-tree.h"
37
38
39
40 /* Handle the machine specific pragma longcall. Its syntax is
41
42 # pragma longcall ( TOGGLE )
43
44 where TOGGLE is either 0 or 1.
45
46 rs6000_default_long_calls is set to the value of TOGGLE, changing
47 whether or not new function declarations receive a longcall
48 attribute by default. */
49
50 #define SYNTAX_ERROR(gmsgid) do { \
51 warning (OPT_Wpragmas, gmsgid); \
52 warning (OPT_Wpragmas, "ignoring malformed #pragma longcall"); \
53 return; \
54 } while (0)
55
56 void
rs6000_pragma_longcall(cpp_reader * pfile ATTRIBUTE_UNUSED)57 rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED)
58 {
59 tree x, n;
60
61 /* If we get here, generic code has already scanned the directive
62 leader and the word "longcall". */
63
64 if (pragma_lex (&x) != CPP_OPEN_PAREN)
65 SYNTAX_ERROR ("missing open paren");
66 if (pragma_lex (&n) != CPP_NUMBER)
67 SYNTAX_ERROR ("missing number");
68 if (pragma_lex (&x) != CPP_CLOSE_PAREN)
69 SYNTAX_ERROR ("missing close paren");
70
71 if (n != integer_zero_node && n != integer_one_node)
72 SYNTAX_ERROR ("number must be 0 or 1");
73
74 if (pragma_lex (&x) != CPP_EOF)
75 warning (OPT_Wpragmas, "junk at end of #pragma longcall");
76
77 rs6000_default_long_calls = (n == integer_one_node);
78 }
79
80 /* Handle defining many CPP flags based on TARGET_xxx. As a general
81 policy, rather than trying to guess what flags a user might want a
82 #define for, it's better to define a flag for everything. */
83
84 #define builtin_define(TXT) cpp_define (pfile, TXT)
85 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
86
87 /* Keep the AltiVec keywords handy for fast comparisons. */
88 static GTY(()) tree __vector_keyword;
89 static GTY(()) tree vector_keyword;
90 static GTY(()) tree __pixel_keyword;
91 static GTY(()) tree pixel_keyword;
92 static GTY(()) tree __bool_keyword;
93 static GTY(()) tree bool_keyword;
94 static GTY(()) tree _Bool_keyword;
95 static GTY(()) tree __int128_type;
96 static GTY(()) tree __uint128_type;
97
98 /* Preserved across calls. */
99 static tree expand_bool_pixel;
100
101 static cpp_hashnode *
altivec_categorize_keyword(const cpp_token * tok)102 altivec_categorize_keyword (const cpp_token *tok)
103 {
104 if (tok->type == CPP_NAME)
105 {
106 cpp_hashnode *ident = tok->val.node.node;
107
108 if (ident == C_CPP_HASHNODE (vector_keyword))
109 return C_CPP_HASHNODE (__vector_keyword);
110
111 if (ident == C_CPP_HASHNODE (pixel_keyword))
112 return C_CPP_HASHNODE (__pixel_keyword);
113
114 if (ident == C_CPP_HASHNODE (bool_keyword))
115 return C_CPP_HASHNODE (__bool_keyword);
116
117 if (ident == C_CPP_HASHNODE (_Bool_keyword))
118 return C_CPP_HASHNODE (__bool_keyword);
119
120 return ident;
121 }
122
123 return 0;
124 }
125
126 static void
init_vector_keywords(void)127 init_vector_keywords (void)
128 {
129 /* Keywords without two leading underscores are context-sensitive, and hence
130 implemented as conditional macros, controlled by the
131 rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit
132 support, record the __int128_t and __uint128_t types. */
133
134 __vector_keyword = get_identifier ("__vector");
135 C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
136
137 __pixel_keyword = get_identifier ("__pixel");
138 C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL;
139
140 __bool_keyword = get_identifier ("__bool");
141 C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL;
142
143 vector_keyword = get_identifier ("vector");
144 C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
145
146 pixel_keyword = get_identifier ("pixel");
147 C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
148
149 bool_keyword = get_identifier ("bool");
150 C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
151
152 _Bool_keyword = get_identifier ("_Bool");
153 C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
154
155 if (TARGET_VADDUQM)
156 {
157 __int128_type = get_identifier ("__int128_t");
158 __uint128_type = get_identifier ("__uint128_t");
159 }
160 }
161
162 /* Helper function to find out which RID_INT_N_* code is the one for
163 __int128, if any. Returns RID_MAX+1 if none apply, which is safe
164 (for our purposes, since we always expect to have __int128) to
165 compare against. */
166 static int
rid_int128(void)167 rid_int128(void)
168 {
169 int i;
170
171 for (i = 0; i < NUM_INT_N_ENTS; i ++)
172 if (int_n_enabled_p[i]
173 && int_n_data[i].bitsize == 128)
174 return RID_INT_N_0 + i;
175
176 return RID_MAX + 1;
177 }
178
179 /* Called to decide whether a conditional macro should be expanded.
180 Since we have exactly one such macro (i.e, 'vector'), we do not
181 need to examine the 'tok' parameter. */
182
183 static cpp_hashnode *
rs6000_macro_to_expand(cpp_reader * pfile,const cpp_token * tok)184 rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
185 {
186 cpp_hashnode *expand_this = tok->val.node.node;
187 cpp_hashnode *ident;
188
189 /* If the current machine does not have altivec, don't look for the
190 keywords. */
191 if (!TARGET_ALTIVEC)
192 return NULL;
193
194 ident = altivec_categorize_keyword (tok);
195
196 if (ident != expand_this)
197 expand_this = NULL;
198
199 if (ident == C_CPP_HASHNODE (__vector_keyword))
200 {
201 int idx = 0;
202 do
203 tok = cpp_peek_token (pfile, idx++);
204 while (tok->type == CPP_PADDING);
205 ident = altivec_categorize_keyword (tok);
206
207 if (ident == C_CPP_HASHNODE (__pixel_keyword))
208 {
209 expand_this = C_CPP_HASHNODE (__vector_keyword);
210 expand_bool_pixel = __pixel_keyword;
211 }
212 else if (ident == C_CPP_HASHNODE (__bool_keyword))
213 {
214 expand_this = C_CPP_HASHNODE (__vector_keyword);
215 expand_bool_pixel = __bool_keyword;
216 }
217 /* The boost libraries have code with Iterator::vector vector in it. If
218 we allow the normal handling, this module will be called recursively,
219 and the vector will be skipped.; */
220 else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword)))
221 {
222 enum rid rid_code = (enum rid)(ident->rid_code);
223 enum node_type itype = ident->type;
224 /* If there is a function-like macro, check if it is going to be
225 invoked with or without arguments. Without following ( treat
226 it like non-macro, otherwise the following cpp_get_token eats
227 what should be preserved. */
228 if (itype == NT_MACRO && cpp_fun_like_macro_p (ident))
229 {
230 int idx2 = idx;
231 do
232 tok = cpp_peek_token (pfile, idx2++);
233 while (tok->type == CPP_PADDING);
234 if (tok->type != CPP_OPEN_PAREN)
235 itype = NT_VOID;
236 }
237 if (itype == NT_MACRO)
238 {
239 do
240 (void) cpp_get_token (pfile);
241 while (--idx > 0);
242 do
243 tok = cpp_peek_token (pfile, idx++);
244 while (tok->type == CPP_PADDING);
245 ident = altivec_categorize_keyword (tok);
246 if (ident == C_CPP_HASHNODE (__pixel_keyword))
247 {
248 expand_this = C_CPP_HASHNODE (__vector_keyword);
249 expand_bool_pixel = __pixel_keyword;
250 rid_code = RID_MAX;
251 }
252 else if (ident == C_CPP_HASHNODE (__bool_keyword))
253 {
254 expand_this = C_CPP_HASHNODE (__vector_keyword);
255 expand_bool_pixel = __bool_keyword;
256 rid_code = RID_MAX;
257 }
258 else if (ident)
259 rid_code = (enum rid)(ident->rid_code);
260 }
261
262 if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
263 || rid_code == RID_SHORT || rid_code == RID_SIGNED
264 || rid_code == RID_INT || rid_code == RID_CHAR
265 || rid_code == RID_FLOAT
266 || (rid_code == RID_DOUBLE && TARGET_VSX)
267 || (rid_code == rid_int128 () && TARGET_VADDUQM))
268 {
269 expand_this = C_CPP_HASHNODE (__vector_keyword);
270 /* If the next keyword is bool or pixel, it
271 will need to be expanded as well. */
272 do
273 tok = cpp_peek_token (pfile, idx++);
274 while (tok->type == CPP_PADDING);
275 ident = altivec_categorize_keyword (tok);
276
277 if (ident == C_CPP_HASHNODE (__pixel_keyword))
278 expand_bool_pixel = __pixel_keyword;
279 else if (ident == C_CPP_HASHNODE (__bool_keyword))
280 expand_bool_pixel = __bool_keyword;
281 else
282 {
283 /* Try two tokens down, too. */
284 do
285 tok = cpp_peek_token (pfile, idx++);
286 while (tok->type == CPP_PADDING);
287 ident = altivec_categorize_keyword (tok);
288 if (ident == C_CPP_HASHNODE (__pixel_keyword))
289 expand_bool_pixel = __pixel_keyword;
290 else if (ident == C_CPP_HASHNODE (__bool_keyword))
291 expand_bool_pixel = __bool_keyword;
292 }
293 }
294
295 /* Support vector __int128_t, but we don't need to worry about bool
296 or pixel on this type. */
297 else if (TARGET_VADDUQM
298 && (ident == C_CPP_HASHNODE (__int128_type)
299 || ident == C_CPP_HASHNODE (__uint128_type)))
300 expand_this = C_CPP_HASHNODE (__vector_keyword);
301 }
302 }
303 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))
304 {
305 expand_this = C_CPP_HASHNODE (__pixel_keyword);
306 expand_bool_pixel = 0;
307 }
308 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword))
309 {
310 expand_this = C_CPP_HASHNODE (__bool_keyword);
311 expand_bool_pixel = 0;
312 }
313
314 return expand_this;
315 }
316
317
318 /* Define or undefine a single macro. */
319
320 static void
rs6000_define_or_undefine_macro(bool define_p,const char * name)321 rs6000_define_or_undefine_macro (bool define_p, const char *name)
322 {
323 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
324 fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name);
325
326 if (define_p)
327 cpp_define (parse_in, name);
328 else
329 cpp_undef (parse_in, name);
330 }
331
332 /* Define or undefine macros based on the current target. If the user does
333 #pragma GCC target, we need to adjust the macros dynamically. Note, some of
334 the options needed for builtins have been moved to separate variables, so
335 have both the target flags and the builtin flags as arguments. */
336
337 void
rs6000_target_modify_macros(bool define_p,HOST_WIDE_INT flags,HOST_WIDE_INT bu_mask)338 rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
339 HOST_WIDE_INT bu_mask)
340 {
341 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
342 fprintf (stderr,
343 "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX
344 ", " HOST_WIDE_INT_PRINT_HEX ")\n",
345 (define_p) ? "define" : "undef",
346 flags, bu_mask);
347
348 /* Each of the flags mentioned below controls whether certain
349 preprocessor macros will be automatically defined when
350 preprocessing source files for compilation by this compiler.
351 While most of these flags can be enabled or disabled
352 explicitly by specifying certain command-line options when
353 invoking the compiler, there are also many ways in which these
354 flags are enabled or disabled implicitly, based on compiler
355 defaults, configuration choices, and on the presence of certain
356 related command-line options. Many, but not all, of these
357 implicit behaviors can be found in file "rs6000.c", the
358 rs6000_option_override_internal() function.
359
360 In general, each of the flags may be automatically enabled in
361 any of the following conditions:
362
363 1. If no -mcpu target is specified on the command line and no
364 --with-cpu target is specified to the configure command line
365 and the TARGET_DEFAULT macro for this default cpu host
366 includes the flag, and the flag has not been explicitly disabled
367 by command-line options.
368
369 2. If the target specified with -mcpu=target on the command line, or
370 in the absence of a -mcpu=target command-line option, if the
371 target specified using --with-cpu=target on the configure
372 command line, is disqualified because the associated binary
373 tools (e.g. the assembler) lack support for the requested cpu,
374 and the TARGET_DEFAULT macro for this default cpu host
375 includes the flag, and the flag has not been explicitly disabled
376 by command-line options.
377
378 3. If either of the above two conditions apply except that the
379 TARGET_DEFAULT macro is defined to equal zero, and
380 TARGET_POWERPC64 and
381 a) BYTES_BIG_ENDIAN and the flag to be enabled is either
382 MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
383 target), or
384 b) !BYTES_BIG_ENDIAN and the flag to be enabled is either
385 MASK_POWERPC64 or it is one of the flags included in
386 ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target).
387
388 4. If a cpu has been requested with a -mcpu=target command-line option
389 and this cpu has not been disqualified due to shortcomings of the
390 binary tools, and the set of flags associated with the requested cpu
391 include the flag to be enabled. See rs6000-cpus.def for macro
392 definitions that represent various ABI standards
393 (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of
394 the specific flags that are associated with each of the cpu
395 choices that can be specified as the target of a -mcpu=target
396 compile option, or as the the target of a --with-cpu=target
397 configure option. Target flags that are specified in either
398 of these two ways are considered "implicit" since the flags
399 are not mentioned specifically by name.
400
401 Additional documentation describing behavior specific to
402 particular flags is provided below, immediately preceding the
403 use of each relevant flag.
404
405 5. If there is no -mcpu=target command-line option, and the cpu
406 requested by a --with-cpu=target command-line option has not
407 been disqualified due to shortcomings of the binary tools, and
408 the set of flags associated with the specified target include
409 the flag to be enabled. See the notes immediately above for a
410 summary of the flags associated with particular cpu
411 definitions. */
412
413 /* rs6000_isa_flags based options. */
414 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
415 if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
416 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
417 if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
418 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
419 if ((flags & OPTION_MASK_POWERPC64) != 0)
420 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
421 if ((flags & OPTION_MASK_MFCRF) != 0)
422 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
423 if ((flags & OPTION_MASK_POPCNTB) != 0)
424 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
425 if ((flags & OPTION_MASK_FPRND) != 0)
426 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
427 if ((flags & OPTION_MASK_CMPB) != 0)
428 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
429 if ((flags & OPTION_MASK_MFPGPR) != 0)
430 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
431 if ((flags & OPTION_MASK_POPCNTD) != 0)
432 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
433 /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
434 turned on in the following condition:
435 1. TARGET_P9_DFORM_SCALAR or TARGET_P9_DFORM_VECTOR are enabled
436 and OPTION_MASK_DIRECT_MOVE is not explicitly disabled.
437 Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
438 have been turned on explicitly.
439 Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
440 turned off in any of the following conditions:
441 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
442 disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
443 enabled.
444 2. TARGET_VSX is off. */
445 if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
446 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
447 if ((flags & OPTION_MASK_MODULO) != 0)
448 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
449 if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
450 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
451 if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
452 rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
453 /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on
454 in any of the following conditions:
455 1. The command line specifies either -maltivec=le or -maltivec=be.
456 2. The operating system is Darwin and it is configured for 64
457 bit. (See darwin_rs6000_override_options.)
458 3. The operating system is Darwin and the operating system
459 version is 10.5 or higher and the user has not explicitly
460 disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and
461 the compiler is not producing code for integration within the
462 kernel. (See darwin_rs6000_override_options.)
463 Note that the OPTION_MASK_ALTIVEC flag is automatically turned
464 off in any of the following conditions:
465 1. The operating system does not support saving of AltiVec
466 registers (OS_MISSING_ALTIVEC).
467 2. If an inner context (as introduced by
468 __attribute__((__target__())) or #pragma GCC target()
469 requests a target that normally enables the
470 OPTION_MASK_ALTIVEC flag but the outer-most "main target"
471 does not support the rs6000_altivec_abi, this flag is
472 turned off for the inner context unless OPTION_MASK_ALTIVEC
473 was explicitly enabled for the inner context. */
474 if ((flags & OPTION_MASK_ALTIVEC) != 0)
475 {
476 const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
477 rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
478 rs6000_define_or_undefine_macro (define_p, vec_str);
479
480 /* Define this when supporting context-sensitive keywords. */
481 if (!flag_iso)
482 rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
483 }
484 /* Note that the OPTION_MASK_VSX flag is automatically turned on in
485 the following conditions:
486 1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX
487 was not explicitly turned off. Hereafter, the OPTION_MASK_VSX
488 flag is considered to have been explicitly turned on.
489 Note that the OPTION_MASK_VSX flag is automatically turned off in
490 the following conditions:
491 1. The operating system does not support saving of AltiVec
492 registers (OS_MISSING_ALTIVEC).
493 2. If any of the options TARGET_HARD_FLOAT, TARGET_FPRS,
494 TARGET_SINGLE_FLOAT, or TARGET_DOUBLE_FLOAT are turned off.
495 Hereafter, the OPTION_MASK_VSX flag is considered to have been
496 turned off explicitly.
497 3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the
498 OPTION_MASK_VSX flag is considered to have been turned off
499 explicitly.
500 4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
501 compilation context, or if it is turned on by any means in an
502 inner compilation context. Hereafter, the OPTION_MASK_VSX
503 flag is considered to have been turned off explicitly.
504 5. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the
505 OPTION_MASK_VSX flag is considered to have been turned off
506 explicitly.
507 6. If an inner context (as introduced by
508 __attribute__((__target__())) or #pragma GCC target()
509 requests a target that normally enables the
510 OPTION_MASK_VSX flag but the outer-most "main target"
511 does not support the rs6000_altivec_abi, this flag is
512 turned off for the inner context unless OPTION_MASK_VSX
513 was explicitly enabled for the inner context. */
514 if ((flags & OPTION_MASK_VSX) != 0)
515 rs6000_define_or_undefine_macro (define_p, "__VSX__");
516 if ((flags & OPTION_MASK_HTM) != 0)
517 {
518 rs6000_define_or_undefine_macro (define_p, "__HTM__");
519 /* Tell the user that our HTM insn patterns act as memory barriers. */
520 rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
521 }
522 /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
523 on in the following conditions:
524 1. TARGET_P9_VECTOR is explicitly turned on and
525 OPTION_MASK_P8_VECTOR is not explicitly turned off.
526 Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to
527 have been turned off explicitly.
528 Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
529 off in the following conditions:
530 1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX
531 were turned off explicitly and OPTION_MASK_P8_VECTOR flag was
532 not turned on explicitly.
533 2. If TARGET_ALTIVEC is turned off. Hereafter, the
534 OPTION_MASK_P8_VECTOR flag is considered to have been turned off
535 explicitly.
536 3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not
537 explicitly enabled. If TARGET_VSX is explicitly enabled, the
538 OPTION_MASK_P8_VECTOR flag is hereafter also considered to
539 have been turned off explicitly. */
540 if ((flags & OPTION_MASK_P8_VECTOR) != 0)
541 rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
542 /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned
543 off in the following conditions:
544 1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is
545 not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR
546 was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is
547 also considered to have been turned off explicitly.
548 Note that the OPTION_MASK_P9_VECTOR is automatically turned on
549 in the following conditions:
550 1. If TARGET_P9_DFORM_SCALAR or TARGET_P9_DFORM_VECTOR and
551 OPTION_MASK_P9_VECTOR was not turned off explicitly.
552 Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to
553 have been turned on explicitly. */
554 if ((flags & OPTION_MASK_P9_VECTOR) != 0)
555 rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__");
556 /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically
557 turned off in the following conditions:
558 1. If TARGET_POWERPC64 is turned off.
559 2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory
560 load/store are disabled on little endian). */
561 if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
562 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
563 /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically
564 turned off in the following conditions:
565 1. If TARGET_POWERPC64 is turned off.
566 Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is
567 automatically turned on in the following conditions:
568 1. If TARGET_QUAD_MEMORY and this flag was not explicitly
569 disabled. */
570 if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
571 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
572 /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off
573 in the following conditions:
574 1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX
575 are turned off explicitly and OPTION_MASK_CRYPTO is not turned
576 on explicitly.
577 2. If TARGET_ALTIVEC is turned off. */
578 if ((flags & OPTION_MASK_CRYPTO) != 0)
579 rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
580 /* Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
581 turned on in the following conditions:
582 1. If TARGET_UPPER_REGS is explicitly turned on and
583 TARGET_VSX is turned on and OPTION_MASK_UPPER_REGS_DF is not
584 explicitly turned off. Hereafter, the
585 OPTION_MASK_UPPER_REGS_DF flag is considered to have been
586 explicitly set.
587 Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
588 turned off in the following conditions:
589 1. If TARGET_UPPER_REGS is explicitly turned off and TARGET_VSX
590 is turned on and OPTION_MASK_UPPER_REGS_DF is not explicitly
591 turned on. Hereafter, the OPTION_MASK_UPPER_REGS_DF flag is
592 considered to have been explicitly cleared.
593 2. If TARGET_UPPER_REGS_DF is turned on but TARGET_VSX is turned
594 off. */
595 if ((flags & OPTION_MASK_UPPER_REGS_DF) != 0)
596 rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
597 /* Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
598 turned on in the following conditions:
599 1. If TARGET_UPPER_REGS is explicitly turned on and
600 TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
601 turned off explicitly. Hereafter, the
602 OPTION_MASK_UPPER_REGS_SF flag is considered to have been
603 explicitly set.
604 Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
605 turned off in the following conditions:
606 1. If TARGET_UPPER_REGS is explicitly turned off and
607 TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
608 turned off explicitly. Hereafter, the
609 OPTION_MASK_UPPER_REGS_SF flag is considered to have been
610 explicitly cleared.
611 2. If TARGET_P8_VECTOR is off. */
612 if ((flags & OPTION_MASK_UPPER_REGS_SF) != 0)
613 rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
614
615 /* options from the builtin masks. */
616 /* Note that RS6000_BTM_SPE is enabled only if TARGET_SPE
617 (e.g. -mspe). */
618 if ((bu_mask & RS6000_BTM_SPE) != 0)
619 rs6000_define_or_undefine_macro (define_p, "__SPE__");
620 /* Note that RS6000_BTM_PAIRED is enabled only if
621 TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */
622 if ((bu_mask & RS6000_BTM_PAIRED) != 0)
623 rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
624 /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
625 PROCESSOR_CELL) (e.g. -mcpu=cell). */
626 if ((bu_mask & RS6000_BTM_CELL) != 0)
627 rs6000_define_or_undefine_macro (define_p, "__PPU__");
628 }
629
630 void
rs6000_cpu_cpp_builtins(cpp_reader * pfile)631 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
632 {
633 /* Define all of the common macros. */
634 rs6000_target_modify_macros (true, rs6000_isa_flags,
635 rs6000_builtin_mask_calculate ());
636
637 if (TARGET_FRE)
638 builtin_define ("__RECIP__");
639 if (TARGET_FRES)
640 builtin_define ("__RECIPF__");
641 if (TARGET_FRSQRTE)
642 builtin_define ("__RSQRTE__");
643 if (TARGET_FRSQRTES)
644 builtin_define ("__RSQRTEF__");
645 if (TARGET_FLOAT128_KEYWORD)
646 builtin_define ("__FLOAT128__");
647 if (TARGET_FLOAT128_TYPE)
648 builtin_define ("__FLOAT128_TYPE__");
649 if (TARGET_FLOAT128_HW)
650 builtin_define ("__FLOAT128_HARDWARE__");
651 if (TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (TFmode))
652 builtin_define ("__ibm128=long double");
653
654 /* We needed to create a keyword if -mfloat128-type was used but not -mfloat,
655 so we used __ieee128. If -mfloat128 was used, create a #define back to
656 the real keyword in case somebody used it. */
657 if (TARGET_FLOAT128_KEYWORD)
658 builtin_define ("__ieee128=__float128");
659
660 if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
661 {
662 /* Define the AltiVec syntactic elements. */
663 builtin_define ("__vector=__attribute__((altivec(vector__)))");
664 builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
665 builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned");
666
667 if (!flag_iso)
668 {
669 builtin_define ("vector=vector");
670 builtin_define ("pixel=pixel");
671 builtin_define ("bool=bool");
672 builtin_define ("_Bool=_Bool");
673 init_vector_keywords ();
674
675 /* Enable context-sensitive macros. */
676 cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
677 }
678 }
679 if ((!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
680 ||(TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_DOUBLE_FLOAT))
681 builtin_define ("_SOFT_DOUBLE");
682 /* Used by lwarx/stwcx. errata work-around. */
683 if (rs6000_cpu == PROCESSOR_PPC405)
684 builtin_define ("__PPC405__");
685 /* Used by libstdc++. */
686 if (TARGET_NO_LWSYNC)
687 builtin_define ("__NO_LWSYNC__");
688
689 if (TARGET_EXTRA_BUILTINS)
690 {
691 /* For the VSX builtin functions identical to Altivec functions, just map
692 the altivec builtin into the vsx version (the altivec functions
693 generate VSX code if -mvsx). */
694 builtin_define ("__builtin_vsx_xxland=__builtin_vec_and");
695 builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc");
696 builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor");
697 builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or");
698 builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor");
699 builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel");
700 builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm");
701
702 /* Also map the a and m versions of the multiply/add instructions to the
703 builtin for people blindly going off the instruction manual. */
704 builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp");
705 builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp");
706 builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp");
707 builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp");
708 builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp");
709 builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp");
710 builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp");
711 builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp");
712 builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp");
713 builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp");
714 builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp");
715 builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp");
716 builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp");
717 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
718 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
719 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
720 }
721
722 /* Tell users they can use __builtin_bswap{16,64}. */
723 builtin_define ("__HAVE_BSWAP__");
724
725 /* May be overridden by target configuration. */
726 RS6000_CPU_CPP_ENDIAN_BUILTINS();
727
728 if (TARGET_LONG_DOUBLE_128)
729 {
730 builtin_define ("__LONG_DOUBLE_128__");
731 builtin_define ("__LONGDOUBLE128");
732
733 if (TARGET_IEEEQUAD)
734 builtin_define ("__LONG_DOUBLE_IEEE128__");
735 else
736 builtin_define ("__LONG_DOUBLE_IBM128__");
737 }
738
739 switch (TARGET_CMODEL)
740 {
741 /* Deliberately omit __CMODEL_SMALL__ since that was the default
742 before --mcmodel support was added. */
743 case CMODEL_MEDIUM:
744 builtin_define ("__CMODEL_MEDIUM__");
745 break;
746 case CMODEL_LARGE:
747 builtin_define ("__CMODEL_LARGE__");
748 break;
749 default:
750 break;
751 }
752
753 switch (rs6000_current_abi)
754 {
755 case ABI_V4:
756 builtin_define ("_CALL_SYSV");
757 break;
758 case ABI_AIX:
759 builtin_define ("_CALL_AIXDESC");
760 builtin_define ("_CALL_AIX");
761 builtin_define ("_CALL_ELF=1");
762 break;
763 case ABI_ELFv2:
764 builtin_define ("_CALL_ELF=2");
765 break;
766 case ABI_DARWIN:
767 builtin_define ("_CALL_DARWIN");
768 break;
769 default:
770 break;
771 }
772
773 /* Vector element order. */
774 if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
775 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
776 else
777 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
778
779 /* Let the compiled code know if 'f' class registers will not be available. */
780 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
781 builtin_define ("__NO_FPRS__");
782
783 /* Whether aggregates passed by value are aligned to a 16 byte boundary
784 if their alignment is 16 bytes or larger. */
785 if ((TARGET_MACHO && rs6000_darwin64_abi)
786 || DEFAULT_ABI == ABI_ELFv2
787 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
788 builtin_define ("__STRUCT_PARM_ALIGN__=16");
789
790 /* Generate defines for Xilinx FPU. */
791 if (rs6000_xilinx_fpu)
792 {
793 builtin_define ("_XFPU");
794 if (rs6000_single_float && ! rs6000_double_float)
795 {
796 if (rs6000_simple_fpu)
797 builtin_define ("_XFPU_SP_LITE");
798 else
799 builtin_define ("_XFPU_SP_FULL");
800 }
801 if (rs6000_double_float)
802 {
803 if (rs6000_simple_fpu)
804 builtin_define ("_XFPU_DP_LITE");
805 else
806 builtin_define ("_XFPU_DP_FULL");
807 }
808 }
809 }
810
811
812 struct altivec_builtin_types
813 {
814 enum rs6000_builtins code;
815 enum rs6000_builtins overloaded_code;
816 signed char ret_type;
817 signed char op1;
818 signed char op2;
819 signed char op3;
820 };
821
822 const struct altivec_builtin_types altivec_overloaded_builtins[] = {
823 /* Unary AltiVec/VSX builtins. */
824 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
825 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
826 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
827 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
828 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
829 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
830 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
831 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
832 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
833 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
834 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
835 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
836 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
837 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
838 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
839 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
840 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
841 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
842 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
843 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
844 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
845 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
846 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
847 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
848 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
849 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
850 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
851 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
852 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
853 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
854 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
855 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
856 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
857 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
858 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
859 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
860 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
861 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
862 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
863 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
864 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
865 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
866 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
867 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
868 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
869 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
870 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
871 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
872 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
873 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
874 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
875 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
876 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
877 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
878 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
879 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
880 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
881 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
882 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
883 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
884 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
885 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
886 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
887 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
888 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
889 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
890 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
891 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
892 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
893 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
894 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
895 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
896 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
897 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
898 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
899 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
900 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
901 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
902 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
903 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
904 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
905 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
906 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
907 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
908 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
909 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
910 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
911 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
912 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
913 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
914 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
915 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
916 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
917 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
918 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
919 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
920 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
921 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
922 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
923 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
924 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
925 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
926 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
927 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
928 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
929 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
930 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
931 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
932 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
933 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
934 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
935 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
936 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
937 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
938 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
939 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
940 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
941 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
942 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
943 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
944 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
945 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
946 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
947 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
948 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
949 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
950 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
951 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
952 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
953 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
954
955 /* Binary AltiVec/VSX builtins. */
956 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
957 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
958 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
959 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
960 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
961 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
962 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
963 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
964 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
965 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
966 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
967 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
968 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
969 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
970 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
971 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
972 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
973 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
974 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
975 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
976 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
977 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
978 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
979 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
980 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
981 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
982 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
983 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
984 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
985 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
986 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
987 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
988 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
989 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
990 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
991 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
992 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
993 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
994 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
995 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
996 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
997 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
998 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
999 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1000 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
1001 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1002 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
1003 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1004 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
1005 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1006 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
1007 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1008 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
1009 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1010 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
1011 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1012 RS6000_BTI_unsigned_V1TI, 0 },
1013 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
1014 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1015 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1016 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1017 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1018 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1019 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1020 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1021 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1022 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1023 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1024 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1025 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1026 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1027 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1028 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1029 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
1030 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1031 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1032 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1033 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1034 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1035 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1036 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1037 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1038 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1039 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1040 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1041 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1042 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1043 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1044 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1045 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1046 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1047 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1048 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1049 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1050 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1051 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1052 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1053 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1054 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1055 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1056 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1057 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1058 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1059 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1060 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1061 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1062 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1063 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1064 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1065 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1066 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1067 RS6000_BTI_unsigned_V4SI, 0 },
1068 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1069 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1070 RS6000_BTI_unsigned_V1TI, 0 },
1071 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1072 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1073 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1074 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1075 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
1076 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1077 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
1078 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1079 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1080 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1081 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1082 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1083 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1084 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1085 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1086 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1087 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1088 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1089 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1090 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1091 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1092 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1093 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1094 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1095 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1096 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1097 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1098 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1099 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1100 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1101 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1102 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1103 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1104 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1105 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1106 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1107 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1108 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1109 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1110 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1111 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1112 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1113 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1114 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1115 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1116 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1117 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1118 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1119 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1120 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1121 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1122 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1123 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1124 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1125 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1126 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1127 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1128 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1129 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1130 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1131 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1132 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1133 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1134 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1135 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1136 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1137 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1138 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1139 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1140 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1141 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1142 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1143 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1144 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1145 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1146 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1147 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1148 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1149 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1150 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1151 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1152 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1153 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1154 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1155 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1156 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1157 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1158 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1159 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1160 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1161 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1162 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1163 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1164 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1165 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1166 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1167 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1168 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1169 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1170 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1171 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1172 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1173 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1174 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1175 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1176 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1177 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1178 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1179 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1180 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1181 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1182 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1183 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1184 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1185 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1186 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1187 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1188 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1189 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1190 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1191 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1192 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1193 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1194 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1195 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1196 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1197 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1198 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1199 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1200 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1201 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1202 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1203 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1204 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1205 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1206 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1207 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1208 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1209 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1210 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1211 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1212 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1213 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1214 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1215 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1216 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1217 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1218 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1219 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1220 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1221 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1222 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1223 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1224 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1225 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1226 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1227 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1228 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1229 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1230 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1231 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1232 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1233 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1234 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1235 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1236 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1237 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1238 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1239 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1240 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1241 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1242 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1243 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1244 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1245 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1246 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1247 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1248 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1249 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1250 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1251 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1252 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1253 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1254 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1255 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1256 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1257 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1258 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1259 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1260 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1261 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1262 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1263 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1264 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1265 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1266 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1267 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1268 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1269 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1270 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1271 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1272 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1273 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1274 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1275 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1276 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1277 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1278 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1279 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1280 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1281 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1282 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1283 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1284 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1285 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1286 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1287 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1288 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1289 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1290 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1291 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1292 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1293 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1294 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1295 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1296 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
1297 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1298 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
1299 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1300 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
1301 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1302 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
1303 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1304 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
1305 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1306 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
1307 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1308 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
1309 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1310 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
1311 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1312 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
1313 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1314 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
1315 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1316 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
1317 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1318 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
1319 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1320 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
1321 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1322 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1323 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1324 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1325 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1326 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1327 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1328 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1329 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1330 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1331 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1332 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1333 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1334 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1335 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1336 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1337 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1338 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1339 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1340 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1341 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1342 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1343 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1344 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1345 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1346 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
1347 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1348 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
1349 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1350 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
1351 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1352
1353 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1354 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1355 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1356 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1357
1358 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1359 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1360 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1361 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1362
1363 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1364 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1365 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1366 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1367
1368 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
1369 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1370 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
1371 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1372 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
1373 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1374 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
1375 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1376 RS6000_BTI_unsigned_V16QI, 0},
1377 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
1378 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1379 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
1380 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1381 RS6000_BTI_unsigned_V8HI, 0},
1382 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
1383 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1384 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
1385 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1386 RS6000_BTI_unsigned_V4SI, 0},
1387 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
1388 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1389 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
1390 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1391 RS6000_BTI_unsigned_V2DI, 0},
1392 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
1393 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1394 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
1395 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1396 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
1397 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1398 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
1399 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1400 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
1401 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1402 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
1403 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1404 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
1405 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1406 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
1407 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1408 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
1409 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1410 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
1411 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1412 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
1413 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1414 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1415 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1416 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1417 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1418 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1419 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1420 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1421 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1422 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1423 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1424 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1425 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1426 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1427 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1428 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1429 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1430 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1431 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1432 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1433 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1434 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1435 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1436 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1437 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1438 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
1439 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1440 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
1441 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1442 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
1443 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1444 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
1445 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1446 RS6000_BTI_unsigned_V16QI, 0},
1447 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
1448 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1449 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
1450 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1451 RS6000_BTI_unsigned_V8HI, 0},
1452 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
1453 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1454 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
1455 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1456 RS6000_BTI_unsigned_V4SI, 0},
1457 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
1458 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1459 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
1460 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1461 RS6000_BTI_unsigned_V2DI, 0},
1462 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
1463 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1464 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
1465 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1466 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
1467 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1468 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
1469 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1470 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
1471 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1472 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
1473 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1474 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
1475 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1476 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
1477 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1478 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
1479 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1480 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
1481 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1482 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
1483 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1484 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
1485 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1486 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
1487 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1488 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
1489 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1490 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
1491 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
1492 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
1493 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
1494 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
1495 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1496 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
1497 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1498 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
1499 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1500 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
1501 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1502 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
1503 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1504 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
1505 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1506 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1507 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1508 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1509 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1510 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1511 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1512 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1513 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1514 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1515 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1516 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1517 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1518 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1519 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1520 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1521 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1522 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1523 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1524 ~RS6000_BTI_unsigned_V2DI, 0 },
1525 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1526 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1527 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1528 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1529 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1530 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1531 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1532 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1533 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1534 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1535 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1536 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1537 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1538 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1539 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1540 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1541 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1542 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1543 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1544 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1545 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1546 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1547 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1548 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1549 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1550 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1551 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1552 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1553 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1554 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1555 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1556 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1557 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1558 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1559 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1560 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1561 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1562 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1563 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1564 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1565 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1566 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1567 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1568 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1569 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1570 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1571 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1572 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1573 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1574 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1575 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1576 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1577 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1578 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1579 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1580 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1581 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1582 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1583 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1584 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1585 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1586 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1587 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1588 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1589 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1590 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1591 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1592 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1593 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1594 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1595 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1596 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1597 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1598 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1599 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1600 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1601 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1602 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1603 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1604 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1605 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1606 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1607 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1608 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1609 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1610 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1611 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1612 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1613 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1614 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1615 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1616 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1617 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1618 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1619 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1620 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1621 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1622 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1623 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1624 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1625 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1626 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1627 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1628 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1629 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1630 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1631 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1632 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1633 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1634 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1635 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1636 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1637 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1638 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1639 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1640 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1641 ~RS6000_BTI_unsigned_V16QI, 0 },
1642 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1643 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1644 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1645 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1646 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1647 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1648 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1649 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1650 ~RS6000_BTI_unsigned_V2DI, 0 },
1651 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1652 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1653 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1654 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1655 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1656 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1657 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1658 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1659 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1660 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1661 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1662 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1663 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1664 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1665 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1666 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1667 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1668 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1669 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1670 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1671 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1672 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1673 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1674 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1675 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1676 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1677 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1678 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1679 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1680 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1681 ~RS6000_BTI_unsigned_long_long, 0 },
1682 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1683 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1684 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1685 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1686 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1687 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1688 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1689 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1690 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1691 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1692 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1693 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1694 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1695 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1696 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1697 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1698 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1699 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1700 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1701 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1702 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1703 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1704 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1705 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1706 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1707 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1708 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1709 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1710 ~RS6000_BTI_unsigned_long_long, 0 },
1711 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1712 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1713 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1714 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1715 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1716 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1717 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1718 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1719 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1720 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1721 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1722 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1723 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1724 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1725 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1726 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1727 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1728 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1729 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1730 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1731 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1732 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1733 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1734 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1735 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1736 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1737 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1738 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1739 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1740 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1741 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1742 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1743 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1744 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1745 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1746 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1747 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1748 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1749 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1750 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1751 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1752 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1753 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1754 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1755 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1756 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1757 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1758 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1759 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1760 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1761 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1762 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1763 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1764 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1765 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1766 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1767 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1768 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1769 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1770 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1771 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1772 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1773 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1774 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1775 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1776 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1777 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1778 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1779 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1780 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1781 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1782 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1783 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1784 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1785 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1786 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1787 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1788 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1789 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1790 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1791 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1792 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1793 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1794 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1795 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1796 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1797 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1798 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1799 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1800 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1801 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1802 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1803 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1804 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1805 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1806 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1807 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1808 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1809 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1810 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1811 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1812 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1813 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1814 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1815 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1816 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1817 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1818 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1819 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1820 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1821 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1822 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1823 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1824 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1825 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1826 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1827 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1828 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1829 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1830 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1831 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1832 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1833 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1834 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1835 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1836 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1837 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1838 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1839 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1840 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1841 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1842 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1843 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1844 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1845 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1846 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1847 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1848 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1849 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1850 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1851 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1852 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1853 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1854 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1855 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1856 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1857 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1858 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1859 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1860 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1861 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1862 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1863 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1864 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1865 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1866 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1867 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1868 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1869 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1870 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1871 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1872 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1873 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1874 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1875 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1876 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1877 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1878 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1879 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1880 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1881 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1882 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1883 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1884 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1885 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1886 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1887 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1888 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1889 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1890 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1891 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1892 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1893 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1894 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1895 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1896 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1897 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1898 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1899 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1900 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1901 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1902 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1903 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1904 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1905 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1906 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1907 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1908 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1909 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1910 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1911 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1912 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1913 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1914 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1915 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1916 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1917 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1918 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1919 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1920 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1921 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1922 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1923 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1924 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1925 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1926 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1927 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1928 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1929 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1930 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1931 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1932 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1933 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1934 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1935 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1936 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1937 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1938 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1939 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1940 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1941 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1942 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1943 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1944 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1945 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1946 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1947 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1948 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1949 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1950 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1951 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1952 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1953 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1954 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1955 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1956 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1957 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1958 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1959 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1960 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1961 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1962 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1963 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1964 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1965 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1966 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1967 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1968 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1969 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1970 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1971 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1972 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1973 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1974 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1975 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1976 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1977 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1978 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1979 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
1980 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1981 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1982 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1983 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1984 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1985 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1986 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1987 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1988 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1989 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1990 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1991 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1992 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1993 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1994 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1995 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1996 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1997 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
1998 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1999 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2000 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2001 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2002 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2003 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2004 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2005 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2006 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2007 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2008 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2009 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2010 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2011 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2012 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2013 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2014 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2015 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2016 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2017 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2018 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2019 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2020 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2021 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2022 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2023 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2024 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2025 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2026 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2027 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2028 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2029 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2030 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2031 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2032 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2033 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2034 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2035 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2036 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2037 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2038 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2039 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
2040 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2041 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2042 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2043 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2044 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2045 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2046 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2047 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2048 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2049 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2050 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2051 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2052 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2053 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2054 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2055 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2056 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2057 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2058 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2059 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2060 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2061 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2062 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2063 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2064 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2065 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2066 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2067 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2068 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2069 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2070 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2071 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2072 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2073 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2074 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2075 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2076 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2077 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2078 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2079 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2080 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2081 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2082 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2083 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2084 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2085 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2086 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2087 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2088 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2089 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2090 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2091 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2092 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2093 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2094 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2095 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2096 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2097 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2098 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2099 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2100 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2101 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2102 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2103 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2104 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2105 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2106 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2107 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2108 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2109 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2110 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2111 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2112 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2113 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2114 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2115 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2116 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2117 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2118 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2119 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2120 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2121 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2122 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2123 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2124 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2125 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
2126 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2127 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
2128 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2129 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
2130 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2131 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2132 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2133 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2134 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2135 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2136 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2137 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2138 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2139 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2140 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2141 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2142 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2143 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2144 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2145 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2146 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2147 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2148 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2149 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2150 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2151 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2152 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2153 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2154 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2155 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2156 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2157 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2158 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2159 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2160 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2161 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2162 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2163 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2164 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2165 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2166 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2167 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2168 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2169 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2170 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2171 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2172 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2173 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2174 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2175 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2176 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2177 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2178 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2179 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
2180 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2181 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
2182 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2183 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2184 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2185 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2186 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2187 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2188 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2189 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2190 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2191 RS6000_BTI_unsigned_V4SI, 0 },
2192 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2193 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2194 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2195 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2196 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2197 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2198 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2199 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2200 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2201 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2202 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2203 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2204 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2205 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2206 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2207 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2208 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2209 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2210 RS6000_BTI_unsigned_V4SI, 0 },
2211 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2212 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2213 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2214 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2215 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
2216 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2217 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2218 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2219 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2220 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2221 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2222 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2223 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2224 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2225 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
2226 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2227 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
2228 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2229 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
2230 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2231 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
2232 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2233 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2234 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2235 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2236 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2237
2238 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V16QI,
2239 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2240 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V8HI,
2241 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2242 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SI,
2243 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2244 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DI,
2245 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2246 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SF,
2247 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2248 { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DF,
2249 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2250
2251 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2252 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2253 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2254 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2255 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2256 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2257 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2258 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2259 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2260 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2261 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2262 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2263 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2264 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2265 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2266 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2267 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2268 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2269 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2270 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2271 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2272 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2273 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2274 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2275 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2276 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2277 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2278 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2279 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2280 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2281 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2282 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2283 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2284 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2285 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2286 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2287 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2288 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2289 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2290 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2291 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2292 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
2293 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2294 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2295 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2296 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
2297 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2298 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
2299 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2300 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2301 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2302 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2303 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2304 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2305 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2306 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2307 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2308 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2309 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2310 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2311 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2312 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2313 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2314 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2315 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2316 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2317 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2318 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2319 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2320 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2321 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2322 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2323 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2324 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2325 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2326 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2327 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2328 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2329 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2330 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2331 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2332 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2333 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2334 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2335 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2336 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2337 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2338 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2339 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2340 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2341 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2342 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2343 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2344 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2345 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2346 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2347 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2348 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2349 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2350 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2351 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2352 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2353 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2354 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2355 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2356 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2357 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2358 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2359 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2360 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2361 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2362 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2363 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2364 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2365 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2366 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2367 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2368 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2369 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2370 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2371 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2372 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2373 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2374 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2375 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2376 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2377 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2378 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2379 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2380 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2381 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2382 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2383 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2384 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2385 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2386 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2387 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2388 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2389 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2390 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2391 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2392 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2393 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2394 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2395 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2396 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2397 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2398 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2399 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2400 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2401 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2402 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2403 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2404 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2405 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2406 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2407 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2408 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2409 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2410 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2411 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2412 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2413 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2414 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2415 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2416 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2417 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2418 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2419 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2420 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2421 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2422 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2423 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2424 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2425 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2426 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2427 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2428 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2429 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2430 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2431 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2432 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2433 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2434 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2435 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2436 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2437 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2438 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2439 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2440 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2441 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2442 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2443 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2444 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2445 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2446 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2447 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2448 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2449 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2450 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2451 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2452 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2453 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2454 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2455 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2456 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2457 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2458 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2459 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2460 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2461 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2462 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2463 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2464 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2465 RS6000_BTI_unsigned_V4SI, 0 },
2466 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2467 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2468 RS6000_BTI_unsigned_V2DI, 0 },
2469 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2470 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2471 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2472 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2473 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2474 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2475 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2476 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2477 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2478 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2479 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2480 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2481 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2482 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2483 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2484 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2485 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2486 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2487 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2488 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2489 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2490 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2491 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2492 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2493 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2494 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2495 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2496 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2497 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2498 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2499 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2500 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2501 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2502 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2503 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2504 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2505 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2506 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2507 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2508 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2509 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2510 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2511 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2512 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2513 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2514 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2515 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2516 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2517 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2518 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2519 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2520 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2521 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2522 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2523 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2524 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2525 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2526 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2527 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2528 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2529 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2530 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2531 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2532 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2533 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2534 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2535 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2536 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2537 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2538 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2539 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2540 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2541 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2542 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2543 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2544 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2545 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2546 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2547 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2548 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2549 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2550 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2551 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2552 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2553 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2554 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2555 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2556 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2557 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2558 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2559 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2560 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2561 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2562 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2563 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2564 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2565 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2566 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2567 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2568 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2569 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2570 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2571 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2572 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2573 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2574 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2575 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2576 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2577 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2578 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2579 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2580 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2581 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2582 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2583 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2584 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2585 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2586 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2587 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2588 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2589 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2590 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2591 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2592 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2593 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2594 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2595 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2596 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2597 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2598 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2599 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2600 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2601 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2602 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2603 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2604 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2605 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2606 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2607 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2608 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2609 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2610 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2611 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2612 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2613 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2614 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2615 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2616 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2617 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2618 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2619 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2620 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2621 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2622 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2623 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2624 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2625 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2626 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2627 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2628 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2629 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2630 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2631 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2632 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2633 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2634 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2635 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2636 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2637 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2638 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2639 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2640 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2641 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2642 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2643 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2644 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2645 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2646 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2647 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2648 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2649 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2650 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2651 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2652 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2653 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2654 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2655 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2656 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2657 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2658 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2659 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2660 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2661 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2662 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2663 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2664 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2665 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2666 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2667 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2668 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2669 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2670 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2671 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2672 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2673 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2674 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2675 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2676 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2677 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2678 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2679 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2680 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2681 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2682 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2683 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2684 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2685 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2686 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2687 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2688 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2689 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2690 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2691 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2692 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2693 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2694 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2695 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2696 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2697 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2698 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2699 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2700 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2701 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2702 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2703 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2704 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2705 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2706 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2707 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2708 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2709 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2710 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2711 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2712 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2713 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2714 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2715 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2716 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2717 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2718 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2719 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2720 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2721 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2722 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2723 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2724 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2725 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2726 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2727 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2728 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2729 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2730 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2731 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2732 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2733 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2734 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2735 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2736 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2737 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2738 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2739 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2740 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2741 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2742 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2743 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2744 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2745 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2746 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2747 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2748 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2749 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2750 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2751 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2752 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2753 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2754 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2755 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2756 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2757 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2758 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2759 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2760 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2761 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2762 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2763 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2764 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2765 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2766 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2767 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2768 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2769 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2770 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2771 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2772 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2773 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2774 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2775 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2776 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2777 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2778 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2779 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2780 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2781 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2782 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2783 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2784 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2785 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2786 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2787 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2788 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2789 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2790 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2791 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2792 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2793 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2794 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2795 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2796 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2797 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2798 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2799 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2800 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2801 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2802 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2803 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2804 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2805 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2806 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2807 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2808 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2809 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2810 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2811 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2812 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2813 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2814 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2815 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2816 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2817 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2818 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2819 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2820 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2821 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2822 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2823 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2824 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2825 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2826 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2827 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2828 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2829 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2830 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2831 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2832 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2833 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2834 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2835 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2836 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2837 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2838 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2839 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2840 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2841 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2842 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2843 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2844 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2845 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2846 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2847 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2848 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2849 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
2850 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2851 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
2852 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2853 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2854 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2855 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2856 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2857 RS6000_BTI_unsigned_V1TI, 0 },
2858 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
2859 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2860 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2861 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2862 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2863 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2864 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2865 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2866 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2867 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2868 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2869 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2870 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2871 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2872 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2873 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2874 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2875 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2876 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2877 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2878 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2879 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2880 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2881 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2882 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2883 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2884 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2885 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2886 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2887 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2888 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2889 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2890 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2891 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2892 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2893 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2894 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2895 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2896 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2897 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2898 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2899 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2900 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2901 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2902 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2903 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2904 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2905 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2906 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2907 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2908 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2909 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2910 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2911 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2912 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2913 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2914 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2915 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2916 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2917 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2918 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2919 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2920 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2921 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2922 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2923 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2924 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2925 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2926 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2927 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2928 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2929 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2930 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2931 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2932 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2933 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2934 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2935 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2936 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2937 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2938 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2939 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2940 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2941 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2942 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2943 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2944 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2945 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2946 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2947 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2948 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2949 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2950 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2951 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2952 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2953 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2954 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2955 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2956 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2957 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2958 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2959 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2960 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2961 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2962 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2963 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2964 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2965 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2966 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
2967 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2968 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2969 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2970 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2971 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2972 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2973 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2974 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2975 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2976 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
2977 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2978 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2979 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2980 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2981 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2982 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
2983 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2984 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2985 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2986 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2987 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2988 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2989 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2990 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2991 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2992 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
2993 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2994 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
2995 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2996 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
2997 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
2998 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
2999 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3000 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
3001 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3002 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
3003 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3004 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
3005 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3006 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
3007 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3008 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
3009 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3010 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF,
3011 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3012 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF,
3013 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3014 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3015 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3016 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3017 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3018 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3019 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3020 ~RS6000_BTI_unsigned_V2DI, 0 },
3021 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3022 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3023 ~RS6000_BTI_unsigned_long_long, 0 },
3024 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF,
3025 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3026 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF,
3027 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3028 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3029 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3030 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3031 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3032 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3033 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3034 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3035 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3036 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3037 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3038 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3039 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3040 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3041 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3042 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3043 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3044 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3045 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3046 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3047 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3048 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3049 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3050 ~RS6000_BTI_unsigned_V16QI, 0 },
3051 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3052 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3053 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3054 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3055 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3056 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
3057 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3058 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
3059 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3060 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3061 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3062 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
3063 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3064 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
3065 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3066 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3067 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3068 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3069 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3070 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3071 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3072 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3073 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3074 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3075 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3076 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3077 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3078 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
3079 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3080 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
3081 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3082 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3083 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3084 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3085 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3086 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3087 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3088 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3089 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3090 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3091 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3092 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3093 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3094 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
3095 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3096 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3097 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3098 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3099 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3100 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3101 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3102 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3103 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3104 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3105 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3106 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3107 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3108 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3109 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3110 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3111 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3112 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3113 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3114 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3115 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3116 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3117 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3118 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3119 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3120 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3121
3122 /* Ternary AltiVec/VSX builtins. */
3123 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3124 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3125 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3126 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3127 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3128 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3129 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3130 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3131 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3132 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3133 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3134 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3135 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3136 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3137 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3138 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3139 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3140 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3141 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3142 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3143 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3144 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3145 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3146 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3147 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3148 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3149 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3150 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3151 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3152 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3153 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3154 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3155 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3156 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3157 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3158 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3159 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3160 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3161 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3162 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3163 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3164 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3165 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3166 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3167 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3168 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3169 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3170 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3171 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3172 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3173 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3174 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3175 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3176 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3177 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3178 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3179 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3180 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3181 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3182 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3183 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3184 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3185 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3186 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3187 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3188 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3189 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3190 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3191 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3192 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3193 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3194 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3195 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3196 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3197 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3198 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3199 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3200 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3201 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3202 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3203 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3204 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3205 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3206 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3207 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3208 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3209 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3210 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3211 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3212 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3213 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3214 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3215 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3216 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3217 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3218 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3219 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3220 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3221 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3222 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3223 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3224 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3225 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3226 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3227 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3228 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3229 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3230 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3231 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3232 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3233 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3234 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3235 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3236 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3237 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3238 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3239 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3240 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3241 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3242 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3243 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3244 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3245 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3246 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3247 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3248 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3249 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3250 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3251 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3252 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3253 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3254 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3255 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3256 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3257 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3258 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3259 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3260 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3261 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3262 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3263 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3264 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3265 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3266 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3267 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3268 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3269 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3270 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3271 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3272 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3273 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3274 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3275 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3276 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3277 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3278 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3279 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3280 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3281 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3282 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3283 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3284 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3285 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3286 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3287 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3288 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3289 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3290 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3291 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3292 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3293 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3294 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3295 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3296 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3297 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3298 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3299 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3300 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3301 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3302 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3303 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3304 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3305 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3306 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3307 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3308 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3309 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3310 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3311 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3312 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3313 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3314 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3315 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3316 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3317 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3318 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3319 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3320 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3321 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3322 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3323 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3324 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3325 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3326 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3327 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3328 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3329 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3330 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3331 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3332 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3333 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3334 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3335 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3336 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3337 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3338 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3339 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3340 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3341 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3342 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3343 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3344 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3345 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3346 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3347 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3348 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3349 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3350 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3351 RS6000_BTI_unsigned_V16QI },
3352 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3353 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3354 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3355 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3356 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3357 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3358 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3359 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3360 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3361 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3362 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3363 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3364 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3365 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3366 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3367 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3368 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3369 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3370 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3371 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3372 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3373 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3374 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3375 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3376 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3377 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3378 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3379 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3380 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3381 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3382 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3383 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3384 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3385 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3386 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3387 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3388 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3389 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3390 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3391 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3392 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3393 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3394 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3395 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3396 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3397 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3398 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3399 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3400 RS6000_BTI_bool_V2DI },
3401 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3402 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3403 RS6000_BTI_unsigned_V2DI },
3404 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3405 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3406 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3407 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3408 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3409 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3410 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3411 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3412 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3413 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3414 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3415 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3416 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3417 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3418 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3419 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3420 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3421 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3422 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3423 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3424 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3425 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3426 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3427 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3428 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3429 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3430 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3431 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3432 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3433 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3434 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3435 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3436 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3437 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3438 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3439 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3440 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3441 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3442 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3443 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3444 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3445 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3446 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3447 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3448 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3449 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3450 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3451 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3452 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3453 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE },
3454 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3455 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
3456 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3457 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3458 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3459 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
3460 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3461 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE },
3462 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3463 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE },
3464 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3465 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3466 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3467 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
3468 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3469 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
3470 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3471 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3472 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3473 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3474 RS6000_BTI_NOT_OPAQUE },
3475 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3476 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3477 RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
3478 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3479 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3480 RS6000_BTI_NOT_OPAQUE },
3481 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3482 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3483 RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
3484 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3485 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3486 RS6000_BTI_NOT_OPAQUE },
3487 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3488 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3489 RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
3490 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3491 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3492 RS6000_BTI_NOT_OPAQUE },
3493 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3494 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3495 RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE },
3496 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3497 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3498 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3499 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3500 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3501 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3502 ~RS6000_BTI_unsigned_V2DI },
3503 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3504 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3505 ~RS6000_BTI_bool_V2DI },
3506 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3507 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3508 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3509 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3510 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3511 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3512 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3513 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3514 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3515 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3516 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3517 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3518 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3519 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3520 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3521 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3522 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3523 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3524 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3525 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3526 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3527 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3528 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3529 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3530 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3531 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3532 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3533 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3534 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3535 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3536 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3537 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3538 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3539 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3540 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3541 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3542 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3543 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3544 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3545 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3546 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3547 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3548 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3549 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3550 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3551 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3552 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3553 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3554 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3555 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3556 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3557 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3558 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3559 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3560 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3561 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3562 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3563 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3564 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3565 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3566 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3567 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3568 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3569 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3570 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3571 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3572 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3573 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3574 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3575 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3576 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3577 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3578 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3579 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3580 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3581 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3582 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3583 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3584 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3585 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3586 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3587 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3588 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3589 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3590 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3591 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3592 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3593 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3594 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3595 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3596 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3597 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3598 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3599 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3600 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3601 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3602 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3603 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3604 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3605 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3606 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3607 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3608 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3609 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3610 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3611 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3612 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3613 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3614 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3615 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3616 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3617 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3618 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3619 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3620 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3621 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3622 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3623 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3624 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3625 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3626 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3627 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3628 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3629 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3630 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3631 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3632 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3633 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3634 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3635 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3636 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3637 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3638 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3639 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3640 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3641 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3642 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3643 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3644 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3645 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3646 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3647 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3648 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3649 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3650 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3651 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3652 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3653 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3654 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3655 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3656 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3657 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3658 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3659 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3660 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3661 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3662 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3663 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3664 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3665 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3666 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3667 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3668 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3669 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3670 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3671 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3672 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3673 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3674 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3675 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3676 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3677 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3678 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3679 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3680 ~RS6000_BTI_unsigned_V2DI },
3681 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3682 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3683 ~RS6000_BTI_bool_V2DI },
3684 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3685 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3686 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3687 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3688 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3689 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3690 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3691 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3692 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3693 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3694 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3695 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3696 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3697 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3698 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3699 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3700 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3701 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3702 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3703 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3704 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3705 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3706 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3707 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3708 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3709 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3710 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3711 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3712 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3713 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3714 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3715 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3716 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3717 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3718 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3719 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3720 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3721 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3722 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3723 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3724 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3725 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3726 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3727 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3728 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3729 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3730 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3731 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3732 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3733 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3734 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3735 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3736 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3737 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3738 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3739 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3740 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3741 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3742 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3743 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3744 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3745 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3746 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3747 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3748 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3749 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3750 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3751 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3752 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3753 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3754 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3755 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3756 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3757 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3758 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3759 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3760 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3761 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3762 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3763 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3764 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3765 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3766 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3767 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3768 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3769 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3770 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3771 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3772 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3773 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3774 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3775 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3776 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3777 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3778 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3779 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3780 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3781 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3782 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3783 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3784 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3785 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3786 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3787 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3788 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3789 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3790 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3791 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3792 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3793 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3794 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3795 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3796 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3797 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3798 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3799 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3800 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3801 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3802 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3803 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3804 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3805 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3806 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3807 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3808 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3809 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3810 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3811 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3812 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3813 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3814 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3815 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3816 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3817 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3818 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3819 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3820 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3821 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3822 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3823 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3824 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3825 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3826 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3827 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3828 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF,
3829 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3830 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF,
3831 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3832 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3833 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3834 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3835 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3836 ~RS6000_BTI_long_long },
3837 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3838 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3839 ~RS6000_BTI_unsigned_V2DI },
3840 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3841 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3842 ~RS6000_BTI_unsigned_long_long },
3843 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF,
3844 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3845 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF,
3846 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3847 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3848 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3849 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3850 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3851 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3852 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3853 ~RS6000_BTI_unsigned_V4SI },
3854 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3855 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3856 ~RS6000_BTI_UINTSI },
3857 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3858 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3859 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3860 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3861 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3862 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3863 ~RS6000_BTI_unsigned_V8HI },
3864 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3865 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3866 ~RS6000_BTI_UINTHI },
3867 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3868 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3869 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3870 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3871 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3872 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3873 ~RS6000_BTI_unsigned_V16QI },
3874 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3875 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3876 ~RS6000_BTI_UINTQI },
3877 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3878 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3879 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3880 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3881 RS6000_BTI_NOT_OPAQUE },
3882 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3883 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3884 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3885 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3886 RS6000_BTI_NOT_OPAQUE },
3887 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3888 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3889 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3890 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3891 RS6000_BTI_NOT_OPAQUE },
3892 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3893 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
3894 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3895 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3896 RS6000_BTI_NOT_OPAQUE },
3897 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
3898 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3899 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
3900 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3901 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
3902 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3903 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3904 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
3905 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3906 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3907 RS6000_BTI_NOT_OPAQUE },
3908 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
3909 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3910 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3911 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3912 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3913 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3914 RS6000_BTI_NOT_OPAQUE },
3915 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3916 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3917 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3918 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3919 RS6000_BTI_NOT_OPAQUE },
3920 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3921 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3922 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3923 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3924 RS6000_BTI_NOT_OPAQUE },
3925
3926 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3927 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3928 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3929 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3930 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3931 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3932 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3933 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3934 ~RS6000_BTI_unsigned_V2DI, 0 },
3935 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3936 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3937 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3938 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3939 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3940 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3941 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3942 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
3943 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3944 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3945 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3946 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3947 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3948 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
3949 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3950 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3951 ~RS6000_BTI_unsigned_V4SI, 0 },
3952 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3953 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3954 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3955 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3956 ~RS6000_BTI_unsigned_long, 0 },
3957 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3958 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
3959 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3960 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
3961 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3962 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3963 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3964 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3965 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3966 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3967 ~RS6000_BTI_unsigned_V8HI, 0 },
3968 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
3969 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3970 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3971 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
3972 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3973 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3974 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3975 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3976 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3977 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3978 ~RS6000_BTI_unsigned_V16QI, 0 },
3979 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
3980 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3981
3982 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3983 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3984 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
3985 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3986 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3987 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3988 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3989 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3990 ~RS6000_BTI_unsigned_V2DI },
3991 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
3992 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3993 ~RS6000_BTI_bool_V2DI },
3994 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3995 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3996 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
3997 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3998 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
3999 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4000 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4001 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4002 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4003 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4004 ~RS6000_BTI_unsigned_V4SI },
4005 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4006 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4007 ~RS6000_BTI_UINTSI },
4008 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4009 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4010 ~RS6000_BTI_bool_V4SI },
4011 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4012 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4013 ~RS6000_BTI_UINTSI },
4014 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4015 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4016 ~RS6000_BTI_INTSI },
4017 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4018 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4019 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4020 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4021 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4022 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4023 ~RS6000_BTI_unsigned_V8HI },
4024 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4025 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4026 ~RS6000_BTI_UINTHI },
4027 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4028 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4029 ~RS6000_BTI_bool_V8HI },
4030 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4031 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4032 ~RS6000_BTI_UINTHI },
4033 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4034 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4035 ~RS6000_BTI_INTHI },
4036 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4037 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4038 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4039 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4040 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4041 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4042 ~RS6000_BTI_unsigned_V16QI },
4043 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4044 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4045 ~RS6000_BTI_UINTQI },
4046 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4047 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4048 ~RS6000_BTI_bool_V16QI },
4049 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4050 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4051 ~RS6000_BTI_UINTQI },
4052 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4053 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4054 ~RS6000_BTI_INTQI },
4055 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4056 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
4057 ~RS6000_BTI_pixel_V8HI },
4058
4059 /* Predicates. */
4060 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4061 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4062 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4063 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4064 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4065 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4066 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4067 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4068 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4069 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4070 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4071 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4072 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4073 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4074 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4075 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4076 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4077 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4078 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4079 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4080 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4081 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4082 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4083 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4084 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4085 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4086 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4087 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4088 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4089 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4090 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4091 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4092 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4093 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4094 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4095 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4096 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4097 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4098 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4099 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4100 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4101 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4102 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4103 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4104 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4105 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4106 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4107 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4108 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
4109 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4110 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4111 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4112
4113
4114 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4115 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4116 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4117 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4118 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4119 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4120 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4121 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4122 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4123 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4124 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4125 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4126 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4127 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4128 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4129 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4130 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4131 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4132 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4133 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4134 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4135 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4136 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4137 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4138 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4139 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4140 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4141 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4142 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4143 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4144 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4145 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4146 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4147 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4148 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4149 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4150 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4151 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4152 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4153 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4154 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4155 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4156 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4157 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4158 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4159 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4160 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4161 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4162 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4163 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4164 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4165 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4166 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4167 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4168 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4169 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4170 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4171 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4172 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4173 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4174 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4175 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4176
4177
4178 /* cmpge is the same as cmpgt for all cases except floating point.
4179 There is further code to deal with this special case in
4180 altivec_build_resolved_builtin. */
4181 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4182 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4183 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4184 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4185 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4186 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4187 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4188 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4189 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4190 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4191 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4192 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4193 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4194 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4195 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4196 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4197 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4198 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4199 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4200 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4201 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4202 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4203 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4204 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4205 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4206 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4207 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4208 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4209 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4210 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4211 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4212 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4213 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4214 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4215 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4216 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4217 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4218 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4219 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4220 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4221 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4222 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4223 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4224 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4225 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4226 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4227 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4228 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4229 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4230 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4231 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4232 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4233
4234 /* Power8 vector overloaded functions. */
4235 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4236 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4237 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4238 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4239 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4240 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4241 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4242 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4243 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4244 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4245 RS6000_BTI_unsigned_V16QI, 0 },
4246 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4247 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4248 RS6000_BTI_bool_V16QI, 0 },
4249 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4250 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4251 RS6000_BTI_unsigned_V16QI, 0 },
4252 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4253 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4254 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4255 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4256 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4257 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4258 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4259 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4260 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4261 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4262 RS6000_BTI_unsigned_V8HI, 0 },
4263 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4264 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4265 RS6000_BTI_bool_V8HI, 0 },
4266 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4267 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4268 RS6000_BTI_unsigned_V8HI, 0 },
4269 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4270 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4271 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4272 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4273 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4274 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4275 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4276 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4277 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4278 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4279 RS6000_BTI_unsigned_V4SI, 0 },
4280 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4281 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4282 RS6000_BTI_bool_V4SI, 0 },
4283 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4284 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4285 RS6000_BTI_unsigned_V4SI, 0 },
4286 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4287 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4288 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4289 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4290 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4291 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4292 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4293 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4294 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4295 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4296 RS6000_BTI_unsigned_V2DI, 0 },
4297 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4298 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4299 RS6000_BTI_bool_V2DI, 0 },
4300 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4301 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4302 RS6000_BTI_unsigned_V2DI, 0 },
4303 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4304 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4305 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4306 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4307
4308 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4309 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4310 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4311 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4312 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4313 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4314 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4315 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4316 RS6000_BTI_unsigned_V16QI, 0 },
4317 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4318 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4319 RS6000_BTI_bool_V16QI, 0 },
4320 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4321 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4322 RS6000_BTI_unsigned_V16QI, 0 },
4323 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4324 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4325 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4326 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4327 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4328 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4329 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4330 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4331 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4332 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4333 RS6000_BTI_unsigned_V8HI, 0 },
4334 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4335 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4336 RS6000_BTI_bool_V8HI, 0 },
4337 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4338 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4339 RS6000_BTI_unsigned_V8HI, 0 },
4340 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4341 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4342 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4343 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4344 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4345 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4346 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4347 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4348 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4349 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4350 RS6000_BTI_unsigned_V4SI, 0 },
4351 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4352 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4353 RS6000_BTI_bool_V4SI, 0 },
4354 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4355 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4356 RS6000_BTI_unsigned_V4SI, 0 },
4357 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4358 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4359 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4360 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4361 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4362 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4363 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4364 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4365 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4366 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4367 RS6000_BTI_unsigned_V2DI, 0 },
4368 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4369 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4370 RS6000_BTI_bool_V2DI, 0 },
4371 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4372 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4373 RS6000_BTI_unsigned_V2DI, 0 },
4374 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4375 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4376 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4377 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4378 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4379 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4380
4381 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4382 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4383 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4384 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4385 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4386 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4387 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4388 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4389 RS6000_BTI_unsigned_V16QI, 0 },
4390 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4391 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4392 RS6000_BTI_bool_V16QI, 0 },
4393 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4394 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4395 RS6000_BTI_unsigned_V16QI, 0 },
4396 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4397 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4398 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4399 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4400 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4401 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4402 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4403 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4404 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4405 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4406 RS6000_BTI_unsigned_V8HI, 0 },
4407 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4408 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4409 RS6000_BTI_bool_V8HI, 0 },
4410 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4411 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4412 RS6000_BTI_unsigned_V8HI, 0 },
4413 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4414 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4415 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4416 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4417 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4418 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4419 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4420 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4421 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4422 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4423 RS6000_BTI_unsigned_V4SI, 0 },
4424 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4425 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4426 RS6000_BTI_bool_V4SI, 0 },
4427 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4428 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4429 RS6000_BTI_unsigned_V4SI, 0 },
4430 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4431 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4432 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4433 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4434 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4435 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4436 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4437 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4438 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4439 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4440 RS6000_BTI_unsigned_V2DI, 0 },
4441 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4442 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4443 RS6000_BTI_bool_V2DI, 0 },
4444 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4445 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4446 RS6000_BTI_unsigned_V2DI, 0 },
4447 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4448 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4449 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4450 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4451 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4452 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4453
4454 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4455 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4456 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4457 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4458 RS6000_BTI_unsigned_V1TI, 0 },
4459
4460 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4461 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4462 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4463 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4464 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4465 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4466 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4467 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4468 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4469 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4470 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4471 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4472
4473 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4474 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4475 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4476 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4477 RS6000_BTI_unsigned_V1TI, 0 },
4478
4479 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4480 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4481 RS6000_BTI_unsigned_V16QI, 0 },
4482 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4483 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4484 RS6000_BTI_unsigned_V16QI, 0 },
4485 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4486 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4487 RS6000_BTI_unsigned_V16QI, 0 },
4488
4489 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4490 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4491 RS6000_BTI_unsigned_V16QI, 0 },
4492 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4493 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4494 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4495 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4496 RS6000_BTI_unsigned_V16QI, 0 },
4497 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4498 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4499 RS6000_BTI_unsigned_V16QI, 0 },
4500
4501 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4502 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4503 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4504 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4505 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4506 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4507 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4508 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4509 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4510 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4511 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4512 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4513 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4514 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4515 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4516 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4517
4518 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4519 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4520 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4521 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4522
4523 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4524 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4525 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4526 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4527
4528 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4529 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4530 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4531 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4532
4533 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4534 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4535 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4536 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4537
4538 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4539 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4540 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4541 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4542
4543 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4544 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4545 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4546 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4547
4548 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4549 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4550 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4551 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4552
4553 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4554 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4555 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4556 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4557
4558 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4559 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4560 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4561 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4562
4563 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4564 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4565 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4566 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4567
4568 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4569 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4570 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4571 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4572
4573 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4574 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4575 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4576 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4577
4578 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4579 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4580 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4581 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4582 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4583 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4584 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4585 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4586 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4587 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4588 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4589 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4590 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4591 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4592 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4593 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4594
4595 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4596 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4597 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4598 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4599
4600 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4601 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4602 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4603 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4604
4605 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4606 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4607 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4608 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4609
4610 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4611 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4612 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4613 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4614
4615 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4616 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4617 RS6000_BTI_unsigned_V16QI, 0 },
4618 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4619 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4620 RS6000_BTI_unsigned_V8HI, 0 },
4621 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4622 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4623 RS6000_BTI_unsigned_V4SI, 0 },
4624
4625 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4626 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4627 RS6000_BTI_unsigned_V16QI, 0 },
4628
4629 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4630 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4631 RS6000_BTI_unsigned_V8HI, 0 },
4632
4633 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4634 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4635 RS6000_BTI_unsigned_V4SI, 0 },
4636
4637 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
4638 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4639 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
4640 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4641
4642 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
4643 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4644 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
4645 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4646
4647 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
4648 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4649 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
4650 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4651
4652 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
4653 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4654 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
4655 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4656
4657 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
4658 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4659 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
4660 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4661
4662 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
4663 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4664 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
4665 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4666
4667 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4668 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4669 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4670 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4671
4672 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4673 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4674 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4675 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4676
4677 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4678 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4679 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4680 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4681
4682 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4683 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4684 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4685 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4686
4687 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
4688 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4689 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
4690 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4691
4692 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
4693 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4694 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
4695 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4696
4697 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
4698 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4699 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
4700 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4701
4702 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
4703 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4704 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
4705 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4706
4707 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
4708 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4709
4710 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
4711 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4712
4713 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
4714 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
4715 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
4716 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
4717
4718 { P9V_BUILTIN_VEC_VSCEDPGT, P9V_BUILTIN_VSCEDPGT,
4719 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4720 { P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VSCEDPLT,
4721 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4722 { P9V_BUILTIN_VEC_VSCEDPEQ, P9V_BUILTIN_VSCEDPEQ,
4723 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4724 { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
4725 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4726
4727 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4728 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4729 RS6000_BTI_unsigned_long_long, 0 },
4730 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4731 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4732 RS6000_BTI_unsigned_long_long, 0 },
4733
4734 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4735 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4736 RS6000_BTI_unsigned_long_long, 0 },
4737 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4738 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4739 RS6000_BTI_unsigned_long_long, 0 },
4740
4741 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4742 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4743 RS6000_BTI_unsigned_long_long, 0 },
4744 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4745 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4746 RS6000_BTI_unsigned_long_long, 0 },
4747
4748 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4749 RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4750 RS6000_BTI_unsigned_long_long, 0 },
4751 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4752 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4753 RS6000_BTI_unsigned_long_long, 0 },
4754
4755 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4756 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4757 RS6000_BTI_unsigned_long_long, 0 },
4758 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4759 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4760 RS6000_BTI_unsigned_long_long, 0 },
4761
4762 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4763 RS6000_BTI_V2DF, ~RS6000_BTI_double,
4764 RS6000_BTI_unsigned_long_long, 0 },
4765 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4766 RS6000_BTI_V4SF, ~RS6000_BTI_float,
4767 RS6000_BTI_unsigned_long_long, 0 },
4768 /* At an appropriate future time, add support for the
4769 RS6000_BTI_Float16 (exact name to be determined) type here. */
4770
4771 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4772 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4773 RS6000_BTI_unsigned_long_long },
4774 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4775 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4776 RS6000_BTI_unsigned_long_long },
4777
4778 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4779 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4780 RS6000_BTI_unsigned_long_long },
4781 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4782 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4783 RS6000_BTI_unsigned_long_long },
4784
4785 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4786 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4787 RS6000_BTI_unsigned_long_long },
4788 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4789 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4790 RS6000_BTI_unsigned_long_long },
4791
4792 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4793 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4794 RS6000_BTI_unsigned_long_long },
4795 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4796 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4797 RS6000_BTI_unsigned_long_long },
4798
4799 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4800 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4801 RS6000_BTI_unsigned_long_long },
4802 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4803 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4804 RS6000_BTI_unsigned_long_long },
4805
4806 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4807 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
4808 RS6000_BTI_unsigned_long_long },
4809 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4810 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
4811 RS6000_BTI_unsigned_long_long },
4812 /* At an appropriate future time, add support for the
4813 RS6000_BTI_Float16 (exact name to be determined) type here. */
4814
4815 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4816 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
4817 RS6000_BTI_bool_V16QI, 0 },
4818 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4819 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4820 RS6000_BTI_V16QI, 0 },
4821 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4822 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4823 RS6000_BTI_unsigned_V16QI, 0 },
4824
4825 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4826 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
4827 RS6000_BTI_bool_V8HI, 0 },
4828 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4829 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4830 RS6000_BTI_V8HI, 0 },
4831 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4832 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4833 RS6000_BTI_unsigned_V8HI, 0 },
4834
4835 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4836 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
4837 RS6000_BTI_bool_V4SI, 0 },
4838 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4839 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
4840 RS6000_BTI_V4SI, 0 },
4841 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4842 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
4843 RS6000_BTI_unsigned_V4SI, 0 },
4844
4845 /* The following 2 entries have been deprecated. */
4846 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4847 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4848 RS6000_BTI_unsigned_V16QI, 0 },
4849 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4850 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4851 RS6000_BTI_bool_V16QI, 0 },
4852 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4853 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4854 RS6000_BTI_unsigned_V16QI, 0 },
4855
4856 /* The following 2 entries have been deprecated. */
4857 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4858 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4859 RS6000_BTI_V16QI, 0 },
4860 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4861 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4862 RS6000_BTI_bool_V16QI, 0 },
4863 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4864 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4865 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4866 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4867 RS6000_BTI_bool_V16QI, 0 },
4868
4869 /* The following 2 entries have been deprecated. */
4870 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4871 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4872 RS6000_BTI_unsigned_V8HI, 0 },
4873 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4874 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4875 RS6000_BTI_bool_V8HI, 0 },
4876 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4877 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4878 RS6000_BTI_unsigned_V8HI, 0 },
4879 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4880 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4881
4882 /* The following 2 entries have been deprecated. */
4883 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4884 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4885 RS6000_BTI_V8HI, 0 },
4886 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4887 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4888 RS6000_BTI_bool_V8HI, 0 },
4889 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4890 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4891 RS6000_BTI_bool_V8HI, 0 },
4892 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4893 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4894 RS6000_BTI_pixel_V8HI, 0 },
4895
4896 /* The following 2 entries have been deprecated. */
4897 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4898 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4899 RS6000_BTI_unsigned_V4SI, 0 },
4900 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4901 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4902 RS6000_BTI_bool_V4SI, 0 },
4903 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4904 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4905 RS6000_BTI_unsigned_V4SI, 0 },
4906
4907 /* The following 2 entries have been deprecated. */
4908 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4909 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4910 RS6000_BTI_V4SI, 0 },
4911 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4912 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4913 RS6000_BTI_bool_V4SI, 0 },
4914 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4915 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4916 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4917 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4918 RS6000_BTI_bool_V4SI, 0 },
4919
4920 /* The following 2 entries have been deprecated. */
4921 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4922 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4923 RS6000_BTI_unsigned_V2DI, 0 },
4924 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4925 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4926 RS6000_BTI_bool_V2DI, 0 },
4927 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4928 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
4929 RS6000_BTI_unsigned_V2DI, 0
4930 },
4931
4932 /* The following 2 entries have been deprecated. */
4933 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4934 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4935 RS6000_BTI_V2DI, 0 },
4936 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4937 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
4938 RS6000_BTI_bool_V2DI, 0 },
4939 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4940 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4941 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
4942 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
4943 RS6000_BTI_bool_V2DI, 0 },
4944
4945 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
4946 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4947 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
4948 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4949
4950 /* The following 2 entries have been deprecated. */
4951 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4952 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4953 RS6000_BTI_unsigned_V16QI, 0 },
4954 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4955 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4956 RS6000_BTI_bool_V16QI, 0 },
4957 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4958 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4959 RS6000_BTI_unsigned_V16QI, 0 },
4960
4961 /* The following 2 entries have been deprecated. */
4962 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4963 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4964 RS6000_BTI_V16QI, 0 },
4965 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4966 RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4967 RS6000_BTI_bool_V16QI, 0 },
4968 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4969 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4970 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
4971 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4972 RS6000_BTI_bool_V16QI, 0 },
4973
4974 /* The following 2 entries have been deprecated. */
4975 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4976 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4977 RS6000_BTI_unsigned_V8HI, 0 },
4978 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4979 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4980 RS6000_BTI_bool_V8HI, 0 },
4981 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4982 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4983 RS6000_BTI_unsigned_V8HI, 0 },
4984 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4985 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4986
4987 /* The following 2 entries have been deprecated. */
4988 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4989 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4990 RS6000_BTI_V8HI, 0 },
4991 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4992 RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4993 RS6000_BTI_bool_V8HI, 0 },
4994 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4995 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4996 RS6000_BTI_bool_V8HI, 0 },
4997 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
4998 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4999 RS6000_BTI_pixel_V8HI, 0 },
5000
5001 /* The following 2 entries have been deprecated. */
5002 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5003 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5004 RS6000_BTI_unsigned_V4SI, 0 },
5005 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5006 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5007 RS6000_BTI_bool_V4SI, 0 },
5008 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5009 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5010 RS6000_BTI_unsigned_V4SI, 0 },
5011
5012 /* The following 2 entries have been deprecated. */
5013 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5014 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5015 RS6000_BTI_V4SI, 0 },
5016 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5017 RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5018 RS6000_BTI_bool_V4SI, 0 },
5019 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5020 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5021 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5022 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5023 RS6000_BTI_bool_V4SI, 0 },
5024
5025 /* The following 2 entries have been deprecated. */
5026 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5027 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5028 RS6000_BTI_unsigned_V2DI, 0 },
5029 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5030 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5031 RS6000_BTI_bool_V2DI, 0 },
5032 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5033 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5034 RS6000_BTI_unsigned_V2DI, 0
5035 },
5036
5037 /* The following 2 entries have been deprecated. */
5038 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5039 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5040 RS6000_BTI_V2DI, 0 },
5041 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5042 RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5043 RS6000_BTI_bool_V2DI, 0 },
5044 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5045 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5046 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5047 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5048 RS6000_BTI_bool_V2DI, 0 },
5049
5050 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
5051 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5052 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
5053 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5054
5055 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5056 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5057 RS6000_BTI_unsigned_V16QI },
5058 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5059 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
5060
5061 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5062 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5063 RS6000_BTI_unsigned_V8HI },
5064 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5065 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
5066
5067 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5068 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5069 RS6000_BTI_unsigned_V4SI },
5070 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5071 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
5072
5073 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5074 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5075 RS6000_BTI_V16QI, 0 },
5076 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5077 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5078 RS6000_BTI_unsigned_V16QI, 0 },
5079
5080 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5081 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5082 RS6000_BTI_V8HI, 0 },
5083 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5084 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5085 RS6000_BTI_unsigned_V8HI, 0 },
5086
5087 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5088 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5089 RS6000_BTI_V4SI, 0 },
5090 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5091 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5092 RS6000_BTI_unsigned_V4SI, 0 },
5093
5094 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5095 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5096 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5097 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5098
5099 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
5100 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5101 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
5102 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5103
5104 { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
5105 RS6000_BTI_INTDI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
5106 { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
5107 RS6000_BTI_INTDI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI, 0 },
5108
5109 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5110 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5111 RS6000_BTI_V16QI, 0 },
5112 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5113 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5114 RS6000_BTI_unsigned_V16QI, 0 },
5115
5116 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5117 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5118 RS6000_BTI_V8HI, 0 },
5119 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5120 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5121 RS6000_BTI_unsigned_V8HI, 0 },
5122
5123 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5124 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5125 RS6000_BTI_V4SI, 0 },
5126 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5127 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5128 RS6000_BTI_unsigned_V4SI, 0 },
5129 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5130 RS6000_BTI_float, RS6000_BTI_UINTSI,
5131 RS6000_BTI_V4SF, 0 },
5132
5133 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5134 RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5135 RS6000_BTI_V16QI, 0 },
5136 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5137 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5138 RS6000_BTI_unsigned_V16QI, 0 },
5139
5140 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5141 RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5142 RS6000_BTI_V8HI, 0 },
5143 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5144 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5145 RS6000_BTI_unsigned_V8HI, 0 },
5146
5147 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5148 RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5149 RS6000_BTI_V4SI, 0 },
5150 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5151 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5152 RS6000_BTI_unsigned_V4SI, 0 },
5153 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5154 RS6000_BTI_float, RS6000_BTI_UINTSI,
5155 RS6000_BTI_V4SF, 0 },
5156
5157 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5158 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5159 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5160 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5161
5162 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5163 RS6000_BTI_V16QI, RS6000_BTI_V4SI,
5164 RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5165 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5166 RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI,
5167 RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5168 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5169 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5170 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
5171 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5172 RS6000_BTI_V16QI, RS6000_BTI_INTDI,
5173 RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5174 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5175 RS6000_BTI_V16QI, RS6000_BTI_UINTDI,
5176 RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5177 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5178 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTDI,
5179 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5180 { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5181 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI,
5182 RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5183
5184 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5185 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5186 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5187 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5188 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5189
5190 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5191 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5192 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5193 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5194 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5195
5196 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5197 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5198 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5199 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5200 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5201
5202 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5203 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5204 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5205 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5206 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5207
5208 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5209 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5210 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5211 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5212 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5213 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5214
5215 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5216 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5217 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5218 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5219 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5220 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5221
5222 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5223 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5224 RS6000_BTI_unsigned_V2DI, 0 },
5225 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5226 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5227 RS6000_BTI_bool_V2DI, 0 },
5228 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5229 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5230 RS6000_BTI_unsigned_V2DI, 0 },
5231
5232 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5233 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5234 RS6000_BTI_unsigned_V2DI, 0 },
5235 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5236 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5237 RS6000_BTI_bool_V2DI, 0 },
5238 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5239 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5240 RS6000_BTI_unsigned_V2DI, 0 },
5241
5242 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
5243 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5244 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
5245 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5246 RS6000_BTI_unsigned_V4SI, 0 },
5247 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW,
5248 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5249
5250 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5251 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5252 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5253 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5254 RS6000_BTI_unsigned_V4SI, 0 },
5255 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5256 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5257
5258 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5259 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5260 RS6000_BTI_unsigned_V16QI, 0 },
5261 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5262 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5263 RS6000_BTI_unsigned_V8HI, 0 },
5264 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5265 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5266 RS6000_BTI_unsigned_V4SI, 0 },
5267 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5268 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5269 RS6000_BTI_unsigned_V2DI, 0 },
5270
5271 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5272 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5273 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5274 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5275 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5276 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5277 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5278 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5279 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5280 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5281 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5282 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5283 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5284 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5285 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5286 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5287
5288 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5289 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5290 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5291 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5292
5293 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5294 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5295 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5296 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5297
5298 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5299 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5300 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5301 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5302
5303 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5304 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5305 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5306 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5307
5308 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5309 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5310 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5311 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5312
5313 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5314 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5315 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5316 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5317
5318 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5319 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5320 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5321 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5322
5323 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5324 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5325 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5326 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5327
5328 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5329 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5330 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5331 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5332 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5333 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5334 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5335 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5336 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5337 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5338 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5339 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5340 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5341 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5342 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5343 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5344
5345 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5346 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5347 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5348 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5349
5350 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5351 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5352 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5353 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5354
5355 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5356 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5357 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5358 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5359 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5360 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5361 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5362 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5363
5364 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5365 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5366 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5367 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5368 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5369 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5370
5371 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5372 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5373 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5374 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5375 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5376 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5377
5378 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5379 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5380
5381 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5382 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5383
5384 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5385 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5386
5387 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5388 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5389 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5390 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5391
5392 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5393 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5394 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5395 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5396
5397 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5398 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5399 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5400 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5401
5402 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5403 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5404 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5405 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5406
5407 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5408 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5409 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5410 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5411 RS6000_BTI_unsigned_V1TI, 0 },
5412
5413 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5414 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5415 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5416 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5417 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5418 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5419 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5420 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5421 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5422 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5423 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5424 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5425
5426 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5427 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5428 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5429 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5430 RS6000_BTI_unsigned_V1TI, 0 },
5431
5432 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5433 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5434 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5435 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5436
5437 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5438 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5439 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5440 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5441
5442 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5443 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5444 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5445 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5446
5447 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5448 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5449 RS6000_BTI_unsigned_V16QI, 0 },
5450 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5451 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5452 RS6000_BTI_unsigned_V16QI, 0 },
5453
5454 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5455 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5456 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5457 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5458 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5459 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5460 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5461 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5462 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5463 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5464 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5465 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5466 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DF,
5467 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5468 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5469 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5470 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5471 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5472 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SF,
5473 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5474 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5475 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5476 { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5477 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5478
5479 /* Crypto builtins. */
5480 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5481 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5482 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5483 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5484 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5485 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5486 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5487 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5488 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5489 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5490 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5491 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5492
5493 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5494 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5495 RS6000_BTI_unsigned_V16QI, 0 },
5496 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5497 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5498 RS6000_BTI_unsigned_V8HI, 0 },
5499 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5500 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5501 RS6000_BTI_unsigned_V4SI, 0 },
5502 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5503 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5504 RS6000_BTI_unsigned_V2DI, 0 },
5505
5506 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5507 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5508 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5509 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5510 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5511 RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5512
5513 { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
5514 };
5515
5516
5517 /* Convert a type stored into a struct altivec_builtin_types as ID,
5518 into a tree. The types are in rs6000_builtin_types: negative values
5519 create a pointer type for the type associated to ~ID. Note it is
5520 a logical NOT, rather than a negation, otherwise you cannot represent
5521 a pointer type for ID 0. */
5522
5523 static inline tree
rs6000_builtin_type(int id)5524 rs6000_builtin_type (int id)
5525 {
5526 tree t;
5527 t = rs6000_builtin_types[id < 0 ? ~id : id];
5528 return id < 0 ? build_pointer_type (t) : t;
5529 }
5530
5531 /* Check whether the type of an argument, T, is compatible with a
5532 type ID stored into a struct altivec_builtin_types. Integer
5533 types are considered compatible; otherwise, the language hook
5534 lang_hooks.types_compatible_p makes the decision. */
5535
5536 static inline bool
rs6000_builtin_type_compatible(tree t,int id)5537 rs6000_builtin_type_compatible (tree t, int id)
5538 {
5539 tree builtin_type;
5540 builtin_type = rs6000_builtin_type (id);
5541 if (t == error_mark_node)
5542 return false;
5543 if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type))
5544 return true;
5545 else
5546 return lang_hooks.types_compatible_p (t, builtin_type);
5547 }
5548
5549
5550 /* In addition to calling fold_convert for EXPR of type TYPE, also
5551 call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be
5552 hiding there (PR47197). */
5553
5554 static tree
fully_fold_convert(tree type,tree expr)5555 fully_fold_convert (tree type, tree expr)
5556 {
5557 tree result = fold_convert (type, expr);
5558 bool maybe_const = true;
5559
5560 if (!c_dialect_cxx ())
5561 result = c_fully_fold (result, false, &maybe_const);
5562
5563 return result;
5564 }
5565
5566 /* Build a tree for a function call to an Altivec non-overloaded builtin.
5567 The overloaded builtin that matched the types and args is described
5568 by DESC. The N arguments are given in ARGS, respectively.
5569
5570 Actually the only thing it does is calling fold_convert on ARGS, with
5571 a small exception for vec_{all,any}_{ge,le} predicates. */
5572
5573 static tree
altivec_build_resolved_builtin(tree * args,int n,const struct altivec_builtin_types * desc)5574 altivec_build_resolved_builtin (tree *args, int n,
5575 const struct altivec_builtin_types *desc)
5576 {
5577 tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code];
5578 tree ret_type = rs6000_builtin_type (desc->ret_type);
5579 tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl));
5580 tree arg_type[3];
5581 tree call;
5582
5583 int i;
5584 for (i = 0; i < n; i++)
5585 arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes);
5586
5587 /* The AltiVec overloading implementation is overall gross, but this
5588 is particularly disgusting. The vec_{all,any}_{ge,le} builtins
5589 are completely different for floating-point vs. integer vector
5590 types, because the former has vcmpgefp, but the latter should use
5591 vcmpgtXX.
5592
5593 In practice, the second and third arguments are swapped, and the
5594 condition (LT vs. EQ, which is recognizable by bit 1 of the first
5595 argument) is reversed. Patch the arguments here before building
5596 the resolved CALL_EXPR. */
5597 if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
5598 && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P
5599 && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P)
5600 {
5601 tree t;
5602 t = args[2], args[2] = args[1], args[1] = t;
5603 t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t;
5604
5605 args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0],
5606 build_int_cst (NULL_TREE, 2));
5607 }
5608
5609 switch (n)
5610 {
5611 case 0:
5612 call = build_call_expr (impl_fndecl, 0);
5613 break;
5614 case 1:
5615 call = build_call_expr (impl_fndecl, 1,
5616 fully_fold_convert (arg_type[0], args[0]));
5617 break;
5618 case 2:
5619 call = build_call_expr (impl_fndecl, 2,
5620 fully_fold_convert (arg_type[0], args[0]),
5621 fully_fold_convert (arg_type[1], args[1]));
5622 break;
5623 case 3:
5624 call = build_call_expr (impl_fndecl, 3,
5625 fully_fold_convert (arg_type[0], args[0]),
5626 fully_fold_convert (arg_type[1], args[1]),
5627 fully_fold_convert (arg_type[2], args[2]));
5628 break;
5629 default:
5630 gcc_unreachable ();
5631 }
5632 return fold_convert (ret_type, call);
5633 }
5634
5635 /* Implementation of the resolve_overloaded_builtin target hook, to
5636 support Altivec's overloaded builtins. */
5637
5638 tree
altivec_resolve_overloaded_builtin(location_t loc,tree fndecl,void * passed_arglist)5639 altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
5640 void *passed_arglist)
5641 {
5642 vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist);
5643 unsigned int nargs = vec_safe_length (arglist);
5644 enum rs6000_builtins fcode
5645 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
5646 tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl));
5647 tree types[3], args[3];
5648 const struct altivec_builtin_types *desc;
5649 unsigned int n;
5650
5651 if (!rs6000_overloaded_builtin_p (fcode))
5652 return NULL_TREE;
5653
5654 if (TARGET_DEBUG_BUILTIN)
5655 fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
5656 (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
5657
5658 /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */
5659 if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG)
5660 warning (OPT_Wdeprecated,
5661 "vec_lvsl is deprecated for little endian; use "
5662 "assignment for unaligned loads and stores");
5663 else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG)
5664 warning (OPT_Wdeprecated,
5665 "vec_lvsr is deprecated for little endian; use "
5666 "assignment for unaligned loads and stores");
5667
5668 if (fcode == ALTIVEC_BUILTIN_VEC_MUL)
5669 {
5670 /* vec_mul needs to be special cased because there are no instructions
5671 for it for the {un}signed char, {un}signed short, and {un}signed int
5672 types. */
5673 if (nargs != 2)
5674 {
5675 error ("vec_mul only accepts 2 arguments");
5676 return error_mark_node;
5677 }
5678
5679 tree arg0 = (*arglist)[0];
5680 tree arg0_type = TREE_TYPE (arg0);
5681 tree arg1 = (*arglist)[1];
5682 tree arg1_type = TREE_TYPE (arg1);
5683
5684 /* Both arguments must be vectors and the types must be compatible. */
5685 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5686 goto bad;
5687 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
5688 goto bad;
5689
5690 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5691 {
5692 case E_QImode:
5693 case E_HImode:
5694 case E_SImode:
5695 case E_DImode:
5696 case E_TImode:
5697 {
5698 /* For scalar types just use a multiply expression. */
5699 return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0,
5700 fold_convert (TREE_TYPE (arg0), arg1));
5701 }
5702 case E_SFmode:
5703 {
5704 /* For floats use the xvmulsp instruction directly. */
5705 tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
5706 return build_call_expr (call, 2, arg0, arg1);
5707 }
5708 case E_DFmode:
5709 {
5710 /* For doubles use the xvmuldp instruction directly. */
5711 tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
5712 return build_call_expr (call, 2, arg0, arg1);
5713 }
5714 /* Other types are errors. */
5715 default:
5716 goto bad;
5717 }
5718 }
5719
5720 if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE)
5721 {
5722 /* vec_cmpne needs to be special cased because there are no instructions
5723 for it (prior to power 9). */
5724 if (nargs != 2)
5725 {
5726 error ("vec_cmpne only accepts 2 arguments");
5727 return error_mark_node;
5728 }
5729
5730 tree arg0 = (*arglist)[0];
5731 tree arg0_type = TREE_TYPE (arg0);
5732 tree arg1 = (*arglist)[1];
5733 tree arg1_type = TREE_TYPE (arg1);
5734
5735 /* Power9 instructions provide the most efficient implementation of
5736 ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode
5737 or SFmode or DFmode. */
5738 if (!TARGET_P9_VECTOR
5739 || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
5740 || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode)
5741 || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode)
5742 || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode))
5743 {
5744 /* Both arguments must be vectors and the types must be compatible. */
5745 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5746 goto bad;
5747 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
5748 goto bad;
5749
5750 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5751 {
5752 /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
5753 vec_cmpeq (va, vb)). */
5754 /* Note: vec_nand also works but opt changes vec_nand's
5755 to vec_nor's anyway. */
5756 case E_QImode:
5757 case E_HImode:
5758 case E_SImode:
5759 case E_DImode:
5760 case E_TImode:
5761 case E_SFmode:
5762 case E_DFmode:
5763 {
5764 /* call = vec_cmpeq (va, vb)
5765 result = vec_nor (call, call). */
5766 vec<tree, va_gc> *params = make_tree_vector ();
5767 vec_safe_push (params, arg0);
5768 vec_safe_push (params, arg1);
5769 tree call = altivec_resolve_overloaded_builtin
5770 (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
5771 params);
5772 /* Use save_expr to ensure that operands used more than once
5773 that may have side effects (like calls) are only evaluated
5774 once. */
5775 call = save_expr (call);
5776 params = make_tree_vector ();
5777 vec_safe_push (params, call);
5778 vec_safe_push (params, call);
5779 return altivec_resolve_overloaded_builtin
5780 (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
5781 }
5782 /* Other types are errors. */
5783 default:
5784 goto bad;
5785 }
5786 }
5787 /* else, fall through and process the Power9 alternative below */
5788 }
5789
5790 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
5791 {
5792 /* vec_adde needs to be special cased because there is no instruction
5793 for the {un}signed int version. */
5794 if (nargs != 3)
5795 {
5796 error ("vec_adde only accepts 3 arguments");
5797 return error_mark_node;
5798 }
5799
5800 tree arg0 = (*arglist)[0];
5801 tree arg0_type = TREE_TYPE (arg0);
5802 tree arg1 = (*arglist)[1];
5803 tree arg1_type = TREE_TYPE (arg1);
5804 tree arg2 = (*arglist)[2];
5805 tree arg2_type = TREE_TYPE (arg2);
5806
5807 /* All 3 arguments must be vectors of (signed or unsigned) (int or
5808 __int128) and the types must be compatible. */
5809 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5810 goto bad;
5811 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type) ||
5812 !lang_hooks.types_compatible_p (arg1_type, arg2_type))
5813 goto bad;
5814
5815 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5816 {
5817 /* For {un}signed ints,
5818 vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
5819 vec_and (carryv, 0x1)). */
5820 case E_SImode:
5821 {
5822 vec<tree, va_gc> *params = make_tree_vector ();
5823 vec_safe_push (params, arg0);
5824 vec_safe_push (params, arg1);
5825 tree add_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
5826 tree call = altivec_resolve_overloaded_builtin (loc, add_builtin,
5827 params);
5828 tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
5829 tree ones_vector = build_vector_from_val (arg0_type, const1);
5830 tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
5831 arg2, ones_vector);
5832 params = make_tree_vector ();
5833 vec_safe_push (params, call);
5834 vec_safe_push (params, and_expr);
5835 return altivec_resolve_overloaded_builtin (loc, add_builtin,
5836 params);
5837 }
5838 /* For {un}signed __int128s use the vaddeuqm instruction
5839 directly. */
5840 case E_TImode:
5841 {
5842 tree adde_bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM];
5843 return altivec_resolve_overloaded_builtin (loc, adde_bii,
5844 arglist);
5845 }
5846
5847 /* Types other than {un}signed int and {un}signed __int128
5848 are errors. */
5849 default:
5850 goto bad;
5851 }
5852 }
5853
5854 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
5855 {
5856 /* vec_addec needs to be special cased because there is no instruction
5857 for the {un}signed int version. */
5858 if (nargs != 3)
5859 {
5860 error ("vec_addec only accepts 3 arguments");
5861 return error_mark_node;
5862 }
5863
5864 tree arg0 = (*arglist)[0];
5865 tree arg0_type = TREE_TYPE (arg0);
5866 tree arg1 = (*arglist)[1];
5867 tree arg1_type = TREE_TYPE (arg1);
5868 tree arg2 = (*arglist)[2];
5869 tree arg2_type = TREE_TYPE (arg2);
5870
5871 /* All 3 arguments must be vectors of (signed or unsigned) (int or
5872 __int128) and the types must be compatible. */
5873 if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5874 goto bad;
5875 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type) ||
5876 !lang_hooks.types_compatible_p (arg1_type, arg2_type))
5877 goto bad;
5878
5879 switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5880 {
5881 /* For {un}signed ints,
5882 vec_addec (va, vb, carryv) ==
5883 vec_or (vec_addc (va, vb),
5884 vec_addc (vec_add (va, vb),
5885 vec_and (carryv, 0x1))). */
5886 case E_SImode:
5887 {
5888 /* Use save_expr to ensure that operands used more than once
5889 that may have side effects (like calls) are only evaluated
5890 once. */
5891 arg0 = save_expr (arg0);
5892 arg1 = save_expr (arg1);
5893 vec<tree, va_gc> *params = make_tree_vector ();
5894 vec_safe_push (params, arg0);
5895 vec_safe_push (params, arg1);
5896 tree addc_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC];
5897 tree call1 = altivec_resolve_overloaded_builtin (loc, addc_builtin,
5898 params);
5899 params = make_tree_vector ();
5900 vec_safe_push (params, arg0);
5901 vec_safe_push (params, arg1);
5902 tree add_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
5903 tree call2 = altivec_resolve_overloaded_builtin (loc, add_builtin,
5904 params);
5905 tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
5906 tree ones_vector = build_vector_from_val (arg0_type, const1);
5907 tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
5908 arg2, ones_vector);
5909 params = make_tree_vector ();
5910 vec_safe_push (params, call2);
5911 vec_safe_push (params, and_expr);
5912 call2 = altivec_resolve_overloaded_builtin (loc, addc_builtin,
5913 params);
5914 params = make_tree_vector ();
5915 vec_safe_push (params, call1);
5916 vec_safe_push (params, call2);
5917 tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR];
5918 return altivec_resolve_overloaded_builtin (loc, or_builtin,
5919 params);
5920 }
5921 /* For {un}signed __int128s use the vaddecuq instruction. */
5922 case E_TImode:
5923 {
5924 tree VADDECUQ_bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ];
5925 return altivec_resolve_overloaded_builtin (loc, VADDECUQ_bii,
5926 arglist);
5927 }
5928 /* Types other than {un}signed int and {un}signed __int128
5929 are errors. */
5930 default:
5931 goto bad;
5932 }
5933 }
5934
5935 /* For now treat vec_splats and vec_promote as the same. */
5936 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS
5937 || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)
5938 {
5939 tree type, arg;
5940 int size;
5941 int i;
5942 bool unsigned_p;
5943 vec<constructor_elt, va_gc> *vec;
5944 const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote";
5945
5946 if (nargs == 0)
5947 {
5948 error ("%s only accepts %d arguments", name, (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)+1 );
5949 return error_mark_node;
5950 }
5951 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1)
5952 {
5953 error ("%s only accepts 1 argument", name);
5954 return error_mark_node;
5955 }
5956 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2)
5957 {
5958 error ("%s only accepts 2 arguments", name);
5959 return error_mark_node;
5960 }
5961 /* Ignore promote's element argument. */
5962 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE
5963 && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1])))
5964 goto bad;
5965
5966 arg = (*arglist)[0];
5967 type = TREE_TYPE (arg);
5968 if (!SCALAR_FLOAT_TYPE_P (type)
5969 && !INTEGRAL_TYPE_P (type))
5970 goto bad;
5971 unsigned_p = TYPE_UNSIGNED (type);
5972 switch (TYPE_MODE (type))
5973 {
5974 case E_TImode:
5975 type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
5976 size = 1;
5977 break;
5978 case E_DImode:
5979 type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
5980 size = 2;
5981 break;
5982 case E_SImode:
5983 type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
5984 size = 4;
5985 break;
5986 case E_HImode:
5987 type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
5988 size = 8;
5989 break;
5990 case E_QImode:
5991 type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
5992 size = 16;
5993 break;
5994 case E_SFmode: type = V4SF_type_node; size = 4; break;
5995 case E_DFmode: type = V2DF_type_node; size = 2; break;
5996 default:
5997 goto bad;
5998 }
5999 arg = save_expr (fold_convert (TREE_TYPE (type), arg));
6000 vec_alloc (vec, size);
6001 for(i = 0; i < size; i++)
6002 {
6003 constructor_elt elt = {NULL_TREE, arg};
6004 vec->quick_push (elt);
6005 }
6006 return build_constructor (type, vec);
6007 }
6008
6009 /* For now use pointer tricks to do the extraction, unless we are on VSX
6010 extracting a double from a constant offset. */
6011 if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)
6012 {
6013 tree arg1;
6014 tree arg1_type;
6015 tree arg2;
6016 tree arg1_inner_type;
6017 tree decl, stmt;
6018 tree innerptrtype;
6019 machine_mode mode;
6020
6021 /* No second argument. */
6022 if (nargs != 2)
6023 {
6024 error ("vec_extract only accepts 2 arguments");
6025 return error_mark_node;
6026 }
6027
6028 arg2 = (*arglist)[1];
6029 arg1 = (*arglist)[0];
6030 arg1_type = TREE_TYPE (arg1);
6031
6032 if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6033 goto bad;
6034 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6035 goto bad;
6036
6037 /* If we are targeting little-endian, but -maltivec=be has been
6038 specified to override the element order, adjust the element
6039 number accordingly. */
6040 if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6041 {
6042 unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6043 arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6044 build_int_cstu (TREE_TYPE (arg2), last_elem),
6045 arg2);
6046 }
6047
6048 /* See if we can optimize vec_extracts with the current VSX instruction
6049 set. */
6050 mode = TYPE_MODE (arg1_type);
6051 if (VECTOR_MEM_VSX_P (mode))
6052
6053 {
6054 tree call = NULL_TREE;
6055 int nunits = GET_MODE_NUNITS (mode);
6056
6057 /* If the second argument is an integer constant, if the value is in
6058 the expected range, generate the built-in code if we can. We need
6059 64-bit and direct move to extract the small integer vectors. */
6060 if (TREE_CODE (arg2) == INTEGER_CST
6061 && wi::ltu_p (wi::to_wide (arg2), nunits))
6062 {
6063 switch (mode)
6064 {
6065 default:
6066 break;
6067
6068 case E_V1TImode:
6069 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
6070 break;
6071
6072 case E_V2DFmode:
6073 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6074 break;
6075
6076 case E_V2DImode:
6077 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6078 break;
6079
6080 case E_V4SFmode:
6081 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6082 break;
6083
6084 case E_V4SImode:
6085 if (TARGET_DIRECT_MOVE_64BIT)
6086 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6087 break;
6088
6089 case E_V8HImode:
6090 if (TARGET_DIRECT_MOVE_64BIT)
6091 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6092 break;
6093
6094 case E_V16QImode:
6095 if (TARGET_DIRECT_MOVE_64BIT)
6096 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6097 break;
6098 }
6099 }
6100
6101 /* If the second argument is variable, we can optimize it if we are
6102 generating 64-bit code on a machine with direct move. */
6103 else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT)
6104 {
6105 switch (mode)
6106 {
6107 default:
6108 break;
6109
6110 case E_V2DFmode:
6111 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6112 break;
6113
6114 case E_V2DImode:
6115 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6116 break;
6117
6118 case E_V4SFmode:
6119 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6120 break;
6121
6122 case E_V4SImode:
6123 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6124 break;
6125
6126 case E_V8HImode:
6127 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6128 break;
6129
6130 case E_V16QImode:
6131 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6132 break;
6133 }
6134 }
6135
6136 if (call)
6137 return build_call_expr (call, 2, arg1, arg2);
6138 }
6139
6140 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
6141 arg1_inner_type = TREE_TYPE (arg1_type);
6142 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6143 build_int_cst (TREE_TYPE (arg2),
6144 TYPE_VECTOR_SUBPARTS (arg1_type)
6145 - 1), 0);
6146 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6147 DECL_EXTERNAL (decl) = 0;
6148 TREE_PUBLIC (decl) = 0;
6149 DECL_CONTEXT (decl) = current_function_decl;
6150 TREE_USED (decl) = 1;
6151 TREE_TYPE (decl) = arg1_type;
6152 TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6153 if (c_dialect_cxx ())
6154 {
6155 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6156 NULL_TREE, NULL_TREE);
6157 SET_EXPR_LOCATION (stmt, loc);
6158 }
6159 else
6160 {
6161 DECL_INITIAL (decl) = arg1;
6162 stmt = build1 (DECL_EXPR, arg1_type, decl);
6163 TREE_ADDRESSABLE (decl) = 1;
6164 SET_EXPR_LOCATION (stmt, loc);
6165 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6166 }
6167
6168 innerptrtype = build_pointer_type (arg1_inner_type);
6169
6170 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6171 stmt = convert (innerptrtype, stmt);
6172 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6173 stmt = build_indirect_ref (loc, stmt, RO_NULL);
6174
6175 return stmt;
6176 }
6177
6178 /* For now use pointer tricks to do the insertion, unless we are on VSX
6179 inserting a double to a constant offset.. */
6180 if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)
6181 {
6182 tree arg0;
6183 tree arg1;
6184 tree arg2;
6185 tree arg1_type;
6186 tree arg1_inner_type;
6187 tree decl, stmt;
6188 tree innerptrtype;
6189 machine_mode mode;
6190
6191 /* No second or third arguments. */
6192 if (nargs != 3)
6193 {
6194 error ("vec_insert only accepts 3 arguments");
6195 return error_mark_node;
6196 }
6197
6198 arg0 = (*arglist)[0];
6199 arg1 = (*arglist)[1];
6200 arg1_type = TREE_TYPE (arg1);
6201 arg2 = (*arglist)[2];
6202
6203 if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6204 goto bad;
6205 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6206 goto bad;
6207
6208 /* If we are targeting little-endian, but -maltivec=be has been
6209 specified to override the element order, adjust the element
6210 number accordingly. */
6211 if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6212 {
6213 unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6214 arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6215 build_int_cstu (TREE_TYPE (arg2), last_elem),
6216 arg2);
6217 }
6218
6219 /* If we can use the VSX xxpermdi instruction, use that for insert. */
6220 mode = TYPE_MODE (arg1_type);
6221 if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
6222 && TREE_CODE (arg2) == INTEGER_CST
6223 && wi::ltu_p (wi::to_wide (arg2), 2))
6224 {
6225 tree call = NULL_TREE;
6226
6227 if (mode == V2DFmode)
6228 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF];
6229 else if (mode == V2DImode)
6230 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI];
6231
6232 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6233 reversed. */
6234 if (call)
6235 return build_call_expr (call, 3, arg1, arg0, arg2);
6236 }
6237 else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)
6238 && TREE_CODE (arg2) == INTEGER_CST
6239 && wi::eq_p (wi::to_wide (arg2), 0))
6240 {
6241 tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];
6242
6243 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6244 reversed. */
6245 return build_call_expr (call, 3, arg1, arg0, arg2);
6246 }
6247
6248 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */
6249 arg1_inner_type = TREE_TYPE (arg1_type);
6250 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6251 build_int_cst (TREE_TYPE (arg2),
6252 TYPE_VECTOR_SUBPARTS (arg1_type)
6253 - 1), 0);
6254 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6255 DECL_EXTERNAL (decl) = 0;
6256 TREE_PUBLIC (decl) = 0;
6257 DECL_CONTEXT (decl) = current_function_decl;
6258 TREE_USED (decl) = 1;
6259 TREE_TYPE (decl) = arg1_type;
6260 TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6261 if (c_dialect_cxx ())
6262 {
6263 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6264 NULL_TREE, NULL_TREE);
6265 SET_EXPR_LOCATION (stmt, loc);
6266 }
6267 else
6268 {
6269 DECL_INITIAL (decl) = arg1;
6270 stmt = build1 (DECL_EXPR, arg1_type, decl);
6271 TREE_ADDRESSABLE (decl) = 1;
6272 SET_EXPR_LOCATION (stmt, loc);
6273 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6274 }
6275
6276 innerptrtype = build_pointer_type (arg1_inner_type);
6277
6278 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6279 stmt = convert (innerptrtype, stmt);
6280 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6281 stmt = build_indirect_ref (loc, stmt, RO_NULL);
6282 stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt,
6283 convert (TREE_TYPE (stmt), arg0));
6284 stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl);
6285 return stmt;
6286 }
6287
6288 /* Expand vec_ld into an expression that masks the address and
6289 performs the load. We need to expand this early to allow
6290 the best aliasing, as by the time we get into RTL we no longer
6291 are able to honor __restrict__, for example. We may want to
6292 consider this for all memory access built-ins.
6293
6294 When -maltivec=be is specified, or the wrong number of arguments
6295 is provided, simply punt to existing built-in processing. */
6296 if (fcode == ALTIVEC_BUILTIN_VEC_LD
6297 && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
6298 && nargs == 2)
6299 {
6300 tree arg0 = (*arglist)[0];
6301 tree arg1 = (*arglist)[1];
6302
6303 /* Strip qualifiers like "const" from the pointer arg. */
6304 tree arg1_type = TREE_TYPE (arg1);
6305 tree inner_type = TREE_TYPE (arg1_type);
6306 if (TYPE_QUALS (TREE_TYPE (arg1_type)) != 0)
6307 {
6308 arg1_type = build_pointer_type (build_qualified_type (inner_type,
6309 0));
6310 arg1 = fold_convert (arg1_type, arg1);
6311 }
6312
6313 /* Construct the masked address. Let existing error handling take
6314 over if we don't have a constant offset. */
6315 arg0 = fold (arg0);
6316
6317 if (TREE_CODE (arg0) == INTEGER_CST)
6318 {
6319 if (!ptrofftype_p (TREE_TYPE (arg0)))
6320 arg0 = build1 (NOP_EXPR, sizetype, arg0);
6321
6322 tree arg1_type = TREE_TYPE (arg1);
6323 if (TREE_CODE (arg1_type) == ARRAY_TYPE)
6324 {
6325 arg1_type = TYPE_POINTER_TO (TREE_TYPE (arg1_type));
6326 tree const0 = build_int_cstu (sizetype, 0);
6327 tree arg1_elt0 = build_array_ref (loc, arg1, const0);
6328 arg1 = build1 (ADDR_EXPR, arg1_type, arg1_elt0);
6329 }
6330
6331 tree addr = fold_build2_loc (loc, POINTER_PLUS_EXPR, arg1_type,
6332 arg1, arg0);
6333 tree aligned = fold_build2_loc (loc, BIT_AND_EXPR, arg1_type, addr,
6334 build_int_cst (arg1_type, -16));
6335
6336 /* Find the built-in to get the return type so we can convert
6337 the result properly (or fall back to default handling if the
6338 arguments aren't compatible). */
6339 for (desc = altivec_overloaded_builtins;
6340 desc->code && desc->code != fcode; desc++)
6341 continue;
6342
6343 for (; desc->code == fcode; desc++)
6344 if (rs6000_builtin_type_compatible (TREE_TYPE (arg0), desc->op1)
6345 && (rs6000_builtin_type_compatible (TREE_TYPE (arg1),
6346 desc->op2)))
6347 {
6348 tree ret_type = rs6000_builtin_type (desc->ret_type);
6349 if (TYPE_MODE (ret_type) == V2DImode)
6350 /* Type-based aliasing analysis thinks vector long
6351 and vector long long are different and will put them
6352 in distinct alias classes. Force our return type
6353 to be a may-alias type to avoid this. */
6354 ret_type
6355 = build_pointer_type_for_mode (ret_type, Pmode,
6356 true/*can_alias_all*/);
6357 else
6358 ret_type = build_pointer_type (ret_type);
6359 aligned = build1 (NOP_EXPR, ret_type, aligned);
6360 tree ret_val = build_indirect_ref (loc, aligned, RO_NULL);
6361 return ret_val;
6362 }
6363 }
6364 }
6365
6366 /* Similarly for stvx. */
6367 if (fcode == ALTIVEC_BUILTIN_VEC_ST
6368 && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)
6369 && nargs == 3)
6370 {
6371 tree arg0 = (*arglist)[0];
6372 tree arg1 = (*arglist)[1];
6373 tree arg2 = (*arglist)[2];
6374
6375 /* Construct the masked address. Let existing error handling take
6376 over if we don't have a constant offset. */
6377 arg1 = fold (arg1);
6378
6379 if (TREE_CODE (arg1) == INTEGER_CST)
6380 {
6381 if (!ptrofftype_p (TREE_TYPE (arg1)))
6382 arg1 = build1 (NOP_EXPR, sizetype, arg1);
6383
6384 tree arg2_type = TREE_TYPE (arg2);
6385 if (TREE_CODE (arg2_type) == ARRAY_TYPE)
6386 {
6387 arg2_type = TYPE_POINTER_TO (TREE_TYPE (arg2_type));
6388 tree const0 = build_int_cstu (sizetype, 0);
6389 tree arg2_elt0 = build_array_ref (loc, arg2, const0);
6390 arg2 = build1 (ADDR_EXPR, arg2_type, arg2_elt0);
6391 }
6392
6393 tree addr = fold_build2_loc (loc, POINTER_PLUS_EXPR, arg2_type,
6394 arg2, arg1);
6395 tree aligned = fold_build2_loc (loc, BIT_AND_EXPR, arg2_type, addr,
6396 build_int_cst (arg2_type, -16));
6397
6398 /* Find the built-in to make sure a compatible one exists; if not
6399 we fall back to default handling to get the error message. */
6400 for (desc = altivec_overloaded_builtins;
6401 desc->code && desc->code != fcode; desc++)
6402 continue;
6403
6404 for (; desc->code == fcode; desc++)
6405 if (rs6000_builtin_type_compatible (TREE_TYPE (arg0), desc->op1)
6406 && rs6000_builtin_type_compatible (TREE_TYPE (arg1), desc->op2)
6407 && rs6000_builtin_type_compatible (TREE_TYPE (arg2),
6408 desc->op3))
6409 {
6410 tree arg0_type = TREE_TYPE (arg0);
6411 if (TYPE_MODE (arg0_type) == V2DImode)
6412 /* Type-based aliasing analysis thinks vector long
6413 and vector long long are different and will put them
6414 in distinct alias classes. Force our address type
6415 to be a may-alias type to avoid this. */
6416 arg0_type
6417 = build_pointer_type_for_mode (arg0_type, Pmode,
6418 true/*can_alias_all*/);
6419 else
6420 arg0_type = build_pointer_type (arg0_type);
6421 aligned = build1 (NOP_EXPR, arg0_type, aligned);
6422 tree stg = build_indirect_ref (loc, aligned, RO_NULL);
6423 tree retval = build2 (MODIFY_EXPR, TREE_TYPE (stg), stg,
6424 convert (TREE_TYPE (stg), arg0));
6425 return retval;
6426 }
6427 }
6428 }
6429
6430 for (n = 0;
6431 !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs;
6432 fnargs = TREE_CHAIN (fnargs), n++)
6433 {
6434 tree decl_type = TREE_VALUE (fnargs);
6435 tree arg = (*arglist)[n];
6436 tree type;
6437
6438 if (arg == error_mark_node)
6439 return error_mark_node;
6440
6441 if (n >= 3)
6442 abort ();
6443
6444 arg = default_conversion (arg);
6445
6446 /* The C++ front-end converts float * to const void * using
6447 NOP_EXPR<const void *> (NOP_EXPR<void *> (x)). */
6448 type = TREE_TYPE (arg);
6449 if (POINTER_TYPE_P (type)
6450 && TREE_CODE (arg) == NOP_EXPR
6451 && lang_hooks.types_compatible_p (TREE_TYPE (arg),
6452 const_ptr_type_node)
6453 && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)),
6454 ptr_type_node))
6455 {
6456 arg = TREE_OPERAND (arg, 0);
6457 type = TREE_TYPE (arg);
6458 }
6459
6460 /* Remove the const from the pointers to simplify the overload
6461 matching further down. */
6462 if (POINTER_TYPE_P (decl_type)
6463 && POINTER_TYPE_P (type)
6464 && TYPE_QUALS (TREE_TYPE (type)) != 0)
6465 {
6466 if (TYPE_READONLY (TREE_TYPE (type))
6467 && !TYPE_READONLY (TREE_TYPE (decl_type)))
6468 warning (0, "passing arg %d of %qE discards qualifiers from "
6469 "pointer target type", n + 1, fndecl);
6470 type = build_pointer_type (build_qualified_type (TREE_TYPE (type),
6471 0));
6472 arg = fold_convert (type, arg);
6473 }
6474
6475 args[n] = arg;
6476 types[n] = type;
6477 }
6478
6479 /* If the number of arguments did not match the prototype, return NULL
6480 and the generic code will issue the appropriate error message. */
6481 if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs)
6482 return NULL;
6483
6484 if (n == 0)
6485 abort ();
6486
6487 if (fcode == ALTIVEC_BUILTIN_VEC_STEP)
6488 {
6489 if (TREE_CODE (types[0]) != VECTOR_TYPE)
6490 goto bad;
6491
6492 return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0]));
6493 }
6494
6495 {
6496 bool unsupported_builtin = false;
6497 for (desc = altivec_overloaded_builtins;
6498 desc->code && desc->code != fcode; desc++)
6499 continue;
6500
6501 /* Need to special case __builtin_cmp because the overloaded forms
6502 of this function take (unsigned int, unsigned int) or (unsigned
6503 long long int, unsigned long long int). Since C conventions
6504 allow the respective argument types to be implicitly coerced into
6505 each other, the default handling does not provide adequate
6506 discrimination between the desired forms of the function. */
6507 if (fcode == P6_OV_BUILTIN_CMPB)
6508 {
6509 int overloaded_code;
6510 machine_mode arg1_mode = TYPE_MODE (types[0]);
6511 machine_mode arg2_mode = TYPE_MODE (types[1]);
6512
6513 if (nargs != 2)
6514 {
6515 error ("__builtin_cmpb only accepts 2 arguments");
6516 return error_mark_node;
6517 }
6518
6519 /* If any supplied arguments are wider than 32 bits, resolve to
6520 64-bit variant of built-in function. */
6521 if ((GET_MODE_PRECISION (arg1_mode) > 32)
6522 || (GET_MODE_PRECISION (arg2_mode) > 32))
6523 {
6524 /* Assure all argument and result types are compatible with
6525 the built-in function represented by P6_BUILTIN_CMPB. */
6526 overloaded_code = P6_BUILTIN_CMPB;
6527 }
6528 else
6529 {
6530 /* Assure all argument and result types are compatible with
6531 the built-in function represented by P6_BUILTIN_CMPB_32. */
6532 overloaded_code = P6_BUILTIN_CMPB_32;
6533 }
6534
6535 while (desc->code && desc->code == fcode &&
6536 desc->overloaded_code != overloaded_code)
6537 desc++;
6538
6539 if (desc->code && (desc->code == fcode)
6540 && rs6000_builtin_type_compatible (types[0], desc->op1)
6541 && rs6000_builtin_type_compatible (types[1], desc->op2))
6542 {
6543 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6544 return altivec_build_resolved_builtin (args, n, desc);
6545 else
6546 unsupported_builtin = true;
6547 }
6548 }
6549 else
6550 {
6551 /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in
6552 the opX fields. */
6553 for (; desc->code == fcode; desc++)
6554 {
6555 if ((desc->op1 == RS6000_BTI_NOT_OPAQUE
6556 || rs6000_builtin_type_compatible (types[0], desc->op1))
6557 && (desc->op2 == RS6000_BTI_NOT_OPAQUE
6558 || rs6000_builtin_type_compatible (types[1], desc->op2))
6559 && (desc->op3 == RS6000_BTI_NOT_OPAQUE
6560 || rs6000_builtin_type_compatible (types[2], desc->op3)))
6561 {
6562 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6563 return altivec_build_resolved_builtin (args, n, desc);
6564 else
6565 unsupported_builtin = true;
6566 }
6567 }
6568 }
6569
6570 if (unsupported_builtin)
6571 {
6572 const char *name = rs6000_overloaded_builtin_name (fcode);
6573 error ("Builtin function %s not supported in this compiler configuration",
6574 name);
6575 return error_mark_node;
6576 }
6577 }
6578 bad:
6579 {
6580 const char *name = rs6000_overloaded_builtin_name (fcode);
6581 error ("invalid parameter combination for AltiVec intrinsic %s", name);
6582 return error_mark_node;
6583 }
6584 }
6585