1;; Predicate definitions for POWER and PowerPC. 2;; Copyright (C) 2005-2018 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Return 1 for anything except PARALLEL. 21(define_predicate "any_operand" 22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem")) 23 24;; Return 1 for any PARALLEL. 25(define_predicate "any_parallel_operand" 26 (match_code "parallel")) 27 28;; Return 1 if op is COUNT register. 29(define_predicate "count_register_operand" 30 (and (match_code "reg") 31 (match_test "REGNO (op) == CTR_REGNO 32 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) 33 34;; Return 1 if op is a SUBREG that is used to look at a SFmode value as 35;; and integer or vice versa. 36;; 37;; In the normal case where SFmode is in a floating point/vector register, it 38;; is stored as a DFmode and has a different format. If we don't transform the 39;; value, things that use logical operations on the values will get the wrong 40;; value. 41;; 42;; If we don't have 64-bit and direct move, this conversion will be done by 43;; store and load, instead of by fiddling with the bits within the register. 44(define_predicate "sf_subreg_operand" 45 (match_code "subreg") 46{ 47 rtx inner_reg = SUBREG_REG (op); 48 machine_mode inner_mode = GET_MODE (inner_reg); 49 50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg)) 51 return 0; 52 53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT) 54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode)) 55 { 56 if (INT_REGNO_P (REGNO (inner_reg))) 57 return 0; 58 59 return 1; 60 } 61 return 0; 62}) 63 64;; Return 1 if op is an Altivec register. 65(define_predicate "altivec_register_operand" 66 (match_operand 0 "register_operand") 67{ 68 if (GET_CODE (op) == SUBREG) 69 { 70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 71 return 0; 72 73 op = SUBREG_REG (op); 74 } 75 76 if (!REG_P (op)) 77 return 0; 78 79 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 80 return 1; 81 82 return ALTIVEC_REGNO_P (REGNO (op)); 83}) 84 85;; Return 1 if op is a VSX register. 86(define_predicate "vsx_register_operand" 87 (match_operand 0 "register_operand") 88{ 89 if (GET_CODE (op) == SUBREG) 90 { 91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 92 return 0; 93 94 op = SUBREG_REG (op); 95 } 96 97 if (!REG_P (op)) 98 return 0; 99 100 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 101 return 1; 102 103 return VSX_REGNO_P (REGNO (op)); 104}) 105 106;; Like vsx_register_operand, but allow SF SUBREGS 107(define_predicate "vsx_reg_sfsubreg_ok" 108 (match_operand 0 "register_operand") 109{ 110 if (GET_CODE (op) == SUBREG) 111 op = SUBREG_REG (op); 112 113 if (!REG_P (op)) 114 return 0; 115 116 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 117 return 1; 118 119 return VSX_REGNO_P (REGNO (op)); 120}) 121 122;; Return 1 if op is a vector register that operates on floating point vectors 123;; (either altivec or VSX). 124(define_predicate "vfloat_operand" 125 (match_operand 0 "register_operand") 126{ 127 if (GET_CODE (op) == SUBREG) 128 { 129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 130 return 0; 131 132 op = SUBREG_REG (op); 133 } 134 135 if (!REG_P (op)) 136 return 0; 137 138 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 139 return 1; 140 141 return VFLOAT_REGNO_P (REGNO (op)); 142}) 143 144;; Return 1 if op is a vector register that operates on integer vectors 145;; (only altivec, VSX doesn't support integer vectors) 146(define_predicate "vint_operand" 147 (match_operand 0 "register_operand") 148{ 149 if (GET_CODE (op) == SUBREG) 150 { 151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 152 return 0; 153 154 op = SUBREG_REG (op); 155 } 156 157 if (!REG_P (op)) 158 return 0; 159 160 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 161 return 1; 162 163 return VINT_REGNO_P (REGNO (op)); 164}) 165 166;; Return 1 if op is a vector register to do logical operations on (and, or, 167;; xor, etc.) 168(define_predicate "vlogical_operand" 169 (match_operand 0 "register_operand") 170{ 171 if (GET_CODE (op) == SUBREG) 172 { 173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 174 return 0; 175 176 op = SUBREG_REG (op); 177 } 178 179 180 if (!REG_P (op)) 181 return 0; 182 183 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 184 return 1; 185 186 return VLOGICAL_REGNO_P (REGNO (op)); 187}) 188 189;; Return 1 if op is the carry register. 190(define_predicate "ca_operand" 191 (match_operand 0 "register_operand") 192{ 193 if (GET_CODE (op) == SUBREG) 194 op = SUBREG_REG (op); 195 196 if (!REG_P (op)) 197 return 0; 198 199 return CA_REGNO_P (REGNO (op)); 200}) 201 202;; Return 1 if op is a signed 5-bit constant integer. 203(define_predicate "s5bit_cint_operand" 204 (and (match_code "const_int") 205 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) 206 207;; Return 1 if op is a unsigned 3-bit constant integer. 208(define_predicate "u3bit_cint_operand" 209 (and (match_code "const_int") 210 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) 211 212;; Return 1 if op is a unsigned 5-bit constant integer. 213(define_predicate "u5bit_cint_operand" 214 (and (match_code "const_int") 215 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) 216 217;; Return 1 if op is a unsigned 6-bit constant integer. 218(define_predicate "u6bit_cint_operand" 219 (and (match_code "const_int") 220 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63"))) 221 222;; Return 1 if op is an unsigned 7-bit constant integer. 223(define_predicate "u7bit_cint_operand" 224 (and (match_code "const_int") 225 (match_test "IN_RANGE (INTVAL (op), 0, 127)"))) 226 227;; Return 1 if op is a signed 8-bit constant integer. 228;; Integer multiplication complete more quickly 229(define_predicate "s8bit_cint_operand" 230 (and (match_code "const_int") 231 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) 232 233;; Return 1 if op is a unsigned 10-bit constant integer. 234(define_predicate "u10bit_cint_operand" 235 (and (match_code "const_int") 236 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023"))) 237 238;; Return 1 if op is a constant integer that can fit in a D field. 239(define_predicate "short_cint_operand" 240 (and (match_code "const_int") 241 (match_test "satisfies_constraint_I (op)"))) 242 243;; Return 1 if op is a constant integer that can fit in an unsigned D field. 244(define_predicate "u_short_cint_operand" 245 (and (match_code "const_int") 246 (match_test "satisfies_constraint_K (op)"))) 247 248;; Return 1 if op is a constant integer that is a signed 16-bit constant 249;; shifted left 16 bits 250(define_predicate "upper16_cint_operand" 251 (and (match_code "const_int") 252 (match_test "satisfies_constraint_L (op)"))) 253 254;; Return 1 if op is a constant integer that cannot fit in a signed D field. 255(define_predicate "non_short_cint_operand" 256 (and (match_code "const_int") 257 (match_test "(unsigned HOST_WIDE_INT) 258 (INTVAL (op) + 0x8000) >= 0x10000"))) 259 260;; Return 1 if op is a positive constant integer that is an exact power of 2. 261(define_predicate "exact_log2_cint_operand" 262 (and (match_code "const_int") 263 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) 264 265;; Match op = 0 or op = 1. 266(define_predicate "const_0_to_1_operand" 267 (and (match_code "const_int") 268 (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) 269 270;; Match op = 0..3. 271(define_predicate "const_0_to_3_operand" 272 (and (match_code "const_int") 273 (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) 274 275;; Match op = 2 or op = 3. 276(define_predicate "const_2_to_3_operand" 277 (and (match_code "const_int") 278 (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) 279 280;; Match op = 0..7. 281(define_predicate "const_0_to_7_operand" 282 (and (match_code "const_int") 283 (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) 284 285;; Match op = 0..11 286(define_predicate "const_0_to_12_operand" 287 (and (match_code "const_int") 288 (match_test "IN_RANGE (INTVAL (op), 0, 12)"))) 289 290;; Match op = 0..15 291(define_predicate "const_0_to_15_operand" 292 (and (match_code "const_int") 293 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) 294 295;; Return 1 if op is a register that is not special. 296;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where 297;; you need to be careful in moving a SFmode to SImode and vice versa due to 298;; the fact that SFmode is represented as DFmode in the VSX registers. 299(define_predicate "gpc_reg_operand" 300 (match_operand 0 "register_operand") 301{ 302 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode)) 303 return 0; 304 305 if (GET_CODE (op) == SUBREG) 306 { 307 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 308 return 0; 309 310 op = SUBREG_REG (op); 311 } 312 313 if (!REG_P (op)) 314 return 0; 315 316 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 317 return 1; 318 319 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op))) 320 return 1; 321 322 if (TARGET_VSX && VSX_REGNO_P (REGNO (op))) 323 return 1; 324 325 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op)); 326}) 327 328;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't 329;; allow floating point or vector registers. Since vector registers are not 330;; allowed, we don't have to reject SFmode/SImode subregs. 331(define_predicate "int_reg_operand" 332 (match_operand 0 "register_operand") 333{ 334 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode)) 335 return 0; 336 337 if (GET_CODE (op) == SUBREG) 338 { 339 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 340 return 0; 341 342 op = SUBREG_REG (op); 343 } 344 345 if (!REG_P (op)) 346 return 0; 347 348 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 349 return 1; 350 351 return INT_REGNO_P (REGNO (op)); 352}) 353 354;; Like int_reg_operand, but don't return true for pseudo registers 355;; We don't have to check for SF SUBREGS because pseudo registers 356;; are not allowed, and SF SUBREGs are ok within GPR registers. 357(define_predicate "int_reg_operand_not_pseudo" 358 (match_operand 0 "register_operand") 359{ 360 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode)) 361 return 0; 362 363 if (GET_CODE (op) == SUBREG) 364 op = SUBREG_REG (op); 365 366 if (!REG_P (op)) 367 return 0; 368 369 if (REGNO (op) >= FIRST_PSEUDO_REGISTER) 370 return 0; 371 372 return INT_REGNO_P (REGNO (op)); 373}) 374 375;; Like int_reg_operand, but only return true for base registers 376(define_predicate "base_reg_operand" 377 (match_operand 0 "int_reg_operand") 378{ 379 if (GET_CODE (op) == SUBREG) 380 op = SUBREG_REG (op); 381 382 if (!REG_P (op)) 383 return 0; 384 385 return (REGNO (op) != FIRST_GPR_REGNO); 386}) 387 388 389;; Return true if this is a traditional floating point register 390(define_predicate "fpr_reg_operand" 391 (match_code "reg,subreg") 392{ 393 HOST_WIDE_INT r; 394 395 if (GET_CODE (op) == SUBREG) 396 op = SUBREG_REG (op); 397 398 if (!REG_P (op)) 399 return 0; 400 401 r = REGNO (op); 402 if (r >= FIRST_PSEUDO_REGISTER) 403 return 1; 404 405 return FP_REGNO_P (r); 406}) 407 408;; Return true if this is a register that can has D-form addressing (GPR and 409;; traditional FPR registers for scalars). ISA 3.0 (power9) adds D-form 410;; addressing for scalars in Altivec registers. 411;; 412;; If this is a pseudo only allow for GPR fusion in power8. If we have the 413;; power9 fusion allow the floating point types. 414(define_predicate "toc_fusion_or_p9_reg_operand" 415 (match_code "reg,subreg") 416{ 417 HOST_WIDE_INT r; 418 bool gpr_p = (mode == QImode || mode == HImode || mode == SImode 419 || mode == SFmode 420 || (TARGET_POWERPC64 && (mode == DImode || mode == DFmode))); 421 bool fpr_p = (TARGET_P9_FUSION 422 && (mode == DFmode || mode == SFmode 423 || (TARGET_POWERPC64 && mode == DImode))); 424 bool vmx_p = (TARGET_P9_FUSION && TARGET_P9_VECTOR 425 && (mode == DFmode || mode == SFmode)); 426 427 if (!TARGET_P8_FUSION) 428 return 0; 429 430 if (GET_CODE (op) == SUBREG) 431 op = SUBREG_REG (op); 432 433 if (!REG_P (op)) 434 return 0; 435 436 r = REGNO (op); 437 if (r >= FIRST_PSEUDO_REGISTER) 438 return (gpr_p || fpr_p || vmx_p); 439 440 if (INT_REGNO_P (r)) 441 return gpr_p; 442 443 if (FP_REGNO_P (r)) 444 return fpr_p; 445 446 if (ALTIVEC_REGNO_P (r)) 447 return vmx_p; 448 449 return 0; 450}) 451 452;; Return 1 if op is a HTM specific SPR register. 453(define_predicate "htm_spr_reg_operand" 454 (match_operand 0 "register_operand") 455{ 456 if (!TARGET_HTM) 457 return 0; 458 459 if (GET_CODE (op) == SUBREG) 460 op = SUBREG_REG (op); 461 462 if (!REG_P (op)) 463 return 0; 464 465 switch (REGNO (op)) 466 { 467 case TFHAR_REGNO: 468 case TFIAR_REGNO: 469 case TEXASR_REGNO: 470 return 1; 471 default: 472 break; 473 } 474 475 /* Unknown SPR. */ 476 return 0; 477}) 478 479;; Return 1 if op is a general purpose register that is an even register 480;; which suitable for a load/store quad operation 481;; Subregs are not allowed here because when they are combine can 482;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to 483;; think the innermost reg needs reloading, in TImode instead of 484;; PTImode. So reload will choose a reg in TImode which has no 485;; requirement that the reg be even. 486(define_predicate "quad_int_reg_operand" 487 (match_code "reg") 488{ 489 HOST_WIDE_INT r; 490 491 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC) 492 return 0; 493 494 r = REGNO (op); 495 if (r >= FIRST_PSEUDO_REGISTER) 496 return 1; 497 498 return (INT_REGNO_P (r) && ((r & 1) == 0)); 499}) 500 501;; Return 1 if op is a register that is a condition register field. 502(define_predicate "cc_reg_operand" 503 (match_operand 0 "register_operand") 504{ 505 if (GET_CODE (op) == SUBREG) 506 op = SUBREG_REG (op); 507 508 if (!REG_P (op)) 509 return 0; 510 511 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 512 return 1; 513 514 return CR_REGNO_P (REGNO (op)); 515}) 516 517;; Return 1 if op is a register that is a condition register field not cr0. 518(define_predicate "cc_reg_not_cr0_operand" 519 (match_operand 0 "register_operand") 520{ 521 if (GET_CODE (op) == SUBREG) 522 op = SUBREG_REG (op); 523 524 if (!REG_P (op)) 525 return 0; 526 527 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 528 return 1; 529 530 return CR_REGNO_NOT_CR0_P (REGNO (op)); 531}) 532 533;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0. 534(define_predicate "cc_reg_not_micro_cr0_operand" 535 (match_operand 0 "register_operand") 536{ 537 if (GET_CODE (op) == SUBREG) 538 op = SUBREG_REG (op); 539 540 if (!REG_P (op)) 541 return 0; 542 543 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 544 return 1; 545 546 if (rs6000_gen_cell_microcode) 547 return CR_REGNO_NOT_CR0_P (REGNO (op)); 548 else 549 return CR_REGNO_P (REGNO (op)); 550}) 551 552;; Return 1 if op is a constant integer valid for D field 553;; or non-special register register. 554(define_predicate "reg_or_short_operand" 555 (if_then_else (match_code "const_int") 556 (match_operand 0 "short_cint_operand") 557 (match_operand 0 "gpc_reg_operand"))) 558 559;; Return 1 if op is a constant integer valid for DS field 560;; or non-special register. 561(define_predicate "reg_or_aligned_short_operand" 562 (if_then_else (match_code "const_int") 563 (and (match_operand 0 "short_cint_operand") 564 (match_test "!(INTVAL (op) & 3)")) 565 (match_operand 0 "gpc_reg_operand"))) 566 567;; Return 1 if op is a constant integer whose high-order 16 bits are zero 568;; or non-special register. 569(define_predicate "reg_or_u_short_operand" 570 (if_then_else (match_code "const_int") 571 (match_operand 0 "u_short_cint_operand") 572 (match_operand 0 "gpc_reg_operand"))) 573 574;; Return 1 if op is any constant integer 575;; or non-special register. 576(define_predicate "reg_or_cint_operand" 577 (ior (match_code "const_int") 578 (match_operand 0 "gpc_reg_operand"))) 579 580;; Return 1 if op is a constant integer valid for addition with addis, addi. 581(define_predicate "add_cint_operand" 582 (and (match_code "const_int") 583 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op) 584 + (mode == SImode ? 0x80000000 : 0x80008000)) 585 < (unsigned HOST_WIDE_INT) 0x100000000ll"))) 586 587;; Return 1 if op is a constant integer valid for addition 588;; or non-special register. 589(define_predicate "reg_or_add_cint_operand" 590 (if_then_else (match_code "const_int") 591 (match_operand 0 "add_cint_operand") 592 (match_operand 0 "gpc_reg_operand"))) 593 594;; Return 1 if op is a constant integer valid for subtraction 595;; or non-special register. 596(define_predicate "reg_or_sub_cint_operand" 597 (if_then_else (match_code "const_int") 598 (match_test "(unsigned HOST_WIDE_INT) 599 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000)) 600 < (unsigned HOST_WIDE_INT) 0x100000000ll") 601 (match_operand 0 "gpc_reg_operand"))) 602 603;; Return 1 if op is any 32-bit unsigned constant integer 604;; or non-special register. 605(define_predicate "reg_or_logical_cint_operand" 606 (if_then_else (match_code "const_int") 607 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 608 && INTVAL (op) >= 0) 609 || ((INTVAL (op) & GET_MODE_MASK (mode) 610 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") 611 (match_operand 0 "gpc_reg_operand"))) 612 613;; Like reg_or_logical_cint_operand, but allow vsx registers 614(define_predicate "vsx_reg_or_cint_operand" 615 (ior (match_operand 0 "vsx_register_operand") 616 (match_operand 0 "reg_or_logical_cint_operand"))) 617 618;; Return 1 if operand is a CONST_DOUBLE that can be set in a register 619;; with no more than one instruction per word. 620(define_predicate "easy_fp_constant" 621 (match_code "const_double") 622{ 623 if (GET_MODE (op) != mode 624 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode)) 625 return 0; 626 627 /* Consider all constants with -msoft-float to be easy. */ 628 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE 629 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT))) 630 && mode != DImode) 631 return 1; 632 633 /* 0.0D is not all zero bits. */ 634 if (DECIMAL_FLOAT_MODE_P (mode)) 635 return 0; 636 637 /* The constant 0.0 is easy under VSX. */ 638 if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode)) 639 return 1; 640 641 /* If we are using V.4 style PIC, consider all constants to be hard. */ 642 if (flag_pic && DEFAULT_ABI == ABI_V4) 643 return 0; 644 645 /* If we have real FPRs, consider floating point constants hard (other than 646 0.0 under VSX), so that the constant gets pushed to memory during the 647 early RTL phases. This has the advantage that double precision constants 648 that can be represented in single precision without a loss of precision 649 will use single precision loads. */ 650 651 switch (mode) 652 { 653 case E_KFmode: 654 case E_IFmode: 655 case E_TFmode: 656 case E_DFmode: 657 case E_SFmode: 658 return 0; 659 660 case E_DImode: 661 return (num_insns_constant (op, DImode) <= 2); 662 663 case E_SImode: 664 return 1; 665 666 default: 667 gcc_unreachable (); 668 } 669}) 670 671;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB 672;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. 673 674(define_predicate "xxspltib_constant_split" 675 (match_code "const_vector,vec_duplicate,const_int") 676{ 677 int value = 256; 678 int num_insns = -1; 679 680 if (!xxspltib_constant_p (op, mode, &num_insns, &value)) 681 return false; 682 683 return num_insns > 1; 684}) 685 686 687;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB 688;; instruction. 689 690(define_predicate "xxspltib_constant_nosplit" 691 (match_code "const_vector,vec_duplicate,const_int") 692{ 693 int value = 256; 694 int num_insns = -1; 695 696 if (!xxspltib_constant_p (op, mode, &num_insns, &value)) 697 return false; 698 699 return num_insns == 1; 700}) 701 702;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a 703;; vector register without using memory. 704(define_predicate "easy_vector_constant" 705 (match_code "const_vector") 706{ 707 /* As the paired vectors are actually FPRs it seems that there is 708 no easy way to load a CONST_VECTOR without using memory. */ 709 if (TARGET_PAIRED_FLOAT) 710 return false; 711 712 /* Because IEEE 128-bit floating point is considered a vector type 713 in order to pass it in VSX registers, it might use this function 714 instead of easy_fp_constant. */ 715 if (FLOAT128_VECTOR_P (mode)) 716 return easy_fp_constant (op, mode); 717 718 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) 719 { 720 int value = 256; 721 int num_insns = -1; 722 723 if (zero_constant (op, mode) || all_ones_constant (op, mode)) 724 return true; 725 726 if (TARGET_P9_VECTOR 727 && xxspltib_constant_p (op, mode, &num_insns, &value)) 728 return true; 729 730 return easy_altivec_constant (op, mode); 731 } 732 733 if (SPE_VECTOR_MODE (mode)) 734 { 735 int cst, cst2; 736 if (zero_constant (op, mode)) 737 return true; 738 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) 739 return false; 740 741 /* Limit SPE vectors to 15 bits signed. These we can generate with: 742 li r0, CONSTANT1 743 evmergelo r0, r0, r0 744 li r0, CONSTANT2 745 746 I don't know how efficient it would be to allow bigger constants, 747 considering we'll have an extra 'ori' for every 'li'. I doubt 5 748 instructions is better than a 64-bit memory load, but I don't 749 have the e500 timing specs. */ 750 if (mode == V2SImode) 751 { 752 cst = INTVAL (CONST_VECTOR_ELT (op, 0)); 753 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); 754 return cst >= -0x7fff && cst <= 0x7fff 755 && cst2 >= -0x7fff && cst2 <= 0x7fff; 756 } 757 } 758 759 return false; 760}) 761 762;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. 763(define_predicate "easy_vector_constant_add_self" 764 (and (match_code "const_vector") 765 (and (match_test "TARGET_ALTIVEC") 766 (match_test "easy_altivec_constant (op, mode)"))) 767{ 768 HOST_WIDE_INT val; 769 int elt; 770 if (mode == V2DImode || mode == V2DFmode) 771 return 0; 772 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; 773 val = const_vector_elt_as_int (op, elt); 774 val = ((val & 0xff) ^ 0x80) - 0x80; 775 return EASY_VECTOR_15_ADD_SELF (val); 776}) 777 778;; Same as easy_vector_constant but only for EASY_VECTOR_MSB. 779(define_predicate "easy_vector_constant_msb" 780 (and (match_code "const_vector") 781 (and (match_test "TARGET_ALTIVEC") 782 (match_test "easy_altivec_constant (op, mode)"))) 783{ 784 HOST_WIDE_INT val; 785 int elt; 786 if (mode == V2DImode || mode == V2DFmode) 787 return 0; 788 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; 789 val = const_vector_elt_as_int (op, elt); 790 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode)); 791}) 792 793;; Return true if this is an easy altivec constant that we form 794;; by using VSLDOI. 795(define_predicate "easy_vector_constant_vsldoi" 796 (and (match_code "const_vector") 797 (and (match_test "TARGET_ALTIVEC") 798 (and (match_test "easy_altivec_constant (op, mode)") 799 (match_test "vspltis_shifted (op) != 0"))))) 800 801;; Return 1 if operand is constant zero (scalars and vectors). 802(define_predicate "zero_constant" 803 (and (match_code "const_int,const_double,const_wide_int,const_vector") 804 (match_test "op == CONST0_RTX (mode)"))) 805 806;; Return 1 if operand is constant -1 (scalars and vectors). 807(define_predicate "all_ones_constant" 808 (and (match_code "const_int,const_double,const_wide_int,const_vector") 809 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)"))) 810 811;; Return 1 if operand is a vector int register or is either a vector constant 812;; of all 0 bits of a vector constant of all 1 bits. 813(define_predicate "vector_int_reg_or_same_bit" 814 (match_code "reg,subreg,const_vector") 815{ 816 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) 817 return 0; 818 819 else if (REG_P (op) || SUBREG_P (op)) 820 return vint_operand (op, mode); 821 822 else 823 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode); 824}) 825 826;; Return 1 if operand is 0.0. 827(define_predicate "zero_fp_constant" 828 (and (match_code "const_double") 829 (match_test "SCALAR_FLOAT_MODE_P (mode) 830 && op == CONST0_RTX (mode)"))) 831 832;; Return 1 if the operand is in volatile memory. Note that during the 833;; RTL generation phase, memory_operand does not return TRUE for volatile 834;; memory references. So this function allows us to recognize volatile 835;; references where it's safe. 836(define_predicate "volatile_mem_operand" 837 (and (and (match_code "mem") 838 (match_test "MEM_VOLATILE_P (op)")) 839 (if_then_else (match_test "reload_completed") 840 (match_operand 0 "memory_operand") 841 (if_then_else (match_test "reload_in_progress") 842 (match_test "strict_memory_address_p (mode, XEXP (op, 0))") 843 (match_test "memory_address_p (mode, XEXP (op, 0))"))))) 844 845;; Return 1 if the operand is an offsettable memory operand. 846(define_predicate "offsettable_mem_operand" 847 (and (match_operand 0 "memory_operand") 848 (match_test "offsettable_nonstrict_memref_p (op)"))) 849 850;; Return 1 if the operand is a simple offsettable memory operand 851;; that does not include pre-increment, post-increment, etc. 852(define_predicate "simple_offsettable_mem_operand" 853 (match_operand 0 "offsettable_mem_operand") 854{ 855 rtx addr = XEXP (op, 0); 856 857 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 858 return 0; 859 860 if (!CONSTANT_P (XEXP (addr, 1))) 861 return 0; 862 863 return base_reg_operand (XEXP (addr, 0), Pmode); 864}) 865 866;; Return 1 if the operand is suitable for load/store quad memory. 867;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). 868(define_predicate "quad_memory_operand" 869 (match_code "mem") 870{ 871 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) 872 return false; 873 874 if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128) 875 return false; 876 877 return quad_address_p (XEXP (op, 0), mode, false); 878}) 879 880;; Return 1 if the operand is suitable for load/store to vector registers with 881;; d-form addressing (register+offset), which was added in ISA 3.0. 882;; Unlike quad_memory_operand, we do not have to check for alignment. 883(define_predicate "vsx_quad_dform_memory_operand" 884 (match_code "mem") 885{ 886 if (!TARGET_P9_DFORM_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16) 887 return false; 888 889 return quad_address_p (XEXP (op, 0), mode, false); 890}) 891 892;; Return 1 if the operand is an indexed or indirect memory operand. 893(define_predicate "indexed_or_indirect_operand" 894 (match_code "mem") 895{ 896 op = XEXP (op, 0); 897 if (VECTOR_MEM_ALTIVEC_P (mode) 898 && GET_CODE (op) == AND 899 && GET_CODE (XEXP (op, 1)) == CONST_INT 900 && INTVAL (XEXP (op, 1)) == -16) 901 op = XEXP (op, 0); 902 903 return indexed_or_indirect_address (op, mode); 904}) 905 906;; Like indexed_or_indirect_operand, but also allow a GPR register if direct 907;; moves are supported. 908(define_predicate "reg_or_indexed_operand" 909 (match_code "mem,reg,subreg") 910{ 911 if (MEM_P (op)) 912 return indexed_or_indirect_operand (op, mode); 913 else if (TARGET_DIRECT_MOVE) 914 return register_operand (op, mode); 915 return 916 0; 917}) 918 919;; Return 1 if the operand is an indexed or indirect memory operand with an 920;; AND -16 in it, used to recognize when we need to switch to Altivec loads 921;; to realign loops instead of VSX (altivec silently ignores the bottom bits, 922;; while VSX uses the full address and traps) 923(define_predicate "altivec_indexed_or_indirect_operand" 924 (match_code "mem") 925{ 926 op = XEXP (op, 0); 927 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) 928 && GET_CODE (op) == AND 929 && GET_CODE (XEXP (op, 1)) == CONST_INT 930 && INTVAL (XEXP (op, 1)) == -16) 931 return indexed_or_indirect_address (XEXP (op, 0), mode); 932 933 return 0; 934}) 935 936;; Return 1 if the operand is an indexed or indirect address. 937(define_special_predicate "indexed_or_indirect_address" 938 (and (match_test "REG_P (op) 939 || (GET_CODE (op) == PLUS 940 /* Omit testing REG_P (XEXP (op, 0)). */ 941 && REG_P (XEXP (op, 1)))") 942 (match_operand 0 "address_operand"))) 943 944;; Return 1 if the operand is an index-form address. 945(define_special_predicate "indexed_address" 946 (match_test "(GET_CODE (op) == PLUS 947 && REG_P (XEXP (op, 0)) 948 && REG_P (XEXP (op, 1)))")) 949 950;; Return 1 if the operand is a MEM with an update-form address. This may 951;; also include update-indexed form. 952(define_special_predicate "update_address_mem" 953 (match_test "(MEM_P (op) 954 && (GET_CODE (XEXP (op, 0)) == PRE_INC 955 || GET_CODE (XEXP (op, 0)) == PRE_DEC 956 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) 957 958;; Return 1 if the operand is a MEM with an indexed-form address. 959(define_special_predicate "indexed_address_mem" 960 (match_test "(MEM_P (op) 961 && (indexed_address (XEXP (op, 0), mode) 962 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY 963 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))")) 964 965;; Return 1 if the operand is either a non-special register or can be used 966;; as the operand of a `mode' add insn. 967(define_predicate "add_operand" 968 (if_then_else (match_code "const_int") 969 (match_test "satisfies_constraint_I (op) 970 || satisfies_constraint_L (op)") 971 (match_operand 0 "gpc_reg_operand"))) 972 973;; Return 1 if the operand is either a non-special register, or 0, or -1. 974(define_predicate "adde_operand" 975 (if_then_else (match_code "const_int") 976 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1") 977 (match_operand 0 "gpc_reg_operand"))) 978 979;; Return 1 if OP is a constant but not a valid add_operand. 980(define_predicate "non_add_cint_operand" 981 (and (match_code "const_int") 982 (match_test "!satisfies_constraint_I (op) 983 && !satisfies_constraint_L (op)"))) 984 985;; Return 1 if the operand is a constant that can be used as the operand 986;; of an OR or XOR. 987(define_predicate "logical_const_operand" 988 (match_code "const_int") 989{ 990 HOST_WIDE_INT opl; 991 992 opl = INTVAL (op) & GET_MODE_MASK (mode); 993 994 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 995 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); 996}) 997 998;; Return 1 if the operand is a non-special register or a constant that 999;; can be used as the operand of an OR or XOR. 1000(define_predicate "logical_operand" 1001 (ior (match_operand 0 "gpc_reg_operand") 1002 (match_operand 0 "logical_const_operand"))) 1003 1004;; Return 1 if op is a constant that is not a logical operand, but could 1005;; be split into one. 1006(define_predicate "non_logical_cint_operand" 1007 (and (match_code "const_int,const_wide_int") 1008 (and (not (match_operand 0 "logical_operand")) 1009 (match_operand 0 "reg_or_logical_cint_operand")))) 1010 1011;; Return 1 if the operand is either a non-special register or a 1012;; constant that can be used as the operand of a logical AND. 1013(define_predicate "and_operand" 1014 (ior (and (match_code "const_int") 1015 (match_test "rs6000_is_valid_and_mask (op, mode)")) 1016 (if_then_else (match_test "fixed_regs[CR0_REGNO]") 1017 (match_operand 0 "gpc_reg_operand") 1018 (match_operand 0 "logical_operand")))) 1019 1020;; Return 1 if the operand is either a logical operand or a short cint operand. 1021(define_predicate "scc_eq_operand" 1022 (ior (match_operand 0 "logical_operand") 1023 (match_operand 0 "short_cint_operand"))) 1024 1025;; Return 1 if the operand is a general non-special register or memory operand. 1026(define_predicate "reg_or_mem_operand" 1027 (ior (match_operand 0 "memory_operand") 1028 (ior (and (match_code "mem") 1029 (match_test "macho_lo_sum_memory_operand (op, mode)")) 1030 (ior (match_operand 0 "volatile_mem_operand") 1031 (match_operand 0 "gpc_reg_operand"))))) 1032 1033;; Return 1 if the operand is either an easy FP constant or memory or reg. 1034(define_predicate "reg_or_none500mem_operand" 1035 (if_then_else (match_code "mem") 1036 (and (match_test "!TARGET_E500_DOUBLE") 1037 (ior (match_operand 0 "memory_operand") 1038 (ior (match_test "macho_lo_sum_memory_operand (op, mode)") 1039 (match_operand 0 "volatile_mem_operand")))) 1040 (match_operand 0 "gpc_reg_operand"))) 1041 1042;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. 1043(define_predicate "zero_reg_mem_operand" 1044 (ior (and (match_test "TARGET_VSX") 1045 (match_operand 0 "zero_fp_constant")) 1046 (match_operand 0 "reg_or_mem_operand"))) 1047 1048;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit 1049;; data types inside of a vector that scalar instructions operate on 1050(define_predicate "vsx_scalar_64bit" 1051 (match_code "const_int") 1052{ 1053 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT); 1054}) 1055 1056;; Return 1 if the operand is a general register or memory operand without 1057;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC 1058;; lwa instruction. 1059(define_predicate "lwa_operand" 1060 (match_code "reg,subreg,mem") 1061{ 1062 rtx inner, addr, offset; 1063 1064 inner = op; 1065 if (reload_completed && GET_CODE (inner) == SUBREG) 1066 inner = SUBREG_REG (inner); 1067 1068 if (gpc_reg_operand (inner, mode)) 1069 return true; 1070 if (!memory_operand (inner, mode)) 1071 return false; 1072 if (!rs6000_gen_cell_microcode) 1073 return false; 1074 1075 addr = XEXP (inner, 0); 1076 if (GET_CODE (addr) == PRE_INC 1077 || GET_CODE (addr) == PRE_DEC 1078 || (GET_CODE (addr) == PRE_MODIFY 1079 && !legitimate_indexed_address_p (XEXP (addr, 1), 0))) 1080 return false; 1081 if (GET_CODE (addr) == LO_SUM 1082 && GET_CODE (XEXP (addr, 0)) == REG 1083 && GET_CODE (XEXP (addr, 1)) == CONST) 1084 addr = XEXP (XEXP (addr, 1), 0); 1085 if (GET_CODE (addr) != PLUS) 1086 return true; 1087 offset = XEXP (addr, 1); 1088 if (GET_CODE (offset) != CONST_INT) 1089 return true; 1090 return INTVAL (offset) % 4 == 0; 1091}) 1092 1093;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. 1094(define_predicate "symbol_ref_operand" 1095 (and (match_code "symbol_ref") 1096 (match_test "(mode == VOIDmode || GET_MODE (op) == mode) 1097 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) 1098 1099;; Return 1 if op is an operand that can be loaded via the GOT. 1100;; or non-special register register field no cr0 1101(define_predicate "got_operand" 1102 (match_code "symbol_ref,const,label_ref")) 1103 1104;; Return 1 if op is a simple reference that can be loaded via the GOT, 1105;; excluding labels involving addition. 1106(define_predicate "got_no_const_operand" 1107 (match_code "symbol_ref,label_ref")) 1108 1109;; Return 1 if op is a SYMBOL_REF for a TLS symbol. 1110(define_predicate "rs6000_tls_symbol_ref" 1111 (and (match_code "symbol_ref") 1112 (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) 1113 1114;; Return 1 if the operand, used inside a MEM, is a valid first argument 1115;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. 1116(define_predicate "call_operand" 1117 (if_then_else (match_code "reg") 1118 (match_test "REGNO (op) == LR_REGNO 1119 || REGNO (op) == CTR_REGNO 1120 || REGNO (op) >= FIRST_PSEUDO_REGISTER") 1121 (match_code "symbol_ref"))) 1122 1123;; Return 1 if the operand is a SYMBOL_REF for a function known to be in 1124;; this file. 1125(define_predicate "current_file_function_operand" 1126 (and (match_code "symbol_ref") 1127 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) 1128 && (SYMBOL_REF_LOCAL_P (op) 1129 || (op == XEXP (DECL_RTL (current_function_decl), 0) 1130 && !decl_replaceable_p (current_function_decl))) 1131 && !((DEFAULT_ABI == ABI_AIX 1132 || DEFAULT_ABI == ABI_ELFv2) 1133 && (SYMBOL_REF_EXTERNAL_P (op) 1134 || SYMBOL_REF_WEAK (op)))"))) 1135 1136;; Return 1 if this operand is a valid input for a move insn. 1137(define_predicate "input_operand" 1138 (match_code "symbol_ref,const,reg,subreg,mem, 1139 const_double,const_wide_int,const_vector,const_int") 1140{ 1141 /* Memory is always valid. */ 1142 if (memory_operand (op, mode)) 1143 return 1; 1144 1145 /* For floating-point, easy constants are valid. */ 1146 if (SCALAR_FLOAT_MODE_P (mode) 1147 && easy_fp_constant (op, mode)) 1148 return 1; 1149 1150 /* Allow any integer constant. */ 1151 if (GET_MODE_CLASS (mode) == MODE_INT 1152 && CONST_SCALAR_INT_P (op)) 1153 return 1; 1154 1155 /* Allow easy vector constants. */ 1156 if (GET_CODE (op) == CONST_VECTOR 1157 && easy_vector_constant (op, mode)) 1158 return 1; 1159 1160 /* Do not allow invalid E500 subregs. */ 1161 if ((TARGET_E500_DOUBLE || TARGET_SPE) 1162 && GET_CODE (op) == SUBREG 1163 && invalid_e500_subreg (op, mode)) 1164 return 0; 1165 1166 /* For floating-point or multi-word mode, the only remaining valid type 1167 is a register. */ 1168 if (SCALAR_FLOAT_MODE_P (mode) 1169 || GET_MODE_SIZE (mode) > UNITS_PER_WORD) 1170 return register_operand (op, mode); 1171 1172 /* We don't allow moving the carry bit around. */ 1173 if (ca_operand (op, mode)) 1174 return 0; 1175 1176 /* The only cases left are integral modes one word or smaller (we 1177 do not get called for MODE_CC values). These can be in any 1178 register. */ 1179 if (register_operand (op, mode)) 1180 return 1; 1181 1182 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region 1183 to be valid. */ 1184 if (DEFAULT_ABI == ABI_V4 1185 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) 1186 && small_data_operand (op, Pmode)) 1187 return 1; 1188 1189 return 0; 1190}) 1191 1192;; Return 1 if this operand is a valid input for a vsx_splat insn. 1193(define_predicate "splat_input_operand" 1194 (match_code "reg,subreg,mem") 1195{ 1196 machine_mode vmode; 1197 1198 if (mode == DFmode) 1199 vmode = V2DFmode; 1200 else if (mode == DImode) 1201 vmode = V2DImode; 1202 else if (mode == SImode && TARGET_P9_VECTOR) 1203 vmode = V4SImode; 1204 else if (mode == SFmode && TARGET_P9_VECTOR) 1205 vmode = V4SFmode; 1206 else 1207 return false; 1208 1209 if (MEM_P (op)) 1210 { 1211 rtx addr = XEXP (op, 0); 1212 1213 if (! volatile_ok && MEM_VOLATILE_P (op)) 1214 return 0; 1215 1216 if (reload_in_progress || lra_in_progress || reload_completed) 1217 return indexed_or_indirect_address (addr, vmode); 1218 else 1219 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op)); 1220 } 1221 return gpc_reg_operand (op, mode); 1222}) 1223 1224;; Return true if OP is a non-immediate operand and not an invalid 1225;; SUBREG operation on the e500. 1226(define_predicate "rs6000_nonimmediate_operand" 1227 (match_code "reg,subreg,mem") 1228{ 1229 if ((TARGET_E500_DOUBLE || TARGET_SPE) 1230 && GET_CODE (op) == SUBREG 1231 && invalid_e500_subreg (op, mode)) 1232 return 0; 1233 1234 return nonimmediate_operand (op, mode); 1235}) 1236 1237;; Return true if operand is an operator used in rotate-and-mask instructions. 1238(define_predicate "rotate_mask_operator" 1239 (match_code "rotate,ashift,lshiftrt")) 1240 1241;; Return true if operand is boolean operator. 1242(define_predicate "boolean_operator" 1243 (match_code "and,ior,xor")) 1244 1245;; Return true if operand is OR-form of boolean operator. 1246(define_predicate "boolean_or_operator" 1247 (match_code "ior,xor")) 1248 1249;; Return true if operand is an equality operator. 1250(define_special_predicate "equality_operator" 1251 (match_code "eq,ne")) 1252 1253;; Return 1 if OP is a comparison operation that is valid for a branch 1254;; instruction. We check the opcode against the mode of the CC value. 1255;; validate_condition_mode is an assertion. 1256(define_predicate "branch_comparison_operator" 1257 (and (match_operand 0 "comparison_operator") 1258 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") 1259 (match_test "validate_condition_mode (GET_CODE (op), 1260 GET_MODE (XEXP (op, 0))), 1261 1")))) 1262 1263;; Return 1 if OP is a valid comparison operator for "cbranch" instructions. 1264;; If we're assuming that FP operations cannot generate user-visible traps, 1265;; then on e500 we can use the ordered-signaling instructions to implement 1266;; the unordered-quiet FP comparison predicates modulo a reversal. 1267(define_predicate "rs6000_cbranch_operator" 1268 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS") 1269 (if_then_else (match_test "flag_trapping_math") 1270 (match_operand 0 "ordered_comparison_operator") 1271 (ior (match_operand 0 "ordered_comparison_operator") 1272 (match_code ("unlt,unle,ungt,unge")))) 1273 (match_operand 0 "comparison_operator"))) 1274 1275;; Return 1 if OP is an unsigned comparison operator. 1276(define_predicate "unsigned_comparison_operator" 1277 (match_code "ltu,gtu,leu,geu")) 1278 1279;; Return 1 if OP is a signed comparison operator. 1280(define_predicate "signed_comparison_operator" 1281 (match_code "lt,gt,le,ge")) 1282 1283;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- 1284;; it must be a positive comparison. 1285(define_predicate "scc_comparison_operator" 1286 (and (match_operand 0 "branch_comparison_operator") 1287 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1288 1289;; Return 1 if OP is a comparison operation whose inverse would be valid for 1290;; an SCC insn. 1291(define_predicate "scc_rev_comparison_operator" 1292 (and (match_operand 0 "branch_comparison_operator") 1293 (match_code "ne,le,ge,leu,geu,ordered"))) 1294 1295;; Return 1 if OP is a comparison operator suitable for floating point 1296;; vector/scalar comparisons that generate a -1/0 mask. 1297(define_predicate "fpmask_comparison_operator" 1298 (match_code "eq,gt,ge")) 1299 1300;; Return 1 if OP is a comparison operator suitable for vector/scalar 1301;; comparisons that generate a 0/-1 mask (i.e. the inverse of 1302;; fpmask_comparison_operator). 1303(define_predicate "invert_fpmask_comparison_operator" 1304 (match_code "ne,unlt,unle")) 1305 1306;; Return 1 if OP is a comparison operation suitable for integer vector/scalar 1307;; comparisons that generate a -1/0 mask. 1308(define_predicate "vecint_comparison_operator" 1309 (match_code "eq,gt,gtu")) 1310 1311;; Return 1 if OP is a comparison operation that is valid for a branch 1312;; insn, which is true if the corresponding bit in the CC register is set. 1313(define_predicate "branch_positive_comparison_operator" 1314 (and (match_operand 0 "branch_comparison_operator") 1315 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1316 1317;; Return 1 if OP is a load multiple operation, known to be a PARALLEL. 1318(define_predicate "load_multiple_operation" 1319 (match_code "parallel") 1320{ 1321 int count = XVECLEN (op, 0); 1322 unsigned int dest_regno; 1323 rtx src_addr; 1324 int i; 1325 1326 /* Perform a quick check so we don't blow up below. */ 1327 if (count <= 1 1328 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1329 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1330 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) 1331 return 0; 1332 1333 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1334 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 1335 1336 for (i = 1; i < count; i++) 1337 { 1338 rtx elt = XVECEXP (op, 0, i); 1339 1340 if (GET_CODE (elt) != SET 1341 || GET_CODE (SET_DEST (elt)) != REG 1342 || GET_MODE (SET_DEST (elt)) != SImode 1343 || REGNO (SET_DEST (elt)) != dest_regno + i 1344 || GET_CODE (SET_SRC (elt)) != MEM 1345 || GET_MODE (SET_SRC (elt)) != SImode 1346 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 1347 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 1348 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT 1349 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) 1350 return 0; 1351 } 1352 1353 return 1; 1354}) 1355 1356;; Return 1 if OP is a store multiple operation, known to be a PARALLEL. 1357;; The second vector element is a CLOBBER. 1358(define_predicate "store_multiple_operation" 1359 (match_code "parallel") 1360{ 1361 int count = XVECLEN (op, 0) - 1; 1362 unsigned int src_regno; 1363 rtx dest_addr; 1364 int i; 1365 1366 /* Perform a quick check so we don't blow up below. */ 1367 if (count <= 1 1368 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1369 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM 1370 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) 1371 return 0; 1372 1373 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 1374 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 1375 1376 for (i = 1; i < count; i++) 1377 { 1378 rtx elt = XVECEXP (op, 0, i + 1); 1379 1380 if (GET_CODE (elt) != SET 1381 || GET_CODE (SET_SRC (elt)) != REG 1382 || GET_MODE (SET_SRC (elt)) != SImode 1383 || REGNO (SET_SRC (elt)) != src_regno + i 1384 || GET_CODE (SET_DEST (elt)) != MEM 1385 || GET_MODE (SET_DEST (elt)) != SImode 1386 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 1387 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) 1388 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT 1389 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) 1390 return 0; 1391 } 1392 1393 return 1; 1394}) 1395 1396;; Return 1 if OP is valid for a save_world call in prologue, known to be 1397;; a PARLLEL. 1398(define_predicate "save_world_operation" 1399 (match_code "parallel") 1400{ 1401 int index; 1402 int i; 1403 rtx elt; 1404 int count = XVECLEN (op, 0); 1405 1406 if (count != 54) 1407 return 0; 1408 1409 index = 0; 1410 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1411 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1412 return 0; 1413 1414 for (i=1; i <= 18; i++) 1415 { 1416 elt = XVECEXP (op, 0, index++); 1417 if (GET_CODE (elt) != SET 1418 || GET_CODE (SET_DEST (elt)) != MEM 1419 || ! memory_operand (SET_DEST (elt), DFmode) 1420 || GET_CODE (SET_SRC (elt)) != REG 1421 || GET_MODE (SET_SRC (elt)) != DFmode) 1422 return 0; 1423 } 1424 1425 for (i=1; i <= 12; i++) 1426 { 1427 elt = XVECEXP (op, 0, index++); 1428 if (GET_CODE (elt) != SET 1429 || GET_CODE (SET_DEST (elt)) != MEM 1430 || GET_CODE (SET_SRC (elt)) != REG 1431 || GET_MODE (SET_SRC (elt)) != V4SImode) 1432 return 0; 1433 } 1434 1435 for (i=1; i <= 19; i++) 1436 { 1437 elt = XVECEXP (op, 0, index++); 1438 if (GET_CODE (elt) != SET 1439 || GET_CODE (SET_DEST (elt)) != MEM 1440 || ! memory_operand (SET_DEST (elt), Pmode) 1441 || GET_CODE (SET_SRC (elt)) != REG 1442 || GET_MODE (SET_SRC (elt)) != Pmode) 1443 return 0; 1444 } 1445 1446 elt = XVECEXP (op, 0, index++); 1447 if (GET_CODE (elt) != SET 1448 || GET_CODE (SET_DEST (elt)) != MEM 1449 || ! memory_operand (SET_DEST (elt), Pmode) 1450 || GET_CODE (SET_SRC (elt)) != REG 1451 || REGNO (SET_SRC (elt)) != CR2_REGNO 1452 || GET_MODE (SET_SRC (elt)) != Pmode) 1453 return 0; 1454 1455 if (GET_CODE (XVECEXP (op, 0, index++)) != SET 1456 || GET_CODE (XVECEXP (op, 0, index++)) != SET) 1457 return 0; 1458 return 1; 1459}) 1460 1461;; Return 1 if OP is valid for a restore_world call in epilogue, known to be 1462;; a PARLLEL. 1463(define_predicate "restore_world_operation" 1464 (match_code "parallel") 1465{ 1466 int index; 1467 int i; 1468 rtx elt; 1469 int count = XVECLEN (op, 0); 1470 1471 if (count != 59) 1472 return 0; 1473 1474 index = 0; 1475 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN 1476 || GET_CODE (XVECEXP (op, 0, index++)) != USE 1477 || GET_CODE (XVECEXP (op, 0, index++)) != USE 1478 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) 1479 return 0; 1480 1481 elt = XVECEXP (op, 0, index++); 1482 if (GET_CODE (elt) != SET 1483 || GET_CODE (SET_SRC (elt)) != MEM 1484 || ! memory_operand (SET_SRC (elt), Pmode) 1485 || GET_CODE (SET_DEST (elt)) != REG 1486 || REGNO (SET_DEST (elt)) != CR2_REGNO 1487 || GET_MODE (SET_DEST (elt)) != Pmode) 1488 return 0; 1489 1490 for (i=1; i <= 19; i++) 1491 { 1492 elt = XVECEXP (op, 0, index++); 1493 if (GET_CODE (elt) != SET 1494 || GET_CODE (SET_SRC (elt)) != MEM 1495 || ! memory_operand (SET_SRC (elt), Pmode) 1496 || GET_CODE (SET_DEST (elt)) != REG 1497 || GET_MODE (SET_DEST (elt)) != Pmode) 1498 return 0; 1499 } 1500 1501 for (i=1; i <= 12; i++) 1502 { 1503 elt = XVECEXP (op, 0, index++); 1504 if (GET_CODE (elt) != SET 1505 || GET_CODE (SET_SRC (elt)) != MEM 1506 || GET_CODE (SET_DEST (elt)) != REG 1507 || GET_MODE (SET_DEST (elt)) != V4SImode) 1508 return 0; 1509 } 1510 1511 for (i=1; i <= 18; i++) 1512 { 1513 elt = XVECEXP (op, 0, index++); 1514 if (GET_CODE (elt) != SET 1515 || GET_CODE (SET_SRC (elt)) != MEM 1516 || ! memory_operand (SET_SRC (elt), DFmode) 1517 || GET_CODE (SET_DEST (elt)) != REG 1518 || GET_MODE (SET_DEST (elt)) != DFmode) 1519 return 0; 1520 } 1521 1522 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1523 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1524 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1525 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1526 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1527 return 0; 1528 return 1; 1529}) 1530 1531;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. 1532(define_predicate "vrsave_operation" 1533 (match_code "parallel") 1534{ 1535 int count = XVECLEN (op, 0); 1536 unsigned int dest_regno, src_regno; 1537 int i; 1538 1539 if (count <= 1 1540 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1541 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1542 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE 1543 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) 1544 return 0; 1545 1546 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1547 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); 1548 1549 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) 1550 return 0; 1551 1552 for (i = 1; i < count; i++) 1553 { 1554 rtx elt = XVECEXP (op, 0, i); 1555 1556 if (GET_CODE (elt) != CLOBBER 1557 && GET_CODE (elt) != SET) 1558 return 0; 1559 } 1560 1561 return 1; 1562}) 1563 1564;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. 1565(define_predicate "mfcr_operation" 1566 (match_code "parallel") 1567{ 1568 int count = XVECLEN (op, 0); 1569 int i; 1570 1571 /* Perform a quick check so we don't blow up below. */ 1572 if (count < 1 1573 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1574 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1575 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1576 return 0; 1577 1578 for (i = 0; i < count; i++) 1579 { 1580 rtx exp = XVECEXP (op, 0, i); 1581 rtx unspec; 1582 int maskval; 1583 rtx src_reg; 1584 1585 src_reg = XVECEXP (SET_SRC (exp), 0, 0); 1586 1587 if (GET_CODE (src_reg) != REG 1588 || GET_MODE (src_reg) != CCmode 1589 || ! CR_REGNO_P (REGNO (src_reg))) 1590 return 0; 1591 1592 if (GET_CODE (exp) != SET 1593 || GET_CODE (SET_DEST (exp)) != REG 1594 || GET_MODE (SET_DEST (exp)) != SImode 1595 || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) 1596 return 0; 1597 unspec = SET_SRC (exp); 1598 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); 1599 1600 if (GET_CODE (unspec) != UNSPEC 1601 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR 1602 || XVECLEN (unspec, 0) != 2 1603 || XVECEXP (unspec, 0, 0) != src_reg 1604 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT 1605 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1606 return 0; 1607 } 1608 return 1; 1609}) 1610 1611;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. 1612(define_predicate "mtcrf_operation" 1613 (match_code "parallel") 1614{ 1615 int count = XVECLEN (op, 0); 1616 int i; 1617 rtx src_reg; 1618 1619 /* Perform a quick check so we don't blow up below. */ 1620 if (count < 1 1621 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1622 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1623 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1624 return 0; 1625 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); 1626 1627 if (GET_CODE (src_reg) != REG 1628 || GET_MODE (src_reg) != SImode 1629 || ! INT_REGNO_P (REGNO (src_reg))) 1630 return 0; 1631 1632 for (i = 0; i < count; i++) 1633 { 1634 rtx exp = XVECEXP (op, 0, i); 1635 rtx unspec; 1636 int maskval; 1637 1638 if (GET_CODE (exp) != SET 1639 || GET_CODE (SET_DEST (exp)) != REG 1640 || GET_MODE (SET_DEST (exp)) != CCmode 1641 || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) 1642 return 0; 1643 unspec = SET_SRC (exp); 1644 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); 1645 1646 if (GET_CODE (unspec) != UNSPEC 1647 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR 1648 || XVECLEN (unspec, 0) != 2 1649 || XVECEXP (unspec, 0, 0) != src_reg 1650 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT 1651 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1652 return 0; 1653 } 1654 return 1; 1655}) 1656 1657;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL. 1658(define_predicate "crsave_operation" 1659 (match_code "parallel") 1660{ 1661 int count = XVECLEN (op, 0); 1662 int i; 1663 1664 for (i = 1; i < count; i++) 1665 { 1666 rtx exp = XVECEXP (op, 0, i); 1667 1668 if (GET_CODE (exp) != USE 1669 || GET_CODE (XEXP (exp, 0)) != REG 1670 || GET_MODE (XEXP (exp, 0)) != CCmode 1671 || ! CR_REGNO_P (REGNO (XEXP (exp, 0)))) 1672 return 0; 1673 } 1674 return 1; 1675}) 1676 1677;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. 1678(define_predicate "lmw_operation" 1679 (match_code "parallel") 1680{ 1681 int count = XVECLEN (op, 0); 1682 unsigned int dest_regno; 1683 rtx src_addr; 1684 unsigned int base_regno; 1685 HOST_WIDE_INT offset; 1686 int i; 1687 1688 /* Perform a quick check so we don't blow up below. */ 1689 if (count <= 1 1690 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1691 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1692 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) 1693 return 0; 1694 1695 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1696 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 1697 1698 if (dest_regno > 31 1699 || count != 32 - (int) dest_regno) 1700 return 0; 1701 1702 if (legitimate_indirect_address_p (src_addr, 0)) 1703 { 1704 offset = 0; 1705 base_regno = REGNO (src_addr); 1706 if (base_regno == 0) 1707 return 0; 1708 } 1709 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false)) 1710 { 1711 offset = INTVAL (XEXP (src_addr, 1)); 1712 base_regno = REGNO (XEXP (src_addr, 0)); 1713 } 1714 else 1715 return 0; 1716 1717 for (i = 0; i < count; i++) 1718 { 1719 rtx elt = XVECEXP (op, 0, i); 1720 rtx newaddr; 1721 rtx addr_reg; 1722 HOST_WIDE_INT newoffset; 1723 1724 if (GET_CODE (elt) != SET 1725 || GET_CODE (SET_DEST (elt)) != REG 1726 || GET_MODE (SET_DEST (elt)) != SImode 1727 || REGNO (SET_DEST (elt)) != dest_regno + i 1728 || GET_CODE (SET_SRC (elt)) != MEM 1729 || GET_MODE (SET_SRC (elt)) != SImode) 1730 return 0; 1731 newaddr = XEXP (SET_SRC (elt), 0); 1732 if (legitimate_indirect_address_p (newaddr, 0)) 1733 { 1734 newoffset = 0; 1735 addr_reg = newaddr; 1736 } 1737 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) 1738 { 1739 addr_reg = XEXP (newaddr, 0); 1740 newoffset = INTVAL (XEXP (newaddr, 1)); 1741 } 1742 else 1743 return 0; 1744 if (REGNO (addr_reg) != base_regno 1745 || newoffset != offset + 4 * i) 1746 return 0; 1747 } 1748 1749 return 1; 1750}) 1751 1752;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. 1753(define_predicate "stmw_operation" 1754 (match_code "parallel") 1755{ 1756 int count = XVECLEN (op, 0); 1757 unsigned int src_regno; 1758 rtx dest_addr; 1759 unsigned int base_regno; 1760 HOST_WIDE_INT offset; 1761 int i; 1762 1763 /* Perform a quick check so we don't blow up below. */ 1764 if (count <= 1 1765 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1766 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM 1767 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) 1768 return 0; 1769 1770 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 1771 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 1772 1773 if (src_regno > 31 1774 || count != 32 - (int) src_regno) 1775 return 0; 1776 1777 if (legitimate_indirect_address_p (dest_addr, 0)) 1778 { 1779 offset = 0; 1780 base_regno = REGNO (dest_addr); 1781 if (base_regno == 0) 1782 return 0; 1783 } 1784 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false)) 1785 { 1786 offset = INTVAL (XEXP (dest_addr, 1)); 1787 base_regno = REGNO (XEXP (dest_addr, 0)); 1788 } 1789 else 1790 return 0; 1791 1792 for (i = 0; i < count; i++) 1793 { 1794 rtx elt = XVECEXP (op, 0, i); 1795 rtx newaddr; 1796 rtx addr_reg; 1797 HOST_WIDE_INT newoffset; 1798 1799 if (GET_CODE (elt) != SET 1800 || GET_CODE (SET_SRC (elt)) != REG 1801 || GET_MODE (SET_SRC (elt)) != SImode 1802 || REGNO (SET_SRC (elt)) != src_regno + i 1803 || GET_CODE (SET_DEST (elt)) != MEM 1804 || GET_MODE (SET_DEST (elt)) != SImode) 1805 return 0; 1806 newaddr = XEXP (SET_DEST (elt), 0); 1807 if (legitimate_indirect_address_p (newaddr, 0)) 1808 { 1809 newoffset = 0; 1810 addr_reg = newaddr; 1811 } 1812 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) 1813 { 1814 addr_reg = XEXP (newaddr, 0); 1815 newoffset = INTVAL (XEXP (newaddr, 1)); 1816 } 1817 else 1818 return 0; 1819 if (REGNO (addr_reg) != base_regno 1820 || newoffset != offset + 4 * i) 1821 return 0; 1822 } 1823 1824 return 1; 1825}) 1826 1827;; Return 1 if OP is a stack tie operand. 1828(define_predicate "tie_operand" 1829 (match_code "parallel") 1830{ 1831 return (GET_CODE (XVECEXP (op, 0, 0)) == SET 1832 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM 1833 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode 1834 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx); 1835}) 1836 1837;; Match a small code model toc reference (or medium and large 1838;; model toc references before reload). 1839(define_predicate "small_toc_ref" 1840 (match_code "unspec,plus") 1841{ 1842 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode)) 1843 op = XEXP (op, 0); 1844 1845 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; 1846}) 1847 1848;; Match the TOC memory operand that can be fused with an addis instruction. 1849;; This is used in matching a potential fused address before register 1850;; allocation. 1851(define_predicate "toc_fusion_mem_raw" 1852 (match_code "mem") 1853{ 1854 if (!TARGET_TOC_FUSION_INT || !can_create_pseudo_p ()) 1855 return false; 1856 1857 return small_toc_ref (XEXP (op, 0), Pmode); 1858}) 1859 1860;; Match the memory operand that has been fused with an addis instruction and 1861;; wrapped inside of an (unspec [...] UNSPEC_FUSION_ADDIS) wrapper. 1862(define_predicate "toc_fusion_mem_wrapped" 1863 (match_code "mem") 1864{ 1865 rtx addr; 1866 1867 if (!TARGET_TOC_FUSION_INT) 1868 return false; 1869 1870 if (!MEM_P (op)) 1871 return false; 1872 1873 addr = XEXP (op, 0); 1874 return (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS); 1875}) 1876 1877;; Match the first insn (addis) in fusing the combination of addis and loads to 1878;; GPR registers on power8. 1879(define_predicate "fusion_gpr_addis" 1880 (match_code "const_int,high,plus") 1881{ 1882 HOST_WIDE_INT value; 1883 rtx int_const; 1884 1885 if (GET_CODE (op) == HIGH) 1886 return 1; 1887 1888 if (CONST_INT_P (op)) 1889 int_const = op; 1890 1891 else if (GET_CODE (op) == PLUS 1892 && base_reg_operand (XEXP (op, 0), Pmode) 1893 && CONST_INT_P (XEXP (op, 1))) 1894 int_const = XEXP (op, 1); 1895 1896 else 1897 return 0; 1898 1899 value = INTVAL (int_const); 1900 if ((value & (HOST_WIDE_INT)0xffff) != 0) 1901 return 0; 1902 1903 if ((value & (HOST_WIDE_INT)0xffff0000) == 0) 1904 return 0; 1905 1906 /* Power8 currently will only do the fusion if the top 11 bits of the addis 1907 value are all 1's or 0's. Ignore this restriction if we are testing 1908 advanced fusion. */ 1909 if (TARGET_P9_FUSION) 1910 return 1; 1911 1912 return (IN_RANGE (value >> 16, -32, 31)); 1913}) 1914 1915;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis 1916;; and loads to GPR registers on power8. 1917(define_predicate "fusion_gpr_mem_load" 1918 (match_code "mem,sign_extend,zero_extend") 1919{ 1920 rtx addr, base, offset; 1921 1922 /* Handle sign/zero extend. */ 1923 if (GET_CODE (op) == ZERO_EXTEND 1924 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND)) 1925 { 1926 op = XEXP (op, 0); 1927 mode = GET_MODE (op); 1928 } 1929 1930 if (!MEM_P (op)) 1931 return 0; 1932 1933 switch (mode) 1934 { 1935 case E_QImode: 1936 case E_HImode: 1937 case E_SImode: 1938 break; 1939 1940 case E_DImode: 1941 if (!TARGET_POWERPC64) 1942 return 0; 1943 break; 1944 1945 default: 1946 return 0; 1947 } 1948 1949 addr = XEXP (op, 0); 1950 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 1951 return 0; 1952 1953 base = XEXP (addr, 0); 1954 if (!base_reg_operand (base, GET_MODE (base))) 1955 return 0; 1956 1957 offset = XEXP (addr, 1); 1958 1959 if (GET_CODE (addr) == PLUS) 1960 return satisfies_constraint_I (offset); 1961 1962 else if (GET_CODE (addr) == LO_SUM) 1963 { 1964 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 1965 return small_toc_ref (offset, GET_MODE (offset)); 1966 1967 else if (TARGET_ELF && !TARGET_POWERPC64) 1968 return CONSTANT_P (offset); 1969 } 1970 1971 return 0; 1972}) 1973 1974;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the 1975;; memory field with both the addis and the memory offset. Sign extension 1976;; is not handled here, since lha and lwa are not fused. 1977;; With P9 fusion, also match a fpr/vector load and float_extend 1978(define_predicate "fusion_addis_mem_combo_load" 1979 (match_code "mem,zero_extend,float_extend") 1980{ 1981 rtx addr, base, offset; 1982 1983 /* Handle zero/float extend. */ 1984 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND) 1985 { 1986 op = XEXP (op, 0); 1987 mode = GET_MODE (op); 1988 } 1989 1990 if (!MEM_P (op)) 1991 return 0; 1992 1993 switch (mode) 1994 { 1995 case E_QImode: 1996 case E_HImode: 1997 case E_SImode: 1998 break; 1999 2000 /* Do not fuse 64-bit DImode in 32-bit since it splits into two 2001 separate instructions. */ 2002 case E_DImode: 2003 if (!TARGET_POWERPC64) 2004 return 0; 2005 break; 2006 2007 /* ISA 2.08/power8 only had fusion of GPR loads. */ 2008 case E_SFmode: 2009 if (!TARGET_P9_FUSION) 2010 return 0; 2011 break; 2012 2013 /* ISA 2.08/power8 only had fusion of GPR loads. Do not allow 64-bit 2014 DFmode in 32-bit if -msoft-float since it splits into two separate 2015 instructions. */ 2016 case E_DFmode: 2017 if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION) 2018 return 0; 2019 break; 2020 2021 default: 2022 return 0; 2023 } 2024 2025 addr = XEXP (op, 0); 2026 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 2027 return 0; 2028 2029 base = XEXP (addr, 0); 2030 if (!fusion_gpr_addis (base, GET_MODE (base))) 2031 return 0; 2032 2033 offset = XEXP (addr, 1); 2034 if (GET_CODE (addr) == PLUS) 2035 return satisfies_constraint_I (offset); 2036 2037 else if (GET_CODE (addr) == LO_SUM) 2038 { 2039 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 2040 return small_toc_ref (offset, GET_MODE (offset)); 2041 2042 else if (TARGET_ELF && !TARGET_POWERPC64) 2043 return CONSTANT_P (offset); 2044 } 2045 2046 return 0; 2047}) 2048 2049;; Like fusion_addis_mem_combo_load, but for stores 2050(define_predicate "fusion_addis_mem_combo_store" 2051 (match_code "mem") 2052{ 2053 rtx addr, base, offset; 2054 2055 if (!MEM_P (op) || !TARGET_P9_FUSION) 2056 return 0; 2057 2058 switch (mode) 2059 { 2060 case E_QImode: 2061 case E_HImode: 2062 case E_SImode: 2063 case E_SFmode: 2064 break; 2065 2066 /* Do not fuse 64-bit DImode in 32-bit since it splits into two 2067 separate instructions. */ 2068 case E_DImode: 2069 if (!TARGET_POWERPC64) 2070 return 0; 2071 break; 2072 2073 /* Do not allow 64-bit DFmode in 32-bit if -msoft-float since it splits 2074 into two separate instructions. Do allow fusion if we have hardware 2075 floating point. */ 2076 case E_DFmode: 2077 if (!TARGET_POWERPC64 && !TARGET_DF_FPR) 2078 return 0; 2079 break; 2080 2081 default: 2082 return 0; 2083 } 2084 2085 addr = XEXP (op, 0); 2086 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 2087 return 0; 2088 2089 base = XEXP (addr, 0); 2090 if (!fusion_gpr_addis (base, GET_MODE (base))) 2091 return 0; 2092 2093 offset = XEXP (addr, 1); 2094 if (GET_CODE (addr) == PLUS) 2095 return satisfies_constraint_I (offset); 2096 2097 else if (GET_CODE (addr) == LO_SUM) 2098 { 2099 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 2100 return small_toc_ref (offset, GET_MODE (offset)); 2101 2102 else if (TARGET_ELF && !TARGET_POWERPC64) 2103 return CONSTANT_P (offset); 2104 } 2105 2106 return 0; 2107}) 2108 2109;; Return true if the operand is a float_extend or zero extend of an 2110;; offsettable memory operand suitable for use in fusion 2111(define_predicate "fusion_offsettable_mem_operand" 2112 (match_code "mem,zero_extend,float_extend") 2113{ 2114 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND) 2115 { 2116 op = XEXP (op, 0); 2117 mode = GET_MODE (op); 2118 } 2119 2120 if (!memory_operand (op, mode)) 2121 return 0; 2122 2123 return offsettable_nonstrict_memref_p (op); 2124}) 2125