1;; Scheduling description for UltraSPARC-III.
2;;   Copyright (C) 2002-2018 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3.  If not see
18;; <http://www.gnu.org/licenses/>.
19
20;; UltraSPARC-III is a quad-issue processor.
21;;
22;; It is also a much simpler beast than Ultra-I/II, no silly
23;; slotting rules and both integer units are fully symmetric.
24;; It does still have single-issue instructions though.
25
26(define_automaton "ultrasparc3_0,ultrasparc3_1")
27
28(define_cpu_unit "us3_ms,us3_br,us3_fpm" "ultrasparc3_0")
29(define_cpu_unit "us3_a0,us3_a1,us3_slot0,\
30                  us3_slot1,us3_slot2,us3_slot3,us3_fpa" "ultrasparc3_1")
31(define_cpu_unit "us3_load_writeback" "ultrasparc3_1")
32
33(define_reservation "us3_slotany" "(us3_slot0 | us3_slot1 | us3_slot2 | us3_slot3)")
34(define_reservation "us3_single_issue" "us3_slot0 + us3_slot1 + us3_slot2 + us3_slot3")
35(define_reservation "us3_ax" "(us3_a0 | us3_a1)")
36
37(define_insn_reservation "us3_single" 1
38  (and (eq_attr "cpu" "ultrasparc3")
39    (eq_attr "type" "multi,savew,flushw,iflush,trap,edge,gsr"))
40  "us3_single_issue")
41
42(define_insn_reservation "us3_integer" 1
43  (and (eq_attr "cpu" "ultrasparc3")
44    (eq_attr "type" "ialu,shift,compare"))
45  "us3_ax + us3_slotany")
46
47(define_insn_reservation "us3_ialuX" 5
48  (and (eq_attr "cpu" "ultrasparc3")
49    (eq_attr "type" "ialuX"))
50  "us3_single_issue*4, nothing")
51
52(define_insn_reservation "us3_cmove" 2
53  (and (eq_attr "cpu" "ultrasparc3")
54    (eq_attr "type" "cmove"))
55  "us3_ms + us3_br + us3_slotany, nothing")
56
57(define_insn_reservation "us3_array" 2
58  (and (eq_attr "cpu" "ultrasparc3")
59    (eq_attr "type" "array,edgen,bmask"))
60  "us3_ms + us3_slotany, nothing")
61
62;; ??? Not entirely accurate.
63;; ??? It can run from 6 to 9 cycles.  The first cycle the MS pipe
64;; ??? is needed, and the instruction group is broken right after
65;; ??? the imul.  Then 'helper' instructions are generated to perform
66;; ??? each further stage of the multiplication, each such 'helper' is
67;; ??? single group.  So, the reservation aspect is represented accurately
68;; ??? here, but the variable cycles are not.
69;; ??? Currently I have no idea how to determine the variability, but once
70;; ??? known we can simply add a define_bypass or similar to model it.
71(define_insn_reservation "us3_imul" 7
72  (and (eq_attr "cpu" "ultrasparc3")
73    (eq_attr "type" "imul"))
74  "us3_ms + us3_slotany, us3_single_issue*4, nothing*2")
75
76(define_insn_reservation "us3_idiv" 72
77  (and (eq_attr "cpu" "ultrasparc3")
78    (eq_attr "type" "idiv"))
79  "us3_ms + us3_slotany, us3_single_issue*69, nothing*2")
80
81;; UltraSPARC-III has a similar load delay as UltraSPARC-I/II except
82;; that all loads except 32-bit/64-bit unsigned loads take the extra
83;; delay for sign/zero extension.
84(define_insn_reservation "us3_2cycle_load" 2
85  (and (eq_attr "cpu" "ultrasparc3")
86    (and (eq_attr "type" "load,fpload")
87      (eq_attr "us3load_type" "2cycle")))
88  "us3_ms + us3_slotany, us3_load_writeback")
89
90(define_insn_reservation "us3_load_delayed" 3
91  (and (eq_attr "cpu" "ultrasparc3")
92    (and (eq_attr "type" "load,sload")
93      (eq_attr "us3load_type" "3cycle")))
94  "us3_ms + us3_slotany, nothing, us3_load_writeback")
95
96(define_insn_reservation "us3_store" 1
97  (and (eq_attr "cpu" "ultrasparc3")
98    (eq_attr "type" "store,fpstore"))
99  "us3_ms + us3_slotany")
100
101(define_insn_reservation "us3_branch" 1
102  (and (eq_attr "cpu" "ultrasparc3")
103    (eq_attr "type" "branch"))
104  "us3_br + us3_slotany")
105
106(define_insn_reservation "us3_call_jmpl" 1
107  (and (eq_attr "cpu" "ultrasparc3")
108    (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch"))
109  "us3_br + us3_ms + us3_slotany")
110
111(define_insn_reservation "us3_fmov" 3
112  (and (eq_attr "cpu" "ultrasparc3")
113    (eq_attr "type" "fpmove"))
114  "us3_fpa + us3_slotany, nothing*2")
115
116(define_insn_reservation "us3_fcmov" 3
117  (and (eq_attr "cpu" "ultrasparc3")
118    (eq_attr "type" "fpcmove"))
119  "us3_fpa + us3_br + us3_slotany, nothing*2")
120
121(define_insn_reservation "us3_fcrmov" 3
122  (and (eq_attr "cpu" "ultrasparc3")
123    (eq_attr "type" "fpcrmove"))
124  "us3_fpa + us3_ms + us3_slotany, nothing*2")
125
126(define_insn_reservation "us3_faddsub" 4
127  (and (eq_attr "cpu" "ultrasparc3")
128    (eq_attr "type" "fp"))
129  "us3_fpa + us3_slotany, nothing*3")
130
131(define_insn_reservation "us3_fpcmp" 5
132  (and (eq_attr "cpu" "ultrasparc3")
133    (eq_attr "type" "fpcmp"))
134  "us3_fpa + us3_slotany, nothing*4")
135
136(define_insn_reservation "us3_fmult" 4
137 (and (eq_attr "cpu" "ultrasparc3")
138    (eq_attr "type" "fpmul"))
139  "us3_fpm + us3_slotany, nothing*3")
140
141(define_insn_reservation "us3_fdivs" 17
142  (and (eq_attr "cpu" "ultrasparc3")
143    (eq_attr "type" "fpdivs"))
144  "(us3_fpm + us3_slotany), us3_fpm*14, nothing*2")
145
146(define_insn_reservation "us3_fsqrts" 20
147  (and (eq_attr "cpu" "ultrasparc3")
148    (eq_attr "type" "fpsqrts"))
149  "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2")
150
151(define_insn_reservation "us3_fdivd" 20
152  (and (eq_attr "cpu" "ultrasparc3")
153    (eq_attr "type" "fpdivd"))
154  "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2")
155
156(define_insn_reservation "us3_fsqrtd" 29
157  (and (eq_attr "cpu" "ultrasparc3")
158    (eq_attr "type" "fpsqrtd"))
159  "(us3_fpm + us3_slotany), us3_fpm*26, nothing*2")
160
161;; Any store may multi issue with the insn creating the source
162;; data as long as that creating insn is not an FPU div/sqrt.
163;; We need a special guard function because this bypass does
164;; not apply to the address inputs of the store.
165(define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store"
166   "store_data_bypass_p")
167
168;; An integer branch may execute in the same cycle as the compare
169;; creating the condition codes.
170(define_bypass 0 "us3_integer" "us3_branch")
171
172;; If FMOVfcc is user of FPCMP, latency is only 1 cycle.
173(define_bypass 1 "us3_fpcmp" "us3_fcmov")
174
175;; VIS scheduling
176(define_insn_reservation "us3_fga"
177  3
178  (and (eq_attr "cpu" "ultrasparc3")
179       (eq_attr "type" "fga,visl,viscmp,vismv"))
180  "us3_fpa + us3_slotany, nothing*2")
181
182(define_insn_reservation "us3_fgm"
183  4
184  (and (eq_attr "cpu" "ultrasparc3")
185       (eq_attr "type" "fgm_pack,fgm_mul"))
186  "us3_fpm + us3_slotany, nothing*3")
187
188(define_insn_reservation "us3_pdist"
189  4
190  (and (eq_attr "cpu" "ultrasparc3")
191       (eq_attr "type" "pdist"))
192  "us3_fpm + us3_slotany, nothing*3")
193
194(define_bypass 1 "us3_pdist" "us3_pdist")
195