1 /* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */ 2 /* { dg-skip-if "" { powerpc*-*-darwin* } } */ 3 /* { dg-require-effective-target powerpc_p9vector_ok } */ 4 /* { dg-options "-mvsx -O2 -mcpu=power9" } */ 5 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ 6 7 /* Expected instruction counts for Little Endian targeting Power9. */ 8 9 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ 10 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */ 11 /* { dg-final { scan-assembler-times "xxlnor" 7 } } */ 12 /* We generate xxlor instructions for many reasons other than or'ing vector 13 operands or calling __builtin_vec_or(), which means we cannot rely on 14 their usage counts being stable. Therefore, we just ensure at least one 15 xxlor instruction was generated. */ 16 /* { dg-final { scan-assembler "xxlor" } } */ 17 /* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */ 18 /* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ 19 /* { dg-final { scan-assembler-times "xvcmpgedp" 8 } } */ 20 /* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ 21 /* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ 22 /* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ 23 /* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ 24 /* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ 25 /* { dg-final { scan-assembler-times "xvmindp" 1 } } */ 26 /* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ 27 /* { dg-final { scan-assembler-times "vperm" 1 } } */ 28 /* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ 29 /* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ 30 /* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ 31 /* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ 32 /* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ 33 /* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ 34 /* { dg-final { scan-assembler-times "xxland" 13 } } */ 35 36 /* Source code for the test in vsx-vector-6.h */ 37 #include "vsx-vector-6.h" 38