1 /* ---------------------------------------------------------------------------- 2 * SAM Software Package License 3 * ---------------------------------------------------------------------------- 4 * Copyright (c) 2012, Atmel Corporation 5 * 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following condition is met: 10 * 11 * - Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the disclaimer below. 13 * 14 * Atmel's name may not be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * ---------------------------------------------------------------------------- 28 */ 29 30 #ifndef _SAM3N2B_ 31 #define _SAM3N2B_ 32 33 /** \addtogroup SAM3N2B_definitions SAM3N2B definitions 34 This file defines all structures and symbols for SAM3N2B: 35 - registers and bitfields 36 - peripheral base address 37 - peripheral ID 38 - PIO definitions 39 */ 40 /*@{*/ 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 47 #include <stdint.h> 48 #ifndef __cplusplus 49 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 50 #else 51 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 52 #endif 53 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 54 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 55 #endif 56 57 /* ************************************************************************** */ 58 /* CMSIS DEFINITIONS FOR SAM3N2B */ 59 /* ************************************************************************** */ 60 /** \addtogroup SAM3N2B_cmsis CMSIS Definitions */ 61 /*@{*/ 62 63 /**< Interrupt Number Definition */ 64 typedef enum IRQn 65 { 66 /****** Cortex-M3 Processor Exceptions Numbers ******************************/ 67 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ 68 MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ 69 BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ 70 UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ 71 SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ 72 DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ 73 PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ 74 SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ 75 /****** SAM3N2B specific Interrupt Numbers *********************************/ 76 77 SUPC_IRQn = 0, /**< 0 SAM3N2B Supply Controller (SUPC) */ 78 RSTC_IRQn = 1, /**< 1 SAM3N2B Reset Controller (RSTC) */ 79 RTC_IRQn = 2, /**< 2 SAM3N2B Real Time Clock (RTC) */ 80 RTT_IRQn = 3, /**< 3 SAM3N2B Real Time Timer (RTT) */ 81 WDT_IRQn = 4, /**< 4 SAM3N2B Watchdog Timer (WDT) */ 82 PMC_IRQn = 5, /**< 5 SAM3N2B Power Management Controller (PMC) */ 83 EFC_IRQn = 6, /**< 6 SAM3N2B Enhanced Flash Controller (EFC) */ 84 UART0_IRQn = 8, /**< 8 SAM3N2B UART 0 (UART0) */ 85 UART1_IRQn = 9, /**< 9 SAM3N2B UART 1 (UART1) */ 86 PIOA_IRQn = 11, /**< 11 SAM3N2B Parallel I/O Controller A (PIOA) */ 87 PIOB_IRQn = 12, /**< 12 SAM3N2B Parallel I/O Controller B (PIOB) */ 88 USART0_IRQn = 14, /**< 14 SAM3N2B USART 0 (USART0) */ 89 USART1_IRQn = 15, /**< 15 SAM3N2B USART 1 (USART1) */ 90 TWI0_IRQn = 19, /**< 19 SAM3N2B Two Wire Interface 0 (TWI0) */ 91 TWI1_IRQn = 20, /**< 20 SAM3N2B Two Wire Interface 1 (TWI1) */ 92 SPI_IRQn = 21, /**< 21 SAM3N2B Serial Peripheral Interface (SPI) */ 93 TC0_IRQn = 23, /**< 23 SAM3N2B Timer/Counter 0 (TC0) */ 94 TC1_IRQn = 24, /**< 24 SAM3N2B Timer/Counter 1 (TC1) */ 95 TC2_IRQn = 25, /**< 25 SAM3N2B Timer/Counter 2 (TC2) */ 96 ADC_IRQn = 29, /**< 29 SAM3N2B Analog To Digital Converter (ADC) */ 97 DACC_IRQn = 30, /**< 30 SAM3N2B Digital To Analog Converter (DACC) */ 98 PWM_IRQn = 31, /**< 31 SAM3N2B Pulse Width Modulation (PWM) */ 99 100 PERIPH_COUNT_IRQn = 32 /**< Number of peripheral IDs */ 101 } IRQn_Type; 102 103 typedef struct _DeviceVectors 104 { 105 /* Stack pointer */ 106 void* pvStack; 107 108 /* Cortex-M handlers */ 109 void* pfnReset_Handler; 110 void* pfnNMI_Handler; 111 void* pfnHardFault_Handler; 112 void* pfnMemManage_Handler; 113 void* pfnBusFault_Handler; 114 void* pfnUsageFault_Handler; 115 void* pfnReserved1_Handler; 116 void* pfnReserved2_Handler; 117 void* pfnReserved3_Handler; 118 void* pfnReserved4_Handler; 119 void* pfnSVC_Handler; 120 void* pfnDebugMon_Handler; 121 void* pfnReserved5_Handler; 122 void* pfnPendSV_Handler; 123 void* pfnSysTick_Handler; 124 125 /* Peripheral handlers */ 126 void* pfnSUPC_Handler; /* 0 Supply Controller */ 127 void* pfnRSTC_Handler; /* 1 Reset Controller */ 128 void* pfnRTC_Handler; /* 2 Real Time Clock */ 129 void* pfnRTT_Handler; /* 3 Real Time Timer */ 130 void* pfnWDT_Handler; /* 4 Watchdog Timer */ 131 void* pfnPMC_Handler; /* 5 Power Management Controller */ 132 void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */ 133 void* pvReserved7; 134 void* pfnUART0_Handler; /* 8 UART 0 */ 135 void* pfnUART1_Handler; /* 9 UART 1 */ 136 void* pvReserved10; 137 void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ 138 void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ 139 void* pvReserved13; 140 void* pfnUSART0_Handler; /* 14 USART 0 */ 141 void* pfnUSART1_Handler; /* 15 USART 1 */ 142 void* pvReserved16; 143 void* pvReserved17; 144 void* pvReserved18; 145 void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ 146 void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ 147 void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ 148 void* pvReserved22; 149 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ 150 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ 151 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ 152 void* pvReserved26; 153 void* pvReserved27; 154 void* pvReserved28; 155 void* pfnADC_Handler; /* 29 Analog To Digital Converter */ 156 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ 157 void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ 158 } DeviceVectors; 159 160 /* Cortex-M3 core handlers */ 161 void Reset_Handler ( void ); 162 void NMI_Handler ( void ); 163 void HardFault_Handler ( void ); 164 void MemManage_Handler ( void ); 165 void BusFault_Handler ( void ); 166 void UsageFault_Handler ( void ); 167 void SVC_Handler ( void ); 168 void DebugMon_Handler ( void ); 169 void PendSV_Handler ( void ); 170 void SysTick_Handler ( void ); 171 172 /* Peripherals handlers */ 173 void ADC_Handler ( void ); 174 void DACC_Handler ( void ); 175 void EFC_Handler ( void ); 176 void PIOA_Handler ( void ); 177 void PIOB_Handler ( void ); 178 void PMC_Handler ( void ); 179 void PWM_Handler ( void ); 180 void RSTC_Handler ( void ); 181 void RTC_Handler ( void ); 182 void RTT_Handler ( void ); 183 void SPI_Handler ( void ); 184 void SUPC_Handler ( void ); 185 void TC0_Handler ( void ); 186 void TC1_Handler ( void ); 187 void TC2_Handler ( void ); 188 void TWI0_Handler ( void ); 189 void TWI1_Handler ( void ); 190 void UART0_Handler ( void ); 191 void UART1_Handler ( void ); 192 void USART0_Handler ( void ); 193 void USART1_Handler ( void ); 194 void WDT_Handler ( void ); 195 196 /** 197 * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 198 */ 199 200 #define __CM3_REV 0x0200 /**< SAM3N2B core revision number ([15:8] revision number, [7:0] patch number) */ 201 #define __MPU_PRESENT 0 /**< SAM3N2B does not provide a MPU */ 202 #define __NVIC_PRIO_BITS 4 /**< SAM3N2B uses 4 Bits for the Priority Levels */ 203 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 204 205 /* 206 * \brief CMSIS includes 207 */ 208 209 #include <core_cm3.h> 210 #if !defined DONT_USE_CMSIS_INIT 211 #include "system_sam3n.h" 212 #endif /* DONT_USE_CMSIS_INIT */ 213 214 /*@}*/ 215 216 /* ************************************************************************** */ 217 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2B */ 218 /* ************************************************************************** */ 219 /** \addtogroup SAM3N2B_api Peripheral Software API */ 220 /*@{*/ 221 222 #include "component/component_adc.h" 223 #include "component/component_chipid.h" 224 #include "component/component_dacc.h" 225 #include "component/component_efc.h" 226 #include "component/component_gpbr.h" 227 #include "component/component_matrix.h" 228 #include "component/component_pdc.h" 229 #include "component/component_pio.h" 230 #include "component/component_pmc.h" 231 #include "component/component_pwm.h" 232 #include "component/component_rstc.h" 233 #include "component/component_rtc.h" 234 #include "component/component_rtt.h" 235 #include "component/component_spi.h" 236 #include "component/component_supc.h" 237 #include "component/component_tc.h" 238 #include "component/component_twi.h" 239 #include "component/component_uart.h" 240 #include "component/component_usart.h" 241 #include "component/component_wdt.h" 242 /*@}*/ 243 244 /* ************************************************************************** */ 245 /* REGISTER ACCESS DEFINITIONS FOR SAM3N2B */ 246 /* ************************************************************************** */ 247 /** \addtogroup SAM3N2B_reg Registers Access Definitions */ 248 /*@{*/ 249 250 #include "instance/instance_spi.h" 251 #include "instance/instance_tc0.h" 252 #include "instance/instance_twi0.h" 253 #include "instance/instance_twi1.h" 254 #include "instance/instance_pwm.h" 255 #include "instance/instance_usart0.h" 256 #include "instance/instance_usart1.h" 257 #include "instance/instance_adc.h" 258 #include "instance/instance_dacc.h" 259 #include "instance/instance_matrix.h" 260 #include "instance/instance_pmc.h" 261 #include "instance/instance_uart0.h" 262 #include "instance/instance_chipid.h" 263 #include "instance/instance_uart1.h" 264 #include "instance/instance_efc.h" 265 #include "instance/instance_pioa.h" 266 #include "instance/instance_piob.h" 267 #include "instance/instance_rstc.h" 268 #include "instance/instance_supc.h" 269 #include "instance/instance_rtt.h" 270 #include "instance/instance_wdt.h" 271 #include "instance/instance_rtc.h" 272 #include "instance/instance_gpbr.h" 273 /*@}*/ 274 275 /* ************************************************************************** */ 276 /* PERIPHERAL ID DEFINITIONS FOR SAM3N2B */ 277 /* ************************************************************************** */ 278 /** \addtogroup SAM3N2B_id Peripheral Ids Definitions */ 279 /*@{*/ 280 281 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 282 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 283 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ 284 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ 285 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ 286 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 287 #define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ 288 #define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ 289 #define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ 290 #define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ 291 #define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ 292 #define ID_USART0 (14) /**< \brief USART 0 (USART0) */ 293 #define ID_USART1 (15) /**< \brief USART 1 (USART1) */ 294 #define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ 295 #define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ 296 #define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ 297 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ 298 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ 299 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ 300 #define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ 301 #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ 302 #define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ 303 304 #define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */ 305 /*@}*/ 306 307 /* ************************************************************************** */ 308 /* BASE ADDRESS DEFINITIONS FOR SAM3N2B */ 309 /* ************************************************************************** */ 310 /** \addtogroup SAM3N2B_base Peripheral Base Address Definitions */ 311 /*@{*/ 312 313 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 314 #define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ 315 #define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ 316 #define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ 317 #define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ 318 #define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ 319 #define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ 320 #define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ 321 #define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ 322 #define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ 323 #define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ 324 #define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ 325 #define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ 326 #define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ 327 #define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ 328 #define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ 329 #define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ 330 #define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ 331 #define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 332 #define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ 333 #define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ 334 #define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ 335 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ 336 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ 337 #define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ 338 #define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ 339 #define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ 340 #define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ 341 #define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ 342 #define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ 343 #else 344 #define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ 345 #define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ 346 #define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ 347 #define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ 348 #define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ 349 #define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ 350 #define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ 351 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ 352 #define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ 353 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ 354 #define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ 355 #define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ 356 #define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ 357 #define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ 358 #define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ 359 #define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ 360 #define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ 361 #define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 362 #define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ 363 #define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ 364 #define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ 365 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 366 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 367 #define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ 368 #define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ 369 #define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ 370 #define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ 371 #define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ 372 #define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ 373 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 374 /*@}*/ 375 376 /* ************************************************************************** */ 377 /* PIO DEFINITIONS FOR SAM3N2B */ 378 /* ************************************************************************** */ 379 /** \addtogroup SAM3N2B_pio Peripheral Pio Definitions */ 380 /*@{*/ 381 382 #include "pio/pio_sam3n2b.h" 383 /*@}*/ 384 385 /* ************************************************************************** */ 386 /* MEMORY MAPPING DEFINITIONS FOR SAM3N2B */ 387 /* ************************************************************************** */ 388 389 #define IFLASH_SIZE (0x20000u) 390 #define IFLASH_PAGE_SIZE (256u) 391 #define IFLASH_LOCK_REGION_SIZE (16384u) 392 #define IFLASH_NB_OF_PAGES (512u) 393 #define IFLASH_NB_OF_LOCK_BITS (8u) 394 #define IRAM_SIZE (0x4000u) 395 396 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ 397 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ 398 #define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ 399 400 /* ************************************************************************** */ 401 /* ELECTRICAL DEFINITIONS FOR SAM3N2B */ 402 /* ************************************************************************** */ 403 404 /* Device characteristics */ 405 #define CHIP_FREQ_SLCK_RC_MIN (20000UL) 406 #define CHIP_FREQ_SLCK_RC (32000UL) 407 #define CHIP_FREQ_SLCK_RC_MAX (44000UL) 408 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) 409 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) 410 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) 411 #define CHIP_FREQ_CPU_MAX (48000000UL) 412 #define CHIP_FREQ_XTAL_32K (32768UL) 413 #define CHIP_FREQ_XTAL_12M (12000000UL) 414 415 /* Embedded Flash Write Wait State */ 416 #define CHIP_FLASH_WRITE_WAIT_STATE (6U) 417 418 /* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ 419 #define CHIP_FREQ_FWS_0 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 420 #define CHIP_FREQ_FWS_1 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 421 #define CHIP_FREQ_FWS_2 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 422 423 424 #ifdef __cplusplus 425 } 426 #endif 427 428 /*@}*/ 429 430 #endif /* _SAM3N2B_ */ 431