1;; Instruction Classification for ARM for GNU compiler. 2 3;; Copyright (C) 1991-2018 Free Software Foundation, Inc. 4;; Contributed by ARM Ltd. 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify it 9;; under the terms of the GNU General Public License as published 10;; by the Free Software Foundation; either version 3, or (at your 11;; option) any later version. 12 13;; GCC is distributed in the hope that it will be useful, but WITHOUT 14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16;; License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22; TYPE attribute is used to classify instructions for use in scheduling. 23; 24; Instruction classification: 25; 26; adc_imm add/subtract with carry and with an immediate operand. 27; adc_reg add/subtract with carry and no immediate operand. 28; adcs_imm as adc_imm, setting condition flags. 29; adcs_reg as adc_reg, setting condition flags. 30; adr calculate address. 31; alu_ext From ARMv8-A: any arithmetic instruction that has a 32; sign/zero-extended. 33; AArch64 Only. 34; source operand 35; alu_imm any arithmetic instruction that doesn't have a shifted 36; operand and has an immediate operand. This 37; excludes MOV, MVN and RSB(S) immediate. 38; alu_sreg any arithmetic instruction that doesn't have a shifted 39; or an immediate operand. This excludes 40; MOV and MVN but includes MOVT. This also excludes 41; DSP-kind instructions. This is also the default. 42; alu_shift_imm any arithmetic instruction that has a source operand 43; shifted by a constant. This excludes simple shifts. 44; alu_shift_reg as alu_shift_imm, with the shift amount specified in a 45; register. 46; alu_dsp_reg any DSP-kind instruction like QSUB8. 47; alus_ext From ARMv8-A: as alu_ext, setting condition flags. 48; AArch64 Only. 49; alus_imm as alu_imm, setting condition flags. 50; alus_sreg as alu_sreg, setting condition flags. 51; alus_shift_imm as alu_shift_imm, setting condition flags. 52; alus_shift_reg as alu_shift_reg, setting condition flags. 53; bfm bitfield move operation. 54; bfx bitfield extract operation. 55; block blockage insn, this blocks all functional units. 56; branch branch. 57; call subroutine call. 58; clz count leading zeros (CLZ). 59; csel From ARMv8-A: conditional select. 60; extend extend instruction (SXTB, SXTH, UXTB, UXTH). 61; f_cvt conversion between float representations. 62; f_cvtf2i conversion between float and integral types. 63; f_cvti2f conversion between integral and float types. 64; f_flag transfer of co-processor flags to the CPSR. 65; f_load[d,s] double/single load from memory. Used for VFP unit. 66; f_mcr transfer arm to vfp reg. 67; f_mcrr transfer two arm regs to vfp reg. 68; f_minmax[d,s] double/single floating point minimum/maximum. 69; f_mrc transfer vfp to arm reg. 70; f_mrrc transfer vfp to two arm regs. 71; f_rint[d,s] double/single floating point rount to integral. 72; f_store[d,s] double/single store to memory. Used for VFP unit. 73; fadd[d,s] double/single floating-point scalar addition. 74; fccmp[d,s] From ARMv8-A: floating-point conditional compare. 75; fcmp[d,s] double/single floating-point compare. 76; fconst[d,s] double/single load immediate. 77; fcsel From ARMv8-A: Floating-point conditional select. 78; fdiv[d,s] double/single precision floating point division. 79; ffarith[d,s] double/single floating point abs/neg/cpy. 80; ffma[d,s] double/single floating point fused multiply-accumulate. 81; float floating point arithmetic operation. 82; fmac[d,s] double/single floating point multiply-accumulate. 83; fmov floating point to floating point register move. 84; fmul[d,s] double/single floating point multiply. 85; fsqrt[d,s] double/single precision floating point square root. 86; load_acq load-acquire. 87; load_byte load 1 byte from memory. 88; load_4 load 4 bytes from memory. 89; load_8 load 8 bytes from memory. 90; load_12 load 12 bytes from memory. 91; load_16 load 16 bytes from memory. 92; logic_imm any logical instruction that doesn't have a shifted 93; operand and has an immediate operand. 94; logic_reg any logical instruction that doesn't have a shifted 95; operand or an immediate operand. 96; logic_shift_imm any logical instruction that has a source operand 97; shifted by a constant. This excludes simple shifts. 98; logic_shift_reg as logic_shift_imm, with the shift amount specified in a 99; register. 100; logics_imm as logic_imm, setting condition flags. 101; logics_reg as logic_reg, setting condition flags. 102; logics_shift_imm as logic_shift_imm, setting condition flags. 103; logics_shift_reg as logic_shift_reg, setting condition flags. 104; mla integer multiply accumulate. 105; mlas integer multiply accumulate, flag setting. 106; mov_imm simple MOV instruction that moves an immediate to 107; register. This includes MOVW, but not MOVT. 108; mov_reg simple MOV instruction that moves a register to another 109; register. This includes MOVW, but not MOVT. 110; mov_shift simple MOV instruction, shifted operand by a constant. 111; mov_shift_reg simple MOV instruction, shifted operand by a register. 112; mrs system/special/co-processor register move. 113; mul integer multiply. 114; muls integer multiply, flag setting. 115; multiple more than one instruction, candidate for future 116; splitting, or better modeling. 117; mvn_imm inverting move instruction, immediate. 118; mvn_reg inverting move instruction, register. 119; mvn_shift inverting move instruction, shifted operand by a constant. 120; mvn_shift_reg inverting move instruction, shifted operand by a register. 121; no_insn an insn which does not represent an instruction in the 122; final output, thus having no impact on scheduling. 123; rbit reverse bits. 124; rev reverse bytes. 125; rotate_imm rotate by immediate. 126; sdiv signed division. 127; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an 128; immediate. 129; shift_reg simple shift by a register. 130; smlad signed multiply accumulate dual. 131; smladx signed multiply accumulate dual reverse. 132; smlal signed multiply accumulate long. 133; smlald signed multiply accumulate long dual. 134; smlals signed multiply accumulate long, flag setting. 135; smlalxy signed multiply accumulate, 16x16-bit, 64-bit accumulate. 136; smlawx signed multiply accumulate, 32x16-bit, 32-bit accumulate. 137; smlawy signed multiply accumulate wide, 32x16-bit, 138; 32-bit accumulate. 139; smlaxy signed multiply accumulate, 16x16-bit, 32-bit accumulate. 140; smlsd signed multiply subtract dual. 141; smlsdx signed multiply subtract dual reverse. 142; smlsld signed multiply subtract long dual. 143; smmla signed most significant word multiply accumulate. 144; smmul signed most significant word multiply. 145; smmulr signed most significant word multiply, rounded. 146; smuad signed dual multiply add. 147; smuadx signed dual multiply add reverse. 148; smull signed multiply long. 149; smulls signed multiply long, flag setting. 150; smulwy signed multiply wide, 32x16-bit, 32-bit accumulate. 151; smulxy signed multiply, 16x16-bit, 32-bit accumulate. 152; smusd signed dual multiply subtract. 153; smusdx signed dual multiply subtract reverse. 154; store_rel store-release. 155; store_4 store 4 bytes to memory. 156; store_8 store 8 bytes to memory. 157; store_12 store 12 bytes to memory. 158; store_16 store 16 bytes (or more) to memory. 159; trap cause a trap in the kernel. 160; udiv unsigned division. 161; umaal unsigned multiply accumulate accumulate long. 162; umlal unsigned multiply accumulate long. 163; umlals unsigned multiply accumulate long, flag setting. 164; umull unsigned multiply long. 165; umulls unsigned multiply long, flag setting. 166; untyped insn without type information - default, and error, 167; case. 168; 169; The classification below is for instructions used by the Wireless MMX 170; Technology. Each attribute value is used to classify an instruction of the 171; same name or family. 172; 173; wmmx_tandc 174; wmmx_tbcst 175; wmmx_textrc 176; wmmx_textrm 177; wmmx_tinsr 178; wmmx_tmcr 179; wmmx_tmcrr 180; wmmx_tmia 181; wmmx_tmiaph 182; wmmx_tmiaxy 183; wmmx_tmrc 184; wmmx_tmrrc 185; wmmx_tmovmsk 186; wmmx_torc 187; wmmx_torvsc 188; wmmx_wabs 189; wmmx_wdiff 190; wmmx_wacc 191; wmmx_wadd 192; wmmx_waddbhus 193; wmmx_waddsubhx 194; wmmx_waligni 195; wmmx_walignr 196; wmmx_wand 197; wmmx_wandn 198; wmmx_wavg2 199; wmmx_wavg4 200; wmmx_wcmpeq 201; wmmx_wcmpgt 202; wmmx_wmac 203; wmmx_wmadd 204; wmmx_wmax 205; wmmx_wmerge 206; wmmx_wmiawxy 207; wmmx_wmiaxy 208; wmmx_wmin 209; wmmx_wmov 210; wmmx_wmul 211; wmmx_wmulw 212; wmmx_wldr 213; wmmx_wor 214; wmmx_wpack 215; wmmx_wqmiaxy 216; wmmx_wqmulm 217; wmmx_wqmulwm 218; wmmx_wror 219; wmmx_wsad 220; wmmx_wshufh 221; wmmx_wsll 222; wmmx_wsra 223; wmmx_wsrl 224; wmmx_wstr 225; wmmx_wsub 226; wmmx_wsubaddhx 227; wmmx_wunpckeh 228; wmmx_wunpckel 229; wmmx_wunpckih 230; wmmx_wunpckil 231; wmmx_wxor 232; 233; The classification below is for NEON instructions. 234; 235; neon_add 236; neon_add_q 237; neon_add_widen 238; neon_add_long 239; neon_qadd 240; neon_qadd_q 241; neon_add_halve 242; neon_add_halve_q 243; neon_add_halve_narrow_q 244; neon_sub 245; neon_sub_q 246; neon_sub_widen 247; neon_sub_long 248; neon_qsub 249; neon_qsub_q 250; neon_sub_halve 251; neon_sub_halve_q 252; neon_sub_halve_narrow_q 253; neon_abs 254; neon_abs_q 255; neon_neg 256; neon_neg_q 257; neon_qneg 258; neon_qneg_q 259; neon_qabs 260; neon_qabs_q 261; neon_abd 262; neon_abd_q 263; neon_abd_long 264; neon_minmax 265; neon_minmax_q 266; neon_compare 267; neon_compare_q 268; neon_compare_zero 269; neon_compare_zero_q 270; neon_arith_acc 271; neon_arith_acc_q 272; neon_reduc_add 273; neon_reduc_add_q 274; neon_reduc_add_long 275; neon_reduc_add_acc 276; neon_reduc_add_acc_q 277; neon_reduc_minmax 278; neon_reduc_minmax_q 279; neon_logic 280; neon_logic_q 281; neon_tst 282; neon_tst_q 283; neon_shift_imm 284; neon_shift_imm_q 285; neon_shift_imm_narrow_q 286; neon_shift_imm_long 287; neon_shift_reg 288; neon_shift_reg_q 289; neon_shift_acc 290; neon_shift_acc_q 291; neon_sat_shift_imm 292; neon_sat_shift_imm_q 293; neon_sat_shift_imm_narrow_q 294; neon_sat_shift_reg 295; neon_sat_shift_reg_q 296; neon_ins 297; neon_ins_q 298; neon_move 299; neon_move_q 300; neon_move_narrow_q 301; neon_permute 302; neon_permute_q 303; neon_zip 304; neon_zip_q 305; neon_tbl1 306; neon_tbl1_q 307; neon_tbl2 308; neon_tbl2_q 309; neon_tbl3 310; neon_tbl3_q 311; neon_tbl4 312; neon_tbl4_q 313; neon_bsl 314; neon_bsl_q 315; neon_cls 316; neon_cls_q 317; neon_cnt 318; neon_cnt_q 319; neon_dot 320; neon_dot_q 321; neon_ext 322; neon_ext_q 323; neon_rbit 324; neon_rbit_q 325; neon_rev 326; neon_rev_q 327; neon_mul_b 328; neon_mul_b_q 329; neon_mul_h 330; neon_mul_h_q 331; neon_mul_s 332; neon_mul_s_q 333; neon_mul_b_long 334; neon_mul_h_long 335; neon_mul_s_long 336; neon_mul_d_long 337; neon_mul_h_scalar 338; neon_mul_h_scalar_q 339; neon_mul_s_scalar 340; neon_mul_s_scalar_q 341; neon_mul_h_scalar_long 342; neon_mul_s_scalar_long 343; neon_sat_mul_b 344; neon_sat_mul_b_q 345; neon_sat_mul_h 346; neon_sat_mul_h_q 347; neon_sat_mul_s 348; neon_sat_mul_s_q 349; neon_sat_mul_b_long 350; neon_sat_mul_h_long 351; neon_sat_mul_s_long 352; neon_sat_mul_h_scalar 353; neon_sat_mul_h_scalar_q 354; neon_sat_mul_s_scalar 355; neon_sat_mul_s_scalar_q 356; neon_sat_mul_h_scalar_long 357; neon_sat_mul_s_scalar_long 358; neon_mla_b 359; neon_mla_b_q 360; neon_mla_h 361; neon_mla_h_q 362; neon_mla_s 363; neon_mla_s_q 364; neon_mla_b_long 365; neon_mla_h_long 366; neon_mla_s_long 367; neon_mla_h_scalar 368; neon_mla_h_scalar_q 369; neon_mla_s_scalar 370; neon_mla_s_scalar_q 371; neon_mla_h_scalar_long 372; neon_mla_s_scalar_long 373; neon_sat_mla_b_long 374; neon_sat_mla_h_long 375; neon_sat_mla_s_long 376; neon_sat_mla_h_scalar_long 377; neon_sat_mla_s_scalar_long 378; neon_to_gp 379; neon_to_gp_q 380; neon_from_gp 381; neon_from_gp_q 382; neon_ldr 383; neon_ldp 384; neon_ldp_q 385; neon_load1_1reg 386; neon_load1_1reg_q 387; neon_load1_2reg 388; neon_load1_2reg_q 389; neon_load1_3reg 390; neon_load1_3reg_q 391; neon_load1_4reg 392; neon_load1_4reg_q 393; neon_load1_all_lanes 394; neon_load1_all_lanes_q 395; neon_load1_one_lane 396; neon_load1_one_lane_q 397; neon_load2_2reg 398; neon_load2_2reg_q 399; neon_load2_4reg 400; neon_load2_4reg_q 401; neon_load2_all_lanes 402; neon_load2_all_lanes_q 403; neon_load2_one_lane 404; neon_load2_one_lane_q 405; neon_load3_3reg 406; neon_load3_3reg_q 407; neon_load3_all_lanes 408; neon_load3_all_lanes_q 409; neon_load3_one_lane 410; neon_load3_one_lane_q 411; neon_load4_4reg 412; neon_load4_4reg_q 413; neon_load4_all_lanes 414; neon_load4_all_lanes_q 415; neon_load4_one_lane 416; neon_load4_one_lane_q 417; neon_str 418; neon_stp 419; neon_stp_q 420; neon_store1_1reg 421; neon_store1_1reg_q 422; neon_store1_2reg 423; neon_store1_2reg_q 424; neon_store1_3reg 425; neon_store1_3reg_q 426; neon_store1_4reg 427; neon_store1_4reg_q 428; neon_store1_one_lane 429; neon_store1_one_lane_q 430; neon_store2_2reg 431; neon_store2_2reg_q 432; neon_store2_4reg 433; neon_store2_4reg_q 434; neon_store2_one_lane 435; neon_store2_one_lane_q 436; neon_store3_3reg 437; neon_store3_3reg_q 438; neon_store3_one_lane 439; neon_store3_one_lane_q 440; neon_store4_4reg 441; neon_store4_4reg_q 442; neon_store4_one_lane 443; neon_store4_one_lane_q 444; neon_fp_abs_s 445; neon_fp_abs_s_q 446; neon_fp_abs_d 447; neon_fp_abs_d_q 448; neon_fp_neg_s 449; neon_fp_neg_s_q 450; neon_fp_neg_d 451; neon_fp_neg_d_q 452; neon_fp_abd_s 453; neon_fp_abd_s_q 454; neon_fp_abd_d 455; neon_fp_abd_d_q 456; neon_fp_addsub_s 457; neon_fp_addsub_s_q 458; neon_fp_addsub_d 459; neon_fp_addsub_d_q 460; neon_fp_compare_s 461; neon_fp_compare_s_q 462; neon_fp_compare_d 463; neon_fp_compare_d_q 464; neon_fp_minmax_s 465; neon_fp_minmax_s_q 466; neon_fp_minmax_d 467; neon_fp_minmax_d_q 468; neon_fp_reduc_add_s 469; neon_fp_reduc_add_s_q 470; neon_fp_reduc_add_d 471; neon_fp_reduc_add_d_q 472; neon_fp_reduc_minmax_s 473; neon_fp_reduc_minmax_s_q 474; neon_fp_reduc_minmax_d 475; neon_fp_reduc_minmax_d_q 476; neon_fp_cvt_narrow_s_q 477; neon_fp_cvt_narrow_d_q 478; neon_fp_cvt_widen_h 479; neon_fp_cvt_widen_s 480; neon_fp_to_int_s 481; neon_fp_to_int_s_q 482; neon_fp_to_int_d 483; neon_fp_to_int_d_q 484; neon_int_to_fp_s 485; neon_int_to_fp_s_q 486; neon_int_to_fp_d 487; neon_int_to_fp_d_q 488; neon_fp_round_s 489; neon_fp_round_s_q 490; neon_fp_round_d 491; neon_fp_round_d_q 492; neon_fp_recpe_s 493; neon_fp_recpe_s_q 494; neon_fp_recpe_d 495; neon_fp_recpe_d_q 496; neon_fp_recps_s 497; neon_fp_recps_s_q 498; neon_fp_recps_d 499; neon_fp_recps_d_q 500; neon_fp_recpx_s 501; neon_fp_recpx_s_q 502; neon_fp_recpx_d 503; neon_fp_recpx_d_q 504; neon_fp_rsqrte_s 505; neon_fp_rsqrte_s_q 506; neon_fp_rsqrte_d 507; neon_fp_rsqrte_d_q 508; neon_fp_rsqrts_s 509; neon_fp_rsqrts_s_q 510; neon_fp_rsqrts_d 511; neon_fp_rsqrts_d_q 512; neon_fp_mul_s 513; neon_fp_mul_s_q 514; neon_fp_mul_s_scalar 515; neon_fp_mul_s_scalar_q 516; neon_fp_mul_d 517; neon_fp_mul_d_q 518; neon_fp_mul_d_scalar_q 519; neon_fp_mla_s 520; neon_fp_mla_s_q 521; neon_fp_mla_s_scalar 522; neon_fp_mla_s_scalar_q 523; neon_fp_mla_d 524; neon_fp_mla_d_q 525; neon_fp_mla_d_scalar_q 526; neon_fp_sqrt_s 527; neon_fp_sqrt_s_q 528; neon_fp_sqrt_d 529; neon_fp_sqrt_d_q 530; neon_fp_div_s 531; neon_fp_div_s_q 532; neon_fp_div_d 533; neon_fp_div_d_q 534; 535; The classification below is for Crypto instructions. 536; 537; crypto_aese 538; crypto_aesmc 539; crypto_sha1_xor 540; crypto_sha1_fast 541; crypto_sha1_slow 542; crypto_sha256_fast 543; crypto_sha256_slow 544; crypto_pmull 545; 546; The classification below is for coprocessor instructions 547; 548; coproc 549 550(define_attr "type" 551 "adc_imm,\ 552 adc_reg,\ 553 adcs_imm,\ 554 adcs_reg,\ 555 adr,\ 556 alu_ext,\ 557 alu_imm,\ 558 alu_sreg,\ 559 alu_shift_imm,\ 560 alu_shift_reg,\ 561 alu_dsp_reg,\ 562 alus_ext,\ 563 alus_imm,\ 564 alus_sreg,\ 565 alus_shift_imm,\ 566 alus_shift_reg,\ 567 bfm,\ 568 bfx,\ 569 block,\ 570 branch,\ 571 call,\ 572 clz,\ 573 no_insn,\ 574 csel,\ 575 crc,\ 576 extend,\ 577 f_cvt,\ 578 f_cvtf2i,\ 579 f_cvti2f,\ 580 f_flag,\ 581 f_loadd,\ 582 f_loads,\ 583 f_mcr,\ 584 f_mcrr,\ 585 f_minmaxd,\ 586 f_minmaxs,\ 587 f_mrc,\ 588 f_mrrc,\ 589 f_rintd,\ 590 f_rints,\ 591 f_stored,\ 592 f_stores,\ 593 faddd,\ 594 fadds,\ 595 fccmpd,\ 596 fccmps,\ 597 fcmpd,\ 598 fcmps,\ 599 fconstd,\ 600 fconsts,\ 601 fcsel,\ 602 fdivd,\ 603 fdivs,\ 604 ffarithd,\ 605 ffariths,\ 606 ffmad,\ 607 ffmas,\ 608 float,\ 609 fmacd,\ 610 fmacs,\ 611 fmov,\ 612 fmuld,\ 613 fmuls,\ 614 fsqrts,\ 615 fsqrtd,\ 616 load_acq,\ 617 load_byte,\ 618 load_4,\ 619 load_8,\ 620 load_12,\ 621 load_16,\ 622 logic_imm,\ 623 logic_reg,\ 624 logic_shift_imm,\ 625 logic_shift_reg,\ 626 logics_imm,\ 627 logics_reg,\ 628 logics_shift_imm,\ 629 logics_shift_reg,\ 630 mla,\ 631 mlas,\ 632 mov_imm,\ 633 mov_reg,\ 634 mov_shift,\ 635 mov_shift_reg,\ 636 mrs,\ 637 mul,\ 638 muls,\ 639 multiple,\ 640 mvn_imm,\ 641 mvn_reg,\ 642 mvn_shift,\ 643 mvn_shift_reg,\ 644 nop,\ 645 rbit,\ 646 rev,\ 647 rotate_imm,\ 648 sdiv,\ 649 shift_imm,\ 650 shift_reg,\ 651 smlad,\ 652 smladx,\ 653 smlal,\ 654 smlald,\ 655 smlals,\ 656 smlalxy,\ 657 smlawx,\ 658 smlawy,\ 659 smlaxy,\ 660 smlsd,\ 661 smlsdx,\ 662 smlsld,\ 663 smmla,\ 664 smmul,\ 665 smmulr,\ 666 smuad,\ 667 smuadx,\ 668 smull,\ 669 smulls,\ 670 smulwy,\ 671 smulxy,\ 672 smusd,\ 673 smusdx,\ 674 store_rel,\ 675 store_4,\ 676 store_8,\ 677 store_12,\ 678 store_16,\ 679 trap,\ 680 udiv,\ 681 umaal,\ 682 umlal,\ 683 umlals,\ 684 umull,\ 685 umulls,\ 686 untyped,\ 687 wmmx_tandc,\ 688 wmmx_tbcst,\ 689 wmmx_textrc,\ 690 wmmx_textrm,\ 691 wmmx_tinsr,\ 692 wmmx_tmcr,\ 693 wmmx_tmcrr,\ 694 wmmx_tmia,\ 695 wmmx_tmiaph,\ 696 wmmx_tmiaxy,\ 697 wmmx_tmrc,\ 698 wmmx_tmrrc,\ 699 wmmx_tmovmsk,\ 700 wmmx_torc,\ 701 wmmx_torvsc,\ 702 wmmx_wabs,\ 703 wmmx_wabsdiff,\ 704 wmmx_wacc,\ 705 wmmx_wadd,\ 706 wmmx_waddbhus,\ 707 wmmx_waddsubhx,\ 708 wmmx_waligni,\ 709 wmmx_walignr,\ 710 wmmx_wand,\ 711 wmmx_wandn,\ 712 wmmx_wavg2,\ 713 wmmx_wavg4,\ 714 wmmx_wcmpeq,\ 715 wmmx_wcmpgt,\ 716 wmmx_wmac,\ 717 wmmx_wmadd,\ 718 wmmx_wmax,\ 719 wmmx_wmerge,\ 720 wmmx_wmiawxy,\ 721 wmmx_wmiaxy,\ 722 wmmx_wmin,\ 723 wmmx_wmov,\ 724 wmmx_wmul,\ 725 wmmx_wmulw,\ 726 wmmx_wldr,\ 727 wmmx_wor,\ 728 wmmx_wpack,\ 729 wmmx_wqmiaxy,\ 730 wmmx_wqmulm,\ 731 wmmx_wqmulwm,\ 732 wmmx_wror,\ 733 wmmx_wsad,\ 734 wmmx_wshufh,\ 735 wmmx_wsll,\ 736 wmmx_wsra,\ 737 wmmx_wsrl,\ 738 wmmx_wstr,\ 739 wmmx_wsub,\ 740 wmmx_wsubaddhx,\ 741 wmmx_wunpckeh,\ 742 wmmx_wunpckel,\ 743 wmmx_wunpckih,\ 744 wmmx_wunpckil,\ 745 wmmx_wxor,\ 746\ 747 neon_add,\ 748 neon_add_q,\ 749 neon_add_widen,\ 750 neon_add_long,\ 751 neon_qadd,\ 752 neon_qadd_q,\ 753 neon_add_halve,\ 754 neon_add_halve_q,\ 755 neon_add_halve_narrow_q,\ 756\ 757 neon_sub,\ 758 neon_sub_q,\ 759 neon_sub_widen,\ 760 neon_sub_long,\ 761 neon_qsub,\ 762 neon_qsub_q,\ 763 neon_sub_halve,\ 764 neon_sub_halve_q,\ 765 neon_sub_halve_narrow_q,\ 766\ 767 neon_abs,\ 768 neon_abs_q,\ 769 neon_dot,\ 770 neon_dot_q,\ 771 neon_neg,\ 772 neon_neg_q,\ 773 neon_qneg,\ 774 neon_qneg_q,\ 775 neon_qabs,\ 776 neon_qabs_q,\ 777 neon_abd,\ 778 neon_abd_q,\ 779 neon_abd_long,\ 780\ 781 neon_minmax,\ 782 neon_minmax_q,\ 783 neon_compare,\ 784 neon_compare_q,\ 785 neon_compare_zero,\ 786 neon_compare_zero_q,\ 787\ 788 neon_arith_acc,\ 789 neon_arith_acc_q,\ 790 neon_reduc_add,\ 791 neon_reduc_add_q,\ 792 neon_reduc_add_long,\ 793 neon_reduc_add_acc,\ 794 neon_reduc_add_acc_q,\ 795 neon_reduc_minmax,\ 796 neon_reduc_minmax_q,\ 797 neon_logic,\ 798 neon_logic_q,\ 799 neon_tst,\ 800 neon_tst_q,\ 801\ 802 neon_shift_imm,\ 803 neon_shift_imm_q,\ 804 neon_shift_imm_narrow_q,\ 805 neon_shift_imm_long,\ 806 neon_shift_reg,\ 807 neon_shift_reg_q,\ 808 neon_shift_acc,\ 809 neon_shift_acc_q,\ 810 neon_sat_shift_imm,\ 811 neon_sat_shift_imm_q,\ 812 neon_sat_shift_imm_narrow_q,\ 813 neon_sat_shift_reg,\ 814 neon_sat_shift_reg_q,\ 815\ 816 neon_ins,\ 817 neon_ins_q,\ 818 neon_move,\ 819 neon_move_q,\ 820 neon_move_narrow_q,\ 821 neon_permute,\ 822 neon_permute_q,\ 823 neon_zip,\ 824 neon_zip_q,\ 825 neon_tbl1,\ 826 neon_tbl1_q,\ 827 neon_tbl2,\ 828 neon_tbl2_q,\ 829 neon_tbl3,\ 830 neon_tbl3_q,\ 831 neon_tbl4,\ 832 neon_tbl4_q,\ 833\ 834 neon_bsl,\ 835 neon_bsl_q,\ 836 neon_cls,\ 837 neon_cls_q,\ 838 neon_cnt,\ 839 neon_cnt_q,\ 840 neon_dup,\ 841 neon_dup_q,\ 842 neon_ext,\ 843 neon_ext_q,\ 844 neon_rbit,\ 845 neon_rbit_q,\ 846 neon_rev,\ 847 neon_rev_q,\ 848\ 849 neon_mul_b,\ 850 neon_mul_b_q,\ 851 neon_mul_h,\ 852 neon_mul_h_q,\ 853 neon_mul_s,\ 854 neon_mul_s_q,\ 855 neon_mul_b_long,\ 856 neon_mul_h_long,\ 857 neon_mul_s_long,\ 858 neon_mul_d_long,\ 859 neon_mul_h_scalar,\ 860 neon_mul_h_scalar_q,\ 861 neon_mul_s_scalar,\ 862 neon_mul_s_scalar_q,\ 863 neon_mul_h_scalar_long,\ 864 neon_mul_s_scalar_long,\ 865\ 866 neon_sat_mul_b,\ 867 neon_sat_mul_b_q,\ 868 neon_sat_mul_h,\ 869 neon_sat_mul_h_q,\ 870 neon_sat_mul_s,\ 871 neon_sat_mul_s_q,\ 872 neon_sat_mul_b_long,\ 873 neon_sat_mul_h_long,\ 874 neon_sat_mul_s_long,\ 875 neon_sat_mul_h_scalar,\ 876 neon_sat_mul_h_scalar_q,\ 877 neon_sat_mul_s_scalar,\ 878 neon_sat_mul_s_scalar_q,\ 879 neon_sat_mul_h_scalar_long,\ 880 neon_sat_mul_s_scalar_long,\ 881\ 882 neon_mla_b,\ 883 neon_mla_b_q,\ 884 neon_mla_h,\ 885 neon_mla_h_q,\ 886 neon_mla_s,\ 887 neon_mla_s_q,\ 888 neon_mla_b_long,\ 889 neon_mla_h_long,\ 890 neon_mla_s_long,\ 891 neon_mla_h_scalar,\ 892 neon_mla_h_scalar_q,\ 893 neon_mla_s_scalar,\ 894 neon_mla_s_scalar_q,\ 895 neon_mla_h_scalar_long,\ 896 neon_mla_s_scalar_long,\ 897\ 898 neon_sat_mla_b_long,\ 899 neon_sat_mla_h_long,\ 900 neon_sat_mla_s_long,\ 901 neon_sat_mla_h_scalar_long,\ 902 neon_sat_mla_s_scalar_long,\ 903\ 904 neon_to_gp,\ 905 neon_to_gp_q,\ 906 neon_from_gp,\ 907 neon_from_gp_q,\ 908\ 909 neon_ldr,\ 910 neon_ldp,\ 911 neon_ldp_q,\ 912 neon_load1_1reg,\ 913 neon_load1_1reg_q,\ 914 neon_load1_2reg,\ 915 neon_load1_2reg_q,\ 916 neon_load1_3reg,\ 917 neon_load1_3reg_q,\ 918 neon_load1_4reg,\ 919 neon_load1_4reg_q,\ 920 neon_load1_all_lanes,\ 921 neon_load1_all_lanes_q,\ 922 neon_load1_one_lane,\ 923 neon_load1_one_lane_q,\ 924\ 925 neon_load2_2reg,\ 926 neon_load2_2reg_q,\ 927 neon_load2_4reg,\ 928 neon_load2_4reg_q,\ 929 neon_load2_all_lanes,\ 930 neon_load2_all_lanes_q,\ 931 neon_load2_one_lane,\ 932 neon_load2_one_lane_q,\ 933\ 934 neon_load3_3reg,\ 935 neon_load3_3reg_q,\ 936 neon_load3_all_lanes,\ 937 neon_load3_all_lanes_q,\ 938 neon_load3_one_lane,\ 939 neon_load3_one_lane_q,\ 940\ 941 neon_load4_4reg,\ 942 neon_load4_4reg_q,\ 943 neon_load4_all_lanes,\ 944 neon_load4_all_lanes_q,\ 945 neon_load4_one_lane,\ 946 neon_load4_one_lane_q,\ 947\ 948 neon_str,\ 949 neon_stp,\ 950 neon_stp_q,\ 951 neon_store1_1reg,\ 952 neon_store1_1reg_q,\ 953 neon_store1_2reg,\ 954 neon_store1_2reg_q,\ 955 neon_store1_3reg,\ 956 neon_store1_3reg_q,\ 957 neon_store1_4reg,\ 958 neon_store1_4reg_q,\ 959 neon_store1_one_lane,\ 960 neon_store1_one_lane_q,\ 961\ 962 neon_store2_2reg,\ 963 neon_store2_2reg_q,\ 964 neon_store2_4reg,\ 965 neon_store2_4reg_q,\ 966 neon_store2_one_lane,\ 967 neon_store2_one_lane_q,\ 968\ 969 neon_store3_3reg,\ 970 neon_store3_3reg_q,\ 971 neon_store3_one_lane,\ 972 neon_store3_one_lane_q,\ 973\ 974 neon_store4_4reg,\ 975 neon_store4_4reg_q,\ 976 neon_store4_one_lane,\ 977 neon_store4_one_lane_q,\ 978\ 979 neon_fp_abs_s,\ 980 neon_fp_abs_s_q,\ 981 neon_fp_abs_d,\ 982 neon_fp_abs_d_q,\ 983 neon_fp_neg_s,\ 984 neon_fp_neg_s_q,\ 985 neon_fp_neg_d,\ 986 neon_fp_neg_d_q,\ 987\ 988 neon_fp_abd_s,\ 989 neon_fp_abd_s_q,\ 990 neon_fp_abd_d,\ 991 neon_fp_abd_d_q,\ 992 neon_fp_addsub_s,\ 993 neon_fp_addsub_s_q,\ 994 neon_fp_addsub_d,\ 995 neon_fp_addsub_d_q,\ 996 neon_fp_compare_s,\ 997 neon_fp_compare_s_q,\ 998 neon_fp_compare_d,\ 999 neon_fp_compare_d_q,\ 1000 neon_fp_minmax_s,\ 1001 neon_fp_minmax_s_q,\ 1002 neon_fp_minmax_d,\ 1003 neon_fp_minmax_d_q,\ 1004\ 1005 neon_fp_reduc_add_s,\ 1006 neon_fp_reduc_add_s_q,\ 1007 neon_fp_reduc_add_d,\ 1008 neon_fp_reduc_add_d_q,\ 1009 neon_fp_reduc_minmax_s,\ 1010 neon_fp_reduc_minmax_s_q,\ 1011 neon_fp_reduc_minmax_d,\ 1012 neon_fp_reduc_minmax_d_q,\ 1013\ 1014 neon_fp_cvt_narrow_s_q,\ 1015 neon_fp_cvt_narrow_d_q,\ 1016 neon_fp_cvt_widen_h,\ 1017 neon_fp_cvt_widen_s,\ 1018\ 1019 neon_fp_to_int_s,\ 1020 neon_fp_to_int_s_q,\ 1021 neon_fp_to_int_d,\ 1022 neon_fp_to_int_d_q,\ 1023 neon_int_to_fp_s,\ 1024 neon_int_to_fp_s_q,\ 1025 neon_int_to_fp_d,\ 1026 neon_int_to_fp_d_q,\ 1027 neon_fp_round_s,\ 1028 neon_fp_round_s_q,\ 1029 neon_fp_round_d,\ 1030 neon_fp_round_d_q,\ 1031\ 1032 neon_fp_recpe_s,\ 1033 neon_fp_recpe_s_q,\ 1034 neon_fp_recpe_d,\ 1035 neon_fp_recpe_d_q,\ 1036 neon_fp_recps_s,\ 1037 neon_fp_recps_s_q,\ 1038 neon_fp_recps_d,\ 1039 neon_fp_recps_d_q,\ 1040 neon_fp_recpx_s,\ 1041 neon_fp_recpx_s_q,\ 1042 neon_fp_recpx_d,\ 1043 neon_fp_recpx_d_q,\ 1044\ 1045 neon_fp_rsqrte_s,\ 1046 neon_fp_rsqrte_s_q,\ 1047 neon_fp_rsqrte_d,\ 1048 neon_fp_rsqrte_d_q,\ 1049 neon_fp_rsqrts_s,\ 1050 neon_fp_rsqrts_s_q,\ 1051 neon_fp_rsqrts_d,\ 1052 neon_fp_rsqrts_d_q,\ 1053\ 1054 neon_fp_mul_s,\ 1055 neon_fp_mul_s_q,\ 1056 neon_fp_mul_s_scalar,\ 1057 neon_fp_mul_s_scalar_q,\ 1058 neon_fp_mul_d,\ 1059 neon_fp_mul_d_q,\ 1060 neon_fp_mul_d_scalar_q,\ 1061\ 1062 neon_fp_mla_s,\ 1063 neon_fp_mla_s_q,\ 1064 neon_fp_mla_s_scalar,\ 1065 neon_fp_mla_s_scalar_q,\ 1066 neon_fp_mla_d,\ 1067 neon_fp_mla_d_q,\ 1068 neon_fp_mla_d_scalar_q,\ 1069\ 1070 neon_fp_sqrt_s,\ 1071 neon_fp_sqrt_s_q,\ 1072 neon_fp_sqrt_d,\ 1073 neon_fp_sqrt_d_q,\ 1074 neon_fp_div_s,\ 1075 neon_fp_div_s_q,\ 1076 neon_fp_div_d,\ 1077 neon_fp_div_d_q,\ 1078\ 1079 crypto_aese,\ 1080 crypto_aesmc,\ 1081 crypto_sha1_xor,\ 1082 crypto_sha1_fast,\ 1083 crypto_sha1_slow,\ 1084 crypto_sha256_fast,\ 1085 crypto_sha256_slow,\ 1086 crypto_pmull,\ 1087 crypto_sha512,\ 1088 crypto_sha3,\ 1089 crypto_sm3,\ 1090 crypto_sm4,\ 1091 coproc" 1092 (const_string "untyped")) 1093 1094; Is this an (integer side) multiply with a 32-bit (or smaller) result? 1095(define_attr "mul32" "no,yes" 1096 (if_then_else 1097 (eq_attr "type" 1098 "smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\ 1099 smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld") 1100 (const_string "yes") 1101 (const_string "no"))) 1102 1103; Is this an (integer side) multiply with a 64-bit result? 1104(define_attr "mul64" "no,yes" 1105 (if_then_else 1106 (eq_attr "type" 1107 "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals") 1108 (const_string "yes") 1109 (const_string "no"))) 1110 1111; YES if the "type" attribute assigned to the insn denotes an 1112; Advanced SIMD instruction, NO otherwise. 1113(define_attr "is_neon_type" "yes,no" 1114 (if_then_else (eq_attr "type" 1115 "neon_add, neon_add_q, neon_add_widen, neon_add_long,\ 1116 neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\ 1117 neon_add_halve_narrow_q,\ 1118 neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\ 1119 neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\ 1120 neon_sub_halve_narrow_q,\ 1121 neon_abs, neon_abs_q, neon_dot, neon_dot_q, neon_neg, neon_neg_q,\ 1122 neon_qneg, neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\ 1123 neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\ 1124 neon_compare_q, neon_compare_zero, neon_compare_zero_q,\ 1125 neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\ 1126 neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\ 1127 neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\ 1128 neon_logic, neon_logic_q, neon_tst, neon_tst_q,\ 1129 neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\ 1130 neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\ 1131 neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\ 1132 neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\ 1133 neon_sat_shift_reg, neon_sat_shift_reg_q,\ 1134 neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\ 1135 neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\ 1136 neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\ 1137 neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\ 1138 neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\ 1139 neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\ 1140 neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\ 1141 neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\ 1142 neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\ 1143 neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\ 1144 neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\ 1145 neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\ 1146 neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\ 1147 neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\ 1148 neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\ 1149 neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ 1150 neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\ 1151 neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\ 1152 neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\ 1153 neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\ 1154 neon_mla_h_scalar_long, neon_mla_s_scalar_long,\ 1155 neon_sat_mla_b_long, neon_sat_mla_h_long,\ 1156 neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ 1157 neon_sat_mla_s_scalar_long,\ 1158 neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\ 1159 neon_ldr, neon_ldp, neon_ldp_q,\ 1160 neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\ 1161 neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\ 1162 neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\ 1163 neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\ 1164 neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\ 1165 neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\ 1166 neon_load2_one_lane, neon_load2_one_lane_q,\ 1167 neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\ 1168 neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\ 1169 neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\ 1170 neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\ 1171 neon_str, neon_stp, neon_stp_q,\ 1172 neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\ 1173 neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\ 1174 neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\ 1175 neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\ 1176 neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\ 1177 neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\ 1178 neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\ 1179 neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\ 1180 neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\ 1181 neon_fp_abs_s, neon_fp_abs_s_q, neon_fp_abs_d, neon_fp_abs_d_q,\ 1182 neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\ 1183 neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\ 1184 neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ 1185 neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ 1186 neon_fp_neg_s, neon_fp_neg_s_q, neon_fp_neg_d, neon_fp_neg_d_q,\ 1187 neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ 1188 neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, 1189 neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ 1190 neon_fp_reduc_minmax_d_q,\ 1191 neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ 1192 neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\ 1193 neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\ 1194 neon_fp_to_int_d, neon_fp_to_int_d_q,\ 1195 neon_int_to_fp_d, neon_int_to_fp_d_q,\ 1196 neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\ 1197 neon_fp_recpe_s_q,\ 1198 neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\ 1199 neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\ 1200 neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\ 1201 neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\ 1202 neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\ 1203 neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\ 1204 neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\ 1205 neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\ 1206 neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\ 1207 neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\ 1208 neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\ 1209 neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\ 1210 neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aese,\ 1211 crypto_aesmc, crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow,\ 1212 crypto_sha256_fast, crypto_sha256_slow") 1213 (const_string "yes") 1214 (const_string "no"))) 1215