1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2014 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha@arm.com) 6 Minor hacks by Nick Clifton (nickc@cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use enum machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE enum machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() \ 49 do \ 50 { \ 51 if (TARGET_DSP_MULTIPLY) \ 52 builtin_define ("__ARM_FEATURE_DSP"); \ 53 if (TARGET_ARM_QBIT) \ 54 builtin_define ("__ARM_FEATURE_QBIT"); \ 55 if (TARGET_ARM_SAT) \ 56 builtin_define ("__ARM_FEATURE_SAT"); \ 57 if (TARGET_CRYPTO) \ 58 builtin_define ("__ARM_FEATURE_CRYPTO"); \ 59 if (unaligned_access) \ 60 builtin_define ("__ARM_FEATURE_UNALIGNED"); \ 61 if (TARGET_CRC32) \ 62 builtin_define ("__ARM_FEATURE_CRC32"); \ 63 if (TARGET_32BIT) \ 64 builtin_define ("__ARM_32BIT_STATE"); \ 65 if (TARGET_ARM_FEATURE_LDREX) \ 66 builtin_define_with_int_value ( \ 67 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \ 68 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \ 69 || TARGET_ARM_ARCH_ISA_THUMB >=2) \ 70 builtin_define ("__ARM_FEATURE_CLZ"); \ 71 if (TARGET_INT_SIMD) \ 72 builtin_define ("__ARM_FEATURE_SIMD32"); \ 73 \ 74 builtin_define_with_int_value ( \ 75 "__ARM_SIZEOF_MINIMAL_ENUM", \ 76 flag_short_enums ? 1 : 4); \ 77 builtin_define_with_int_value ( \ 78 "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE); \ 79 if (TARGET_ARM_ARCH_PROFILE) \ 80 builtin_define_with_int_value ( \ 81 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ 82 \ 83 /* Define __arm__ even when in thumb mode, for \ 84 consistency with armcc. */ \ 85 builtin_define ("__arm__"); \ 86 if (TARGET_ARM_ARCH) \ 87 builtin_define_with_int_value ( \ 88 "__ARM_ARCH", TARGET_ARM_ARCH); \ 89 if (arm_arch_notm) \ 90 builtin_define ("__ARM_ARCH_ISA_ARM"); \ 91 builtin_define ("__APCS_32__"); \ 92 if (TARGET_THUMB) \ 93 builtin_define ("__thumb__"); \ 94 if (TARGET_THUMB2) \ 95 builtin_define ("__thumb2__"); \ 96 if (TARGET_ARM_ARCH_ISA_THUMB) \ 97 builtin_define_with_int_value ( \ 98 "__ARM_ARCH_ISA_THUMB", \ 99 TARGET_ARM_ARCH_ISA_THUMB); \ 100 \ 101 if (TARGET_BIG_END) \ 102 { \ 103 builtin_define ("__ARMEB__"); \ 104 builtin_define ("__ARM_BIG_ENDIAN"); \ 105 if (TARGET_THUMB) \ 106 builtin_define ("__THUMBEB__"); \ 107 if (TARGET_LITTLE_WORDS) \ 108 builtin_define ("__ARMWEL__"); \ 109 } \ 110 else \ 111 { \ 112 builtin_define ("__ARMEL__"); \ 113 if (TARGET_THUMB) \ 114 builtin_define ("__THUMBEL__"); \ 115 } \ 116 \ 117 if (TARGET_SOFT_FLOAT) \ 118 builtin_define ("__SOFTFP__"); \ 119 \ 120 if (TARGET_VFP) \ 121 builtin_define ("__VFP_FP__"); \ 122 \ 123 if (TARGET_ARM_FP) \ 124 builtin_define_with_int_value ( \ 125 "__ARM_FP", TARGET_ARM_FP); \ 126 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \ 127 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \ 128 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \ 129 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \ 130 if (TARGET_FMA) \ 131 builtin_define ("__ARM_FEATURE_FMA"); \ 132 \ 133 if (TARGET_NEON) \ 134 { \ 135 builtin_define ("__ARM_NEON__"); \ 136 builtin_define ("__ARM_NEON"); \ 137 } \ 138 if (TARGET_NEON_FP) \ 139 builtin_define_with_int_value ( \ 140 "__ARM_NEON_FP", TARGET_NEON_FP); \ 141 \ 142 /* Add a define for interworking. \ 143 Needed when building libgcc.a. */ \ 144 if (arm_cpp_interwork) \ 145 builtin_define ("__THUMB_INTERWORK__"); \ 146 \ 147 builtin_assert ("cpu=arm"); \ 148 builtin_assert ("machine=arm"); \ 149 \ 150 builtin_define (arm_arch_name); \ 151 if (arm_arch_xscale) \ 152 builtin_define ("__XSCALE__"); \ 153 if (arm_arch_iwmmxt) \ 154 { \ 155 builtin_define ("__IWMMXT__"); \ 156 builtin_define ("__ARM_WMMX"); \ 157 } \ 158 if (arm_arch_iwmmxt2) \ 159 builtin_define ("__IWMMXT2__"); \ 160 if (TARGET_AAPCS_BASED) \ 161 { \ 162 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ 163 builtin_define ("__ARM_PCS_VFP"); \ 164 else if (arm_pcs_default == ARM_PCS_AAPCS) \ 165 builtin_define ("__ARM_PCS"); \ 166 builtin_define ("__ARM_EABI__"); \ 167 } \ 168 if (TARGET_IDIV) \ 169 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 170 } while (0) 171 172 #include "config/arm/arm-opts.h" 173 174 enum target_cpus 175 { 176 #define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ 177 TARGET_CPU_##INTERNAL_IDENT, 178 #include "arm-cores.def" 179 #undef ARM_CORE 180 TARGET_CPU_generic 181 }; 182 183 /* The processor for which instructions should be scheduled. */ 184 extern enum processor_type arm_tune; 185 186 typedef enum arm_cond_code 187 { 188 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 189 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 190 } 191 arm_cc; 192 193 extern arm_cc arm_current_cc; 194 195 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 196 197 /* The maximum number of instructions that is beneficial to 198 conditionally execute. */ 199 #undef MAX_CONDITIONAL_EXECUTE 200 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 201 202 extern int arm_target_label; 203 extern int arm_ccfsm_state; 204 extern GTY(()) rtx arm_target_insn; 205 /* The label of the current constant pool. */ 206 extern rtx pool_vector_label; 207 /* Set to 1 when a return insn is output, this means that the epilogue 208 is not needed. */ 209 extern int return_used_this_function; 210 /* Callback to output language specific object attributes. */ 211 extern void (*arm_lang_output_object_attributes_hook)(void); 212 213 /* Just in case configure has failed to define anything. */ 214 #ifndef TARGET_CPU_DEFAULT 215 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 216 #endif 217 218 219 #undef CPP_SPEC 220 #define CPP_SPEC "%(subtarget_cpp_spec) \ 221 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 222 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 223 %{mbig-endian:%{mlittle-endian: \ 224 %e-mbig-endian and -mlittle-endian may not be used together}}" 225 226 #ifndef CC1_SPEC 227 #define CC1_SPEC "" 228 #endif 229 230 /* This macro defines names of additional specifications to put in the specs 231 that can be used in various specifications like CC1_SPEC. Its definition 232 is an initializer with a subgrouping for each command option. 233 234 Each subgrouping contains a string constant, that defines the 235 specification name, and a string constant that used by the GCC driver 236 program. 237 238 Do not define this macro if it does not need to do anything. */ 239 #define EXTRA_SPECS \ 240 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 241 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 242 SUBTARGET_EXTRA_SPECS 243 244 #ifndef SUBTARGET_EXTRA_SPECS 245 #define SUBTARGET_EXTRA_SPECS 246 #endif 247 248 #ifndef SUBTARGET_CPP_SPEC 249 #define SUBTARGET_CPP_SPEC "" 250 #endif 251 252 /* Run-time Target Specification. */ 253 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 254 /* Use hardware floating point instructions. */ 255 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 256 /* Use hardware floating point calling convention. */ 257 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 258 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 259 #define TARGET_IWMMXT (arm_arch_iwmmxt) 260 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 261 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 262 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 263 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 264 #define TARGET_ARM (! TARGET_THUMB) 265 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 266 #define TARGET_BACKTRACE (leaf_function_p () \ 267 ? TARGET_TPCS_LEAF_FRAME \ 268 : TARGET_TPCS_FRAME) 269 #define TARGET_AAPCS_BASED \ 270 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 271 272 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 273 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 274 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 275 276 /* Only 16-bit thumb code. */ 277 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 278 /* Arm or Thumb-2 32-bit code. */ 279 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 280 /* 32-bit Thumb-2 code. */ 281 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 282 /* Thumb-1 only. */ 283 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 284 285 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 286 && !TARGET_THUMB1) 287 288 #define TARGET_CRC32 (arm_arch_crc) 289 290 /* The following two macros concern the ability to execute coprocessor 291 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 292 only ever tested when we know we are generating for VFP hardware; we need 293 to be more careful with TARGET_NEON as noted below. */ 294 295 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 296 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 297 298 /* FPU supports VFPv3 instructions. */ 299 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 300 301 /* FPU only supports VFP single-precision instructions. */ 302 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 303 304 /* FPU supports VFP double-precision instructions. */ 305 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 306 307 /* FPU supports half-precision floating-point with NEON element load/store. */ 308 #define TARGET_NEON_FP16 \ 309 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 310 311 /* FPU supports VFP half-precision floating-point. */ 312 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 313 314 /* FPU supports fused-multiply-add operations. */ 315 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) 316 317 /* FPU is ARMv8 compatible. */ 318 #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8) 319 320 /* FPU supports Crypto extensions. */ 321 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) 322 323 /* FPU supports Neon instructions. The setting of this macro gets 324 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 325 and TARGET_HARD_FLOAT to ensure that NEON instructions are 326 available. */ 327 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 328 && TARGET_VFP && arm_fpu_desc->neon) 329 330 /* Q-bit is present. */ 331 #define TARGET_ARM_QBIT \ 332 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 333 /* Saturation operation, e.g. SSAT. */ 334 #define TARGET_ARM_SAT \ 335 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 336 /* "DSP" multiply instructions, eg. SMULxy. */ 337 #define TARGET_DSP_MULTIPLY \ 338 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 339 /* Integer SIMD instructions, and extend-accumulate instructions. */ 340 #define TARGET_INT_SIMD \ 341 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 342 343 /* Should MOVW/MOVT be used in preference to a constant pool. */ 344 #define TARGET_USE_MOVT \ 345 (arm_arch_thumb2 \ 346 && (arm_disable_literal_pool \ 347 || (!optimize_size && !current_tune->prefer_constant_pool))) 348 349 /* We could use unified syntax for arm mode, but for now we just use it 350 for Thumb-2. */ 351 #define TARGET_UNIFIED_ASM TARGET_THUMB2 352 353 /* Nonzero if this chip provides the DMB instruction. */ 354 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 355 356 /* Nonzero if this chip implements a memory barrier via CP15. */ 357 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 358 && ! TARGET_THUMB1) 359 360 /* Nonzero if this chip implements a memory barrier instruction. */ 361 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 362 363 /* Nonzero if this chip supports ldrex and strex */ 364 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) 365 366 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 367 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) 368 369 /* Nonzero if this chip supports ldrexd and strexd. */ 370 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ 371 && arm_arch_notm) 372 373 /* Nonzero if this chip supports load-acquire and store-release. */ 374 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 375 376 /* Nonzero if integer division instructions supported. */ 377 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 378 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) 379 380 /* Should NEON be used for 64-bits bitops. */ 381 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 382 383 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 384 then TARGET_AAPCS_BASED must be true -- but the converse does not 385 hold. TARGET_BPABI implies the use of the BPABI runtime library, 386 etc., in addition to just the AAPCS calling conventions. */ 387 #ifndef TARGET_BPABI 388 #define TARGET_BPABI false 389 #endif 390 391 /* Support for a compile-time default CPU, et cetera. The rules are: 392 --with-arch is ignored if -march or -mcpu are specified. 393 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 394 by --with-arch. 395 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 396 by -march). 397 --with-float is ignored if -mfloat-abi is specified. 398 --with-fpu is ignored if -mfpu is specified. 399 --with-abi is ignored if -mabi is specified. 400 --with-tls is ignored if -mtls-dialect is specified. */ 401 #define OPTION_DEFAULT_SPECS \ 402 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 403 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 404 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 405 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 406 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 407 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 408 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 409 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 410 411 /* Which floating point model to use. */ 412 enum arm_fp_model 413 { 414 ARM_FP_MODEL_UNKNOWN, 415 /* VFP floating point model. */ 416 ARM_FP_MODEL_VFP 417 }; 418 419 enum vfp_reg_type 420 { 421 VFP_NONE = 0, 422 VFP_REG_D16, 423 VFP_REG_D32, 424 VFP_REG_SINGLE 425 }; 426 427 extern const struct arm_fpu_desc 428 { 429 const char *name; 430 enum arm_fp_model model; 431 int rev; 432 enum vfp_reg_type regs; 433 int neon; 434 int fp16; 435 int crypto; 436 } *arm_fpu_desc; 437 438 /* Which floating point hardware to schedule for. */ 439 extern int arm_fpu_attr; 440 441 #ifndef TARGET_DEFAULT_FLOAT_ABI 442 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 443 #endif 444 445 #define LARGEST_EXPONENT_IS_NORMAL(bits) \ 446 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) 447 448 #ifndef ARM_DEFAULT_ABI 449 #define ARM_DEFAULT_ABI ARM_ABI_APCS 450 #endif 451 452 /* Map each of the micro-architecture variants to their corresponding 453 major architecture revision. */ 454 455 enum base_architecture 456 { 457 BASE_ARCH_0 = 0, 458 BASE_ARCH_2 = 2, 459 BASE_ARCH_3 = 3, 460 BASE_ARCH_3M = 3, 461 BASE_ARCH_4 = 4, 462 BASE_ARCH_4T = 4, 463 BASE_ARCH_5 = 5, 464 BASE_ARCH_5E = 5, 465 BASE_ARCH_5T = 5, 466 BASE_ARCH_5TE = 5, 467 BASE_ARCH_5TEJ = 5, 468 BASE_ARCH_6 = 6, 469 BASE_ARCH_6J = 6, 470 BASE_ARCH_6ZK = 6, 471 BASE_ARCH_6K = 6, 472 BASE_ARCH_6T2 = 6, 473 BASE_ARCH_6M = 6, 474 BASE_ARCH_6Z = 6, 475 BASE_ARCH_7 = 7, 476 BASE_ARCH_7A = 7, 477 BASE_ARCH_7R = 7, 478 BASE_ARCH_7M = 7, 479 BASE_ARCH_7EM = 7, 480 BASE_ARCH_8A = 8 481 }; 482 483 /* The major revision number of the ARM Architecture implemented by the target. */ 484 extern enum base_architecture arm_base_arch; 485 486 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 487 extern int arm_arch3m; 488 489 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 490 extern int arm_arch4; 491 492 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 493 extern int arm_arch4t; 494 495 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 496 extern int arm_arch5; 497 498 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 499 extern int arm_arch5e; 500 501 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 502 extern int arm_arch6; 503 504 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 505 extern int arm_arch6k; 506 507 /* Nonzero if instructions present in ARMv6-M can be used. */ 508 extern int arm_arch6m; 509 510 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 511 extern int arm_arch7; 512 513 /* Nonzero if instructions not present in the 'M' profile can be used. */ 514 extern int arm_arch_notm; 515 516 /* Nonzero if instructions present in ARMv7E-M can be used. */ 517 extern int arm_arch7em; 518 519 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 520 extern int arm_arch8; 521 522 /* Nonzero if this chip can benefit from load scheduling. */ 523 extern int arm_ld_sched; 524 525 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ 526 extern int thumb_code; 527 528 /* Nonzero if generating Thumb-1 code. */ 529 extern int thumb1_code; 530 531 /* Nonzero if this chip is a StrongARM. */ 532 extern int arm_tune_strongarm; 533 534 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 535 extern int arm_arch_iwmmxt; 536 537 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 538 extern int arm_arch_iwmmxt2; 539 540 /* Nonzero if this chip is an XScale. */ 541 extern int arm_arch_xscale; 542 543 /* Nonzero if tuning for XScale. */ 544 extern int arm_tune_xscale; 545 546 /* Nonzero if tuning for stores via the write buffer. */ 547 extern int arm_tune_wbuf; 548 549 /* Nonzero if tuning for Cortex-A9. */ 550 extern int arm_tune_cortex_a9; 551 552 /* Nonzero if we should define __THUMB_INTERWORK__ in the 553 preprocessor. 554 XXX This is a bit of a hack, it's intended to help work around 555 problems in GLD which doesn't understand that armv5t code is 556 interworking clean. */ 557 extern int arm_cpp_interwork; 558 559 /* Nonzero if chip supports Thumb 2. */ 560 extern int arm_arch_thumb2; 561 562 /* Nonzero if chip supports integer division instruction in ARM mode. */ 563 extern int arm_arch_arm_hwdiv; 564 565 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 566 extern int arm_arch_thumb_hwdiv; 567 568 /* Nonzero if we should use Neon to handle 64-bits operations rather 569 than core registers. */ 570 extern int prefer_neon_for_64bits; 571 572 /* Nonzero if we shouldn't use literal pools. */ 573 #ifndef USED_FOR_TARGET 574 extern bool arm_disable_literal_pool; 575 #endif 576 577 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 578 extern int arm_arch_crc; 579 580 #ifndef TARGET_DEFAULT 581 #define TARGET_DEFAULT (MASK_APCS_FRAME) 582 #endif 583 584 /* Nonzero if PIC code requires explicit qualifiers to generate 585 PLT and GOT relocs rather than the assembler doing so implicitly. 586 Subtargets can override these if required. */ 587 #ifndef NEED_GOT_RELOC 588 #define NEED_GOT_RELOC 0 589 #endif 590 #ifndef NEED_PLT_RELOC 591 #define NEED_PLT_RELOC 0 592 #endif 593 594 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 595 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 596 #endif 597 598 /* Nonzero if we need to refer to the GOT with a PC-relative 599 offset. In other words, generate 600 601 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 602 603 rather than 604 605 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 606 607 The default is true, which matches NetBSD. Subtargets can 608 override this if required. */ 609 #ifndef GOT_PCREL 610 #define GOT_PCREL 1 611 #endif 612 613 /* Target machine storage Layout. */ 614 615 616 /* Define this macro if it is advisable to hold scalars in registers 617 in a wider mode than that declared by the program. In such cases, 618 the value is constrained to be within the bounds of the declared 619 type, but kept valid in the wider mode. The signedness of the 620 extension may differ from that of the type. */ 621 622 /* It is far faster to zero extend chars than to sign extend them */ 623 624 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 625 if (GET_MODE_CLASS (MODE) == MODE_INT \ 626 && GET_MODE_SIZE (MODE) < 4) \ 627 { \ 628 if (MODE == QImode) \ 629 UNSIGNEDP = 1; \ 630 else if (MODE == HImode) \ 631 UNSIGNEDP = 1; \ 632 (MODE) = SImode; \ 633 } 634 635 /* Define this if most significant bit is lowest numbered 636 in instructions that operate on numbered bit-fields. */ 637 #define BITS_BIG_ENDIAN 0 638 639 /* Define this if most significant byte of a word is the lowest numbered. 640 Most ARM processors are run in little endian mode, so that is the default. 641 If you want to have it run-time selectable, change the definition in a 642 cover file to be TARGET_BIG_ENDIAN. */ 643 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 644 645 /* Define this if most significant word of a multiword number is the lowest 646 numbered. 647 This is always false, even when in big-endian mode. */ 648 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 649 650 #define UNITS_PER_WORD 4 651 652 /* True if natural alignment is used for doubleword types. */ 653 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 654 655 #define DOUBLEWORD_ALIGNMENT 64 656 657 #define PARM_BOUNDARY 32 658 659 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 660 661 #define PREFERRED_STACK_BOUNDARY \ 662 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 663 664 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 665 666 /* The lowest bit is used to indicate Thumb-mode functions, so the 667 vbit must go into the delta field of pointers to member 668 functions. */ 669 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 670 671 #define EMPTY_FIELD_BOUNDARY 32 672 673 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 674 675 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 676 677 /* XXX Blah -- this macro is used directly by libobjc. Since it 678 supports no vector modes, cut out the complexity and fall back 679 on BIGGEST_FIELD_ALIGNMENT. */ 680 #ifdef IN_TARGET_LIBS 681 #define BIGGEST_FIELD_ALIGNMENT 64 682 #endif 683 684 /* Make strings word-aligned so strcpy from constants will be faster. */ 685 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 686 687 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 688 ((TREE_CODE (EXP) == STRING_CST \ 689 && !optimize_size \ 690 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 691 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 692 693 /* Align definitions of arrays, unions and structures so that 694 initializations and copies can be made more efficient. This is not 695 ABI-changing, so it only affects places where we can see the 696 definition. Increasing the alignment tends to introduce padding, 697 so don't do this when optimizing for size/conserving stack space. */ 698 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 699 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 700 && (TREE_CODE (EXP) == ARRAY_TYPE \ 701 || TREE_CODE (EXP) == UNION_TYPE \ 702 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 703 704 /* Align global data. */ 705 #define DATA_ALIGNMENT(EXP, ALIGN) \ 706 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 707 708 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 709 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 710 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 711 712 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 713 value set in previous versions of this toolchain was 8, which produces more 714 compact structures. The command line option -mstructure_size_boundary=<n> 715 can be used to change this value. For compatibility with the ARM SDK 716 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 717 0020D) page 2-20 says "Structures are aligned on word boundaries". 718 The AAPCS specifies a value of 8. */ 719 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 720 721 /* This is the value used to initialize arm_structure_size_boundary. If a 722 particular arm target wants to change the default value it should change 723 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 724 for an example of this. */ 725 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 726 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 727 #endif 728 729 /* Nonzero if move instructions will actually fail to work 730 when given unaligned data. */ 731 #define STRICT_ALIGNMENT 1 732 733 /* wchar_t is unsigned under the AAPCS. */ 734 #ifndef WCHAR_TYPE 735 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 736 737 #define WCHAR_TYPE_SIZE BITS_PER_WORD 738 #endif 739 740 /* Sized for fixed-point types. */ 741 742 #define SHORT_FRACT_TYPE_SIZE 8 743 #define FRACT_TYPE_SIZE 16 744 #define LONG_FRACT_TYPE_SIZE 32 745 #define LONG_LONG_FRACT_TYPE_SIZE 64 746 747 #define SHORT_ACCUM_TYPE_SIZE 16 748 #define ACCUM_TYPE_SIZE 32 749 #define LONG_ACCUM_TYPE_SIZE 64 750 #define LONG_LONG_ACCUM_TYPE_SIZE 64 751 752 #define MAX_FIXED_MODE_SIZE 64 753 754 #ifndef SIZE_TYPE 755 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 756 #endif 757 758 #ifndef PTRDIFF_TYPE 759 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 760 #endif 761 762 /* AAPCS requires that structure alignment is affected by bitfields. */ 763 #ifndef PCC_BITFIELD_TYPE_MATTERS 764 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 765 #endif 766 767 768 /* Standard register usage. */ 769 770 /* Register allocation in ARM Procedure Call Standard 771 (S - saved over call). 772 773 r0 * argument word/integer result 774 r1-r3 argument word 775 776 r4-r8 S register variable 777 r9 S (rfp) register variable (real frame pointer) 778 779 r10 F S (sl) stack limit (used by -mapcs-stack-check) 780 r11 F S (fp) argument pointer 781 r12 (ip) temp workspace 782 r13 F S (sp) lower end of current stack frame 783 r14 (lr) link address/workspace 784 r15 F (pc) program counter 785 786 cc This is NOT a real register, but is used internally 787 to represent things that use or set the condition 788 codes. 789 sfp This isn't either. It is used during rtl generation 790 since the offset between the frame pointer and the 791 auto's isn't known until after register allocation. 792 afp Nor this, we only need this because of non-local 793 goto. Without it fp appears to be used and the 794 elimination code won't get rid of sfp. It tracks 795 fp exactly at all times. 796 797 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 798 799 /* s0-s15 VFP scratch (aka d0-d7). 800 s16-s31 S VFP variable (aka d8-d15). 801 vfpcc Not a real register. Represents the VFP condition 802 code flags. */ 803 804 /* The stack backtrace structure is as follows: 805 fp points to here: | save code pointer | [fp] 806 | return link value | [fp, #-4] 807 | return sp value | [fp, #-8] 808 | return fp value | [fp, #-12] 809 [| saved r10 value |] 810 [| saved r9 value |] 811 [| saved r8 value |] 812 [| saved r7 value |] 813 [| saved r6 value |] 814 [| saved r5 value |] 815 [| saved r4 value |] 816 [| saved r3 value |] 817 [| saved r2 value |] 818 [| saved r1 value |] 819 [| saved r0 value |] 820 r0-r3 are not normally saved in a C function. */ 821 822 /* 1 for registers that have pervasive standard uses 823 and are not available for the register allocator. */ 824 #define FIXED_REGISTERS \ 825 { \ 826 /* Core regs. */ \ 827 0,0,0,0,0,0,0,0, \ 828 0,0,0,0,0,1,0,1, \ 829 /* VFP regs. */ \ 830 1,1,1,1,1,1,1,1, \ 831 1,1,1,1,1,1,1,1, \ 832 1,1,1,1,1,1,1,1, \ 833 1,1,1,1,1,1,1,1, \ 834 1,1,1,1,1,1,1,1, \ 835 1,1,1,1,1,1,1,1, \ 836 1,1,1,1,1,1,1,1, \ 837 1,1,1,1,1,1,1,1, \ 838 /* IWMMXT regs. */ \ 839 1,1,1,1,1,1,1,1, \ 840 1,1,1,1,1,1,1,1, \ 841 1,1,1,1, \ 842 /* Specials. */ \ 843 1,1,1,1 \ 844 } 845 846 /* 1 for registers not available across function calls. 847 These must include the FIXED_REGISTERS and also any 848 registers that can be used without being saved. 849 The latter must include the registers where values are returned 850 and the register where structure-value addresses are passed. 851 Aside from that, you can include as many other registers as you like. 852 The CC is not preserved over function calls on the ARM 6, so it is 853 easier to assume this for all. SFP is preserved, since FP is. */ 854 #define CALL_USED_REGISTERS \ 855 { \ 856 /* Core regs. */ \ 857 1,1,1,1,0,0,0,0, \ 858 0,0,0,0,1,1,1,1, \ 859 /* VFP Regs. */ \ 860 1,1,1,1,1,1,1,1, \ 861 1,1,1,1,1,1,1,1, \ 862 1,1,1,1,1,1,1,1, \ 863 1,1,1,1,1,1,1,1, \ 864 1,1,1,1,1,1,1,1, \ 865 1,1,1,1,1,1,1,1, \ 866 1,1,1,1,1,1,1,1, \ 867 1,1,1,1,1,1,1,1, \ 868 /* IWMMXT regs. */ \ 869 1,1,1,1,1,1,1,1, \ 870 1,1,1,1,1,1,1,1, \ 871 1,1,1,1, \ 872 /* Specials. */ \ 873 1,1,1,1 \ 874 } 875 876 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 877 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 878 #endif 879 880 /* These are a couple of extensions to the formats accepted 881 by asm_fprintf: 882 %@ prints out ASM_COMMENT_START 883 %r prints out REGISTER_PREFIX reg_names[arg] */ 884 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 885 case '@': \ 886 fputs (ASM_COMMENT_START, FILE); \ 887 break; \ 888 \ 889 case 'r': \ 890 fputs (REGISTER_PREFIX, FILE); \ 891 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 892 break; 893 894 /* Round X up to the nearest word. */ 895 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 896 897 /* Convert fron bytes to ints. */ 898 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 899 900 /* The number of (integer) registers required to hold a quantity of type MODE. 901 Also used for VFP registers. */ 902 #define ARM_NUM_REGS(MODE) \ 903 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 904 905 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 906 #define ARM_NUM_REGS2(MODE, TYPE) \ 907 ARM_NUM_INTS ((MODE) == BLKmode ? \ 908 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 909 910 /* The number of (integer) argument register available. */ 911 #define NUM_ARG_REGS 4 912 913 /* And similarly for the VFP. */ 914 #define NUM_VFP_ARG_REGS 16 915 916 /* Return the register number of the N'th (integer) argument. */ 917 #define ARG_REGISTER(N) (N - 1) 918 919 /* Specify the registers used for certain standard purposes. 920 The values of these macros are register numbers. */ 921 922 /* The number of the last argument register. */ 923 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 924 925 /* The numbers of the Thumb register ranges. */ 926 #define FIRST_LO_REGNUM 0 927 #define LAST_LO_REGNUM 7 928 #define FIRST_HI_REGNUM 8 929 #define LAST_HI_REGNUM 11 930 931 /* Overridden by config/arm/bpabi.h. */ 932 #ifndef ARM_UNWIND_INFO 933 #define ARM_UNWIND_INFO 0 934 #endif 935 936 /* Use r0 and r1 to pass exception handling information. */ 937 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 938 939 /* The register that holds the return address in exception handlers. */ 940 #define ARM_EH_STACKADJ_REGNUM 2 941 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 942 943 #ifndef ARM_TARGET2_DWARF_FORMAT 944 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 945 #endif 946 947 /* ttype entries (the only interesting data references used) 948 use TARGET2 relocations. */ 949 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 950 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 951 : DW_EH_PE_absptr) 952 953 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 954 as an invisible last argument (possible since varargs don't exist in 955 Pascal), so the following is not true. */ 956 #define STATIC_CHAIN_REGNUM 12 957 958 /* Define this to be where the real frame pointer is if it is not possible to 959 work out the offset between the frame pointer and the automatic variables 960 until after register allocation has taken place. FRAME_POINTER_REGNUM 961 should point to a special register that we will make sure is eliminated. 962 963 For the Thumb we have another problem. The TPCS defines the frame pointer 964 as r11, and GCC believes that it is always possible to use the frame pointer 965 as base register for addressing purposes. (See comments in 966 find_reloads_address()). But - the Thumb does not allow high registers, 967 including r11, to be used as base address registers. Hence our problem. 968 969 The solution used here, and in the old thumb port is to use r7 instead of 970 r11 as the hard frame pointer and to have special code to generate 971 backtrace structures on the stack (if required to do so via a command line 972 option) using r11. This is the only 'user visible' use of r11 as a frame 973 pointer. */ 974 #define ARM_HARD_FRAME_POINTER_REGNUM 11 975 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 976 977 #define HARD_FRAME_POINTER_REGNUM \ 978 (TARGET_ARM \ 979 ? ARM_HARD_FRAME_POINTER_REGNUM \ 980 : THUMB_HARD_FRAME_POINTER_REGNUM) 981 982 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 983 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 984 985 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 986 987 /* Register to use for pushing function arguments. */ 988 #define STACK_POINTER_REGNUM SP_REGNUM 989 990 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 991 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 992 993 /* Need to sync with WCGR in iwmmxt.md. */ 994 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 995 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 996 997 #define IS_IWMMXT_REGNUM(REGNUM) \ 998 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 999 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1000 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1001 1002 /* Base register for access to local variables of the function. */ 1003 #define FRAME_POINTER_REGNUM 102 1004 1005 /* Base register for access to arguments of the function. */ 1006 #define ARG_POINTER_REGNUM 103 1007 1008 #define FIRST_VFP_REGNUM 16 1009 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1010 #define LAST_VFP_REGNUM \ 1011 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1012 1013 #define IS_VFP_REGNUM(REGNUM) \ 1014 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1015 1016 /* VFP registers are split into two types: those defined by VFP versions < 3 1017 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1018 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1019 in various parts of the backend, we implement as "fake" single-precision 1020 registers (which would be S32-S63, but cannot be used in that way). The 1021 following macros define these ranges of registers. */ 1022 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1023 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1024 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1025 1026 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1027 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1028 1029 /* DFmode values are only valid in even register pairs. */ 1030 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1031 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1032 1033 /* Neon Quad values must start at a multiple of four registers. */ 1034 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1035 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1036 1037 /* Neon structures of vectors must be in even register pairs and there 1038 must be enough registers available. Because of various patterns 1039 requiring quad registers, we require them to start at a multiple of 1040 four. */ 1041 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1042 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1043 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1044 1045 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 1046 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1047 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1048 #define FIRST_PSEUDO_REGISTER 104 1049 1050 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1051 1052 /* Value should be nonzero if functions must have frame pointers. 1053 Zero means the frame pointer need not be set up (and parms may be accessed 1054 via the stack pointer) in functions that seem suitable. 1055 If we have to have a frame pointer we might as well make use of it. 1056 APCS says that the frame pointer does not need to be pushed in leaf 1057 functions, or simple tail call functions. */ 1058 1059 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1060 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1061 #endif 1062 1063 /* Return number of consecutive hard regs needed starting at reg REGNO 1064 to hold something of mode MODE. 1065 This is ordinarily the length in words of a value of mode MODE 1066 but can be less for certain modes in special long registers. 1067 1068 On the ARM core regs are UNITS_PER_WORD bits wide. */ 1069 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1070 ((TARGET_32BIT \ 1071 && REGNO > PC_REGNUM \ 1072 && REGNO != FRAME_POINTER_REGNUM \ 1073 && REGNO != ARG_POINTER_REGNUM) \ 1074 && !IS_VFP_REGNUM (REGNO) \ 1075 ? 1 : ARM_NUM_REGS (MODE)) 1076 1077 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1078 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1079 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1080 1081 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) 1082 1083 #define VALID_IWMMXT_REG_MODE(MODE) \ 1084 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1085 1086 /* Modes valid for Neon D registers. */ 1087 #define VALID_NEON_DREG_MODE(MODE) \ 1088 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1089 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1090 1091 /* Modes valid for Neon Q registers. */ 1092 #define VALID_NEON_QREG_MODE(MODE) \ 1093 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1094 || (MODE) == V4SFmode || (MODE) == V2DImode) 1095 1096 /* Structure modes valid for Neon registers. */ 1097 #define VALID_NEON_STRUCT_MODE(MODE) \ 1098 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1099 || (MODE) == CImode || (MODE) == XImode) 1100 1101 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1102 extern int arm_regs_in_sequence[]; 1103 1104 /* The order in which register should be allocated. It is good to use ip 1105 since no saving is required (though calls clobber it) and it never contains 1106 function parameters. It is quite good to use lr since other calls may 1107 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1108 least likely to contain a function parameter; in addition results are 1109 returned in r0. 1110 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1111 then D8-D15. The reason for doing this is to attempt to reduce register 1112 pressure when both single- and double-precision registers are used in a 1113 function. */ 1114 1115 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1116 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1117 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1118 1119 #define REG_ALLOC_ORDER \ 1120 { \ 1121 /* General registers. */ \ 1122 3, 2, 1, 0, 12, 14, 4, 5, \ 1123 6, 7, 8, 9, 10, 11, \ 1124 /* High VFP registers. */ \ 1125 VREG(32), VREG(33), VREG(34), VREG(35), \ 1126 VREG(36), VREG(37), VREG(38), VREG(39), \ 1127 VREG(40), VREG(41), VREG(42), VREG(43), \ 1128 VREG(44), VREG(45), VREG(46), VREG(47), \ 1129 VREG(48), VREG(49), VREG(50), VREG(51), \ 1130 VREG(52), VREG(53), VREG(54), VREG(55), \ 1131 VREG(56), VREG(57), VREG(58), VREG(59), \ 1132 VREG(60), VREG(61), VREG(62), VREG(63), \ 1133 /* VFP argument registers. */ \ 1134 VREG(15), VREG(14), VREG(13), VREG(12), \ 1135 VREG(11), VREG(10), VREG(9), VREG(8), \ 1136 VREG(7), VREG(6), VREG(5), VREG(4), \ 1137 VREG(3), VREG(2), VREG(1), VREG(0), \ 1138 /* VFP call-saved registers. */ \ 1139 VREG(16), VREG(17), VREG(18), VREG(19), \ 1140 VREG(20), VREG(21), VREG(22), VREG(23), \ 1141 VREG(24), VREG(25), VREG(26), VREG(27), \ 1142 VREG(28), VREG(29), VREG(30), VREG(31), \ 1143 /* IWMMX registers. */ \ 1144 WREG(0), WREG(1), WREG(2), WREG(3), \ 1145 WREG(4), WREG(5), WREG(6), WREG(7), \ 1146 WREG(8), WREG(9), WREG(10), WREG(11), \ 1147 WREG(12), WREG(13), WREG(14), WREG(15), \ 1148 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1149 /* Registers not for general use. */ \ 1150 CC_REGNUM, VFPCC_REGNUM, \ 1151 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1152 SP_REGNUM, PC_REGNUM \ 1153 } 1154 1155 /* Use different register alloc ordering for Thumb. */ 1156 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1157 1158 /* Tell IRA to use the order we define rather than messing it up with its 1159 own cost calculations. */ 1160 #define HONOR_REG_ALLOC_ORDER 1161 1162 /* Interrupt functions can only use registers that have already been 1163 saved by the prologue, even if they would normally be 1164 call-clobbered. */ 1165 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1166 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1167 df_regs_ever_live_p (DST)) 1168 1169 /* Register and constant classes. */ 1170 1171 /* Register classes. */ 1172 enum reg_class 1173 { 1174 NO_REGS, 1175 LO_REGS, 1176 STACK_REG, 1177 BASE_REGS, 1178 HI_REGS, 1179 CALLER_SAVE_REGS, 1180 GENERAL_REGS, 1181 CORE_REGS, 1182 VFP_D0_D7_REGS, 1183 VFP_LO_REGS, 1184 VFP_HI_REGS, 1185 VFP_REGS, 1186 IWMMXT_REGS, 1187 IWMMXT_GR_REGS, 1188 CC_REG, 1189 VFPCC_REG, 1190 SFP_REG, 1191 AFP_REG, 1192 ALL_REGS, 1193 LIM_REG_CLASSES 1194 }; 1195 1196 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1197 1198 /* Give names of register classes as strings for dump file. */ 1199 #define REG_CLASS_NAMES \ 1200 { \ 1201 "NO_REGS", \ 1202 "LO_REGS", \ 1203 "STACK_REG", \ 1204 "BASE_REGS", \ 1205 "HI_REGS", \ 1206 "CALLER_SAVE_REGS", \ 1207 "GENERAL_REGS", \ 1208 "CORE_REGS", \ 1209 "VFP_D0_D7_REGS", \ 1210 "VFP_LO_REGS", \ 1211 "VFP_HI_REGS", \ 1212 "VFP_REGS", \ 1213 "IWMMXT_REGS", \ 1214 "IWMMXT_GR_REGS", \ 1215 "CC_REG", \ 1216 "VFPCC_REG", \ 1217 "SFP_REG", \ 1218 "AFP_REG", \ 1219 "ALL_REGS" \ 1220 } 1221 1222 /* Define which registers fit in which classes. 1223 This is an initializer for a vector of HARD_REG_SET 1224 of length N_REG_CLASSES. */ 1225 #define REG_CLASS_CONTENTS \ 1226 { \ 1227 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1228 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1229 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1230 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1231 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1232 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1233 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1234 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1235 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1236 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1237 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1238 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1239 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1240 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1241 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1242 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1243 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1244 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1245 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1246 } 1247 1248 /* Any of the VFP register classes. */ 1249 #define IS_VFP_CLASS(X) \ 1250 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1251 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1252 1253 /* The same information, inverted: 1254 Return the class number of the smallest class containing 1255 reg number REGNO. This could be a conditional expression 1256 or could index an array. */ 1257 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1258 1259 /* In VFPv1, VFP registers could only be accessed in the mode they 1260 were set, so subregs would be invalid there. However, we don't 1261 support VFPv1 at the moment, and the restriction was lifted in 1262 VFPv2. 1263 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in 1264 VFP registers in little-endian order. We can't describe that accurately to 1265 GCC, so avoid taking subregs of such values. 1266 The only exception is going from a 128-bit to a 64-bit type. In that case 1267 the data layout happens to be consistent for big-endian, so we explicitly allow 1268 that case. */ 1269 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1270 (TARGET_VFP && TARGET_BIG_END \ 1271 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ 1272 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ 1273 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ 1274 && reg_classes_intersect_p (VFP_REGS, (CLASS))) 1275 1276 /* The class value for index registers, and the one for base regs. */ 1277 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1278 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1279 1280 /* For the Thumb the high registers cannot be used as base registers 1281 when addressing quantities in QI or HI mode; if we don't know the 1282 mode, then we must be conservative. */ 1283 #define MODE_BASE_REG_CLASS(MODE) \ 1284 (arm_lra_flag \ 1285 ? (TARGET_32BIT ? CORE_REGS \ 1286 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1287 : LO_REGS) \ 1288 : ((TARGET_ARM || (TARGET_THUMB2 && !optimize_size)) ? CORE_REGS \ 1289 : ((MODE) == SImode) ? BASE_REGS \ 1290 : LO_REGS)) 1291 1292 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1293 instead of BASE_REGS. */ 1294 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1295 1296 /* When this hook returns true for MODE, the compiler allows 1297 registers explicitly used in the rtl to be used as spill registers 1298 but prevents the compiler from extending the lifetime of these 1299 registers. */ 1300 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1301 arm_small_register_classes_for_mode_p 1302 1303 /* Must leave BASE_REGS reloads alone */ 1304 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1305 (lra_in_progress ? NO_REGS \ 1306 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1307 ? ((true_regnum (X) == -1 ? LO_REGS \ 1308 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1309 : NO_REGS)) \ 1310 : NO_REGS)) 1311 1312 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1313 (lra_in_progress ? NO_REGS \ 1314 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1315 ? ((true_regnum (X) == -1 ? LO_REGS \ 1316 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1317 : NO_REGS)) \ 1318 : NO_REGS) 1319 1320 /* Return the register class of a scratch register needed to copy IN into 1321 or out of a register in CLASS in MODE. If it can be done directly, 1322 NO_REGS is returned. */ 1323 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1324 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1325 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1326 && IS_VFP_CLASS (CLASS)) \ 1327 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1328 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1329 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1330 : TARGET_32BIT \ 1331 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1332 ? GENERAL_REGS : NO_REGS) \ 1333 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1334 1335 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1336 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1337 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1338 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1339 && IS_VFP_CLASS (CLASS)) \ 1340 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1341 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1342 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1343 (TARGET_32BIT ? \ 1344 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1345 && CONSTANT_P (X)) \ 1346 ? GENERAL_REGS : \ 1347 (((MODE) == HImode && ! arm_arch4 \ 1348 && (MEM_P (X) \ 1349 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1350 && true_regnum (X) == -1))) \ 1351 ? GENERAL_REGS : NO_REGS) \ 1352 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1353 1354 /* Try a machine-dependent way of reloading an illegitimate address 1355 operand. If we find one, push the reload and jump to WIN. This 1356 macro is used in only one place: `find_reloads_address' in reload.c. 1357 1358 For the ARM, we wish to handle large displacements off a base 1359 register by splitting the addend across a MOV and the mem insn. 1360 This can cut the number of reloads needed. */ 1361 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1362 do \ 1363 { \ 1364 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ 1365 goto WIN; \ 1366 } \ 1367 while (0) 1368 1369 /* XXX If an HImode FP+large_offset address is converted to an HImode 1370 SP+large_offset address, then reload won't know how to fix it. It sees 1371 only that SP isn't valid for HImode, and so reloads the SP into an index 1372 register, but the resulting address is still invalid because the offset 1373 is too big. We fix it here instead by reloading the entire address. */ 1374 /* We could probably achieve better results by defining PROMOTE_MODE to help 1375 cope with the variances between the Thumb's signed and unsigned byte and 1376 halfword load instructions. */ 1377 /* ??? This should be safe for thumb2, but we may be able to do better. */ 1378 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1379 do { \ 1380 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1381 if (new_x) \ 1382 { \ 1383 X = new_x; \ 1384 goto WIN; \ 1385 } \ 1386 } while (0) 1387 1388 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1389 if (TARGET_ARM) \ 1390 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1391 else \ 1392 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1393 1394 /* Return the maximum number of consecutive registers 1395 needed to represent mode MODE in a register of class CLASS. 1396 ARM regs are UNITS_PER_WORD bits. 1397 FIXME: Is this true for iWMMX? */ 1398 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1399 (ARM_NUM_REGS (MODE)) 1400 1401 /* If defined, gives a class of registers that cannot be used as the 1402 operand of a SUBREG that changes the mode of the object illegally. */ 1403 1404 /* Stack layout; function entry, exit and calling. */ 1405 1406 /* Define this if pushing a word on the stack 1407 makes the stack pointer a smaller address. */ 1408 #define STACK_GROWS_DOWNWARD 1 1409 1410 /* Define this to nonzero if the nominal address of the stack frame 1411 is at the high-address end of the local variables; 1412 that is, each additional local variable allocated 1413 goes at a more negative offset in the frame. */ 1414 #define FRAME_GROWS_DOWNWARD 1 1415 1416 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1417 When present, it is one word in size, and sits at the top of the frame, 1418 between the soft frame pointer and either r7 or r11. 1419 1420 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1421 and only then if some outgoing arguments are passed on the stack. It would 1422 be tempting to also check whether the stack arguments are passed by indirect 1423 calls, but there seems to be no reason in principle why a post-reload pass 1424 couldn't convert a direct call into an indirect one. */ 1425 #define CALLER_INTERWORKING_SLOT_SIZE \ 1426 (TARGET_CALLER_INTERWORKING \ 1427 && crtl->outgoing_args_size != 0 \ 1428 ? UNITS_PER_WORD : 0) 1429 1430 /* Offset within stack frame to start allocating local variables at. 1431 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1432 first local allocated. Otherwise, it is the offset to the BEGINNING 1433 of the first local allocated. */ 1434 #define STARTING_FRAME_OFFSET 0 1435 1436 /* If we generate an insn to push BYTES bytes, 1437 this says how many the stack pointer really advances by. */ 1438 /* The push insns do not do this rounding implicitly. 1439 So don't define this. */ 1440 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1441 1442 /* Define this if the maximum size of all the outgoing args is to be 1443 accumulated and pushed during the prologue. The amount can be 1444 found in the variable crtl->outgoing_args_size. */ 1445 #define ACCUMULATE_OUTGOING_ARGS 1 1446 1447 /* Offset of first parameter from the argument pointer register value. */ 1448 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1449 1450 /* Amount of memory needed for an untyped call to save all possible return 1451 registers. */ 1452 #define APPLY_RESULT_SIZE arm_apply_result_size() 1453 1454 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1455 values must be in memory. On the ARM, they need only do so if larger 1456 than a word, or if they contain elements offset from zero in the struct. */ 1457 #define DEFAULT_PCC_STRUCT_RETURN 0 1458 1459 /* These bits describe the different types of function supported 1460 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1461 normal function and an interworked function, for example. Knowing the 1462 type of a function is important for determining its prologue and 1463 epilogue sequences. 1464 Note value 7 is currently unassigned. Also note that the interrupt 1465 function types all have bit 2 set, so that they can be tested for easily. 1466 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1467 machine_function structure is initialized (to zero) func_type will 1468 default to unknown. This will force the first use of arm_current_func_type 1469 to call arm_compute_func_type. */ 1470 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1471 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1472 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1473 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1474 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1475 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1476 1477 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1478 1479 /* In addition functions can have several type modifiers, 1480 outlined by these bit masks: */ 1481 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1482 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1483 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1484 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1485 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1486 1487 /* Some macros to test these flags. */ 1488 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1489 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1490 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1491 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1492 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1493 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1494 1495 1496 /* Structure used to hold the function stack frame layout. Offsets are 1497 relative to the stack pointer on function entry. Positive offsets are 1498 in the direction of stack growth. 1499 Only soft_frame is used in thumb mode. */ 1500 1501 typedef struct GTY(()) arm_stack_offsets 1502 { 1503 int saved_args; /* ARG_POINTER_REGNUM. */ 1504 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1505 int saved_regs; 1506 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1507 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1508 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1509 unsigned int saved_regs_mask; 1510 } 1511 arm_stack_offsets; 1512 1513 #ifndef GENERATOR_FILE 1514 /* A C structure for machine-specific, per-function data. 1515 This is added to the cfun structure. */ 1516 typedef struct GTY(()) machine_function 1517 { 1518 /* Additional stack adjustment in __builtin_eh_throw. */ 1519 rtx eh_epilogue_sp_ofs; 1520 /* Records if LR has to be saved for far jumps. */ 1521 int far_jump_used; 1522 /* Records if ARG_POINTER was ever live. */ 1523 int arg_pointer_live; 1524 /* Records if the save of LR has been eliminated. */ 1525 int lr_save_eliminated; 1526 /* The size of the stack frame. Only valid after reload. */ 1527 arm_stack_offsets stack_offsets; 1528 /* Records the type of the current function. */ 1529 unsigned long func_type; 1530 /* Record if the function has a variable argument list. */ 1531 int uses_anonymous_args; 1532 /* Records if sibcalls are blocked because an argument 1533 register is needed to preserve stack alignment. */ 1534 int sibcall_blocked; 1535 /* The PIC register for this function. This might be a pseudo. */ 1536 rtx pic_reg; 1537 /* Labels for per-function Thumb call-via stubs. One per potential calling 1538 register. We can never call via LR or PC. We can call via SP if a 1539 trampoline happens to be on the top of the stack. */ 1540 rtx call_via[14]; 1541 /* Set to 1 when a return insn is output, this means that the epilogue 1542 is not needed. */ 1543 int return_used_this_function; 1544 /* When outputting Thumb-1 code, record the last insn that provides 1545 information about condition codes, and the comparison operands. */ 1546 rtx thumb1_cc_insn; 1547 rtx thumb1_cc_op0; 1548 rtx thumb1_cc_op1; 1549 /* Also record the CC mode that is supported. */ 1550 enum machine_mode thumb1_cc_mode; 1551 } 1552 machine_function; 1553 #endif 1554 1555 /* As in the machine_function, a global set of call-via labels, for code 1556 that is in text_section. */ 1557 extern GTY(()) rtx thumb_call_via_label[14]; 1558 1559 /* The number of potential ways of assigning to a co-processor. */ 1560 #define ARM_NUM_COPROC_SLOTS 1 1561 1562 /* Enumeration of procedure calling standard variants. We don't really 1563 support all of these yet. */ 1564 enum arm_pcs 1565 { 1566 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1567 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1568 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1569 /* This must be the last AAPCS variant. */ 1570 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1571 ARM_PCS_ATPCS, /* ATPCS. */ 1572 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1573 ARM_PCS_UNKNOWN 1574 }; 1575 1576 /* Default procedure calling standard of current compilation unit. */ 1577 extern enum arm_pcs arm_pcs_default; 1578 1579 /* A C type for declaring a variable that is used as the first argument of 1580 `FUNCTION_ARG' and other related values. */ 1581 typedef struct 1582 { 1583 /* This is the number of registers of arguments scanned so far. */ 1584 int nregs; 1585 /* This is the number of iWMMXt register arguments scanned so far. */ 1586 int iwmmxt_nregs; 1587 int named_count; 1588 int nargs; 1589 /* Which procedure call variant to use for this call. */ 1590 enum arm_pcs pcs_variant; 1591 1592 /* AAPCS related state tracking. */ 1593 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1594 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1595 this argument, or -1 if using core 1596 registers. */ 1597 int aapcs_ncrn; 1598 int aapcs_next_ncrn; 1599 rtx aapcs_reg; /* Register assigned to this argument. */ 1600 int aapcs_partial; /* How many bytes are passed in regs (if 1601 split between core regs and stack. 1602 Zero otherwise. */ 1603 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1604 int can_split; /* Argument can be split between core regs 1605 and the stack. */ 1606 /* Private data for tracking VFP register allocation */ 1607 unsigned aapcs_vfp_regs_free; 1608 unsigned aapcs_vfp_reg_alloc; 1609 int aapcs_vfp_rcount; 1610 MACHMODE aapcs_vfp_rmode; 1611 } CUMULATIVE_ARGS; 1612 1613 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1614 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1615 1616 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1617 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1618 1619 /* For AAPCS, padding should never be below the argument. For other ABIs, 1620 * mimic the default. */ 1621 #define PAD_VARARGS_DOWN \ 1622 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1623 1624 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1625 for a call to a function whose data type is FNTYPE. 1626 For a library call, FNTYPE is 0. 1627 On the ARM, the offset starts at 0. */ 1628 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1629 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1630 1631 /* 1 if N is a possible register number for function argument passing. 1632 On the ARM, r0-r3 are used to pass args. */ 1633 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1634 (IN_RANGE ((REGNO), 0, 3) \ 1635 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1636 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1637 || (TARGET_IWMMXT_ABI \ 1638 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1639 1640 1641 /* If your target environment doesn't prefix user functions with an 1642 underscore, you may wish to re-define this to prevent any conflicts. */ 1643 #ifndef ARM_MCOUNT_NAME 1644 #define ARM_MCOUNT_NAME "*mcount" 1645 #endif 1646 1647 /* Call the function profiler with a given profile label. The Acorn 1648 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1649 On the ARM the full profile code will look like: 1650 .data 1651 LP1 1652 .word 0 1653 .text 1654 mov ip, lr 1655 bl mcount 1656 .word LP1 1657 1658 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1659 will output the .text section. 1660 1661 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1662 ``prof'' doesn't seem to mind about this! 1663 1664 Note - this version of the code is designed to work in both ARM and 1665 Thumb modes. */ 1666 #ifndef ARM_FUNCTION_PROFILER 1667 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1668 { \ 1669 char temp[20]; \ 1670 rtx sym; \ 1671 \ 1672 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1673 IP_REGNUM, LR_REGNUM); \ 1674 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1675 fputc ('\n', STREAM); \ 1676 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1677 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1678 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1679 } 1680 #endif 1681 1682 #ifdef THUMB_FUNCTION_PROFILER 1683 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1684 if (TARGET_ARM) \ 1685 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1686 else \ 1687 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1688 #else 1689 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1690 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1691 #endif 1692 1693 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1694 the stack pointer does not matter. The value is tested only in 1695 functions that have frame pointers. 1696 No definition is equivalent to always zero. 1697 1698 On the ARM, the function epilogue recovers the stack pointer from the 1699 frame. */ 1700 #define EXIT_IGNORE_STACK 1 1701 1702 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1703 1704 /* Determine if the epilogue should be output as RTL. 1705 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1706 #define USE_RETURN_INSN(ISCOND) \ 1707 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1708 1709 /* Definitions for register eliminations. 1710 1711 This is an array of structures. Each structure initializes one pair 1712 of eliminable registers. The "from" register number is given first, 1713 followed by "to". Eliminations of the same "from" register are listed 1714 in order of preference. 1715 1716 We have two registers that can be eliminated on the ARM. First, the 1717 arg pointer register can often be eliminated in favor of the stack 1718 pointer register. Secondly, the pseudo frame pointer register can always 1719 be eliminated; it is replaced with either the stack or the real frame 1720 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1721 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1722 1723 #define ELIMINABLE_REGS \ 1724 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1725 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1726 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1727 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1728 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1729 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1730 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1731 1732 /* Define the offset between two registers, one to be eliminated, and the 1733 other its replacement, at the start of a routine. */ 1734 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1735 if (TARGET_ARM) \ 1736 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1737 else \ 1738 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1739 1740 /* Special case handling of the location of arguments passed on the stack. */ 1741 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1742 1743 /* Initialize data used by insn expanders. This is called from insn_emit, 1744 once for every function before code is generated. */ 1745 #define INIT_EXPANDERS arm_init_expanders () 1746 1747 /* Length in units of the trampoline for entering a nested function. */ 1748 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1749 1750 /* Alignment required for a trampoline in bits. */ 1751 #define TRAMPOLINE_ALIGNMENT 32 1752 1753 /* Addressing modes, and classification of registers for them. */ 1754 #define HAVE_POST_INCREMENT 1 1755 #define HAVE_PRE_INCREMENT TARGET_32BIT 1756 #define HAVE_POST_DECREMENT TARGET_32BIT 1757 #define HAVE_PRE_DECREMENT TARGET_32BIT 1758 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1759 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1760 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1761 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1762 1763 enum arm_auto_incmodes 1764 { 1765 ARM_POST_INC, 1766 ARM_PRE_INC, 1767 ARM_POST_DEC, 1768 ARM_PRE_DEC 1769 }; 1770 1771 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1772 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1773 #define USE_LOAD_POST_INCREMENT(mode) \ 1774 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1775 #define USE_LOAD_PRE_INCREMENT(mode) \ 1776 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1777 #define USE_LOAD_POST_DECREMENT(mode) \ 1778 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1779 #define USE_LOAD_PRE_DECREMENT(mode) \ 1780 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1781 1782 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1783 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1784 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1785 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1786 1787 /* Macros to check register numbers against specific register classes. */ 1788 1789 /* These assume that REGNO is a hard or pseudo reg number. 1790 They give nonzero only if REGNO is a hard reg of the suitable class 1791 or a pseudo reg currently allocated to a suitable hard reg. 1792 Since they use reg_renumber, they are safe only once reg_renumber 1793 has been allocated, which happens in reginfo.c during register 1794 allocation. */ 1795 #define TEST_REGNO(R, TEST, VALUE) \ 1796 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1797 1798 /* Don't allow the pc to be used. */ 1799 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1800 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1801 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1802 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1803 1804 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1805 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1806 || (GET_MODE_SIZE (MODE) >= 4 \ 1807 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1808 1809 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1810 (TARGET_THUMB1 \ 1811 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1812 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1813 1814 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1815 For Thumb, we can not use SP + reg, so reject SP. */ 1816 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1817 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1818 1819 /* For ARM code, we don't care about the mode, but for Thumb, the index 1820 must be suitable for use in a QImode load. */ 1821 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1822 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1823 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1824 1825 /* Maximum number of registers that can appear in a valid memory address. 1826 Shifts in addresses can't be by a register. */ 1827 #define MAX_REGS_PER_ADDRESS 2 1828 1829 /* Recognize any constant value that is a valid address. */ 1830 /* XXX We can address any constant, eventually... */ 1831 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1832 #define CONSTANT_ADDRESS_P(X) \ 1833 (GET_CODE (X) == SYMBOL_REF \ 1834 && (CONSTANT_POOL_ADDRESS_P (X) \ 1835 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1836 1837 /* True if SYMBOL + OFFSET constants must refer to something within 1838 SYMBOL's section. */ 1839 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1840 1841 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1842 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1843 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1844 #endif 1845 1846 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1847 #define SUBTARGET_NAME_ENCODING_LENGTHS 1848 #endif 1849 1850 /* This is a C fragment for the inside of a switch statement. 1851 Each case label should return the number of characters to 1852 be stripped from the start of a function's name, if that 1853 name starts with the indicated character. */ 1854 #define ARM_NAME_ENCODING_LENGTHS \ 1855 case '*': return 1; \ 1856 SUBTARGET_NAME_ENCODING_LENGTHS 1857 1858 /* This is how to output a reference to a user-level label named NAME. 1859 `assemble_name' uses this. */ 1860 #undef ASM_OUTPUT_LABELREF 1861 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1862 arm_asm_output_labelref (FILE, NAME) 1863 1864 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1865 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1866 if (TARGET_THUMB2) \ 1867 thumb2_asm_output_opcode (STREAM); 1868 1869 /* The EABI specifies that constructors should go in .init_array. 1870 Other targets use .ctors for compatibility. */ 1871 #ifndef ARM_EABI_CTORS_SECTION_OP 1872 #define ARM_EABI_CTORS_SECTION_OP \ 1873 "\t.section\t.init_array,\"aw\",%init_array" 1874 #endif 1875 #ifndef ARM_EABI_DTORS_SECTION_OP 1876 #define ARM_EABI_DTORS_SECTION_OP \ 1877 "\t.section\t.fini_array,\"aw\",%fini_array" 1878 #endif 1879 #define ARM_CTORS_SECTION_OP \ 1880 "\t.section\t.ctors,\"aw\",%progbits" 1881 #define ARM_DTORS_SECTION_OP \ 1882 "\t.section\t.dtors,\"aw\",%progbits" 1883 1884 /* Define CTORS_SECTION_ASM_OP. */ 1885 #undef CTORS_SECTION_ASM_OP 1886 #undef DTORS_SECTION_ASM_OP 1887 #ifndef IN_LIBGCC2 1888 # define CTORS_SECTION_ASM_OP \ 1889 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1890 # define DTORS_SECTION_ASM_OP \ 1891 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1892 #else /* !defined (IN_LIBGCC2) */ 1893 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1894 so we cannot use the definition above. */ 1895 # ifdef __ARM_EABI__ 1896 /* The .ctors section is not part of the EABI, so we do not define 1897 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1898 from trying to use it. We do define it when doing normal 1899 compilation, as .init_array can be used instead of .ctors. */ 1900 /* There is no need to emit begin or end markers when using 1901 init_array; the dynamic linker will compute the size of the 1902 array itself based on special symbols created by the static 1903 linker. However, we do need to arrange to set up 1904 exception-handling here. */ 1905 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1906 # define CTOR_LIST_END /* empty */ 1907 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1908 # define DTOR_LIST_END /* empty */ 1909 # else /* !defined (__ARM_EABI__) */ 1910 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1911 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1912 # endif /* !defined (__ARM_EABI__) */ 1913 #endif /* !defined (IN_LIBCC2) */ 1914 1915 /* True if the operating system can merge entities with vague linkage 1916 (e.g., symbols in COMDAT group) during dynamic linking. */ 1917 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1918 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1919 #endif 1920 1921 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1922 1923 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1924 and check its validity for a certain class. 1925 We have two alternate definitions for each of them. 1926 The usual definition accepts all pseudo regs; the other rejects 1927 them unless they have been allocated suitable hard regs. 1928 The symbol REG_OK_STRICT causes the latter definition to be used. 1929 Thumb-2 has the same restrictions as arm. */ 1930 #ifndef REG_OK_STRICT 1931 1932 #define ARM_REG_OK_FOR_BASE_P(X) \ 1933 (REGNO (X) <= LAST_ARM_REGNUM \ 1934 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1935 || REGNO (X) == FRAME_POINTER_REGNUM \ 1936 || REGNO (X) == ARG_POINTER_REGNUM) 1937 1938 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1939 ((REGNO (X) <= LAST_ARM_REGNUM \ 1940 && REGNO (X) != STACK_POINTER_REGNUM) \ 1941 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1942 || REGNO (X) == FRAME_POINTER_REGNUM \ 1943 || REGNO (X) == ARG_POINTER_REGNUM) 1944 1945 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1946 (REGNO (X) <= LAST_LO_REGNUM \ 1947 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1948 || (GET_MODE_SIZE (MODE) >= 4 \ 1949 && (REGNO (X) == STACK_POINTER_REGNUM \ 1950 || (X) == hard_frame_pointer_rtx \ 1951 || (X) == arg_pointer_rtx))) 1952 1953 #define REG_STRICT_P 0 1954 1955 #else /* REG_OK_STRICT */ 1956 1957 #define ARM_REG_OK_FOR_BASE_P(X) \ 1958 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1959 1960 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1961 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1962 1963 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1964 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1965 1966 #define REG_STRICT_P 1 1967 1968 #endif /* REG_OK_STRICT */ 1969 1970 /* Now define some helpers in terms of the above. */ 1971 1972 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1973 (TARGET_THUMB1 \ 1974 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1975 : ARM_REG_OK_FOR_BASE_P (X)) 1976 1977 /* For 16-bit Thumb, a valid index register is anything that can be used in 1978 a byte load instruction. */ 1979 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1980 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1981 1982 /* Nonzero if X is a hard reg that can be used as an index 1983 or if it is a pseudo reg. On the Thumb, the stack pointer 1984 is not suitable. */ 1985 #define REG_OK_FOR_INDEX_P(X) \ 1986 (TARGET_THUMB1 \ 1987 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1988 : ARM_REG_OK_FOR_INDEX_P (X)) 1989 1990 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1991 For Thumb, we can not use SP + reg, so reject SP. */ 1992 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1993 REG_OK_FOR_INDEX_P (X) 1994 1995 #define ARM_BASE_REGISTER_RTX_P(X) \ 1996 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1997 1998 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1999 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 2000 2001 /* Specify the machine mode that this machine uses 2002 for the index in the tablejump instruction. */ 2003 #define CASE_VECTOR_MODE Pmode 2004 2005 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 2006 || (TARGET_THUMB1 \ 2007 && (optimize_size || flag_pic))) 2008 2009 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2010 (TARGET_THUMB1 \ 2011 ? (min >= 0 && max < 512 \ 2012 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2013 : min >= -256 && max < 256 \ 2014 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2015 : min >= 0 && max < 8192 \ 2016 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2017 : min >= -4096 && max < 4096 \ 2018 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2019 : SImode) \ 2020 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2021 : (max >= 0x200) ? HImode \ 2022 : QImode)) 2023 2024 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2025 unsigned is probably best, but may break some code. */ 2026 #ifndef DEFAULT_SIGNED_CHAR 2027 #define DEFAULT_SIGNED_CHAR 0 2028 #endif 2029 2030 /* Max number of bytes we can move from memory to memory 2031 in one reasonably fast instruction. */ 2032 #define MOVE_MAX 4 2033 2034 #undef MOVE_RATIO 2035 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2036 2037 /* Define if operations between registers always perform the operation 2038 on the full register even if a narrower mode is specified. */ 2039 #define WORD_REGISTER_OPERATIONS 2040 2041 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2042 will either zero-extend or sign-extend. The value of this macro should 2043 be the code that says which one of the two operations is implicitly 2044 done, UNKNOWN if none. */ 2045 #define LOAD_EXTEND_OP(MODE) \ 2046 (TARGET_THUMB ? ZERO_EXTEND : \ 2047 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2048 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2049 2050 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2051 #define SLOW_BYTE_ACCESS 0 2052 2053 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2054 2055 /* Immediate shift counts are truncated by the output routines (or was it 2056 the assembler?). Shift counts in a register are truncated by ARM. Note 2057 that the native compiler puts too large (> 32) immediate shift counts 2058 into a register and shifts by the register, letting the ARM decide what 2059 to do instead of doing that itself. */ 2060 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2061 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2062 On the arm, Y in a register is used modulo 256 for the shift. Only for 2063 rotates is modulo 32 used. */ 2064 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2065 2066 /* All integers have the same format so truncation is easy. */ 2067 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2068 2069 /* Calling from registers is a massive pain. */ 2070 #define NO_FUNCTION_CSE 1 2071 2072 /* The machine modes of pointers and functions */ 2073 #define Pmode SImode 2074 #define FUNCTION_MODE Pmode 2075 2076 #define ARM_FRAME_RTX(X) \ 2077 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2078 || (X) == arg_pointer_rtx) 2079 2080 /* Try to generate sequences that don't involve branches, we can then use 2081 conditional instructions. */ 2082 #define BRANCH_COST(speed_p, predictable_p) \ 2083 (current_tune->branch_cost (speed_p, predictable_p)) 2084 2085 /* False if short circuit operation is preferred. */ 2086 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2087 ((optimize_size) \ 2088 ? (TARGET_THUMB ? false : true) \ 2089 : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) 2090 2091 2092 /* Position Independent Code. */ 2093 /* We decide which register to use based on the compilation options and 2094 the assembler in use; this is more general than the APCS restriction of 2095 using sb (r9) all the time. */ 2096 extern unsigned arm_pic_register; 2097 2098 /* The register number of the register used to address a table of static 2099 data addresses in memory. */ 2100 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2101 2102 /* We can't directly access anything that contains a symbol, 2103 nor can we indirect via the constant pool. One exception is 2104 UNSPEC_TLS, which is always PIC. */ 2105 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2106 (!(symbol_mentioned_p (X) \ 2107 || label_mentioned_p (X) \ 2108 || (GET_CODE (X) == SYMBOL_REF \ 2109 && CONSTANT_POOL_ADDRESS_P (X) \ 2110 && (symbol_mentioned_p (get_pool_constant (X)) \ 2111 || label_mentioned_p (get_pool_constant (X))))) \ 2112 || tls_mentioned_p (X)) 2113 2114 /* We need to know when we are making a constant pool; this determines 2115 whether data needs to be in the GOT or can be referenced via a GOT 2116 offset. */ 2117 extern int making_const_table; 2118 2119 /* Handle pragmas for compatibility with Intel's compilers. */ 2120 /* Also abuse this to register additional C specific EABI attributes. */ 2121 #define REGISTER_TARGET_PRAGMAS() do { \ 2122 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2123 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2124 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2125 arm_lang_object_attributes_init(); \ 2126 } while (0) 2127 2128 /* Condition code information. */ 2129 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2130 return the mode to be used for the comparison. */ 2131 2132 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2133 2134 #define REVERSIBLE_CC_MODE(MODE) 1 2135 2136 #define REVERSE_CONDITION(CODE,MODE) \ 2137 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2138 ? reverse_condition_maybe_unordered (code) \ 2139 : reverse_condition (code)) 2140 2141 /* The arm5 clz instruction returns 32. */ 2142 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2143 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2144 2145 #define CC_STATUS_INIT \ 2146 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2147 2148 #undef ASM_APP_OFF 2149 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ 2150 TARGET_THUMB2 ? "\t.thumb\n" : "") 2151 2152 /* Output a push or a pop instruction (only used when profiling). 2153 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2154 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2155 that r7 isn't used by the function profiler, so we can use it as a 2156 scratch reg. WARNING: This isn't safe in the general case! It may be 2157 sensitive to future changes in final.c:profile_function. */ 2158 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2159 do \ 2160 { \ 2161 if (TARGET_ARM) \ 2162 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2163 STACK_POINTER_REGNUM, REGNO); \ 2164 else if (TARGET_THUMB1 \ 2165 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2166 { \ 2167 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2168 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2169 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2170 } \ 2171 else \ 2172 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2173 } while (0) 2174 2175 2176 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2177 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2178 do \ 2179 { \ 2180 if (TARGET_ARM) \ 2181 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2182 STACK_POINTER_REGNUM, REGNO); \ 2183 else if (TARGET_THUMB1 \ 2184 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2185 { \ 2186 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2187 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2188 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2189 } \ 2190 else \ 2191 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2192 } while (0) 2193 2194 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2195 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2196 2197 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2198 default alignment from elfos.h. */ 2199 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2200 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2201 2202 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2203 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2204 ? 1 : 0) 2205 2206 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2207 do \ 2208 { \ 2209 if (TARGET_THUMB) \ 2210 { \ 2211 if (is_called_in_ARM_mode (DECL) \ 2212 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2213 && cfun->is_thunk)) \ 2214 fprintf (STREAM, "\t.code 32\n") ; \ 2215 else if (TARGET_THUMB1) \ 2216 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2217 else \ 2218 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2219 } \ 2220 if (TARGET_POKE_FUNCTION_NAME) \ 2221 arm_poke_function_name (STREAM, (const char *) NAME); \ 2222 } \ 2223 while (0) 2224 2225 /* For aliases of functions we use .thumb_set instead. */ 2226 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2227 do \ 2228 { \ 2229 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2230 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2231 \ 2232 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2233 { \ 2234 fprintf (FILE, "\t.thumb_set "); \ 2235 assemble_name (FILE, LABEL1); \ 2236 fprintf (FILE, ","); \ 2237 assemble_name (FILE, LABEL2); \ 2238 fprintf (FILE, "\n"); \ 2239 } \ 2240 else \ 2241 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2242 } \ 2243 while (0) 2244 2245 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2246 /* To support -falign-* switches we need to use .p2align so 2247 that alignment directives in code sections will be padded 2248 with no-op instructions, rather than zeroes. */ 2249 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2250 if ((LOG) != 0) \ 2251 { \ 2252 if ((MAX_SKIP) == 0) \ 2253 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2254 else \ 2255 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2256 (int) (LOG), (int) (MAX_SKIP)); \ 2257 } 2258 #endif 2259 2260 /* Add two bytes to the length of conditionally executed Thumb-2 2261 instructions for the IT instruction. */ 2262 #define ADJUST_INSN_LENGTH(insn, length) \ 2263 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2264 length += 2; 2265 2266 /* Only perform branch elimination (by making instructions conditional) if 2267 we're optimizing. For Thumb-2 check if any IT instructions need 2268 outputting. */ 2269 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2270 if (TARGET_ARM && optimize) \ 2271 arm_final_prescan_insn (INSN); \ 2272 else if (TARGET_THUMB2) \ 2273 thumb2_final_prescan_insn (INSN); \ 2274 else if (TARGET_THUMB1) \ 2275 thumb1_final_prescan_insn (INSN) 2276 2277 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2278 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2279 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2280 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2281 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2282 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2283 : 0)))) 2284 2285 /* A C expression whose value is RTL representing the value of the return 2286 address for the frame COUNT steps up from the current frame. */ 2287 2288 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2289 arm_return_addr (COUNT, FRAME) 2290 2291 /* Mask of the bits in the PC that contain the real return address 2292 when running in 26-bit mode. */ 2293 #define RETURN_ADDR_MASK26 (0x03fffffc) 2294 2295 /* Pick up the return address upon entry to a procedure. Used for 2296 dwarf2 unwind information. This also enables the table driven 2297 mechanism. */ 2298 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2299 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2300 2301 /* Used to mask out junk bits from the return address, such as 2302 processor state, interrupt status, condition codes and the like. */ 2303 #define MASK_RETURN_ADDR \ 2304 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2305 in 26 bit mode, the condition codes must be masked out of the \ 2306 return address. This does not apply to ARM6 and later processors \ 2307 when running in 32 bit mode. */ \ 2308 ((arm_arch4 || TARGET_THUMB) \ 2309 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2310 : arm_gen_return_addr_mask ()) 2311 2312 2313 /* Do not emit .note.GNU-stack by default. */ 2314 #ifndef NEED_INDICATE_EXEC_STACK 2315 #define NEED_INDICATE_EXEC_STACK 0 2316 #endif 2317 2318 #define TARGET_ARM_ARCH \ 2319 (arm_base_arch) \ 2320 2321 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) 2322 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) 2323 2324 /* The highest Thumb instruction set version supported by the chip. */ 2325 #define TARGET_ARM_ARCH_ISA_THUMB \ 2326 (arm_arch_thumb2 ? 2 \ 2327 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) 2328 2329 /* Expands to an upper-case char of the target's architectural 2330 profile. */ 2331 #define TARGET_ARM_ARCH_PROFILE \ 2332 (!arm_arch_notm \ 2333 ? 'M' \ 2334 : (arm_arch7 \ 2335 ? (strlen (arm_arch_name) >=3 \ 2336 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ 2337 : 0) \ 2338 : 0)) 2339 2340 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2341 Bit 0 for bytes, up to bit 3 for double-words. */ 2342 #define TARGET_ARM_FEATURE_LDREX \ 2343 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2344 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2345 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2346 2347 /* Set as a bit mask indicating the available widths of hardware floating 2348 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2349 32-bit support, bit 3 indicates 64-bit support. */ 2350 #define TARGET_ARM_FP \ 2351 (TARGET_VFP_SINGLE ? 4 \ 2352 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) 2353 2354 2355 /* Set as a bit mask indicating the available widths of floating point 2356 types for hardware NEON floating point. This is the same as 2357 TARGET_ARM_FP without the 64-bit bit set. */ 2358 #ifdef TARGET_NEON 2359 #define TARGET_NEON_FP \ 2360 (TARGET_ARM_FP & (0xff ^ 0x08)) 2361 #endif 2362 2363 /* The maximum number of parallel loads or stores we support in an ldm/stm 2364 instruction. */ 2365 #define MAX_LDM_STM_OPS 4 2366 2367 #define BIG_LITTLE_SPEC \ 2368 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" 2369 2370 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2371 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2372 { "rewrite_mcpu", arm_rewrite_mcpu }, 2373 2374 #define ASM_CPU_SPEC \ 2375 " %{mcpu=generic-*:-march=%*;" \ 2376 " :%{march=*:-march=%*}}" \ 2377 BIG_LITTLE_SPEC 2378 2379 /* -mcpu=native handling only makes sense with compiler running on 2380 an ARM chip. */ 2381 #if defined(__arm__) 2382 extern const char *host_detect_local_cpu (int argc, const char **argv); 2383 # define EXTRA_SPEC_FUNCTIONS \ 2384 { "local_cpu_detect", host_detect_local_cpu }, \ 2385 BIG_LITTLE_CPU_SPEC_FUNCTIONS 2386 2387 # define MCPU_MTUNE_NATIVE_SPECS \ 2388 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2389 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2390 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2391 #else 2392 # define MCPU_MTUNE_NATIVE_SPECS "" 2393 # define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS 2394 #endif 2395 2396 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS 2397 2398 #endif /* ! GCC_ARM_H */ 2399