1 ifndef regcop8inc ; avoid multiple inclusion 2regcop8inc equ 1 3 4 save 5 listing off ; no listing over this file 6;**************************************************************************** 7;* * 8;* AS 1.42 - File REGCOP8.INC * 9;* * 10;* Contains Register Definitions for COP8 Controllers * 11;* * 12;**************************************************************************** 13 14 if MOMPASS=1 15 switch MOMCPUNAME 16 case "COP87L84" 17 message "including COP87L84-registers" 18 elsecase 19 fatal "invalid processor type: only COP87L84 allowed" 20 endcase 21 endif 22 23;---------------------------------------------------------------------------- 24; Processor Core 25 26__REG set 0 27 rept 10 28R{"\{__REG}"} equ __REG+0xf0 29__REG set __REG+1,data 30 endm 31 rept 6 32R1{"\{__REG-10}"} equ __REG+0xf0 33__REG set __REG+1,data 34 endm 35 36psw sfr 0xef ; Flags 37gie equ 0 ; Global Interrupt Enable 38exen equ 1 ; External Interrupt Enable 39busy equ 2 ; Microwire Busy 40expnd equ 3 ; External Interrupt Pending 41t1ena equ 4 ; Timer 1 Interrupt Enable 42t1pnda equ 5 ; Timer 1 Interrupt Pending 43c equ 6 ; Carry 44hc equ 7 ; Half Carry 45x sfr 0xfc ; X-Register 46sp sfr 0xfd ; Stack Pointer 47b sfr 0xfe ; B Register 48 49;---------------------------------------------------------------------------- 50; Peripheral Control Registers 51 52cntrl sfr 0xee ; Globale Control 53sl0 equ 0 ; Microwire Clock Divider 54sl1 equ 1 55iedg equ 2 ; External Interrupt Edge Select 56msel equ 3 ; Microwire use G4/G5 57t1c0 equ 4 ; Timer 1 Interrupt/Start-Stop 58t1c1 equ 5 ; Timer 1 Mode Select 59t1c2 equ 6 60t1c3 equ 7 61 62icntrl sfr 0xe8 ; Continuation... 63t1enb equ 0 ; Timer 1 Capture Interrupt Enable 64t1pndb equ 1 ; Timer 1 Capture Interrupt Pending 65uwen equ 2 ; MicroWire-Interrupt Enable 66uwpnd equ 3 ; MicroWire-Interrupt Pending 67t0en equ 4 ; Timer 0 Interrupt Enable 68t0pndb equ 5 ; Timer 0 Interrupt Pending 69lpen equ 6 ; Port L-Interrupt Enable 70 71;---------------------------------------------------------------------------- 72; Timer 73 74t1rblo sfr 0xe6 ; Timer 1 Reload Value B 75t1rbhi sfr 0xe7 76 77tmr1lo sfr 0xea ; Timer 1 Count Value 78tmr1hi sfr 0xeb 79 80t1ralo sfr 0xec ; Timer 1 Reload Value B 81t1rahi sfr 0xed 82 83;---------------------------------------------------------------------------- 84; PWM 85 86pscal sfr 0xa0 ; PWM Prescaler 87 88rlon sfr 0xa1 ; PWM Duty Cycle 89 90pwmcon sfr 0xa2 ; PWM Control 91pwen0 equ 0 ; PWM0 Output to I/O Port 92pwen1 equ 1 ; PWM1 Output to I/O Port 93pwon equ 2 ; PWM Start/Stop 94pwmd equ 3 ; PWM Mode 95pwie equ 4 ; PWM Interrupt Enable 96pwpnd equ 5 ; PWM Interrupt Pending 97esel equ 6 ; PWM Edge Select 98 99;---------------------------------------------------------------------------- 100; MicroWire Interface 101 102wkedg sfr 0xc8 103wken sfr 0xc9 104wkpnd sfr 0xca 105 106sior sfr 0xe9 ; Shift register 107 108;---------------------------------------------------------------------------- 109; CAN Interface 110 111txd1 sfr 0xb0 ; Transmit Data (Byte 1,3,5,7,...) 112txd2 sfr 0xb1 ; Transmit Data (Byte 2,4,6,8,...) 113 114tdlc sfr 0xb2 ; Transmit Length/Identifier(L) Register 115tdlc0 equ 0 ; Transmit Length 116tdlc1 equ 1 117tdlc2 equ 2 118tdlc3 equ 3 119tid0 equ 4 ; Transmit Identification (Bits 0..3) 120tid1 equ 5 121tid2 equ 6 122tid3 equ 7 123 124tid sfr 0xb3 ; Transmit Identification Register 125tid4 equ 0 ; Transmit Identification (Bits 4..10) 126tid5 equ 1 127tid6 equ 2 128tid7 equ 3 129tid8 equ 4 130tid9 equ 5 131tid10 equ 6 132trtr equ 7 ; Transmit Frame Remote 133 134rxd1 sfr 0xb4 ; Receive Data (Byte 1,3,5,7,...) 135rxd2 sfr 0xb5 ; Receive Data (Byte 2,4,6,8,...) 136 137ridl sfr 0xb6 ; Receive Length/Identifier(L) Register 138rdlc0 equ 0 ; Receive Length 139rdlc1 equ 1 140rdlc2 equ 2 141rdlc3 equ 3 142rid0 equ 4 ; Receive Identification (Bits 0..3) 143rid1 equ 5 144rid2 equ 6 145rid3 equ 7 146 147rid sfr 0xb7 ; Receive Identification Register 148rid4 equ 0 ; Receive Identification (Bits 4..10) 149rid5 equ 1 150rid6 equ 2 151rid7 equ 3 152rid8 equ 4 153rid9 equ 5 154rid10 equ 6 155 156cscal sfr 0xb8 ; CAN Clock Prescaler 157 158ctim sfr 0xb9 ; CAN Bus Timing Register 159ps0 equ 2 ; Phase Segment 160ps1 equ 3 161ps2 equ 4 162pps0 equ 5 ; Propagation Segment 163pps1 equ 6 164pps2 equ 7 165 166cbus sfr 0xba ; CAN Bus Timing Register 167fmod equ 1 ; Fault Confinement Mode 168rxred0 equ 2 ; Apply Reference Voltage to Rx0 169rxref1 equ 3 ; Apply Reference Voltage to Tx0 170txen0 equ 4 ; Enable TxD Output Drivers 171txen1 equ 5 172riaf equ 6 ; Receive Filter Enable 173 174tcntl sfr 0xbb ; CAN Bus Control/Status Register 175txss equ 0 ; Transmitter Start/Stop 176rie equ 1 ; Receive Interrupt Enable 177tie equ 2 ; Transmit Interrupt Enable 178ceie equ 3 ; CAN Interrupt Enable 179rerr equ 4 ; Receive Error 180terr equ 5 ; Transmit Error 181ns0 equ 6 ; Node State 182ns1 equ 7 183 184rtstat sfr 0xbc ; CAN Bus Transmitter/Receiver State 185rbf equ 0 ; Receive Buffer Full 186rcv equ 1 ; Reception Running 187rfv equ 2 ; Received Frame Valid 188rorn equ 3 ; Receiver Overflow 189rold equ 4 ; Receiver Frame Overflow 190rrtr equ 5 ; Remote-Bit Set in Received Frame 191txpnd equ 6 ; Transmission Pending 192tbe equ 7 ; Transmit Buffer Empty 193 194tec sfr 0xbd ; Transmit Error Counter 195rec sfr 0xbe ; Receive Error Counter 196 197;---------------------------------------------------------------------------- 198; Comparators 199 200cmpsl sfr 0xd3 ; Comparator Control Register 201cmp1en equ 1 ; Comparator 1 Enable 202cmp1rd equ 2 ; Comparator 1 Output Value 203cmp1oe equ 3 ; Comparator 1 Output Enable 204cmp2en equ 4 ; Comparator 2 Enable 205cmp2rd equ 5 ; Comparator 2 Output Value 206cmp2oe equ 6 ; Comparator 2 Output Enable 207cmp2sel equ 7 ; Comparator 2 Output on L3/L5 208 209;---------------------------------------------------------------------------- 210; Ports 211 212portld sfr 0xd0 ; Port L Output Register 213portlc sfr 0xd1 ; Port L Configuration Register 214portlp sfr 0xd2 ; Port L Input Register 215 216portgd sfr 0xd4 ; Port G Output Register 217portgc sfr 0xd5 ; Port G Configuration Register 218portgp sfr 0xd6 ; Port G Input Register 219 220portd sfr 0xdc ; Port D Output Register 221 222;---------------------------------------------------------------------------- 223; Vector Addresses 224 225;---------------------------------------------------------------------------- 226; Memory Addresses 227 228iram sfr 0x00 ; Internal RAM Area 229iramend sfr 0x2f 230 231;---------------------------------------------------------------------------- 232 233 restore ; re-enable listing 234 235 endif ; regcop8inc 236 237 238