1 ifndef regmspinc ; avoid multiple inclusion 2regmspinc equ 1 3 4 save 5 listing off ; no listing over this file 6;**************************************************************************** 7;* * 8;* AS 1.42 - File REGMSP.INC * 9;* * 10;* Contains Macro and Register Definitions for MSP430 * 11;* * 12;**************************************************************************** 13 14 if (MOMCPUNAME<>"MSP430")&&(MOMCPUNAME<>"MSP430X") 15 fatal "wrong target selected: only MSP430(X) supported" 16 endif 17 18 if MOMPASS=1 19 message "MSP430 Register Definitionen (C) 1996/2007 Alfred Arnold, Jose Da Silva" 20 endif 21 22;---------------------------------------------------------------------------- 23; General Memory Layout 24; ---------------------- 25; 26; 0000 - 000f : Special Function Registers 27; 0010 - 00ff : 8bit Peripheral Modules 28; 0100 - 01ff : 16bit Peripheral Modules 29; 0200 - .... : RAM Memory 30; .... - ffdf : Flash Memory 31; ffe0 - ffff : Interrupt Vector Table 32; 33;---------------------------------------------------------------------------- 34 35;---------------------------------------------------------------------------- 36; Status Register 37 38SCG1 equ 128 ; System Clock Generator 1. 1=Turn_Off_SMCLK 39SCG0 equ 64 ; System Clock Generator 0. 1=Turn_Off_DCO 40OSCOFF equ 32 ; Oscillator Off. 1=Turn_Off_LFXT1CLK 41CPUOFF equ 16 ; CPU Off. 1=Turn_Off_CPU (SR) 42GIE equ 8 ; General Interrupt Enable (SR) 43 44;---------------------------------------------------------------------------- 45; Special Function Register of MSP430x1xx Family, Byte Access 46 47IE1 equ 000h ; Interrupt Enable 48ACCVIE equ 32 ; Flash Access Interrupt Enable (IE1.5) 49NMIIE equ 16 ; NMI Enable (IE1.4) 50OFIE equ 2 ; Osc Fault Interrupt Enable (IE1.1) 51WDTIE equ 1 ; Watchdog Interrupt Enable (IE1.0) 52 53IFG1 equ 002h ; Interrupt Flag 54NMIIFG equ 16 ; Set Via !RST/NMI Pin (IFG1.4) 55RSTIFG equ 8 ; External Reset Interrupt Flag (IFG1.3) 56PORIFG equ 4 ; Power-on-Reset Interrupt Flag (IFG1.2) 57OFIFG equ 2 ; Flag on Oscillator Fault (IFG1.1) 58WDTIFG equ 1 ; Watchdog or Security Key Violation (IFG1.0) 59 60ME1 equ 004h ; Module Enable 61 62; MSP43012xx devices only, only for MSP43012xx devices. 63 64IE2 equ 001h 65UTXIE0 equ 2 ; USART0 Transmit Int-Enable Bit (IE2.2) 66URXIE0 equ 1 ; USART0 Receive Int-Enable Bit (IE2.1) 67 68IFG2 equ 003h 69UTXIFG0 equ 2 ; USART0 and SPI Transmit Flag (IFG2.1) 70URXIFG0 equ 1 ; USART0 and SPI Receive Flag (IFG2.0) 71 72ME2 equ 005h 73UTXE0 equ 2 ; USART0 Transmit Enable Bit (ME2.1) 74URXE0 equ 1 ; USART0 Receive Enable Bit (ME2.0) 75USPIE0 equ 1 ; SPI Transmit+Receive Enable (ME2.0) 76 77;---------------------------------------------------------------------------- 78; Digital I/O, Byte Access 79 80P0IN equ 010h ; Read Register (Pin State) 81P0OUT equ 011h ; Write Register (Latches) 82P0DIR equ 012h ; Direction Register 83P0IFG equ 013h ; Interrupt Flags 84P0IES equ 014h ; Interrupt Edge Selection 85P0IE equ 015h ; Interrupt Enables 86 87P3IN equ 018h ; Input Register 88P3OUT equ 019h ; Output Register 89P3DIR equ 01Ah ; Direction Register 90P3SEL equ 01Bh ; Function Select 91 92P4IN equ 01Ch ; Input Register 93P4OUT equ 01Dh ; Output Register 94P4DIR equ 01Eh ; Direction Register 95P4SEL equ 01Fh ; Function Select 96 97P1IN equ 020h ; Input Register 98P1OUT equ 021h ; Output Register 99P1DIR equ 022h ; Direction Register 100P1IFG equ 023h ; Interrupt Flags 101P1IES equ 024h ; Interrupt Edge Select 102P1IE equ 025h ; Interrupt Enable 103P1SEL equ 026h ; Function Select 104 105P2IN equ 028h ; Input Register 106P2OUT equ 029h ; Output Register 107P2DIR equ 02Ah ; Direction Register 108P2IFG equ 02Bh ; Interrupt Flags 109P2IES equ 02Ch ; Interrupt Edge Select 110P2IE equ 02Dh ; Interrupt Enable 111P2SEL equ 02Eh ; Function Select 112 113P5IN equ 030h ; Input Register 114P5OUT equ 031h ; Output Register 115P5DIR equ 032h ; Direction Register 116P5SEL equ 033h ; Function Select 117 118P6IN equ 034h ; Input Register 119P6OUT equ 035h ; Output Register 120P6DIR equ 036h ; Direction Register 121P6SEL equ 037h ; Function Select 122 123;---------------------------------------------------------------------------- 124; LCD-Interface 125 126LCDCTL equ 030h ; Control 127LCD_Start equ 031h ; Start Address 128LCD_Stop equ 03fh ; End Address 129__TMP set 1 ; Individual Definitions 130 rept 9 131LCD{"\{__TMP}"} equ 030h+__TMP 132__TMP set __TMP+1 133 endm 134 rept 6 135LCD1{"\{__TMP-10}"} equ 030h+__TMP 136__TMP set __TMP+1 137 endm 138 139;---------------------------------------------------------------------------- 140; Timer 141 142BTCTL equ 040h ; Timer 1 Basic Control Register 143 144TCCTL equ 042h 145TCPLD equ 043h ; Preaload Value 146TCDAT equ 044h ; Count Value 147 148BTCNT1 equ 046h ; Count Register 149BTCNT2 equ 047h 150 151TPCTL equ 04Bh ; Timer/Port Control Register 152TPCNT1 equ 04Ch ; Count Register 153TPCNT2 equ 04Dh 154TPD equ 04Eh ; Data Register 155TPE equ 04Fh ; Enable Register 156 157;---------------------------------------------------------------------------- 158; Clock Generator 159 160SCFI0 equ 050h ; Integrator 161SCFI1 equ 051h 162SCFQCTL equ 052h ; Crystal Frequency Multiplicator 163CBCTL equ 053h ; Buffer Control 164 165;---------------------------------------------------------------------------- 166; EPROM Control Registers, Byte Access 167 168EPCTL equ 054h ; EPROM Control 169 170;---------------------------------------------------------------------------- 171; Basic Clock Registers, Byte Access 172 173DCOCTL equ 056h 174DCO2 equ 128 ; DCO Freq Select, see RSELx (DCOCTL.7) 175DCO1 equ 64 ; (DCOCTL.6) 176DCO0 equ 32 ; (DCOCTL.5) 177MOD4 equ 16 ; Modulator Selection (DCOCTL.4) 178MOD3 equ 8 ; (DCOCTL.3) 179MOD2 equ 4 ; (DCOCTL.2) 180MOD1 equ 2 ; (DCOCTL.1) 181MOD0 equ 1 ; (DCOCTL.0) 182 183BCSCTL1 equ 057h 184XT2OFF equ 128 ; XT2 Off. Turn Off XT2 Oscil (BCSCTL1.7) 185XTS equ 64 ; LFXT1 Mode. 0=LowFreq,1=HiFreq (BCSCTL1.6) 186DIVA1 equ 32 ; Divider for ACLK. (BCSCTL1.5) 187DIVA0 equ 16 ; 00=/1, 01=/2, 10=/4, 11=/8 (BCSCTL1.4) 188XT5V equ 8 ; Unused. Always Reset to Zero (BCSCTL1.3) 189RSEL2 equ 4 ; Resistor Select. Internal R (BCSCTL1.2) 190RSEL1 equ 2 ; Lowest R=0 (BCSCTL1.1) 191RSEL0 equ 1 ; (BCSCTL1.0) 192RSEL_7 equ 7 ; (BCSCTL1.0-2) 193RSEL_6 equ 6 ; (BCSCTL1.0-2) 194RSEL_5 equ 5 ; (BCSCTL1.0-2) 195RSEL_4 equ 4 ; (BCSCTL1.0-2) 196RSEL_3 equ 3 ; (BCSCTL1.0-2) 197RSEL_2 equ 2 ; (BCSCTL1.0-2) 198RSEL_1 equ 1 ; (BCSCTL1.0-2) 199RSEL_0 equ 0 ; (BCSCTL1.0-2) 200 201BCSCTL2 equ 058h 202SELM_3 equ 128+64 ; Select MCLK. 11=LFXT1CLK (BCSCTL2.6.7) 203SELM_2 equ 128 ; MCLK 10=XT2CLK or LFXT1CLK (BCSCTL2.6.7) 204SELM_1 equ 64 ; Select MCLK. 01=DCOCLK (BCSCTL2.6.7) 205SELM_0 equ 0 ; Select MCLK. 00=DCOCLK (BCSCTL2.6.7) 206SELM1 equ 128 ; Select MCLK. 00=01=DCOCLK (BCSCTL2.7) 207SELM0 equ 64 ; 10=XT2CLK or LFXT1CLK=11 (BCSCTL2.6) 208DIVM1 equ 32 ; Divider for MCLK, (BCSCTL2.5) 209DIVM0 equ 16 ; 00=/1, 01=/2, 10=/4, 11=/8 (BCSCTL2.4) 210SELS equ 8 ; Select SMCLK 0=DCOCLK,1=XT2CLK (BCSCTL2.3) 211DIVS1 equ 4 ; Divider for SMCLK, (BCSCTL2.2) 212DIVS0 equ 2 ; 00=/1, 01=/2, 10=/4, 11=/8 (BCSCTL2.1) 213DCOR equ 1 ; DCO Resistor. 0=Intern,1=1xtn (BCSCTL2.0) 214 215;---------------------------------------------------------------------------- 216; Comparator_A Registers, Byte Access 217 218CACTL1 equ 059h ; Comparator A Control Register 1 219CACTL2 equ 05Ah ; Comparator A Control Register 2 220CAPD equ 05Bh ; Comparator A Port Disable 221 222;---------------------------------------------------------------------------- 223; PWM 224 225PWMCTL equ 058h ; Count Value 226PWMDTB equ 059h ; Pulse Width (Buffer) 227PWMDTR equ 05Ah ; Pulse Width 228PWMCNT equ 05Bh ; Control 229 230;---------------------------------------------------------------------------- 231; USART 0 232 233U0CTL equ 070h 234U0TCTL equ 071h 235U0RCTL equ 072h 236U0MCTL equ 073h 237U0BR0 equ 074h 238U0BR1 equ 075h 239U0RXBUF equ 076h 240U0TXBUF equ 077h 241 242;---------------------------------------------------------------------------- 243; USART 1 244 245U1CTL equ 078h 246U1TCTL equ 079h 247U1RCTL equ 07Ah 248U1MCTL equ 07Bh 249U1BR0 equ 07Ch 250U1BR1 equ 07Dh 251U1RXBUF equ 07Eh 252U1TXBUF equ 07Fh 253 254;---------------------------------------------------------------------------- 255; USART Register Bits 256 257FE equ 128 ; Framing Error (low stop bit) (UxRCTL.7) 258PE equ 64 ; Parity Error (PE=0 if PENA=0) (UxRCTL.6) 259OE equ 32 ; Overrun Error (Buffer Overrun) (UxRCTL.5) 260BRK equ 16 ; Break Detect Flag (UxRCTL.4) 261URXEIE equ 8 ; Rec Err Chars Sets URXIFG) (UxRCTL.3) 262URXWIE equ 4 ; Rec Wakeup Int Enable (URXIFG) (UxRCTL.2) 263RXWAKE equ 2 ; Rec Wakeup Flag (UxRCTL.1) 264RXERR equ 1 ; Rec Error Flag (FE,PE,OE,BRK) (UxRCTL.0) 265 266CKPL equ 64 ; Clock Polarity 0=UCLKI=UCLK (UxTCTL.6) 267SSEL1 equ 32 ; Source 00=UCLKI, 01=ACLK (UxTCTL.5) 268SSEL0 equ 16 ; Source 10=SMCLKI, 11=SMCLK (UxTCTL.4) 269URXSE equ 8 ; Receive Start-Edge, 1=Enabled (UxTCTL.3) 270TXWAKE equ 4 ; Transmitter Wake, 0=Data,1=Adr (UxTCTL.2) 271TXEPT equ 1 ; Transmitter Empty Flag (UxTCTL.0) 272 273PENA equ 128 ; Parity Enable, 1=Enabled (UxCTL.7) 274PEV equ 64 ; Parity Select, 1=Even,0=Odd (UxCTL.6) 275SPB equ 32 ; Stop Bit, 0=1Stop,1=2Stop (UxCTL.5) 276CHAR equ 16 ; Char Length, 0=7Bit,1=8Bit (UxCTL.4) 277LISTEN equ 8 ; Listen Enable, 1=Loopback->RX (UxCTL.3) 278SYNC equ 4 ; Synch Mode, 0=USART,1=SPI (UxCTL.2) 279MM equ 2 ; Multiprocessor, 1=Use_Protocol (UxCTL.1) 280SWRST equ 1 ; Software Reset, 1=Held_Reset (UxCTL.0) 281 282;---------------------------------------------------------------------------- 283; ADC12 Low Bytes 284 285ADC12MCTL0 equ 080h 286ADC12MCTL1 equ 081h 287ADC12MCTL2 equ 082h 288ADC12MCTL3 equ 083h 289ADC12MCTL4 equ 084h 290ADC12MCTL5 equ 085h 291ADC12MCTL6 equ 086h 292ADC12MCTL7 equ 087h 293ADC12MCTL8 equ 088h 294ADC12MCTL9 equ 089h 295ADC12MCTL10 equ 08Ah 296ADC12MCTL11 equ 08Bh 297ADC12MCTL12 equ 08Ch 298ADC12MCTL13 equ 08Dh 299ADC12MCTL14 equ 08Eh 300ADC12MCTL15 equ 08Fh 301 302;---------------------------------------------------------------------------- 303; LCD Registers 304 305LCDC equ 090h 306__TMP set 1 ; Individual Definitions 307 rept 19 308LCDmemory{"\{__TMP}"} equ LCDC+__TMP 309__TMP set __TMP+1 310 endm 311 312;---------------------------------------------------------------------------- 313; A/D-Wandler, Word Access 314 315AIN equ 0110h ; Input Register 316AEN equ 0112h ; Input Enables 317ACTL equ 0114h ; Control 318ADAT equ 0118h ; Data 319 320;---------------------------------------------------------------------------- 321; Timer_B Interrupt Vector, Word Access 322 323TBIV equ 011Eh 324 325;---------------------------------------------------------------------------- 326; Watchdog/Timer, Word Access 327 328WDTCTL equ 0120h 329WDTHOLD equ 128 ; Watchdog Timer Hold. 1=Stopped (WDTCTL.6) 330WDTNMIES equ 64 ; NMI Edge Select 0=Rise,1=Fall (WDTCTL.6) 331WDTNMI equ 32 ; NMI Pin Select, 0=!Reset,1=NMI (WDTCTL.5) 332WDTTMSEL equ 16 ; Mode Select 0=Watchdog,1=Timer (WDTCTL.4) 333WDTCNTCL equ 8 ; Counter Clear, 1=Clear_Counter (WDTCTL.3) 334WDTSSEL equ 4 ; Source Select, 0=SMCLK,1=ACLK (WDTCTL.2) 335WDTIS1 equ 2 ; Watchdog Timer Interval Select (WDTCTL.1) 336WDTIS0 equ 1 ; 00=32768,01=8192,10=512,11=64 (WDTCTL.0) 337 338;---------------------------------------------------------------------------- 339; Timer_A Interrupt Vector, Word Access 340 341TAIV equ 012Eh 342 343;---------------------------------------------------------------------------- 344; Flash Control, Word Access 345 346FCTL1 equ 0128h 347FCTL2 equ 012Ah 348FCTL3 equ 012Ch 349 350;---------------------------------------------------------------------------- 351; Hardware Multiplier, Word Access 352 353MPY equ 0130h ; Multiply Unsigned 354MPYS equ 0132h ; Multiply Signed 355MAC equ 0134h ; MPY+ACC 356MACS equ 0136h ; MPYS+ACC 357OP2 equ 0138h ; Second Operand 358ResLo equ 013Ah ; Result Low Word 359ResHi equ 013Ch ; Result High Word 360SumExt equ 013Eh ; Sum Extend 361 362;---------------------------------------------------------------------------- 363; ADC12 High Bytes, Word Access 364 365ADC12MEM0 equ 0140h 366ADC12MEM1 equ 0142h 367ADC12MEM2 equ 0144h 368ADC12MEM3 equ 0146h 369ADC12MEM4 equ 0148h 370ADC12MEM5 equ 014Ah 371ADC12MEM6 equ 014Ch 372ADC12MEM7 equ 014Eh 373ADC12MEM8 equ 0150h 374ADC12MEM9 equ 0152h 375ADC12MEM10 equ 0154h 376ADC12MEM11 equ 0156h 377ADC12MEM12 equ 0158h 378ADC12MEM13 equ 015Ah 379ADC12MEM14 equ 015Ch 380ADC12MEM15 equ 015Eh 381 382;---------------------------------------------------------------------------- 383; Timer_A Registers, Word Access 384 385TACTL equ 0160h 386CCTL0 equ 0162h 387CCTL1 equ 0164h 388CCTL2 equ 0166h 389CCTL3 equ 0168h 390CCTL4 equ 016Ah 391TAR equ 0170h 392CCR0 equ 0172h 393CCR1 equ 0174h 394CCR2 equ 0176h 395CCR3 equ 0178h 396CCR4 equ 017Ah 397 398;---------------------------------------------------------------------------- 399; Timer_B Registers, Word Access 400 401TBCTL equ 0180h 402TBCCTL0 equ 0182h 403TBCCTL1 equ 0184h 404TBCCTL2 equ 0186h 405TBCCTL3 equ 0188h 406TBCCTL4 equ 018Ah 407TBCCTL5 equ 018Ch 408TBCCTL6 equ 018Eh 409TBR equ 0190h 410TBCCR0 equ 0192h 411TBCCR1 equ 0194h 412TBCCR2 equ 0196h 413TBCCR3 equ 0198h 414TBCCR4 equ 019Ah 415TBCCR5 equ 019Ch 416TBCCR6 equ 019Eh 417 418;---------------------------------------------------------------------------- 419; ADC12 Registers, Byte and Word Access 420 421ADC12CTL0 equ 01A0h 422ADC12CTL1 equ 01A2h 423ADC12FG equ 01A4h 424ADC12IE equ 01A6h 425 426;---------------------------------------------------------------------------- 427 428 restore ; wieder erlauben 429 430 endif ; regmspinc 431