1 /* CPU data for mep.
2 
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
5 Copyright 1996-2010 Free Software Foundation, Inc.
6 
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
9    This file is free software; you can redistribute it and/or modify
10    it under the terms of the GNU General Public License as published by
11    the Free Software Foundation; either version 3, or (at your option)
12    any later version.
13 
14    It is distributed in the hope that it will be useful, but WITHOUT
15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17    License for more details.
18 
19    You should have received a copy of the GNU General Public License along
20    with this program; if not, write to the Free Software Foundation, Inc.,
21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22 
23 */
24 
25 #include "sysdep.h"
26 #include <stdio.h>
27 #include <stdarg.h>
28 #include "ansidecl.h"
29 #include "bfd.h"
30 #include "symcat.h"
31 #include "mep-desc.h"
32 #include "mep-opc.h"
33 #include "opintl.h"
34 #include "libiberty.h"
35 #include "xregex.h"
36 
37 /* Attributes.  */
38 
39 static const CGEN_ATTR_ENTRY bool_attr[] =
40 {
41   { "#f", 0 },
42   { "#t", 1 },
43   { 0, 0 }
44 };
45 
46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47 {
48   { "base", MACH_BASE },
49   { "mep", MACH_MEP },
50   { "h1", MACH_H1 },
51   { "c5", MACH_C5 },
52   { "max", MACH_MAX },
53   { 0, 0 }
54 };
55 
56 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
57 {
58   { "mep", ISA_MEP },
59   { "ext_core1", ISA_EXT_CORE1 },
60   { "ext_cop1_16", ISA_EXT_COP1_16 },
61   { "ext_cop1_32", ISA_EXT_COP1_32 },
62   { "ext_cop1_48", ISA_EXT_COP1_48 },
63   { "ext_cop1_64", ISA_EXT_COP1_64 },
64   { "max", ISA_MAX },
65   { 0, 0 }
66 };
67 
68 static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED =
69 {
70   { "LABEL", CDATA_LABEL },
71   { "REGNUM", CDATA_REGNUM },
72   { "FMAX_FLOAT", CDATA_FMAX_FLOAT },
73   { "FMAX_INT", CDATA_FMAX_INT },
74   { "POINTER", CDATA_POINTER },
75   { "LONG", CDATA_LONG },
76   { "ULONG", CDATA_ULONG },
77   { "SHORT", CDATA_SHORT },
78   { "USHORT", CDATA_USHORT },
79   { "CHAR", CDATA_CHAR },
80   { "UCHAR", CDATA_UCHAR },
81   { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT },
82   { 0, 0 }
83 };
84 
85 static const CGEN_ATTR_ENTRY CPTYPE_attr[] ATTRIBUTE_UNUSED =
86 {
87   { "CP_DATA_BUS_INT", CPTYPE_CP_DATA_BUS_INT },
88   { "VECT", CPTYPE_VECT },
89   { "V2SI", CPTYPE_V2SI },
90   { "V4HI", CPTYPE_V4HI },
91   { "V8QI", CPTYPE_V8QI },
92   { "V2USI", CPTYPE_V2USI },
93   { "V4UHI", CPTYPE_V4UHI },
94   { "V8UQI", CPTYPE_V8UQI },
95   { 0, 0 }
96 };
97 
98 static const CGEN_ATTR_ENTRY CRET_attr[] ATTRIBUTE_UNUSED =
99 {
100   { "VOID", CRET_VOID },
101   { "FIRST", CRET_FIRST },
102   { "FIRSTCOPY", CRET_FIRSTCOPY },
103   { 0, 0 }
104 };
105 
106 static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
107 {
108   {"integer", 1},
109   { 0, 0 }
110 };
111 
112 static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
113 {
114   {"integer", 0},
115   { 0, 0 }
116 };
117 
118 static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED =
119 {
120   { "NONE", CONFIG_NONE },
121   { "default", CONFIG_DEFAULT },
122   { 0, 0 }
123 };
124 
125 static const CGEN_ATTR_ENTRY SLOTS_attr[] ATTRIBUTE_UNUSED =
126 {
127   { "CORE", SLOTS_CORE },
128   { "C3", SLOTS_C3 },
129   { "P0S", SLOTS_P0S },
130   { "P0", SLOTS_P0 },
131   { "P1", SLOTS_P1 },
132   { 0, 0 }
133 };
134 
135 const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] =
136 {
137   { "MACH", & MACH_attr[0], & MACH_attr[0] },
138   { "ISA", & ISA_attr[0], & ISA_attr[0] },
139   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
140   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
141   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
142   { "RESERVED", &bool_attr[0], &bool_attr[0] },
143   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
144   { "SIGNED", &bool_attr[0], &bool_attr[0] },
145   { 0, 0, 0 }
146 };
147 
148 const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] =
149 {
150   { "MACH", & MACH_attr[0], & MACH_attr[0] },
151   { "ISA", & ISA_attr[0], & ISA_attr[0] },
152   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
153   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
154   { "PC", &bool_attr[0], &bool_attr[0] },
155   { "PROFILE", &bool_attr[0], &bool_attr[0] },
156   { "IS_FLOAT", &bool_attr[0], &bool_attr[0] },
157   { 0, 0, 0 }
158 };
159 
160 const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] =
161 {
162   { "MACH", & MACH_attr[0], & MACH_attr[0] },
163   { "ISA", & ISA_attr[0], & ISA_attr[0] },
164   { "CDATA", & CDATA_attr[0], & CDATA_attr[0] },
165   { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] },
166   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
167   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
168   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
169   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
170   { "SIGNED", &bool_attr[0], &bool_attr[0] },
171   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
172   { "RELAX", &bool_attr[0], &bool_attr[0] },
173   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
174   { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] },
175   { 0, 0, 0 }
176 };
177 
178 const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] =
179 {
180   { "MACH", & MACH_attr[0], & MACH_attr[0] },
181   { "ISA", & ISA_attr[0], & ISA_attr[0] },
182   { "CPTYPE", & CPTYPE_attr[0], & CPTYPE_attr[0] },
183   { "CRET", & CRET_attr[0], & CRET_attr[0] },
184   { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
185   { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
186   { "SLOTS", & SLOTS_attr[0], & SLOTS_attr[0] },
187   { "ALIAS", &bool_attr[0], &bool_attr[0] },
188   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
189   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
190   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
191   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
192   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
193   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
194   { "RELAXED", &bool_attr[0], &bool_attr[0] },
195   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
196   { "PBB", &bool_attr[0], &bool_attr[0] },
197   { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] },
198   { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] },
199   { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] },
200   { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] },
201   { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] },
202   { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] },
203   { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] },
204   { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] },
205   { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] },
206   { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] },
207   { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] },
208   { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] },
209   { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] },
210   { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] },
211   { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] },
212   { "MAY_TRAP", &bool_attr[0], &bool_attr[0] },
213   { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] },
214   { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] },
215   { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] },
216   { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
217   { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
218   { "VOLATILE", &bool_attr[0], &bool_attr[0] },
219   { 0, 0, 0 }
220 };
221 
222 /* Instruction set variants.  */
223 
224 static const CGEN_ISA mep_cgen_isa_table[] = {
225   { "mep", 32, 32, 16, 32 },
226   { "ext_core1", 32, 32, 16, 32 },
227   { "ext_cop1_16", 32, 32, 32, 32 },
228   { "ext_cop1_32", 32, 32, 32, 32 },
229   { "ext_cop1_48", 32, 32, 32, 32 },
230   { "ext_cop1_64", 32, 32, 32, 32 },
231   { 0, 0, 0, 0, 0 }
232 };
233 
234 /* Machine variants.  */
235 
236 static const CGEN_MACH mep_cgen_mach_table[] = {
237   { "mep", "mep", MACH_MEP, 16 },
238   { "h1", "h1", MACH_H1, 16 },
239   { "c5", "c5", MACH_C5, 16 },
240   { 0, 0, 0, 0 }
241 };
242 
243 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] =
244 {
245   { "$0", 0, {0, {{{0, 0}}}}, 0, 0 },
246   { "$1", 1, {0, {{{0, 0}}}}, 0, 0 },
247   { "$2", 2, {0, {{{0, 0}}}}, 0, 0 },
248   { "$3", 3, {0, {{{0, 0}}}}, 0, 0 },
249   { "$4", 4, {0, {{{0, 0}}}}, 0, 0 },
250   { "$5", 5, {0, {{{0, 0}}}}, 0, 0 },
251   { "$6", 6, {0, {{{0, 0}}}}, 0, 0 },
252   { "$7", 7, {0, {{{0, 0}}}}, 0, 0 },
253   { "$8", 8, {0, {{{0, 0}}}}, 0, 0 },
254   { "$9", 9, {0, {{{0, 0}}}}, 0, 0 },
255   { "$10", 10, {0, {{{0, 0}}}}, 0, 0 },
256   { "$11", 11, {0, {{{0, 0}}}}, 0, 0 },
257   { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 },
258   { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 },
259   { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 },
260   { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 },
261   { "$12", 12, {0, {{{0, 0}}}}, 0, 0 },
262   { "$13", 13, {0, {{{0, 0}}}}, 0, 0 },
263   { "$14", 14, {0, {{{0, 0}}}}, 0, 0 },
264   { "$15", 15, {0, {{{0, 0}}}}, 0, 0 }
265 };
266 
267 CGEN_KEYWORD mep_cgen_opval_h_gpr =
268 {
269   & mep_cgen_opval_h_gpr_entries[0],
270   20,
271   0, 0, 0, 0, ""
272 };
273 
274 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] =
275 {
276   { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 },
277   { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 },
278   { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 },
279   { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 },
280   { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 },
281   { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 },
282   { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 },
283   { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 },
284   { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 },
285   { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 },
286   { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 },
287   { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 },
288   { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 },
289   { "$id", 17, {0, {{{0, 0}}}}, 0, 0 },
290   { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 },
291   { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 },
292   { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 },
293   { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 },
294   { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 },
295   { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 },
296   { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 },
297   { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 },
298   { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 },
299   { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 },
300   { "$vid", 22, {0, {{{0, 0}}}}, 0, 0 }
301 };
302 
303 CGEN_KEYWORD mep_cgen_opval_h_csr =
304 {
305   & mep_cgen_opval_h_csr_entries[0],
306   25,
307   0, 0, 0, 0, ""
308 };
309 
310 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] =
311 {
312   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
313   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
314   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
315   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
316   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
317   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
318   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
319   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
320   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
321   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
322   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
323   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
324   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
325   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
326   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
327   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
328   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
329   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
330   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
331   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
332   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
333   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
334   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
335   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
336   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
337   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
338   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
339   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
340   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
341   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
342   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
343   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
344 };
345 
346 CGEN_KEYWORD mep_cgen_opval_h_cr64 =
347 {
348   & mep_cgen_opval_h_cr64_entries[0],
349   32,
350   0, 0, 0, 0, ""
351 };
352 
353 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] =
354 {
355   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
356   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
357   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
358   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
359   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
360   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
361   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
362   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
363   { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
364   { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
365   { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
366   { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
367   { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
368   { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
369   { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
370   { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
371   { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
372   { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
373   { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
374   { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
375   { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
376   { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
377   { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
378   { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
379   { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
380   { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
381   { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
382   { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
383   { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
384   { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
385   { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
386   { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
387 };
388 
389 CGEN_KEYWORD mep_cgen_opval_h_cr =
390 {
391   & mep_cgen_opval_h_cr_entries[0],
392   32,
393   0, 0, 0, 0, ""
394 };
395 
396 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] =
397 {
398   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
399   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
400   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
401   { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
402   { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
403   { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
404   { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
405   { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
406   { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
407   { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
408   { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
409   { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
410   { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
411   { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
412   { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
413   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
414   { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
415   { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
416   { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
417   { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
418   { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
419   { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
420   { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
421   { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
422   { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
423   { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
424   { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
425   { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
426   { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
427   { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
428   { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
429   { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 },
430   { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 },
431   { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 },
432   { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 },
433   { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 },
434   { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 },
435   { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 },
436   { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 },
437   { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 },
438   { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 },
439   { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 },
440   { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 },
441   { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 },
442   { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 },
443   { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 },
444   { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 },
445   { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 },
446   { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 },
447   { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 },
448   { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 },
449   { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 },
450   { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 },
451   { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 },
452   { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 },
453   { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 },
454   { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 },
455   { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 },
456   { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 },
457   { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 },
458   { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 },
459   { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 },
460   { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 },
461   { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 }
462 };
463 
464 CGEN_KEYWORD mep_cgen_opval_h_ccr =
465 {
466   & mep_cgen_opval_h_ccr_entries[0],
467   64,
468   0, 0, 0, 0, ""
469 };
470 
471 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_ivc2_entries[] =
472 {
473   { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
474   { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
475   { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
476   { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
477   { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
478   { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
479   { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
480   { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }
481 };
482 
483 CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2 =
484 {
485   & mep_cgen_opval_h_cr_ivc2_entries[0],
486   8,
487   0, 0, 0, 0, ""
488 };
489 
490 static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_ivc2_entries[] =
491 {
492   { "$csar0", 0, {0, {{{0, 0}}}}, 0, 0 },
493   { "$cc", 1, {0, {{{0, 0}}}}, 0, 0 },
494   { "$cofr0", 4, {0, {{{0, 0}}}}, 0, 0 },
495   { "$cofr1", 5, {0, {{{0, 0}}}}, 0, 0 },
496   { "$cofa0", 6, {0, {{{0, 0}}}}, 0, 0 },
497   { "$cofa1", 7, {0, {{{0, 0}}}}, 0, 0 },
498   { "$csar1", 15, {0, {{{0, 0}}}}, 0, 0 },
499   { "$acc0_0", 16, {0, {{{0, 0}}}}, 0, 0 },
500   { "$acc0_1", 17, {0, {{{0, 0}}}}, 0, 0 },
501   { "$acc0_2", 18, {0, {{{0, 0}}}}, 0, 0 },
502   { "$acc0_3", 19, {0, {{{0, 0}}}}, 0, 0 },
503   { "$acc0_4", 20, {0, {{{0, 0}}}}, 0, 0 },
504   { "$acc0_5", 21, {0, {{{0, 0}}}}, 0, 0 },
505   { "$acc0_6", 22, {0, {{{0, 0}}}}, 0, 0 },
506   { "$acc0_7", 23, {0, {{{0, 0}}}}, 0, 0 },
507   { "$acc1_0", 24, {0, {{{0, 0}}}}, 0, 0 },
508   { "$acc1_1", 25, {0, {{{0, 0}}}}, 0, 0 },
509   { "$acc1_2", 26, {0, {{{0, 0}}}}, 0, 0 },
510   { "$acc1_3", 27, {0, {{{0, 0}}}}, 0, 0 },
511   { "$acc1_4", 28, {0, {{{0, 0}}}}, 0, 0 },
512   { "$acc1_5", 29, {0, {{{0, 0}}}}, 0, 0 },
513   { "$acc1_6", 30, {0, {{{0, 0}}}}, 0, 0 },
514   { "$acc1_7", 31, {0, {{{0, 0}}}}, 0, 0 },
515   { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
516   { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
517   { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
518   { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
519   { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
520   { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
521   { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
522   { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
523   { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
524   { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
525   { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
526   { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
527   { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
528   { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
529   { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
530   { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
531   { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
532   { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
533   { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
534   { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
535   { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
536   { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
537   { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
538   { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
539   { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
540   { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
541   { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
542   { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
543   { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
544   { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
545   { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
546   { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 }
547 };
548 
549 CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2 =
550 {
551   & mep_cgen_opval_h_ccr_ivc2_entries[0],
552   55,
553   0, 0, 0, 0, ""
554 };
555 
556 
557 /* The hardware table.  */
558 
559 #define A(a) (1 << CGEN_HW_##a)
560 
561 const CGEN_HW_ENTRY mep_cgen_hw_table[] =
562 {
563   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
564   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
565   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
566   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
567   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
568   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
569   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
570   { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
571   { "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
572   { "h-cr64-w", HW_H_CR64_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
573   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
574   { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
575   { "h-ccr-w", HW_H_CCR_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
576   { "h-cr-ivc2", HW_H_CR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
577   { "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
578   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
579 };
580 
581 #undef A
582 
583 
584 /* The instruction field table.  */
585 
586 #define A(a) (1 << CGEN_IFLD_##a)
587 
588 const CGEN_IFLD mep_cgen_ifld_table[] =
589 {
590   { MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
591   { MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
592   { MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
593   { MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
594   { MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
595   { MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
596   { MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
597   { MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
598   { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
599   { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
600   { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
601   { MEP_F_EXT4, "f-ext4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
602   { MEP_F_EXT62, "f-ext62", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
603   { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
604   { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
605   { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
606   { MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
607   { MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
608   { MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
609   { MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
610   { MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
611   { MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
612   { MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
613   { MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
614   { MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
615   { MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
616   { MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
617   { MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
618   { MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
619   { MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
620   { MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
621   { MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
622   { MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
623   { MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
624   { MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
625   { MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
626   { MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
627   { MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
628   { MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
629   { MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
630   { MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
631   { MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
632   { MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
633   { MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
634   { MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
635   { MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
636   { MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
637   { MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
638   { MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
639   { MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
640   { MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
641   { MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
642   { MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
643   { MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
644   { MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
645   { MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
646   { MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
647   { MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
648   { MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
649   { MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
650   { MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
651   { MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
652   { MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
653   { MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
654   { MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
655   { MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
656   { MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
657   { MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
658   { MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
659   { MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
660   { MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
661   { MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
662   { MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
663   { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
664   { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
665   { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
666   { MEP_F_CDISP10, "f-cdisp10", 0, 32, 22, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
667   { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
668   { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
669   { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
670   { MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
671   { MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
672   { MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
673   { MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
674   { MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
675   { MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
676   { MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
677   { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
678   { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
679   { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
680   { MEP_F_C5N4, "f-c5n4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
681   { MEP_F_C5N5, "f-c5n5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
682   { MEP_F_C5N6, "f-c5n6", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
683   { MEP_F_C5N7, "f-c5n7", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
684   { MEP_F_RL5, "f-rl5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
685   { MEP_F_12S20, "f-12s20", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } }  },
686   { MEP_F_C5_RNM, "f-c5-rnm", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
687   { MEP_F_C5_RM, "f-c5-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
688   { MEP_F_C5_16U16, "f-c5-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
689   { MEP_F_C5_RMUIMM20, "f-c5-rmuimm20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
690   { MEP_F_C5_RNMUIMM24, "f-c5-rnmuimm24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
691   { MEP_F_IVC2_2U4, "f-ivc2-2u4", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
692   { MEP_F_IVC2_3U4, "f-ivc2-3u4", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
693   { MEP_F_IVC2_8U4, "f-ivc2-8u4", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
694   { MEP_F_IVC2_8S4, "f-ivc2-8s4", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
695   { MEP_F_IVC2_1U6, "f-ivc2-1u6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
696   { MEP_F_IVC2_2U6, "f-ivc2-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
697   { MEP_F_IVC2_3U6, "f-ivc2-3u6", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
698   { MEP_F_IVC2_6U6, "f-ivc2-6u6", 0, 32, 6, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
699   { MEP_F_IVC2_5U7, "f-ivc2-5u7", 0, 32, 7, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
700   { MEP_F_IVC2_4U8, "f-ivc2-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
701   { MEP_F_IVC2_3U9, "f-ivc2-3u9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
702   { MEP_F_IVC2_5U16, "f-ivc2-5u16", 0, 32, 16, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
703   { MEP_F_IVC2_5U21, "f-ivc2-5u21", 0, 32, 21, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
704   { MEP_F_IVC2_5U26, "f-ivc2-5u26", 0, 32, 26, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
705   { MEP_F_IVC2_1U31, "f-ivc2-1u31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
706   { MEP_F_IVC2_4U16, "f-ivc2-4u16", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
707   { MEP_F_IVC2_4U20, "f-ivc2-4u20", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
708   { MEP_F_IVC2_4U24, "f-ivc2-4u24", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
709   { MEP_F_IVC2_4U28, "f-ivc2-4u28", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
710   { MEP_F_IVC2_2U0, "f-ivc2-2u0", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
711   { MEP_F_IVC2_3U0, "f-ivc2-3u0", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
712   { MEP_F_IVC2_4U0, "f-ivc2-4u0", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
713   { MEP_F_IVC2_5U0, "f-ivc2-5u0", 0, 32, 0, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
714   { MEP_F_IVC2_8U0, "f-ivc2-8u0", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
715   { MEP_F_IVC2_8S0, "f-ivc2-8s0", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
716   { MEP_F_IVC2_6U2, "f-ivc2-6u2", 0, 32, 2, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
717   { MEP_F_IVC2_5U3, "f-ivc2-5u3", 0, 32, 3, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
718   { MEP_F_IVC2_4U4, "f-ivc2-4u4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
719   { MEP_F_IVC2_3U5, "f-ivc2-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
720   { MEP_F_IVC2_5U8, "f-ivc2-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
721   { MEP_F_IVC2_4U10, "f-ivc2-4u10", 0, 32, 10, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
722   { MEP_F_IVC2_3U12, "f-ivc2-3u12", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
723   { MEP_F_IVC2_5U13, "f-ivc2-5u13", 0, 32, 13, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
724   { MEP_F_IVC2_2U18, "f-ivc2-2u18", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
725   { MEP_F_IVC2_5U18, "f-ivc2-5u18", 0, 32, 18, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
726   { MEP_F_IVC2_8U20, "f-ivc2-8u20", 0, 32, 20, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
727   { MEP_F_IVC2_8S20, "f-ivc2-8s20", 0, 32, 20, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
728   { MEP_F_IVC2_5U23, "f-ivc2-5u23", 0, 32, 23, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
729   { MEP_F_IVC2_2U23, "f-ivc2-2u23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
730   { MEP_F_IVC2_3U25, "f-ivc2-3u25", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
731   { MEP_F_IVC2_IMM16P0, "f-ivc2-imm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
732   { MEP_F_IVC2_SIMM16P0, "f-ivc2-simm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
733   { MEP_F_IVC2_CCRN_C3HI, "f-ivc2-ccrn-c3hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
734   { MEP_F_IVC2_CCRN_C3LO, "f-ivc2-ccrn-c3lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
735   { MEP_F_IVC2_CRN, "f-ivc2-crn", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
736   { MEP_F_IVC2_CRM, "f-ivc2-crm", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
737   { MEP_F_IVC2_CCRN_H1, "f-ivc2-ccrn-h1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
738   { MEP_F_IVC2_CCRN_H2, "f-ivc2-ccrn-h2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
739   { MEP_F_IVC2_CCRN_LO, "f-ivc2-ccrn-lo", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
740   { MEP_F_IVC2_CMOV1, "f-ivc2-cmov1", 0, 32, 8, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
741   { MEP_F_IVC2_CMOV2, "f-ivc2-cmov2", 0, 32, 22, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
742   { MEP_F_IVC2_CMOV3, "f-ivc2-cmov3", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
743   { MEP_F_IVC2_CCRN_C3, "f-ivc2-ccrn-c3", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
744   { MEP_F_IVC2_CCRN, "f-ivc2-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
745   { MEP_F_IVC2_CRNX, "f-ivc2-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } }  },
746   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
747 };
748 
749 #undef A
750 
751 
752 
753 /* multi ifield declarations */
754 
755 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [];
756 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [];
757 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [];
758 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [];
759 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [];
760 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
761 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
762 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
763 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
764 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [];
765 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [];
766 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [];
767 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [];
768 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [];
769 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [];
770 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [];
771 
772 
773 /* multi ifield definitions */
774 
775 const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
776 {
777     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
778     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
779     { 0, { (const PTR) 0 } }
780 };
781 const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
782 {
783     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
784     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
785     { 0, { (const PTR) 0 } }
786 };
787 const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
788 {
789     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
790     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
791     { 0, { (const PTR) 0 } }
792 };
793 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
794 {
795     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
796     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
797     { 0, { (const PTR) 0 } }
798 };
799 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
800 {
801     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
802     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
803     { 0, { (const PTR) 0 } }
804 };
805 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
806 {
807     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
808     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
809     { 0, { (const PTR) 0 } }
810 };
811 const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
812 {
813     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
814     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
815     { 0, { (const PTR) 0 } }
816 };
817 const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
818 {
819     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
820     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
821     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
822     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
823     { 0, { (const PTR) 0 } }
824 };
825 const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
826 {
827     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
828     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
829     { 0, { (const PTR) 0 } }
830 };
831 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [] =
832 {
833     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RM] } },
834     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
835     { 0, { (const PTR) 0 } }
836 };
837 const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [] =
838 {
839     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
840     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
841     { 0, { (const PTR) 0 } }
842 };
843 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [] =
844 {
845     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
846     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
847     { 0, { (const PTR) 0 } }
848 };
849 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [] =
850 {
851     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
852     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
853     { 0, { (const PTR) 0 } }
854 };
855 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [] =
856 {
857     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3HI] } },
858     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3LO] } },
859     { 0, { (const PTR) 0 } }
860 };
861 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [] =
862 {
863     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H2] } },
864     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
865     { 0, { (const PTR) 0 } }
866 };
867 const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [] =
868 {
869     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H1] } },
870     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
871     { 0, { (const PTR) 0 } }
872 };
873 
874 /* The operand table.  */
875 
876 #define A(a) (1 << CGEN_OPERAND_##a)
877 #define OPERAND(op) MEP_OPERAND_##op
878 
879 const CGEN_OPERAND mep_cgen_operand_table[] =
880 {
881 /* pc: program counter */
882   { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
883     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
884     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
885 /* r0: register 0 */
886   { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
887     { 0, { (const PTR) 0 } },
888     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
889 /* rn: register Rn */
890   { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
891     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
892     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
893 /* rm: register Rm */
894   { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
895     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
896     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
897 /* rl: register Rl */
898   { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
899     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
900     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
901 /* rn3: register 0-7 */
902   { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
903     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
904     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
905 /* rma: register Rm holding pointer */
906   { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
907     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
908     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } }  },
909 /* rnc: register Rn holding char */
910   { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
911     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
912     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
913 /* rnuc: register Rn holding unsigned char */
914   { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
915     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
916     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
917 /* rns: register Rn holding short */
918   { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
919     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
920     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
921 /* rnus: register Rn holding unsigned short */
922   { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
923     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
924     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
925 /* rnl: register Rn holding long */
926   { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
927     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
928     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
929 /* rnul: register Rn holding unsigned  long */
930   { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
931     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
932     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
933 /* rn3c: register 0-7 holding unsigned char */
934   { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
935     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
936     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
937 /* rn3uc: register 0-7 holding byte */
938   { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
939     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
940     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
941 /* rn3s: register 0-7 holding unsigned short */
942   { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
943     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
944     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
945 /* rn3us: register 0-7 holding short */
946   { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
947     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
948     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
949 /* rn3l: register 0-7 holding unsigned long */
950   { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
951     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
952     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
953 /* rn3ul: register 0-7 holding long */
954   { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
955     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
956     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } }  },
957 /* lp: link pointer */
958   { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
959     { 0, { (const PTR) 0 } },
960     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
961 /* sar: shift amount register */
962   { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
963     { 0, { (const PTR) 0 } },
964     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
965 /* hi: high result */
966   { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
967     { 0, { (const PTR) 0 } },
968     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
969 /* lo: low result */
970   { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
971     { 0, { (const PTR) 0 } },
972     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
973 /* mb0: modulo begin register 0 */
974   { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
975     { 0, { (const PTR) 0 } },
976     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
977 /* me0: modulo end register 0 */
978   { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
979     { 0, { (const PTR) 0 } },
980     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
981 /* mb1: modulo begin register 1 */
982   { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
983     { 0, { (const PTR) 0 } },
984     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
985 /* me1: modulo end register 1 */
986   { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
987     { 0, { (const PTR) 0 } },
988     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
989 /* psw: program status word */
990   { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
991     { 0, { (const PTR) 0 } },
992     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
993 /* epc: exception prog counter */
994   { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
995     { 0, { (const PTR) 0 } },
996     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
997 /* exc: exception cause */
998   { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
999     { 0, { (const PTR) 0 } },
1000     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1001 /* npc: nmi program counter */
1002   { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
1003     { 0, { (const PTR) 0 } },
1004     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1005 /* dbg: debug register */
1006   { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
1007     { 0, { (const PTR) 0 } },
1008     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1009 /* depc: debug exception pc */
1010   { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
1011     { 0, { (const PTR) 0 } },
1012     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1013 /* opt: option register */
1014   { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
1015     { 0, { (const PTR) 0 } },
1016     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1017 /* r1: register 1 */
1018   { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
1019     { 0, { (const PTR) 0 } },
1020     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1021 /* tp: tiny data area pointer */
1022   { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
1023     { 0, { (const PTR) 0 } },
1024     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1025 /* sp: stack pointer */
1026   { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
1027     { 0, { (const PTR) 0 } },
1028     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1029 /* tpr: comment */
1030   { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
1031     { 0, { (const PTR) 0 } },
1032     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1033 /* spr: comment */
1034   { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
1035     { 0, { (const PTR) 0 } },
1036     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1037 /* csrn: control/special register */
1038   { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
1039     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
1040     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1041 /* csrn-idx: control/special reg idx */
1042   { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
1043     { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
1044     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1045 /* crn64: copro Rn (64-bit) */
1046   { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
1047     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
1048     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1049 /* crn: copro Rn (32-bit) */
1050   { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
1051     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
1052     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1053 /* crnx64: copro Rn (0-31, 64-bit) */
1054   { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
1055     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
1056     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1057 /* crnx: copro Rn (0-31, 32-bit) */
1058   { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
1059     { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
1060     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1061 /* ccrn: copro control reg CCRn */
1062   { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
1063     { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
1064     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1065 /* cccc: copro flags */
1066   { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
1067     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
1068     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1069 /* pcrel8a2: comment */
1070   { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
1071     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
1072     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1073 /* pcrel12a2: comment */
1074   { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
1075     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
1076     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1077 /* pcrel17a2: comment */
1078   { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
1079     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
1080     { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1081 /* pcrel24a2: comment */
1082   { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
1083     { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
1084     { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1085 /* pcabs24a2: comment */
1086   { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
1087     { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
1088     { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } }  },
1089 /* sdisp16: comment */
1090   { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
1091     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
1092     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1093 /* simm16: comment */
1094   { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
1095     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
1096     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1097 /* uimm16: comment */
1098   { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
1099     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
1100     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1101 /* code16: uci/dsp code (16 bits) */
1102   { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
1103     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
1104     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1105 /* udisp2: SSARB addend (2 bits) */
1106   { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
1107     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
1108     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1109 /* uimm2: interrupt (2 bits) */
1110   { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
1111     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
1112     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1113 /* simm6: add const (6 bits) */
1114   { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
1115     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
1116     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1117 /* simm8: mov const (8 bits) */
1118   { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
1119     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
1120     { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1121 /* addr24a4: comment */
1122   { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
1123     { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
1124     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1125 /* code24: coprocessor code */
1126   { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
1127     { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
1128     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1129 /* callnum: system call number */
1130   { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
1131     { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
1132     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1133 /* uimm3: bit immediate (3 bits) */
1134   { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
1135     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
1136     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1137 /* uimm4: bCC const (4 bits) */
1138   { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
1139     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
1140     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1141 /* uimm5: bit/shift val (5 bits) */
1142   { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
1143     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
1144     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1145 /* udisp7: comment */
1146   { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
1147     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
1148     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1149 /* udisp7a2: comment */
1150   { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
1151     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
1152     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } }  },
1153 /* udisp7a4: comment */
1154   { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
1155     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
1156     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1157 /* uimm7a4: comment */
1158   { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
1159     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
1160     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } }  },
1161 /* uimm24: immediate (24 bits) */
1162   { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
1163     { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
1164     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1165 /* cimm4: cache immed'te (4 bits) */
1166   { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
1167     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
1168     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1169 /* cimm5: clip immediate (5 bits) */
1170   { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
1171     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
1172     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1173 /* cdisp10: comment */
1174   { "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
1175     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1176     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1177 /* cdisp10a2: comment */
1178   { "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
1179     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1180     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1181 /* cdisp10a4: comment */
1182   { "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
1183     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1184     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1185 /* cdisp10a8: comment */
1186   { "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
1187     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
1188     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1189 /* zero: Zero operand */
1190   { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0,
1191     { 0, { (const PTR) 0 } },
1192     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1193 /* rl5: register Rl c5 */
1194   { "rl5", MEP_OPERAND_RL5, HW_H_GPR, 20, 4,
1195     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL5] } },
1196     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1197 /* cdisp12: copro addend (12 bits) */
1198   { "cdisp12", MEP_OPERAND_CDISP12, HW_H_SINT, 20, 12,
1199     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S20] } },
1200     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1201 /* c5rmuimm20: 20-bit immediate in rm and imm16 */
1202   { "c5rmuimm20", MEP_OPERAND_C5RMUIMM20, HW_H_UINT, 8, 20,
1203     { 2, { (const PTR) &MEP_F_C5_RMUIMM20_MULTI_IFIELD[0] } },
1204     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1205 /* c5rnmuimm24: 24-bit immediate in rn, rm, and imm16 */
1206   { "c5rnmuimm24", MEP_OPERAND_C5RNMUIMM24, HW_H_UINT, 4, 24,
1207     { 2, { (const PTR) &MEP_F_C5_RNMUIMM24_MULTI_IFIELD[0] } },
1208     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1209 /* cp_flag: branch condition register */
1210   { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
1211     { 0, { (const PTR) 0 } },
1212     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1213 /* ivc2_csar0: ivc2_csar0 */
1214   { "ivc2_csar0", MEP_OPERAND_IVC2_CSAR0, HW_H_CCR_IVC2, 0, 0,
1215     { 0, { (const PTR) 0 } },
1216     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1217 /* ivc2_cc: ivc2_cc */
1218   { "ivc2_cc", MEP_OPERAND_IVC2_CC, HW_H_CCR_IVC2, 0, 0,
1219     { 0, { (const PTR) 0 } },
1220     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1221 /* ivc2_cofr0: ivc2_cofr0 */
1222   { "ivc2_cofr0", MEP_OPERAND_IVC2_COFR0, HW_H_CCR_IVC2, 0, 0,
1223     { 0, { (const PTR) 0 } },
1224     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1225 /* ivc2_cofr1: ivc2_cofr1 */
1226   { "ivc2_cofr1", MEP_OPERAND_IVC2_COFR1, HW_H_CCR_IVC2, 0, 0,
1227     { 0, { (const PTR) 0 } },
1228     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1229 /* ivc2_cofa0: ivc2_cofa0 */
1230   { "ivc2_cofa0", MEP_OPERAND_IVC2_COFA0, HW_H_CCR_IVC2, 0, 0,
1231     { 0, { (const PTR) 0 } },
1232     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1233 /* ivc2_cofa1: ivc2_cofa1 */
1234   { "ivc2_cofa1", MEP_OPERAND_IVC2_COFA1, HW_H_CCR_IVC2, 0, 0,
1235     { 0, { (const PTR) 0 } },
1236     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1237 /* ivc2_csar1: ivc2_csar1 */
1238   { "ivc2_csar1", MEP_OPERAND_IVC2_CSAR1, HW_H_CCR_IVC2, 0, 0,
1239     { 0, { (const PTR) 0 } },
1240     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1241 /* ivc2_acc0_0: acc0_0 */
1242   { "ivc2_acc0_0", MEP_OPERAND_IVC2_ACC0_0, HW_H_CCR_IVC2, 0, 0,
1243     { 0, { (const PTR) 0 } },
1244     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1245 /* ivc2_acc0_1: acc0_1 */
1246   { "ivc2_acc0_1", MEP_OPERAND_IVC2_ACC0_1, HW_H_CCR_IVC2, 0, 0,
1247     { 0, { (const PTR) 0 } },
1248     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1249 /* ivc2_acc0_2: acc0_2 */
1250   { "ivc2_acc0_2", MEP_OPERAND_IVC2_ACC0_2, HW_H_CCR_IVC2, 0, 0,
1251     { 0, { (const PTR) 0 } },
1252     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1253 /* ivc2_acc0_3: acc0_3 */
1254   { "ivc2_acc0_3", MEP_OPERAND_IVC2_ACC0_3, HW_H_CCR_IVC2, 0, 0,
1255     { 0, { (const PTR) 0 } },
1256     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1257 /* ivc2_acc0_4: acc0_4 */
1258   { "ivc2_acc0_4", MEP_OPERAND_IVC2_ACC0_4, HW_H_CCR_IVC2, 0, 0,
1259     { 0, { (const PTR) 0 } },
1260     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1261 /* ivc2_acc0_5: acc0_5 */
1262   { "ivc2_acc0_5", MEP_OPERAND_IVC2_ACC0_5, HW_H_CCR_IVC2, 0, 0,
1263     { 0, { (const PTR) 0 } },
1264     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1265 /* ivc2_acc0_6: acc0_6 */
1266   { "ivc2_acc0_6", MEP_OPERAND_IVC2_ACC0_6, HW_H_CCR_IVC2, 0, 0,
1267     { 0, { (const PTR) 0 } },
1268     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1269 /* ivc2_acc0_7: acc0_7 */
1270   { "ivc2_acc0_7", MEP_OPERAND_IVC2_ACC0_7, HW_H_CCR_IVC2, 0, 0,
1271     { 0, { (const PTR) 0 } },
1272     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1273 /* ivc2_acc1_0: acc1_0 */
1274   { "ivc2_acc1_0", MEP_OPERAND_IVC2_ACC1_0, HW_H_CCR_IVC2, 0, 0,
1275     { 0, { (const PTR) 0 } },
1276     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1277 /* ivc2_acc1_1: acc1_1 */
1278   { "ivc2_acc1_1", MEP_OPERAND_IVC2_ACC1_1, HW_H_CCR_IVC2, 0, 0,
1279     { 0, { (const PTR) 0 } },
1280     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1281 /* ivc2_acc1_2: acc1_2 */
1282   { "ivc2_acc1_2", MEP_OPERAND_IVC2_ACC1_2, HW_H_CCR_IVC2, 0, 0,
1283     { 0, { (const PTR) 0 } },
1284     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1285 /* ivc2_acc1_3: acc1_3 */
1286   { "ivc2_acc1_3", MEP_OPERAND_IVC2_ACC1_3, HW_H_CCR_IVC2, 0, 0,
1287     { 0, { (const PTR) 0 } },
1288     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1289 /* ivc2_acc1_4: acc1_4 */
1290   { "ivc2_acc1_4", MEP_OPERAND_IVC2_ACC1_4, HW_H_CCR_IVC2, 0, 0,
1291     { 0, { (const PTR) 0 } },
1292     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1293 /* ivc2_acc1_5: acc1_5 */
1294   { "ivc2_acc1_5", MEP_OPERAND_IVC2_ACC1_5, HW_H_CCR_IVC2, 0, 0,
1295     { 0, { (const PTR) 0 } },
1296     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1297 /* ivc2_acc1_6: acc1_6 */
1298   { "ivc2_acc1_6", MEP_OPERAND_IVC2_ACC1_6, HW_H_CCR_IVC2, 0, 0,
1299     { 0, { (const PTR) 0 } },
1300     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1301 /* ivc2_acc1_7: acc1_7 */
1302   { "ivc2_acc1_7", MEP_OPERAND_IVC2_ACC1_7, HW_H_CCR_IVC2, 0, 0,
1303     { 0, { (const PTR) 0 } },
1304     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1305 /* croc: $CRo C3 */
1306   { "croc", MEP_OPERAND_CROC, HW_H_CR64, 7, 5,
1307     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
1308     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1309 /* crqc: $CRq C3 */
1310   { "crqc", MEP_OPERAND_CRQC, HW_H_CR64, 21, 5,
1311     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
1312     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1313 /* crpc: $CRp C3 */
1314   { "crpc", MEP_OPERAND_CRPC, HW_H_CR64, 26, 5,
1315     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
1316     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1317 /* ivc-x-6-1: filler */
1318   { "ivc-x-6-1", MEP_OPERAND_IVC_X_6_1, HW_H_UINT, 6, 1,
1319     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
1320     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1321 /* ivc-x-6-2: filler */
1322   { "ivc-x-6-2", MEP_OPERAND_IVC_X_6_2, HW_H_UINT, 6, 2,
1323     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U6] } },
1324     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1325 /* ivc-x-6-3: filler */
1326   { "ivc-x-6-3", MEP_OPERAND_IVC_X_6_3, HW_H_UINT, 6, 3,
1327     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U6] } },
1328     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1329 /* imm3p4: Imm3p4 */
1330   { "imm3p4", MEP_OPERAND_IMM3P4, HW_H_UINT, 4, 3,
1331     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U4] } },
1332     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1333 /* imm3p9: Imm3p9 */
1334   { "imm3p9", MEP_OPERAND_IMM3P9, HW_H_UINT, 9, 3,
1335     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U9] } },
1336     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1337 /* imm4p8: Imm4p8 */
1338   { "imm4p8", MEP_OPERAND_IMM4P8, HW_H_UINT, 8, 4,
1339     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U8] } },
1340     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1341 /* imm5p7: Imm5p7 */
1342   { "imm5p7", MEP_OPERAND_IMM5P7, HW_H_UINT, 7, 5,
1343     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
1344     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1345 /* imm6p6: Imm6p6 */
1346   { "imm6p6", MEP_OPERAND_IMM6P6, HW_H_UINT, 6, 6,
1347     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U6] } },
1348     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1349 /* imm8p4: Imm8p4 */
1350   { "imm8p4", MEP_OPERAND_IMM8P4, HW_H_UINT, 4, 8,
1351     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U4] } },
1352     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1353 /* simm8p4: sImm8p4 */
1354   { "simm8p4", MEP_OPERAND_SIMM8P4, HW_H_SINT, 4, 8,
1355     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S4] } },
1356     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1357 /* imm3p5: Imm3p5 */
1358   { "imm3p5", MEP_OPERAND_IMM3P5, HW_H_UINT, 5, 3,
1359     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U5] } },
1360     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1361 /* imm3p12: Imm3p12 */
1362   { "imm3p12", MEP_OPERAND_IMM3P12, HW_H_UINT, 12, 3,
1363     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U12] } },
1364     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1365 /* imm4p4: Imm4p4 */
1366   { "imm4p4", MEP_OPERAND_IMM4P4, HW_H_UINT, 4, 4,
1367     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U4] } },
1368     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1369 /* imm4p10: Imm4p10 */
1370   { "imm4p10", MEP_OPERAND_IMM4P10, HW_H_UINT, 10, 4,
1371     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U10] } },
1372     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1373 /* imm5p8: Imm5p8 */
1374   { "imm5p8", MEP_OPERAND_IMM5P8, HW_H_UINT, 8, 5,
1375     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U8] } },
1376     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1377 /* imm5p3: Imm5p3 */
1378   { "imm5p3", MEP_OPERAND_IMM5P3, HW_H_UINT, 3, 5,
1379     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U3] } },
1380     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1381 /* imm6p2: Imm6p2 */
1382   { "imm6p2", MEP_OPERAND_IMM6P2, HW_H_UINT, 2, 6,
1383     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_6U2] } },
1384     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1385 /* imm5p23: Imm5p23 */
1386   { "imm5p23", MEP_OPERAND_IMM5P23, HW_H_UINT, 23, 5,
1387     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
1388     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1389 /* imm3p25: Imm3p25 */
1390   { "imm3p25", MEP_OPERAND_IMM3P25, HW_H_UINT, 25, 3,
1391     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U25] } },
1392     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1393 /* imm8p0: Imm8p0 */
1394   { "imm8p0", MEP_OPERAND_IMM8P0, HW_H_UINT, 0, 8,
1395     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
1396     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1397 /* simm8p0: sImm8p0 */
1398   { "simm8p0", MEP_OPERAND_SIMM8P0, HW_H_SINT, 0, 8,
1399     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S0] } },
1400     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1401 /* simm8p20: sImm8p20 */
1402   { "simm8p20", MEP_OPERAND_SIMM8P20, HW_H_SINT, 20, 8,
1403     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8S20] } },
1404     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1405 /* imm8p20: Imm8p20 */
1406   { "imm8p20", MEP_OPERAND_IMM8P20, HW_H_UINT, 20, 8,
1407     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
1408     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1409 /* crop: $CRo Pn */
1410   { "crop", MEP_OPERAND_CROP, HW_H_CR64, 23, 5,
1411     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
1412     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1413 /* crqp: $CRq Pn */
1414   { "crqp", MEP_OPERAND_CRQP, HW_H_CR64, 13, 5,
1415     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
1416     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1417 /* crpp: $CRp Pn */
1418   { "crpp", MEP_OPERAND_CRPP, HW_H_CR64, 18, 5,
1419     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
1420     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1421 /* ivc-x-0-2: filler */
1422   { "ivc-x-0-2", MEP_OPERAND_IVC_X_0_2, HW_H_UINT, 0, 2,
1423     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
1424     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1425 /* ivc-x-0-3: filler */
1426   { "ivc-x-0-3", MEP_OPERAND_IVC_X_0_3, HW_H_UINT, 0, 3,
1427     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_3U0] } },
1428     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1429 /* ivc-x-0-4: filler */
1430   { "ivc-x-0-4", MEP_OPERAND_IVC_X_0_4, HW_H_UINT, 0, 4,
1431     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_4U0] } },
1432     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1433 /* ivc-x-0-5: filler */
1434   { "ivc-x-0-5", MEP_OPERAND_IVC_X_0_5, HW_H_UINT, 0, 5,
1435     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U0] } },
1436     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1437 /* imm16p0: comment */
1438   { "imm16p0", MEP_OPERAND_IMM16P0, HW_H_UINT, 0, 16,
1439     { 2, { (const PTR) &MEP_F_IVC2_IMM16P0_MULTI_IFIELD[0] } },
1440     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1441 /* simm16p0: comment */
1442   { "simm16p0", MEP_OPERAND_SIMM16P0, HW_H_SINT, 0, 16,
1443     { 2, { (const PTR) &MEP_F_IVC2_SIMM16P0_MULTI_IFIELD[0] } },
1444     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1445 /* ivc2rm: reg Rm */
1446   { "ivc2rm", MEP_OPERAND_IVC2RM, HW_H_GPR, 4, 4,
1447     { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CRM] } },
1448     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } }  },
1449 /* ivc2crn: copro Rn (0-31, 64-bit */
1450   { "ivc2crn", MEP_OPERAND_IVC2CRN, HW_H_CR64, 0, 5,
1451     { 2, { (const PTR) &MEP_F_IVC2_CRNX_MULTI_IFIELD[0] } },
1452     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } }  },
1453 /* ivc2ccrn: copro control reg CCRn */
1454   { "ivc2ccrn", MEP_OPERAND_IVC2CCRN, HW_H_CCR_IVC2, 0, 6,
1455     { 2, { (const PTR) &MEP_F_IVC2_CCRN_MULTI_IFIELD[0] } },
1456     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1457 /* ivc2c3ccrn: copro control reg CCRn */
1458   { "ivc2c3ccrn", MEP_OPERAND_IVC2C3CCRN, HW_H_CCR_IVC2, 4, 6,
1459     { 2, { (const PTR) &MEP_F_IVC2_CCRN_C3_MULTI_IFIELD[0] } },
1460     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } }  },
1461 /* sentinel */
1462   { 0, 0, 0, 0, 0,
1463     { 0, { (const PTR) 0 } },
1464     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }
1465 };
1466 
1467 #undef A
1468 
1469 
1470 /* The instruction table.  */
1471 
1472 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1473 #define A(a) (1 << CGEN_INSN_##a)
1474 
1475 static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] =
1476 {
1477   /* Special null first entry.
1478      A `num' value of zero is thus invalid.
1479      Also, the special `invalid' insn resides here.  */
1480   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } } },
1481 /* stcb $rn,($rma) */
1482   {
1483     MEP_INSN_STCB_R, "stcb_r", "stcb", 16,
1484     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1485   },
1486 /* ldcb $rn,($rma) */
1487   {
1488     MEP_INSN_LDCB_R, "ldcb_r", "ldcb", 16,
1489     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1490   },
1491 /* pref $cimm4,($rma) */
1492   {
1493     MEP_INSN_PREF, "pref", "pref", 16,
1494     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1495   },
1496 /* pref $cimm4,$sdisp16($rma) */
1497   {
1498     MEP_INSN_PREFD, "prefd", "pref", 32,
1499     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1500   },
1501 /* casb3 $rl5,$rn,($rm) */
1502   {
1503     MEP_INSN_CASB3, "casb3", "casb3", 32,
1504     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1505   },
1506 /* cash3 $rl5,$rn,($rm) */
1507   {
1508     MEP_INSN_CASH3, "cash3", "cash3", 32,
1509     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1510   },
1511 /* casw3 $rl5,$rn,($rm) */
1512   {
1513     MEP_INSN_CASW3, "casw3", "casw3", 32,
1514     { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1515   },
1516 /* sbcp $crn,$cdisp12($rma) */
1517   {
1518     MEP_INSN_SBCP, "sbcp", "sbcp", 32,
1519     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1520   },
1521 /* lbcp $crn,$cdisp12($rma) */
1522   {
1523     MEP_INSN_LBCP, "lbcp", "lbcp", 32,
1524     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1525   },
1526 /* lbucp $crn,$cdisp12($rma) */
1527   {
1528     MEP_INSN_LBUCP, "lbucp", "lbucp", 32,
1529     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1530   },
1531 /* shcp $crn,$cdisp12($rma) */
1532   {
1533     MEP_INSN_SHCP, "shcp", "shcp", 32,
1534     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1535   },
1536 /* lhcp $crn,$cdisp12($rma) */
1537   {
1538     MEP_INSN_LHCP, "lhcp", "lhcp", 32,
1539     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1540   },
1541 /* lhucp $crn,$cdisp12($rma) */
1542   {
1543     MEP_INSN_LHUCP, "lhucp", "lhucp", 32,
1544     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1545   },
1546 /* lbucpa $crn,($rma+),$cdisp10 */
1547   {
1548     MEP_INSN_LBUCPA, "lbucpa", "lbucpa", 32,
1549     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1550   },
1551 /* lhucpa $crn,($rma+),$cdisp10a2 */
1552   {
1553     MEP_INSN_LHUCPA, "lhucpa", "lhucpa", 32,
1554     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1555   },
1556 /* lbucpm0 $crn,($rma+),$cdisp10 */
1557   {
1558     MEP_INSN_LBUCPM0, "lbucpm0", "lbucpm0", 32,
1559     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1560   },
1561 /* lhucpm0 $crn,($rma+),$cdisp10a2 */
1562   {
1563     MEP_INSN_LHUCPM0, "lhucpm0", "lhucpm0", 32,
1564     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1565   },
1566 /* lbucpm1 $crn,($rma+),$cdisp10 */
1567   {
1568     MEP_INSN_LBUCPM1, "lbucpm1", "lbucpm1", 32,
1569     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1570   },
1571 /* lhucpm1 $crn,($rma+),$cdisp10a2 */
1572   {
1573     MEP_INSN_LHUCPM1, "lhucpm1", "lhucpm1", 32,
1574     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1575   },
1576 /* uci $rn,$rm,$uimm16 */
1577   {
1578     MEP_INSN_UCI, "uci", "uci", 32,
1579     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1580   },
1581 /* dsp $rn,$rm,$uimm16 */
1582   {
1583     MEP_INSN_DSP, "dsp", "dsp", 32,
1584     { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1585   },
1586 /* dsp0 $c5rnmuimm24 */
1587   {
1588     -1, "dsp0", "dsp0", 32,
1589     { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1590   },
1591 /* dsp1 $rn,$c5rmuimm20 */
1592   {
1593     -1, "dsp1", "dsp1", 32,
1594     { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1595   },
1596 /* sb $rnc,($rma) */
1597   {
1598     MEP_INSN_SB, "sb", "sb", 16,
1599     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1600   },
1601 /* sh $rns,($rma) */
1602   {
1603     MEP_INSN_SH, "sh", "sh", 16,
1604     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1605   },
1606 /* sw $rnl,($rma) */
1607   {
1608     MEP_INSN_SW, "sw", "sw", 16,
1609     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1610   },
1611 /* lb $rnc,($rma) */
1612   {
1613     MEP_INSN_LB, "lb", "lb", 16,
1614     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1615   },
1616 /* lh $rns,($rma) */
1617   {
1618     MEP_INSN_LH, "lh", "lh", 16,
1619     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1620   },
1621 /* lw $rnl,($rma) */
1622   {
1623     MEP_INSN_LW, "lw", "lw", 16,
1624     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1625   },
1626 /* lbu $rnuc,($rma) */
1627   {
1628     MEP_INSN_LBU, "lbu", "lbu", 16,
1629     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1630   },
1631 /* lhu $rnus,($rma) */
1632   {
1633     MEP_INSN_LHU, "lhu", "lhu", 16,
1634     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1635   },
1636 /* sw $rnl,$udisp7a4($spr) */
1637   {
1638     MEP_INSN_SW_SP, "sw-sp", "sw", 16,
1639     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1640   },
1641 /* lw $rnl,$udisp7a4($spr) */
1642   {
1643     MEP_INSN_LW_SP, "lw-sp", "lw", 16,
1644     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1645   },
1646 /* sb $rn3c,$udisp7($tpr) */
1647   {
1648     MEP_INSN_SB_TP, "sb-tp", "sb", 16,
1649     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1650   },
1651 /* sh $rn3s,$udisp7a2($tpr) */
1652   {
1653     MEP_INSN_SH_TP, "sh-tp", "sh", 16,
1654     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1655   },
1656 /* sw $rn3l,$udisp7a4($tpr) */
1657   {
1658     MEP_INSN_SW_TP, "sw-tp", "sw", 16,
1659     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1660   },
1661 /* lb $rn3c,$udisp7($tpr) */
1662   {
1663     MEP_INSN_LB_TP, "lb-tp", "lb", 16,
1664     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1665   },
1666 /* lh $rn3s,$udisp7a2($tpr) */
1667   {
1668     MEP_INSN_LH_TP, "lh-tp", "lh", 16,
1669     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1670   },
1671 /* lw $rn3l,$udisp7a4($tpr) */
1672   {
1673     MEP_INSN_LW_TP, "lw-tp", "lw", 16,
1674     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1675   },
1676 /* lbu $rn3uc,$udisp7($tpr) */
1677   {
1678     MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16,
1679     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1680   },
1681 /* lhu $rn3us,$udisp7a2($tpr) */
1682   {
1683     MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16,
1684     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1685   },
1686 /* sb $rnc,$sdisp16($rma) */
1687   {
1688     MEP_INSN_SB16, "sb16", "sb", 32,
1689     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1690   },
1691 /* sh $rns,$sdisp16($rma) */
1692   {
1693     MEP_INSN_SH16, "sh16", "sh", 32,
1694     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1695   },
1696 /* sw $rnl,$sdisp16($rma) */
1697   {
1698     MEP_INSN_SW16, "sw16", "sw", 32,
1699     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1700   },
1701 /* lb $rnc,$sdisp16($rma) */
1702   {
1703     MEP_INSN_LB16, "lb16", "lb", 32,
1704     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1705   },
1706 /* lh $rns,$sdisp16($rma) */
1707   {
1708     MEP_INSN_LH16, "lh16", "lh", 32,
1709     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1710   },
1711 /* lw $rnl,$sdisp16($rma) */
1712   {
1713     MEP_INSN_LW16, "lw16", "lw", 32,
1714     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1715   },
1716 /* lbu $rnuc,$sdisp16($rma) */
1717   {
1718     MEP_INSN_LBU16, "lbu16", "lbu", 32,
1719     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1720   },
1721 /* lhu $rnus,$sdisp16($rma) */
1722   {
1723     MEP_INSN_LHU16, "lhu16", "lhu", 32,
1724     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1725   },
1726 /* sw $rnl,($addr24a4) */
1727   {
1728     MEP_INSN_SW24, "sw24", "sw", 32,
1729     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1730   },
1731 /* lw $rnl,($addr24a4) */
1732   {
1733     MEP_INSN_LW24, "lw24", "lw", 32,
1734     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1735   },
1736 /* extb $rn */
1737   {
1738     MEP_INSN_EXTB, "extb", "extb", 16,
1739     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1740   },
1741 /* exth $rn */
1742   {
1743     MEP_INSN_EXTH, "exth", "exth", 16,
1744     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1745   },
1746 /* extub $rn */
1747   {
1748     MEP_INSN_EXTUB, "extub", "extub", 16,
1749     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1750   },
1751 /* extuh $rn */
1752   {
1753     MEP_INSN_EXTUH, "extuh", "extuh", 16,
1754     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1755   },
1756 /* ssarb $udisp2($rm) */
1757   {
1758     MEP_INSN_SSARB, "ssarb", "ssarb", 16,
1759     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1760   },
1761 /* mov $rn,$rm */
1762   {
1763     MEP_INSN_MOV, "mov", "mov", 16,
1764     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1765   },
1766 /* mov $rn,$simm8 */
1767   {
1768     MEP_INSN_MOVI8, "movi8", "mov", 16,
1769     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1770   },
1771 /* mov $rn,$simm16 */
1772   {
1773     MEP_INSN_MOVI16, "movi16", "mov", 32,
1774     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1775   },
1776 /* movu $rn3,$uimm24 */
1777   {
1778     MEP_INSN_MOVU24, "movu24", "movu", 32,
1779     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1780   },
1781 /* movu $rn,$uimm16 */
1782   {
1783     MEP_INSN_MOVU16, "movu16", "movu", 32,
1784     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1785   },
1786 /* movh $rn,$uimm16 */
1787   {
1788     MEP_INSN_MOVH, "movh", "movh", 32,
1789     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1790   },
1791 /* add3 $rl,$rn,$rm */
1792   {
1793     MEP_INSN_ADD3, "add3", "add3", 16,
1794     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1795   },
1796 /* add $rn,$simm6 */
1797   {
1798     MEP_INSN_ADD, "add", "add", 16,
1799     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1800   },
1801 /* add3 $rn,$spr,$uimm7a4 */
1802   {
1803     MEP_INSN_ADD3I, "add3i", "add3", 16,
1804     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1805   },
1806 /* advck3 \$0,$rn,$rm */
1807   {
1808     MEP_INSN_ADVCK3, "advck3", "advck3", 16,
1809     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1810   },
1811 /* sub $rn,$rm */
1812   {
1813     MEP_INSN_SUB, "sub", "sub", 16,
1814     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1815   },
1816 /* sbvck3 \$0,$rn,$rm */
1817   {
1818     MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16,
1819     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1820   },
1821 /* neg $rn,$rm */
1822   {
1823     MEP_INSN_NEG, "neg", "neg", 16,
1824     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1825   },
1826 /* slt3 \$0,$rn,$rm */
1827   {
1828     MEP_INSN_SLT3, "slt3", "slt3", 16,
1829     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1830   },
1831 /* sltu3 \$0,$rn,$rm */
1832   {
1833     MEP_INSN_SLTU3, "sltu3", "sltu3", 16,
1834     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1835   },
1836 /* slt3 \$0,$rn,$uimm5 */
1837   {
1838     MEP_INSN_SLT3I, "slt3i", "slt3", 16,
1839     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1840   },
1841 /* sltu3 \$0,$rn,$uimm5 */
1842   {
1843     MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16,
1844     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1845   },
1846 /* sl1ad3 \$0,$rn,$rm */
1847   {
1848     MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16,
1849     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1850   },
1851 /* sl2ad3 \$0,$rn,$rm */
1852   {
1853     MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16,
1854     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1855   },
1856 /* add3 $rn,$rm,$simm16 */
1857   {
1858     MEP_INSN_ADD3X, "add3x", "add3", 32,
1859     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1860   },
1861 /* slt3 $rn,$rm,$simm16 */
1862   {
1863     MEP_INSN_SLT3X, "slt3x", "slt3", 32,
1864     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1865   },
1866 /* sltu3 $rn,$rm,$uimm16 */
1867   {
1868     MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32,
1869     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1870   },
1871 /* or $rn,$rm */
1872   {
1873     MEP_INSN_OR, "or", "or", 16,
1874     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1875   },
1876 /* and $rn,$rm */
1877   {
1878     MEP_INSN_AND, "and", "and", 16,
1879     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1880   },
1881 /* xor $rn,$rm */
1882   {
1883     MEP_INSN_XOR, "xor", "xor", 16,
1884     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1885   },
1886 /* nor $rn,$rm */
1887   {
1888     MEP_INSN_NOR, "nor", "nor", 16,
1889     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1890   },
1891 /* or3 $rn,$rm,$uimm16 */
1892   {
1893     MEP_INSN_OR3, "or3", "or3", 32,
1894     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1895   },
1896 /* and3 $rn,$rm,$uimm16 */
1897   {
1898     MEP_INSN_AND3, "and3", "and3", 32,
1899     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1900   },
1901 /* xor3 $rn,$rm,$uimm16 */
1902   {
1903     MEP_INSN_XOR3, "xor3", "xor3", 32,
1904     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1905   },
1906 /* sra $rn,$rm */
1907   {
1908     MEP_INSN_SRA, "sra", "sra", 16,
1909     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1910   },
1911 /* srl $rn,$rm */
1912   {
1913     MEP_INSN_SRL, "srl", "srl", 16,
1914     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1915   },
1916 /* sll $rn,$rm */
1917   {
1918     MEP_INSN_SLL, "sll", "sll", 16,
1919     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1920   },
1921 /* sra $rn,$uimm5 */
1922   {
1923     MEP_INSN_SRAI, "srai", "sra", 16,
1924     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1925   },
1926 /* srl $rn,$uimm5 */
1927   {
1928     MEP_INSN_SRLI, "srli", "srl", 16,
1929     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1930   },
1931 /* sll $rn,$uimm5 */
1932   {
1933     MEP_INSN_SLLI, "slli", "sll", 16,
1934     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1935   },
1936 /* sll3 \$0,$rn,$uimm5 */
1937   {
1938     MEP_INSN_SLL3, "sll3", "sll3", 16,
1939     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1940   },
1941 /* fsft $rn,$rm */
1942   {
1943     MEP_INSN_FSFT, "fsft", "fsft", 16,
1944     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1945   },
1946 /* bra $pcrel12a2 */
1947   {
1948     MEP_INSN_BRA, "bra", "bra", 16,
1949     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1950   },
1951 /* beqz $rn,$pcrel8a2 */
1952   {
1953     MEP_INSN_BEQZ, "beqz", "beqz", 16,
1954     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1955   },
1956 /* bnez $rn,$pcrel8a2 */
1957   {
1958     MEP_INSN_BNEZ, "bnez", "bnez", 16,
1959     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1960   },
1961 /* beqi $rn,$uimm4,$pcrel17a2 */
1962   {
1963     MEP_INSN_BEQI, "beqi", "beqi", 32,
1964     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1965   },
1966 /* bnei $rn,$uimm4,$pcrel17a2 */
1967   {
1968     MEP_INSN_BNEI, "bnei", "bnei", 32,
1969     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1970   },
1971 /* blti $rn,$uimm4,$pcrel17a2 */
1972   {
1973     MEP_INSN_BLTI, "blti", "blti", 32,
1974     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1975   },
1976 /* bgei $rn,$uimm4,$pcrel17a2 */
1977   {
1978     MEP_INSN_BGEI, "bgei", "bgei", 32,
1979     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1980   },
1981 /* beq $rn,$rm,$pcrel17a2 */
1982   {
1983     MEP_INSN_BEQ, "beq", "beq", 32,
1984     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1985   },
1986 /* bne $rn,$rm,$pcrel17a2 */
1987   {
1988     MEP_INSN_BNE, "bne", "bne", 32,
1989     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1990   },
1991 /* bsr $pcrel12a2 */
1992   {
1993     MEP_INSN_BSR12, "bsr12", "bsr", 16,
1994     { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
1995   },
1996 /* bsr $pcrel24a2 */
1997   {
1998     MEP_INSN_BSR24, "bsr24", "bsr", 32,
1999     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2000   },
2001 /* jmp $rm */
2002   {
2003     MEP_INSN_JMP, "jmp", "jmp", 16,
2004     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2005   },
2006 /* jmp $pcabs24a2 */
2007   {
2008     MEP_INSN_JMP24, "jmp24", "jmp", 32,
2009     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2010   },
2011 /* jsr $rm */
2012   {
2013     MEP_INSN_JSR, "jsr", "jsr", 16,
2014     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2015   },
2016 /* ret */
2017   {
2018     MEP_INSN_RET, "ret", "ret", 16,
2019     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2020   },
2021 /* repeat $rn,$pcrel17a2 */
2022   {
2023     MEP_INSN_REPEAT, "repeat", "repeat", 32,
2024     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2025   },
2026 /* erepeat $pcrel17a2 */
2027   {
2028     MEP_INSN_EREPEAT, "erepeat", "erepeat", 32,
2029     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2030   },
2031 /* stc $rn,\$lp */
2032   {
2033     MEP_INSN_STC_LP, "stc_lp", "stc", 16,
2034     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2035   },
2036 /* stc $rn,\$hi */
2037   {
2038     MEP_INSN_STC_HI, "stc_hi", "stc", 16,
2039     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2040   },
2041 /* stc $rn,\$lo */
2042   {
2043     MEP_INSN_STC_LO, "stc_lo", "stc", 16,
2044     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2045   },
2046 /* stc $rn,$csrn */
2047   {
2048     MEP_INSN_STC, "stc", "stc", 16,
2049     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2050   },
2051 /* ldc $rn,\$lp */
2052   {
2053     MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16,
2054     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2055   },
2056 /* ldc $rn,\$hi */
2057   {
2058     MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16,
2059     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2060   },
2061 /* ldc $rn,\$lo */
2062   {
2063     MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16,
2064     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2065   },
2066 /* ldc $rn,$csrn */
2067   {
2068     MEP_INSN_LDC, "ldc", "ldc", 16,
2069     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2070   },
2071 /* di */
2072   {
2073     MEP_INSN_DI, "di", "di", 16,
2074     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2075   },
2076 /* ei */
2077   {
2078     MEP_INSN_EI, "ei", "ei", 16,
2079     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2080   },
2081 /* reti */
2082   {
2083     MEP_INSN_RETI, "reti", "reti", 16,
2084     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2085   },
2086 /* halt */
2087   {
2088     MEP_INSN_HALT, "halt", "halt", 16,
2089     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2090   },
2091 /* sleep */
2092   {
2093     MEP_INSN_SLEEP, "sleep", "sleep", 16,
2094     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2095   },
2096 /* swi $uimm2 */
2097   {
2098     MEP_INSN_SWI, "swi", "swi", 16,
2099     { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2100   },
2101 /* break */
2102   {
2103     MEP_INSN_BREAK, "break", "break", 16,
2104     { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2105   },
2106 /* syncm */
2107   {
2108     MEP_INSN_SYNCM, "syncm", "syncm", 16,
2109     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2110   },
2111 /* stcb $rn,$uimm16 */
2112   {
2113     MEP_INSN_STCB, "stcb", "stcb", 32,
2114     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2115   },
2116 /* ldcb $rn,$uimm16 */
2117   {
2118     MEP_INSN_LDCB, "ldcb", "ldcb", 32,
2119     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2120   },
2121 /* bsetm ($rma),$uimm3 */
2122   {
2123     MEP_INSN_BSETM, "bsetm", "bsetm", 16,
2124     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2125   },
2126 /* bclrm ($rma),$uimm3 */
2127   {
2128     MEP_INSN_BCLRM, "bclrm", "bclrm", 16,
2129     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2130   },
2131 /* bnotm ($rma),$uimm3 */
2132   {
2133     MEP_INSN_BNOTM, "bnotm", "bnotm", 16,
2134     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2135   },
2136 /* btstm \$0,($rma),$uimm3 */
2137   {
2138     MEP_INSN_BTSTM, "btstm", "btstm", 16,
2139     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2140   },
2141 /* tas $rn,($rma) */
2142   {
2143     MEP_INSN_TAS, "tas", "tas", 16,
2144     { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2145   },
2146 /* cache $cimm4,($rma) */
2147   {
2148     MEP_INSN_CACHE, "cache", "cache", 16,
2149     { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2150   },
2151 /* mul $rn,$rm */
2152   {
2153     MEP_INSN_MUL, "mul", "mul", 16,
2154     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2155   },
2156 /* mulu $rn,$rm */
2157   {
2158     MEP_INSN_MULU, "mulu", "mulu", 16,
2159     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2160   },
2161 /* mulr $rn,$rm */
2162   {
2163     MEP_INSN_MULR, "mulr", "mulr", 16,
2164     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2165   },
2166 /* mulru $rn,$rm */
2167   {
2168     MEP_INSN_MULRU, "mulru", "mulru", 16,
2169     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2170   },
2171 /* madd $rn,$rm */
2172   {
2173     MEP_INSN_MADD, "madd", "madd", 32,
2174     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2175   },
2176 /* maddu $rn,$rm */
2177   {
2178     MEP_INSN_MADDU, "maddu", "maddu", 32,
2179     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2180   },
2181 /* maddr $rn,$rm */
2182   {
2183     MEP_INSN_MADDR, "maddr", "maddr", 32,
2184     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2185   },
2186 /* maddru $rn,$rm */
2187   {
2188     MEP_INSN_MADDRU, "maddru", "maddru", 32,
2189     { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2190   },
2191 /* div $rn,$rm */
2192   {
2193     MEP_INSN_DIV, "div", "div", 16,
2194     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2195   },
2196 /* divu $rn,$rm */
2197   {
2198     MEP_INSN_DIVU, "divu", "divu", 16,
2199     { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2200   },
2201 /* dret */
2202   {
2203     MEP_INSN_DRET, "dret", "dret", 16,
2204     { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2205   },
2206 /* dbreak */
2207   {
2208     MEP_INSN_DBREAK, "dbreak", "dbreak", 16,
2209     { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2210   },
2211 /* ldz $rn,$rm */
2212   {
2213     MEP_INSN_LDZ, "ldz", "ldz", 32,
2214     { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2215   },
2216 /* abs $rn,$rm */
2217   {
2218     MEP_INSN_ABS, "abs", "abs", 32,
2219     { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2220   },
2221 /* ave $rn,$rm */
2222   {
2223     MEP_INSN_AVE, "ave", "ave", 32,
2224     { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2225   },
2226 /* min $rn,$rm */
2227   {
2228     MEP_INSN_MIN, "min", "min", 32,
2229     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2230   },
2231 /* max $rn,$rm */
2232   {
2233     MEP_INSN_MAX, "max", "max", 32,
2234     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2235   },
2236 /* minu $rn,$rm */
2237   {
2238     MEP_INSN_MINU, "minu", "minu", 32,
2239     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2240   },
2241 /* maxu $rn,$rm */
2242   {
2243     MEP_INSN_MAXU, "maxu", "maxu", 32,
2244     { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2245   },
2246 /* clip $rn,$cimm5 */
2247   {
2248     MEP_INSN_CLIP, "clip", "clip", 32,
2249     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2250   },
2251 /* clipu $rn,$cimm5 */
2252   {
2253     MEP_INSN_CLIPU, "clipu", "clipu", 32,
2254     { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2255   },
2256 /* sadd $rn,$rm */
2257   {
2258     MEP_INSN_SADD, "sadd", "sadd", 32,
2259     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2260   },
2261 /* ssub $rn,$rm */
2262   {
2263     MEP_INSN_SSUB, "ssub", "ssub", 32,
2264     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2265   },
2266 /* saddu $rn,$rm */
2267   {
2268     MEP_INSN_SADDU, "saddu", "saddu", 32,
2269     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2270   },
2271 /* ssubu $rn,$rm */
2272   {
2273     MEP_INSN_SSUBU, "ssubu", "ssubu", 32,
2274     { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2275   },
2276 /* swcp $crn,($rma) */
2277   {
2278     MEP_INSN_SWCP, "swcp", "swcp", 16,
2279     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2280   },
2281 /* lwcp $crn,($rma) */
2282   {
2283     MEP_INSN_LWCP, "lwcp", "lwcp", 16,
2284     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2285   },
2286 /* smcp $crn64,($rma) */
2287   {
2288     MEP_INSN_SMCP, "smcp", "smcp", 16,
2289     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2290   },
2291 /* lmcp $crn64,($rma) */
2292   {
2293     MEP_INSN_LMCP, "lmcp", "lmcp", 16,
2294     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2295   },
2296 /* swcpi $crn,($rma+) */
2297   {
2298     MEP_INSN_SWCPI, "swcpi", "swcpi", 16,
2299     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2300   },
2301 /* lwcpi $crn,($rma+) */
2302   {
2303     MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16,
2304     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2305   },
2306 /* smcpi $crn64,($rma+) */
2307   {
2308     MEP_INSN_SMCPI, "smcpi", "smcpi", 16,
2309     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2310   },
2311 /* lmcpi $crn64,($rma+) */
2312   {
2313     MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16,
2314     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2315   },
2316 /* swcp $crn,$sdisp16($rma) */
2317   {
2318     MEP_INSN_SWCP16, "swcp16", "swcp", 32,
2319     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2320   },
2321 /* lwcp $crn,$sdisp16($rma) */
2322   {
2323     MEP_INSN_LWCP16, "lwcp16", "lwcp", 32,
2324     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2325   },
2326 /* smcp $crn64,$sdisp16($rma) */
2327   {
2328     MEP_INSN_SMCP16, "smcp16", "smcp", 32,
2329     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2330   },
2331 /* lmcp $crn64,$sdisp16($rma) */
2332   {
2333     MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
2334     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2335   },
2336 /* sbcpa $crn,($rma+),$cdisp10 */
2337   {
2338     MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
2339     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2340   },
2341 /* lbcpa $crn,($rma+),$cdisp10 */
2342   {
2343     MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
2344     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2345   },
2346 /* shcpa $crn,($rma+),$cdisp10a2 */
2347   {
2348     MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
2349     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2350   },
2351 /* lhcpa $crn,($rma+),$cdisp10a2 */
2352   {
2353     MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
2354     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2355   },
2356 /* swcpa $crn,($rma+),$cdisp10a4 */
2357   {
2358     MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
2359     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2360   },
2361 /* lwcpa $crn,($rma+),$cdisp10a4 */
2362   {
2363     MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
2364     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2365   },
2366 /* smcpa $crn64,($rma+),$cdisp10a8 */
2367   {
2368     MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
2369     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2370   },
2371 /* lmcpa $crn64,($rma+),$cdisp10a8 */
2372   {
2373     MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
2374     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2375   },
2376 /* sbcpm0 $crn,($rma+),$cdisp10 */
2377   {
2378     MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
2379     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2380   },
2381 /* lbcpm0 $crn,($rma+),$cdisp10 */
2382   {
2383     MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
2384     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2385   },
2386 /* shcpm0 $crn,($rma+),$cdisp10a2 */
2387   {
2388     MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
2389     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2390   },
2391 /* lhcpm0 $crn,($rma+),$cdisp10a2 */
2392   {
2393     MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
2394     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2395   },
2396 /* swcpm0 $crn,($rma+),$cdisp10a4 */
2397   {
2398     MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
2399     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2400   },
2401 /* lwcpm0 $crn,($rma+),$cdisp10a4 */
2402   {
2403     MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
2404     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2405   },
2406 /* smcpm0 $crn64,($rma+),$cdisp10a8 */
2407   {
2408     MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
2409     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2410   },
2411 /* lmcpm0 $crn64,($rma+),$cdisp10a8 */
2412   {
2413     MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
2414     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2415   },
2416 /* sbcpm1 $crn,($rma+),$cdisp10 */
2417   {
2418     MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
2419     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2420   },
2421 /* lbcpm1 $crn,($rma+),$cdisp10 */
2422   {
2423     MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
2424     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2425   },
2426 /* shcpm1 $crn,($rma+),$cdisp10a2 */
2427   {
2428     MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
2429     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2430   },
2431 /* lhcpm1 $crn,($rma+),$cdisp10a2 */
2432   {
2433     MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
2434     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2435   },
2436 /* swcpm1 $crn,($rma+),$cdisp10a4 */
2437   {
2438     MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
2439     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2440   },
2441 /* lwcpm1 $crn,($rma+),$cdisp10a4 */
2442   {
2443     MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
2444     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2445   },
2446 /* smcpm1 $crn64,($rma+),$cdisp10a8 */
2447   {
2448     MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
2449     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2450   },
2451 /* lmcpm1 $crn64,($rma+),$cdisp10a8 */
2452   {
2453     MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
2454     { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2455   },
2456 /* bcpeq $cccc,$pcrel17a2 */
2457   {
2458     MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32,
2459     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2460   },
2461 /* bcpne $cccc,$pcrel17a2 */
2462   {
2463     MEP_INSN_BCPNE, "bcpne", "bcpne", 32,
2464     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2465   },
2466 /* bcpat $cccc,$pcrel17a2 */
2467   {
2468     MEP_INSN_BCPAT, "bcpat", "bcpat", 32,
2469     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2470   },
2471 /* bcpaf $cccc,$pcrel17a2 */
2472   {
2473     MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32,
2474     { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2475   },
2476 /* synccp */
2477   {
2478     MEP_INSN_SYNCCP, "synccp", "synccp", 16,
2479     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2480   },
2481 /* jsrv $rm */
2482   {
2483     MEP_INSN_JSRV, "jsrv", "jsrv", 16,
2484     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2485   },
2486 /* bsrv $pcrel24a2 */
2487   {
2488     MEP_INSN_BSRV, "bsrv", "bsrv", 32,
2489     { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2490   },
2491 /* --syscall-- */
2492   {
2493     MEP_INSN_SIM_SYSCALL, "sim-syscall", "--syscall--", 16,
2494     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2495   },
2496 /* --reserved-- */
2497   {
2498     MEP_INSN_RI_0, "ri-0", "--reserved--", 16,
2499     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2500   },
2501 /* --reserved-- */
2502   {
2503     MEP_INSN_RI_1, "ri-1", "--reserved--", 16,
2504     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2505   },
2506 /* --reserved-- */
2507   {
2508     MEP_INSN_RI_2, "ri-2", "--reserved--", 16,
2509     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2510   },
2511 /* --reserved-- */
2512   {
2513     MEP_INSN_RI_3, "ri-3", "--reserved--", 16,
2514     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2515   },
2516 /* --reserved-- */
2517   {
2518     MEP_INSN_RI_4, "ri-4", "--reserved--", 16,
2519     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2520   },
2521 /* --reserved-- */
2522   {
2523     MEP_INSN_RI_5, "ri-5", "--reserved--", 16,
2524     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2525   },
2526 /* --reserved-- */
2527   {
2528     MEP_INSN_RI_6, "ri-6", "--reserved--", 16,
2529     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2530   },
2531 /* --reserved-- */
2532   {
2533     MEP_INSN_RI_7, "ri-7", "--reserved--", 16,
2534     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2535   },
2536 /* --reserved-- */
2537   {
2538     MEP_INSN_RI_8, "ri-8", "--reserved--", 16,
2539     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2540   },
2541 /* --reserved-- */
2542   {
2543     MEP_INSN_RI_9, "ri-9", "--reserved--", 16,
2544     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2545   },
2546 /* --reserved-- */
2547   {
2548     MEP_INSN_RI_10, "ri-10", "--reserved--", 16,
2549     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2550   },
2551 /* --reserved-- */
2552   {
2553     MEP_INSN_RI_11, "ri-11", "--reserved--", 16,
2554     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2555   },
2556 /* --reserved-- */
2557   {
2558     MEP_INSN_RI_12, "ri-12", "--reserved--", 16,
2559     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2560   },
2561 /* --reserved-- */
2562   {
2563     MEP_INSN_RI_13, "ri-13", "--reserved--", 16,
2564     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2565   },
2566 /* --reserved-- */
2567   {
2568     MEP_INSN_RI_14, "ri-14", "--reserved--", 16,
2569     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2570   },
2571 /* --reserved-- */
2572   {
2573     MEP_INSN_RI_15, "ri-15", "--reserved--", 16,
2574     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2575   },
2576 /* --reserved-- */
2577   {
2578     MEP_INSN_RI_17, "ri-17", "--reserved--", 16,
2579     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2580   },
2581 /* --reserved-- */
2582   {
2583     MEP_INSN_RI_20, "ri-20", "--reserved--", 16,
2584     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2585   },
2586 /* --reserved-- */
2587   {
2588     MEP_INSN_RI_21, "ri-21", "--reserved--", 16,
2589     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2590   },
2591 /* --reserved-- */
2592   {
2593     MEP_INSN_RI_22, "ri-22", "--reserved--", 16,
2594     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2595   },
2596 /* --reserved-- */
2597   {
2598     MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
2599     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2600   },
2601 /* --reserved-- */
2602   {
2603     MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
2604     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
2605   },
2606 /* cmov $crnx64,$rm */
2607   {
2608     MEP_INSN_CMOV_CRN_RM, "cmov-crn-rm", "cmov", 32,
2609     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2610   },
2611 /* cmov $rm,$crnx64 */
2612   {
2613     MEP_INSN_CMOV_RN_CRM, "cmov-rn-crm", "cmov", 32,
2614     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2615   },
2616 /* cmovc $ivc2c3ccrn,$rm */
2617   {
2618     MEP_INSN_CMOVC_CCRN_RM, "cmovc-ccrn-rm", "cmovc", 32,
2619     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2620   },
2621 /* cmovc $rm,$ivc2c3ccrn */
2622   {
2623     MEP_INSN_CMOVC_RN_CCRM, "cmovc-rn-ccrm", "cmovc", 32,
2624     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2625   },
2626 /* cmovh $crnx64,$rm */
2627   {
2628     MEP_INSN_CMOVH_CRN_RM, "cmovh-crn-rm", "cmovh", 32,
2629     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2630   },
2631 /* cmovh $rm,$crnx64 */
2632   {
2633     MEP_INSN_CMOVH_RN_CRM, "cmovh-rn-crm", "cmovh", 32,
2634     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2635   },
2636 /* cmov $ivc2crn,$ivc2rm */
2637   {
2638     MEP_INSN_CMOV_CRN_RM_P0, "cmov-crn-rm-p0", "cmov", 32,
2639     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2640   },
2641 /* cmov $ivc2rm,$ivc2crn */
2642   {
2643     MEP_INSN_CMOV_RN_CRM_P0, "cmov-rn-crm-p0", "cmov", 32,
2644     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2645   },
2646 /* cmovc $ivc2ccrn,$ivc2rm */
2647   {
2648     MEP_INSN_CMOVC_CCRN_RM_P0, "cmovc-ccrn-rm-p0", "cmovc", 32,
2649     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2650   },
2651 /* cmovc $ivc2rm,$ivc2ccrn */
2652   {
2653     MEP_INSN_CMOVC_RN_CCRM_P0, "cmovc-rn-ccrm-p0", "cmovc", 32,
2654     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2655   },
2656 /* cmovh $ivc2crn,$ivc2rm */
2657   {
2658     MEP_INSN_CMOVH_CRN_RM_P0, "cmovh-crn-rm-p0", "cmovh", 32,
2659     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2660   },
2661 /* cmovh $ivc2rm,$ivc2crn */
2662   {
2663     MEP_INSN_CMOVH_RN_CRM_P0, "cmovh-rn-crm-p0", "cmovh", 32,
2664     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
2665   },
2666 /* cpadd3.b $croc,$crqc,$crpc */
2667   {
2668     MEP_INSN_CPADD3_B_C3, "cpadd3_b_C3", "cpadd3.b", 32,
2669     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2670   },
2671 /* cpadd3.h $croc,$crqc,$crpc */
2672   {
2673     MEP_INSN_CPADD3_H_C3, "cpadd3_h_C3", "cpadd3.h", 32,
2674     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2675   },
2676 /* cpadd3.w $croc,$crqc,$crpc */
2677   {
2678     MEP_INSN_CPADD3_W_C3, "cpadd3_w_C3", "cpadd3.w", 32,
2679     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2680   },
2681 /* cdadd3 $croc,$crqc,$crpc */
2682   {
2683     MEP_INSN_CDADD3_C3, "cdadd3_C3", "cdadd3", 32,
2684     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2685   },
2686 /* cpsub3.b $croc,$crqc,$crpc */
2687   {
2688     MEP_INSN_CPSUB3_B_C3, "cpsub3_b_C3", "cpsub3.b", 32,
2689     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2690   },
2691 /* cpsub3.h $croc,$crqc,$crpc */
2692   {
2693     MEP_INSN_CPSUB3_H_C3, "cpsub3_h_C3", "cpsub3.h", 32,
2694     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2695   },
2696 /* cpsub3.w $croc,$crqc,$crpc */
2697   {
2698     MEP_INSN_CPSUB3_W_C3, "cpsub3_w_C3", "cpsub3.w", 32,
2699     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2700   },
2701 /* cdsub3 $croc,$crqc,$crpc */
2702   {
2703     MEP_INSN_CDSUB3_C3, "cdsub3_C3", "cdsub3", 32,
2704     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2705   },
2706 /* cpand3 $croc,$crqc,$crpc */
2707   {
2708     MEP_INSN_CPAND3_C3, "cpand3_C3", "cpand3", 32,
2709     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2710   },
2711 /* cpor3 $croc,$crqc,$crpc */
2712   {
2713     MEP_INSN_CPOR3_C3, "cpor3_C3", "cpor3", 32,
2714     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2715   },
2716 /* cpnor3 $croc,$crqc,$crpc */
2717   {
2718     MEP_INSN_CPNOR3_C3, "cpnor3_C3", "cpnor3", 32,
2719     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2720   },
2721 /* cpxor3 $croc,$crqc,$crpc */
2722   {
2723     MEP_INSN_CPXOR3_C3, "cpxor3_C3", "cpxor3", 32,
2724     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2725   },
2726 /* cpsel $croc,$crqc,$crpc */
2727   {
2728     MEP_INSN_CPSEL_C3, "cpsel_C3", "cpsel", 32,
2729     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2730   },
2731 /* cpfsftbi $croc,$crqc,$crpc,$imm3p4 */
2732   {
2733     MEP_INSN_CPFSFTBI_C3, "cpfsftbi_C3", "cpfsftbi", 32,
2734     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2735   },
2736 /* cpfsftbs0 $croc,$crqc,$crpc */
2737   {
2738     MEP_INSN_CPFSFTBS0_C3, "cpfsftbs0_C3", "cpfsftbs0", 32,
2739     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2740   },
2741 /* cpfsftbs1 $croc,$crqc,$crpc */
2742   {
2743     MEP_INSN_CPFSFTBS1_C3, "cpfsftbs1_C3", "cpfsftbs1", 32,
2744     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2745   },
2746 /* cpunpacku.b $croc,$crqc,$crpc */
2747   {
2748     MEP_INSN_CPUNPACKU_B_C3, "cpunpacku_b_C3", "cpunpacku.b", 32,
2749     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2750   },
2751 /* cpunpacku.h $croc,$crqc,$crpc */
2752   {
2753     MEP_INSN_CPUNPACKU_H_C3, "cpunpacku_h_C3", "cpunpacku.h", 32,
2754     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2755   },
2756 /* cpunpacku.w $croc,$crqc,$crpc */
2757   {
2758     MEP_INSN_CPUNPACKU_W_C3, "cpunpacku_w_C3", "cpunpacku.w", 32,
2759     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2760   },
2761 /* cpunpackl.b $croc,$crqc,$crpc */
2762   {
2763     MEP_INSN_CPUNPACKL_B_C3, "cpunpackl_b_C3", "cpunpackl.b", 32,
2764     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2765   },
2766 /* cpunpackl.h $croc,$crqc,$crpc */
2767   {
2768     MEP_INSN_CPUNPACKL_H_C3, "cpunpackl_h_C3", "cpunpackl.h", 32,
2769     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2770   },
2771 /* cpunpackl.w $croc,$crqc,$crpc */
2772   {
2773     MEP_INSN_CPUNPACKL_W_C3, "cpunpackl_w_C3", "cpunpackl.w", 32,
2774     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2775   },
2776 /* cppacku.b $croc,$crqc,$crpc */
2777   {
2778     MEP_INSN_CPPACKU_B_C3, "cppacku_b_C3", "cppacku.b", 32,
2779     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2780   },
2781 /* cppack.b $croc,$crqc,$crpc */
2782   {
2783     MEP_INSN_CPPACK_B_C3, "cppack_b_C3", "cppack.b", 32,
2784     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2785   },
2786 /* cppack.h $croc,$crqc,$crpc */
2787   {
2788     MEP_INSN_CPPACK_H_C3, "cppack_h_C3", "cppack.h", 32,
2789     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2790   },
2791 /* cpsrl3.b $croc,$crqc,$crpc */
2792   {
2793     MEP_INSN_CPSRL3_B_C3, "cpsrl3_b_C3", "cpsrl3.b", 32,
2794     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2795   },
2796 /* cpssrl3.b $croc,$crqc,$crpc */
2797   {
2798     MEP_INSN_CPSSRL3_B_C3, "cpssrl3_b_C3", "cpssrl3.b", 32,
2799     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2800   },
2801 /* cpsrl3.h $croc,$crqc,$crpc */
2802   {
2803     MEP_INSN_CPSRL3_H_C3, "cpsrl3_h_C3", "cpsrl3.h", 32,
2804     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2805   },
2806 /* cpssrl3.h $croc,$crqc,$crpc */
2807   {
2808     MEP_INSN_CPSSRL3_H_C3, "cpssrl3_h_C3", "cpssrl3.h", 32,
2809     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2810   },
2811 /* cpsrl3.w $croc,$crqc,$crpc */
2812   {
2813     MEP_INSN_CPSRL3_W_C3, "cpsrl3_w_C3", "cpsrl3.w", 32,
2814     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2815   },
2816 /* cpssrl3.w $croc,$crqc,$crpc */
2817   {
2818     MEP_INSN_CPSSRL3_W_C3, "cpssrl3_w_C3", "cpssrl3.w", 32,
2819     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2820   },
2821 /* cdsrl3 $croc,$crqc,$crpc */
2822   {
2823     MEP_INSN_CDSRL3_C3, "cdsrl3_C3", "cdsrl3", 32,
2824     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2825   },
2826 /* cpsra3.b $croc,$crqc,$crpc */
2827   {
2828     MEP_INSN_CPSRA3_B_C3, "cpsra3_b_C3", "cpsra3.b", 32,
2829     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2830   },
2831 /* cpssra3.b $croc,$crqc,$crpc */
2832   {
2833     MEP_INSN_CPSSRA3_B_C3, "cpssra3_b_C3", "cpssra3.b", 32,
2834     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2835   },
2836 /* cpsra3.h $croc,$crqc,$crpc */
2837   {
2838     MEP_INSN_CPSRA3_H_C3, "cpsra3_h_C3", "cpsra3.h", 32,
2839     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2840   },
2841 /* cpssra3.h $croc,$crqc,$crpc */
2842   {
2843     MEP_INSN_CPSSRA3_H_C3, "cpssra3_h_C3", "cpssra3.h", 32,
2844     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2845   },
2846 /* cpsra3.w $croc,$crqc,$crpc */
2847   {
2848     MEP_INSN_CPSRA3_W_C3, "cpsra3_w_C3", "cpsra3.w", 32,
2849     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2850   },
2851 /* cpssra3.w $croc,$crqc,$crpc */
2852   {
2853     MEP_INSN_CPSSRA3_W_C3, "cpssra3_w_C3", "cpssra3.w", 32,
2854     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2855   },
2856 /* cdsra3 $croc,$crqc,$crpc */
2857   {
2858     MEP_INSN_CDSRA3_C3, "cdsra3_C3", "cdsra3", 32,
2859     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2860   },
2861 /* cpsll3.b $croc,$crqc,$crpc */
2862   {
2863     MEP_INSN_CPSLL3_B_C3, "cpsll3_b_C3", "cpsll3.b", 32,
2864     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2865   },
2866 /* cpssll3.b $croc,$crqc,$crpc */
2867   {
2868     MEP_INSN_CPSSLL3_B_C3, "cpssll3_b_C3", "cpssll3.b", 32,
2869     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2870   },
2871 /* cpsll3.h $croc,$crqc,$crpc */
2872   {
2873     MEP_INSN_CPSLL3_H_C3, "cpsll3_h_C3", "cpsll3.h", 32,
2874     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2875   },
2876 /* cpssll3.h $croc,$crqc,$crpc */
2877   {
2878     MEP_INSN_CPSSLL3_H_C3, "cpssll3_h_C3", "cpssll3.h", 32,
2879     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2880   },
2881 /* cpsll3.w $croc,$crqc,$crpc */
2882   {
2883     MEP_INSN_CPSLL3_W_C3, "cpsll3_w_C3", "cpsll3.w", 32,
2884     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2885   },
2886 /* cpssll3.w $croc,$crqc,$crpc */
2887   {
2888     MEP_INSN_CPSSLL3_W_C3, "cpssll3_w_C3", "cpssll3.w", 32,
2889     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2890   },
2891 /* cdsll3 $croc,$crqc,$crpc */
2892   {
2893     MEP_INSN_CDSLL3_C3, "cdsll3_C3", "cdsll3", 32,
2894     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2895   },
2896 /* cpsla3.h $croc,$crqc,$crpc */
2897   {
2898     MEP_INSN_CPSLA3_H_C3, "cpsla3_h_C3", "cpsla3.h", 32,
2899     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2900   },
2901 /* cpsla3.w $croc,$crqc,$crpc */
2902   {
2903     MEP_INSN_CPSLA3_W_C3, "cpsla3_w_C3", "cpsla3.w", 32,
2904     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2905   },
2906 /* cpsadd3.h $croc,$crqc,$crpc */
2907   {
2908     MEP_INSN_CPSADD3_H_C3, "cpsadd3_h_C3", "cpsadd3.h", 32,
2909     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2910   },
2911 /* cpsadd3.w $croc,$crqc,$crpc */
2912   {
2913     MEP_INSN_CPSADD3_W_C3, "cpsadd3_w_C3", "cpsadd3.w", 32,
2914     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2915   },
2916 /* cpssub3.h $croc,$crqc,$crpc */
2917   {
2918     MEP_INSN_CPSSUB3_H_C3, "cpssub3_h_C3", "cpssub3.h", 32,
2919     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2920   },
2921 /* cpssub3.w $croc,$crqc,$crpc */
2922   {
2923     MEP_INSN_CPSSUB3_W_C3, "cpssub3_w_C3", "cpssub3.w", 32,
2924     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2925   },
2926 /* cpextuaddu3.b $croc,$crqc,$crpc */
2927   {
2928     MEP_INSN_CPEXTUADDU3_B_C3, "cpextuaddu3_b_C3", "cpextuaddu3.b", 32,
2929     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2930   },
2931 /* cpextuadd3.b $croc,$crqc,$crpc */
2932   {
2933     MEP_INSN_CPEXTUADD3_B_C3, "cpextuadd3_b_C3", "cpextuadd3.b", 32,
2934     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2935   },
2936 /* cpextladdu3.b $croc,$crqc,$crpc */
2937   {
2938     MEP_INSN_CPEXTLADDU3_B_C3, "cpextladdu3_b_C3", "cpextladdu3.b", 32,
2939     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2940   },
2941 /* cpextladd3.b $croc,$crqc,$crpc */
2942   {
2943     MEP_INSN_CPEXTLADD3_B_C3, "cpextladd3_b_C3", "cpextladd3.b", 32,
2944     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2945   },
2946 /* cpextusubu3.b $croc,$crqc,$crpc */
2947   {
2948     MEP_INSN_CPEXTUSUBU3_B_C3, "cpextusubu3_b_C3", "cpextusubu3.b", 32,
2949     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2950   },
2951 /* cpextusub3.b $croc,$crqc,$crpc */
2952   {
2953     MEP_INSN_CPEXTUSUB3_B_C3, "cpextusub3_b_C3", "cpextusub3.b", 32,
2954     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2955   },
2956 /* cpextlsubu3.b $croc,$crqc,$crpc */
2957   {
2958     MEP_INSN_CPEXTLSUBU3_B_C3, "cpextlsubu3_b_C3", "cpextlsubu3.b", 32,
2959     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2960   },
2961 /* cpextlsub3.b $croc,$crqc,$crpc */
2962   {
2963     MEP_INSN_CPEXTLSUB3_B_C3, "cpextlsub3_b_C3", "cpextlsub3.b", 32,
2964     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2965   },
2966 /* cpaveu3.b $croc,$crqc,$crpc */
2967   {
2968     MEP_INSN_CPAVEU3_B_C3, "cpaveu3_b_C3", "cpaveu3.b", 32,
2969     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2970   },
2971 /* cpave3.b $croc,$crqc,$crpc */
2972   {
2973     MEP_INSN_CPAVE3_B_C3, "cpave3_b_C3", "cpave3.b", 32,
2974     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2975   },
2976 /* cpave3.h $croc,$crqc,$crpc */
2977   {
2978     MEP_INSN_CPAVE3_H_C3, "cpave3_h_C3", "cpave3.h", 32,
2979     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2980   },
2981 /* cpave3.w $croc,$crqc,$crpc */
2982   {
2983     MEP_INSN_CPAVE3_W_C3, "cpave3_w_C3", "cpave3.w", 32,
2984     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2985   },
2986 /* cpaddsru3.b $croc,$crqc,$crpc */
2987   {
2988     MEP_INSN_CPADDSRU3_B_C3, "cpaddsru3_b_C3", "cpaddsru3.b", 32,
2989     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2990   },
2991 /* cpaddsr3.b $croc,$crqc,$crpc */
2992   {
2993     MEP_INSN_CPADDSR3_B_C3, "cpaddsr3_b_C3", "cpaddsr3.b", 32,
2994     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
2995   },
2996 /* cpaddsr3.h $croc,$crqc,$crpc */
2997   {
2998     MEP_INSN_CPADDSR3_H_C3, "cpaddsr3_h_C3", "cpaddsr3.h", 32,
2999     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3000   },
3001 /* cpaddsr3.w $croc,$crqc,$crpc */
3002   {
3003     MEP_INSN_CPADDSR3_W_C3, "cpaddsr3_w_C3", "cpaddsr3.w", 32,
3004     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3005   },
3006 /* cpabsu3.b $croc,$crqc,$crpc */
3007   {
3008     MEP_INSN_CPABSU3_B_C3, "cpabsu3_b_C3", "cpabsu3.b", 32,
3009     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3010   },
3011 /* cpabs3.b $croc,$crqc,$crpc */
3012   {
3013     MEP_INSN_CPABS3_B_C3, "cpabs3_b_C3", "cpabs3.b", 32,
3014     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3015   },
3016 /* cpabs3.h $croc,$crqc,$crpc */
3017   {
3018     MEP_INSN_CPABS3_H_C3, "cpabs3_h_C3", "cpabs3.h", 32,
3019     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3020   },
3021 /* cpmaxu3.b $croc,$crqc,$crpc */
3022   {
3023     MEP_INSN_CPMAXU3_B_C3, "cpmaxu3_b_C3", "cpmaxu3.b", 32,
3024     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3025   },
3026 /* cpmax3.b $croc,$crqc,$crpc */
3027   {
3028     MEP_INSN_CPMAX3_B_C3, "cpmax3_b_C3", "cpmax3.b", 32,
3029     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3030   },
3031 /* cpmax3.h $croc,$crqc,$crpc */
3032   {
3033     MEP_INSN_CPMAX3_H_C3, "cpmax3_h_C3", "cpmax3.h", 32,
3034     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3035   },
3036 /* cpmaxu3.w $croc,$crqc,$crpc */
3037   {
3038     MEP_INSN_CPMAXU3_W_C3, "cpmaxu3_w_C3", "cpmaxu3.w", 32,
3039     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3040   },
3041 /* cpmax3.w $croc,$crqc,$crpc */
3042   {
3043     MEP_INSN_CPMAX3_W_C3, "cpmax3_w_C3", "cpmax3.w", 32,
3044     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3045   },
3046 /* cpminu3.b $croc,$crqc,$crpc */
3047   {
3048     MEP_INSN_CPMINU3_B_C3, "cpminu3_b_C3", "cpminu3.b", 32,
3049     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3050   },
3051 /* cpmin3.b $croc,$crqc,$crpc */
3052   {
3053     MEP_INSN_CPMIN3_B_C3, "cpmin3_b_C3", "cpmin3.b", 32,
3054     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3055   },
3056 /* cpmin3.h $croc,$crqc,$crpc */
3057   {
3058     MEP_INSN_CPMIN3_H_C3, "cpmin3_h_C3", "cpmin3.h", 32,
3059     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3060   },
3061 /* cpminu3.w $croc,$crqc,$crpc */
3062   {
3063     MEP_INSN_CPMINU3_W_C3, "cpminu3_w_C3", "cpminu3.w", 32,
3064     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3065   },
3066 /* cpmin3.w $croc,$crqc,$crpc */
3067   {
3068     MEP_INSN_CPMIN3_W_C3, "cpmin3_w_C3", "cpmin3.w", 32,
3069     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3070   },
3071 /* cpmovfrcsar0 $croc */
3072   {
3073     MEP_INSN_CPMOVFRCSAR0_C3, "cpmovfrcsar0_C3", "cpmovfrcsar0", 32,
3074     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3075   },
3076 /* cpmovfrcsar1 $croc */
3077   {
3078     MEP_INSN_CPMOVFRCSAR1_C3, "cpmovfrcsar1_C3", "cpmovfrcsar1", 32,
3079     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3080   },
3081 /* cpmovfrcc $croc */
3082   {
3083     MEP_INSN_CPMOVFRCC_C3, "cpmovfrcc_C3", "cpmovfrcc", 32,
3084     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3085   },
3086 /* cpmovtocsar0 $crqc */
3087   {
3088     MEP_INSN_CPMOVTOCSAR0_C3, "cpmovtocsar0_C3", "cpmovtocsar0", 32,
3089     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3090   },
3091 /* cpmovtocsar1 $crqc */
3092   {
3093     MEP_INSN_CPMOVTOCSAR1_C3, "cpmovtocsar1_C3", "cpmovtocsar1", 32,
3094     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3095   },
3096 /* cpmovtocc $crqc */
3097   {
3098     MEP_INSN_CPMOVTOCC_C3, "cpmovtocc_C3", "cpmovtocc", 32,
3099     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3100   },
3101 /* cpmov $croc,$crqc */
3102   {
3103     MEP_INSN_CPMOV_C3, "cpmov_C3", "cpmov", 32,
3104     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3105   },
3106 /* cpabsz.b $croc,$crqc */
3107   {
3108     MEP_INSN_CPABSZ_B_C3, "cpabsz_b_C3", "cpabsz.b", 32,
3109     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3110   },
3111 /* cpabsz.h $croc,$crqc */
3112   {
3113     MEP_INSN_CPABSZ_H_C3, "cpabsz_h_C3", "cpabsz.h", 32,
3114     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3115   },
3116 /* cpabsz.w $croc,$crqc */
3117   {
3118     MEP_INSN_CPABSZ_W_C3, "cpabsz_w_C3", "cpabsz.w", 32,
3119     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3120   },
3121 /* cpldz.h $croc,$crqc */
3122   {
3123     MEP_INSN_CPLDZ_H_C3, "cpldz_h_C3", "cpldz.h", 32,
3124     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3125   },
3126 /* cpldz.w $croc,$crqc */
3127   {
3128     MEP_INSN_CPLDZ_W_C3, "cpldz_w_C3", "cpldz.w", 32,
3129     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3130   },
3131 /* cpnorm.h $croc,$crqc */
3132   {
3133     MEP_INSN_CPNORM_H_C3, "cpnorm_h_C3", "cpnorm.h", 32,
3134     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3135   },
3136 /* cpnorm.w $croc,$crqc */
3137   {
3138     MEP_INSN_CPNORM_W_C3, "cpnorm_w_C3", "cpnorm.w", 32,
3139     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3140   },
3141 /* cphaddu.b $croc,$crqc */
3142   {
3143     MEP_INSN_CPHADDU_B_C3, "cphaddu_b_C3", "cphaddu.b", 32,
3144     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3145   },
3146 /* cphadd.b $croc,$crqc */
3147   {
3148     MEP_INSN_CPHADD_B_C3, "cphadd_b_C3", "cphadd.b", 32,
3149     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3150   },
3151 /* cphadd.h $croc,$crqc */
3152   {
3153     MEP_INSN_CPHADD_H_C3, "cphadd_h_C3", "cphadd.h", 32,
3154     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3155   },
3156 /* cphadd.w $croc,$crqc */
3157   {
3158     MEP_INSN_CPHADD_W_C3, "cphadd_w_C3", "cphadd.w", 32,
3159     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3160   },
3161 /* cpccadd.b $crqc */
3162   {
3163     MEP_INSN_CPCCADD_B_C3, "cpccadd_b_C3", "cpccadd.b", 32,
3164     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRSTCOPY, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3165   },
3166 /* cpbcast.b $croc,$crqc */
3167   {
3168     MEP_INSN_CPBCAST_B_C3, "cpbcast_b_C3", "cpbcast.b", 32,
3169     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3170   },
3171 /* cpbcast.h $croc,$crqc */
3172   {
3173     MEP_INSN_CPBCAST_H_C3, "cpbcast_h_C3", "cpbcast.h", 32,
3174     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3175   },
3176 /* cpbcast.w $croc,$crqc */
3177   {
3178     MEP_INSN_CPBCAST_W_C3, "cpbcast_w_C3", "cpbcast.w", 32,
3179     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3180   },
3181 /* cpextuu.b $croc,$crqc */
3182   {
3183     MEP_INSN_CPEXTUU_B_C3, "cpextuu_b_C3", "cpextuu.b", 32,
3184     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3185   },
3186 /* cpextu.b $croc,$crqc */
3187   {
3188     MEP_INSN_CPEXTU_B_C3, "cpextu_b_C3", "cpextu.b", 32,
3189     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3190   },
3191 /* cpextuu.h $croc,$crqc */
3192   {
3193     MEP_INSN_CPEXTUU_H_C3, "cpextuu_h_C3", "cpextuu.h", 32,
3194     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3195   },
3196 /* cpextu.h $croc,$crqc */
3197   {
3198     MEP_INSN_CPEXTU_H_C3, "cpextu_h_C3", "cpextu.h", 32,
3199     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3200   },
3201 /* cpextlu.b $croc,$crqc */
3202   {
3203     MEP_INSN_CPEXTLU_B_C3, "cpextlu_b_C3", "cpextlu.b", 32,
3204     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3205   },
3206 /* cpextl.b $croc,$crqc */
3207   {
3208     MEP_INSN_CPEXTL_B_C3, "cpextl_b_C3", "cpextl.b", 32,
3209     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3210   },
3211 /* cpextlu.h $croc,$crqc */
3212   {
3213     MEP_INSN_CPEXTLU_H_C3, "cpextlu_h_C3", "cpextlu.h", 32,
3214     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3215   },
3216 /* cpextl.h $croc,$crqc */
3217   {
3218     MEP_INSN_CPEXTL_H_C3, "cpextl_h_C3", "cpextl.h", 32,
3219     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3220   },
3221 /* cpcastub.h $croc,$crqc */
3222   {
3223     MEP_INSN_CPCASTUB_H_C3, "cpcastub_h_C3", "cpcastub.h", 32,
3224     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3225   },
3226 /* cpcastb.h $croc,$crqc */
3227   {
3228     MEP_INSN_CPCASTB_H_C3, "cpcastb_h_C3", "cpcastb.h", 32,
3229     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3230   },
3231 /* cpcastub.w $croc,$crqc */
3232   {
3233     MEP_INSN_CPCASTUB_W_C3, "cpcastub_w_C3", "cpcastub.w", 32,
3234     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3235   },
3236 /* cpcastb.w $croc,$crqc */
3237   {
3238     MEP_INSN_CPCASTB_W_C3, "cpcastb_w_C3", "cpcastb.w", 32,
3239     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3240   },
3241 /* cpcastuh.w $croc,$crqc */
3242   {
3243     MEP_INSN_CPCASTUH_W_C3, "cpcastuh_w_C3", "cpcastuh.w", 32,
3244     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3245   },
3246 /* cpcasth.w $croc,$crqc */
3247   {
3248     MEP_INSN_CPCASTH_W_C3, "cpcasth_w_C3", "cpcasth.w", 32,
3249     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3250   },
3251 /* cdcastuw $croc,$crqc */
3252   {
3253     MEP_INSN_CDCASTUW_C3, "cdcastuw_C3", "cdcastuw", 32,
3254     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3255   },
3256 /* cdcastw $croc,$crqc */
3257   {
3258     MEP_INSN_CDCASTW_C3, "cdcastw_C3", "cdcastw", 32,
3259     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3260   },
3261 /* cpcmpeqz.b $crqc,$crpc */
3262   {
3263     MEP_INSN_CPCMPEQZ_B_C3, "cpcmpeqz_b_C3", "cpcmpeqz.b", 32,
3264     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3265   },
3266 /* cpcmpeq.b $crqc,$crpc */
3267   {
3268     MEP_INSN_CPCMPEQ_B_C3, "cpcmpeq_b_C3", "cpcmpeq.b", 32,
3269     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3270   },
3271 /* cpcmpeq.h $crqc,$crpc */
3272   {
3273     MEP_INSN_CPCMPEQ_H_C3, "cpcmpeq_h_C3", "cpcmpeq.h", 32,
3274     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3275   },
3276 /* cpcmpeq.w $crqc,$crpc */
3277   {
3278     MEP_INSN_CPCMPEQ_W_C3, "cpcmpeq_w_C3", "cpcmpeq.w", 32,
3279     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3280   },
3281 /* cpcmpne.b $crqc,$crpc */
3282   {
3283     MEP_INSN_CPCMPNE_B_C3, "cpcmpne_b_C3", "cpcmpne.b", 32,
3284     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3285   },
3286 /* cpcmpne.h $crqc,$crpc */
3287   {
3288     MEP_INSN_CPCMPNE_H_C3, "cpcmpne_h_C3", "cpcmpne.h", 32,
3289     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3290   },
3291 /* cpcmpne.w $crqc,$crpc */
3292   {
3293     MEP_INSN_CPCMPNE_W_C3, "cpcmpne_w_C3", "cpcmpne.w", 32,
3294     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3295   },
3296 /* cpcmpgtu.b $crqc,$crpc */
3297   {
3298     MEP_INSN_CPCMPGTU_B_C3, "cpcmpgtu_b_C3", "cpcmpgtu.b", 32,
3299     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3300   },
3301 /* cpcmpgt.b $crqc,$crpc */
3302   {
3303     MEP_INSN_CPCMPGT_B_C3, "cpcmpgt_b_C3", "cpcmpgt.b", 32,
3304     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3305   },
3306 /* cpcmpgt.h $crqc,$crpc */
3307   {
3308     MEP_INSN_CPCMPGT_H_C3, "cpcmpgt_h_C3", "cpcmpgt.h", 32,
3309     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3310   },
3311 /* cpcmpgtu.w $crqc,$crpc */
3312   {
3313     MEP_INSN_CPCMPGTU_W_C3, "cpcmpgtu_w_C3", "cpcmpgtu.w", 32,
3314     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3315   },
3316 /* cpcmpgt.w $crqc,$crpc */
3317   {
3318     MEP_INSN_CPCMPGT_W_C3, "cpcmpgt_w_C3", "cpcmpgt.w", 32,
3319     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3320   },
3321 /* cpcmpgeu.b $crqc,$crpc */
3322   {
3323     MEP_INSN_CPCMPGEU_B_C3, "cpcmpgeu_b_C3", "cpcmpgeu.b", 32,
3324     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3325   },
3326 /* cpcmpge.b $crqc,$crpc */
3327   {
3328     MEP_INSN_CPCMPGE_B_C3, "cpcmpge_b_C3", "cpcmpge.b", 32,
3329     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3330   },
3331 /* cpcmpge.h $crqc,$crpc */
3332   {
3333     MEP_INSN_CPCMPGE_H_C3, "cpcmpge_h_C3", "cpcmpge.h", 32,
3334     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3335   },
3336 /* cpcmpgeu.w $crqc,$crpc */
3337   {
3338     MEP_INSN_CPCMPGEU_W_C3, "cpcmpgeu_w_C3", "cpcmpgeu.w", 32,
3339     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3340   },
3341 /* cpcmpge.w $crqc,$crpc */
3342   {
3343     MEP_INSN_CPCMPGE_W_C3, "cpcmpge_w_C3", "cpcmpge.w", 32,
3344     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3345   },
3346 /* cpacmpeq.b $crqc,$crpc */
3347   {
3348     MEP_INSN_CPACMPEQ_B_C3, "cpacmpeq_b_C3", "cpacmpeq.b", 32,
3349     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3350   },
3351 /* cpacmpeq.h $crqc,$crpc */
3352   {
3353     MEP_INSN_CPACMPEQ_H_C3, "cpacmpeq_h_C3", "cpacmpeq.h", 32,
3354     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3355   },
3356 /* cpacmpeq.w $crqc,$crpc */
3357   {
3358     MEP_INSN_CPACMPEQ_W_C3, "cpacmpeq_w_C3", "cpacmpeq.w", 32,
3359     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3360   },
3361 /* cpacmpne.b $crqc,$crpc */
3362   {
3363     MEP_INSN_CPACMPNE_B_C3, "cpacmpne_b_C3", "cpacmpne.b", 32,
3364     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3365   },
3366 /* cpacmpne.h $crqc,$crpc */
3367   {
3368     MEP_INSN_CPACMPNE_H_C3, "cpacmpne_h_C3", "cpacmpne.h", 32,
3369     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3370   },
3371 /* cpacmpne.w $crqc,$crpc */
3372   {
3373     MEP_INSN_CPACMPNE_W_C3, "cpacmpne_w_C3", "cpacmpne.w", 32,
3374     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3375   },
3376 /* cpacmpgtu.b $crqc,$crpc */
3377   {
3378     MEP_INSN_CPACMPGTU_B_C3, "cpacmpgtu_b_C3", "cpacmpgtu.b", 32,
3379     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3380   },
3381 /* cpacmpgt.b $crqc,$crpc */
3382   {
3383     MEP_INSN_CPACMPGT_B_C3, "cpacmpgt_b_C3", "cpacmpgt.b", 32,
3384     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3385   },
3386 /* cpacmpgt.h $crqc,$crpc */
3387   {
3388     MEP_INSN_CPACMPGT_H_C3, "cpacmpgt_h_C3", "cpacmpgt.h", 32,
3389     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3390   },
3391 /* cpacmpgtu.w $crqc,$crpc */
3392   {
3393     MEP_INSN_CPACMPGTU_W_C3, "cpacmpgtu_w_C3", "cpacmpgtu.w", 32,
3394     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3395   },
3396 /* cpacmpgt.w $crqc,$crpc */
3397   {
3398     MEP_INSN_CPACMPGT_W_C3, "cpacmpgt_w_C3", "cpacmpgt.w", 32,
3399     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3400   },
3401 /* cpacmpgeu.b $crqc,$crpc */
3402   {
3403     MEP_INSN_CPACMPGEU_B_C3, "cpacmpgeu_b_C3", "cpacmpgeu.b", 32,
3404     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3405   },
3406 /* cpacmpge.b $crqc,$crpc */
3407   {
3408     MEP_INSN_CPACMPGE_B_C3, "cpacmpge_b_C3", "cpacmpge.b", 32,
3409     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3410   },
3411 /* cpacmpge.h $crqc,$crpc */
3412   {
3413     MEP_INSN_CPACMPGE_H_C3, "cpacmpge_h_C3", "cpacmpge.h", 32,
3414     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3415   },
3416 /* cpacmpgeu.w $crqc,$crpc */
3417   {
3418     MEP_INSN_CPACMPGEU_W_C3, "cpacmpgeu_w_C3", "cpacmpgeu.w", 32,
3419     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3420   },
3421 /* cpacmpge.w $crqc,$crpc */
3422   {
3423     MEP_INSN_CPACMPGE_W_C3, "cpacmpge_w_C3", "cpacmpge.w", 32,
3424     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3425   },
3426 /* cpocmpeq.b $crqc,$crpc */
3427   {
3428     MEP_INSN_CPOCMPEQ_B_C3, "cpocmpeq_b_C3", "cpocmpeq.b", 32,
3429     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3430   },
3431 /* cpocmpeq.h $crqc,$crpc */
3432   {
3433     MEP_INSN_CPOCMPEQ_H_C3, "cpocmpeq_h_C3", "cpocmpeq.h", 32,
3434     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3435   },
3436 /* cpocmpeq.w $crqc,$crpc */
3437   {
3438     MEP_INSN_CPOCMPEQ_W_C3, "cpocmpeq_w_C3", "cpocmpeq.w", 32,
3439     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3440   },
3441 /* cpocmpne.b $crqc,$crpc */
3442   {
3443     MEP_INSN_CPOCMPNE_B_C3, "cpocmpne_b_C3", "cpocmpne.b", 32,
3444     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3445   },
3446 /* cpocmpne.h $crqc,$crpc */
3447   {
3448     MEP_INSN_CPOCMPNE_H_C3, "cpocmpne_h_C3", "cpocmpne.h", 32,
3449     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3450   },
3451 /* cpocmpne.w $crqc,$crpc */
3452   {
3453     MEP_INSN_CPOCMPNE_W_C3, "cpocmpne_w_C3", "cpocmpne.w", 32,
3454     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3455   },
3456 /* cpocmpgtu.b $crqc,$crpc */
3457   {
3458     MEP_INSN_CPOCMPGTU_B_C3, "cpocmpgtu_b_C3", "cpocmpgtu.b", 32,
3459     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3460   },
3461 /* cpocmpgt.b $crqc,$crpc */
3462   {
3463     MEP_INSN_CPOCMPGT_B_C3, "cpocmpgt_b_C3", "cpocmpgt.b", 32,
3464     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3465   },
3466 /* cpocmpgt.h $crqc,$crpc */
3467   {
3468     MEP_INSN_CPOCMPGT_H_C3, "cpocmpgt_h_C3", "cpocmpgt.h", 32,
3469     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3470   },
3471 /* cpocmpgtu.w $crqc,$crpc */
3472   {
3473     MEP_INSN_CPOCMPGTU_W_C3, "cpocmpgtu_w_C3", "cpocmpgtu.w", 32,
3474     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3475   },
3476 /* cpocmpgt.w $crqc,$crpc */
3477   {
3478     MEP_INSN_CPOCMPGT_W_C3, "cpocmpgt_w_C3", "cpocmpgt.w", 32,
3479     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3480   },
3481 /* cpocmpgeu.b $crqc,$crpc */
3482   {
3483     MEP_INSN_CPOCMPGEU_B_C3, "cpocmpgeu_b_C3", "cpocmpgeu.b", 32,
3484     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3485   },
3486 /* cpocmpge.b $crqc,$crpc */
3487   {
3488     MEP_INSN_CPOCMPGE_B_C3, "cpocmpge_b_C3", "cpocmpge.b", 32,
3489     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3490   },
3491 /* cpocmpge.h $crqc,$crpc */
3492   {
3493     MEP_INSN_CPOCMPGE_H_C3, "cpocmpge_h_C3", "cpocmpge.h", 32,
3494     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3495   },
3496 /* cpocmpgeu.w $crqc,$crpc */
3497   {
3498     MEP_INSN_CPOCMPGEU_W_C3, "cpocmpgeu_w_C3", "cpocmpgeu.w", 32,
3499     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3500   },
3501 /* cpocmpge.w $crqc,$crpc */
3502   {
3503     MEP_INSN_CPOCMPGE_W_C3, "cpocmpge_w_C3", "cpocmpge.w", 32,
3504     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3505   },
3506 /* cpsrli3.b $crqc,$crpc,$imm3p9 */
3507   {
3508     MEP_INSN_CPSRLI3_B_C3, "cpsrli3_b_C3", "cpsrli3.b", 32,
3509     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3510   },
3511 /* cpsrli3.h $crqc,$crpc,$imm4p8 */
3512   {
3513     MEP_INSN_CPSRLI3_H_C3, "cpsrli3_h_C3", "cpsrli3.h", 32,
3514     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3515   },
3516 /* cpsrli3.w $crqc,$crpc,$imm5p7 */
3517   {
3518     MEP_INSN_CPSRLI3_W_C3, "cpsrli3_w_C3", "cpsrli3.w", 32,
3519     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3520   },
3521 /* cdsrli3 $crqc,$crpc,$imm6p6 */
3522   {
3523     MEP_INSN_CDSRLI3_C3, "cdsrli3_C3", "cdsrli3", 32,
3524     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3525   },
3526 /* cpsrai3.b $crqc,$crpc,$imm3p9 */
3527   {
3528     MEP_INSN_CPSRAI3_B_C3, "cpsrai3_b_C3", "cpsrai3.b", 32,
3529     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3530   },
3531 /* cpsrai3.h $crqc,$crpc,$imm4p8 */
3532   {
3533     MEP_INSN_CPSRAI3_H_C3, "cpsrai3_h_C3", "cpsrai3.h", 32,
3534     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3535   },
3536 /* cpsrai3.w $crqc,$crpc,$imm5p7 */
3537   {
3538     MEP_INSN_CPSRAI3_W_C3, "cpsrai3_w_C3", "cpsrai3.w", 32,
3539     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3540   },
3541 /* cdsrai3 $crqc,$crpc,$imm6p6 */
3542   {
3543     MEP_INSN_CDSRAI3_C3, "cdsrai3_C3", "cdsrai3", 32,
3544     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3545   },
3546 /* cpslli3.b $crqc,$crpc,$imm3p9 */
3547   {
3548     MEP_INSN_CPSLLI3_B_C3, "cpslli3_b_C3", "cpslli3.b", 32,
3549     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3550   },
3551 /* cpslli3.h $crqc,$crpc,$imm4p8 */
3552   {
3553     MEP_INSN_CPSLLI3_H_C3, "cpslli3_h_C3", "cpslli3.h", 32,
3554     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3555   },
3556 /* cpslli3.w $crqc,$crpc,$imm5p7 */
3557   {
3558     MEP_INSN_CPSLLI3_W_C3, "cpslli3_w_C3", "cpslli3.w", 32,
3559     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3560   },
3561 /* cdslli3 $crqc,$crpc,$imm6p6 */
3562   {
3563     MEP_INSN_CDSLLI3_C3, "cdslli3_C3", "cdslli3", 32,
3564     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3565   },
3566 /* cpslai3.h $crqc,$crpc,$imm4p8 */
3567   {
3568     MEP_INSN_CPSLAI3_H_C3, "cpslai3_h_C3", "cpslai3.h", 32,
3569     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3570   },
3571 /* cpslai3.w $crqc,$crpc,$imm5p7 */
3572   {
3573     MEP_INSN_CPSLAI3_W_C3, "cpslai3_w_C3", "cpslai3.w", 32,
3574     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3575   },
3576 /* cpclipiu3.w $crqc,$crpc,$imm5p7 */
3577   {
3578     MEP_INSN_CPCLIPIU3_W_C3, "cpclipiu3_w_C3", "cpclipiu3.w", 32,
3579     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3580   },
3581 /* cpclipi3.w $crqc,$crpc,$imm5p7 */
3582   {
3583     MEP_INSN_CPCLIPI3_W_C3, "cpclipi3_w_C3", "cpclipi3.w", 32,
3584     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3585   },
3586 /* cdclipiu3 $crqc,$crpc,$imm6p6 */
3587   {
3588     MEP_INSN_CDCLIPIU3_C3, "cdclipiu3_C3", "cdclipiu3", 32,
3589     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3590   },
3591 /* cdclipi3 $crqc,$crpc,$imm6p6 */
3592   {
3593     MEP_INSN_CDCLIPI3_C3, "cdclipi3_C3", "cdclipi3", 32,
3594     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3595   },
3596 /* cpmovi.b $crqc,$simm8p4 */
3597   {
3598     MEP_INSN_CPMOVI_B_C3, "cpmovi_b_C3", "cpmovi.b", 32,
3599     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3600   },
3601 /* cpmoviu.h $crqc,$imm8p4 */
3602   {
3603     MEP_INSN_CPMOVIU_H_C3, "cpmoviu_h_C3", "cpmoviu.h", 32,
3604     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3605   },
3606 /* cpmovi.h $crqc,$simm8p4 */
3607   {
3608     MEP_INSN_CPMOVI_H_C3, "cpmovi_h_C3", "cpmovi.h", 32,
3609     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3610   },
3611 /* cpmoviu.w $crqc,$imm8p4 */
3612   {
3613     MEP_INSN_CPMOVIU_W_C3, "cpmoviu_w_C3", "cpmoviu.w", 32,
3614     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3615   },
3616 /* cpmovi.w $crqc,$simm8p4 */
3617   {
3618     MEP_INSN_CPMOVI_W_C3, "cpmovi_w_C3", "cpmovi.w", 32,
3619     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3620   },
3621 /* cdmoviu $crqc,$imm8p4 */
3622   {
3623     MEP_INSN_CDMOVIU_C3, "cdmoviu_C3", "cdmoviu", 32,
3624     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3625   },
3626 /* cdmovi $crqc,$simm8p4 */
3627   {
3628     MEP_INSN_CDMOVI_C3, "cdmovi_C3", "cdmovi", 32,
3629     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3630   },
3631 /* cpadda1u.b $crqc,$crpc */
3632   {
3633     MEP_INSN_CPADDA1U_B_C3, "cpadda1u_b_C3", "cpadda1u.b", 32,
3634     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3635   },
3636 /* cpadda1.b $crqc,$crpc */
3637   {
3638     MEP_INSN_CPADDA1_B_C3, "cpadda1_b_C3", "cpadda1.b", 32,
3639     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3640   },
3641 /* cpaddua1.h $crqc,$crpc */
3642   {
3643     MEP_INSN_CPADDUA1_H_C3, "cpaddua1_h_C3", "cpaddua1.h", 32,
3644     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3645   },
3646 /* cpaddla1.h $crqc,$crpc */
3647   {
3648     MEP_INSN_CPADDLA1_H_C3, "cpaddla1_h_C3", "cpaddla1.h", 32,
3649     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3650   },
3651 /* cpaddaca1u.b $crqc,$crpc */
3652   {
3653     MEP_INSN_CPADDACA1U_B_C3, "cpaddaca1u_b_C3", "cpaddaca1u.b", 32,
3654     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3655   },
3656 /* cpaddaca1.b $crqc,$crpc */
3657   {
3658     MEP_INSN_CPADDACA1_B_C3, "cpaddaca1_b_C3", "cpaddaca1.b", 32,
3659     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3660   },
3661 /* cpaddacua1.h $crqc,$crpc */
3662   {
3663     MEP_INSN_CPADDACUA1_H_C3, "cpaddacua1_h_C3", "cpaddacua1.h", 32,
3664     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3665   },
3666 /* cpaddacla1.h $crqc,$crpc */
3667   {
3668     MEP_INSN_CPADDACLA1_H_C3, "cpaddacla1_h_C3", "cpaddacla1.h", 32,
3669     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3670   },
3671 /* cpsuba1u.b $crqc,$crpc */
3672   {
3673     MEP_INSN_CPSUBA1U_B_C3, "cpsuba1u_b_C3", "cpsuba1u.b", 32,
3674     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3675   },
3676 /* cpsuba1.b $crqc,$crpc */
3677   {
3678     MEP_INSN_CPSUBA1_B_C3, "cpsuba1_b_C3", "cpsuba1.b", 32,
3679     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3680   },
3681 /* cpsubua1.h $crqc,$crpc */
3682   {
3683     MEP_INSN_CPSUBUA1_H_C3, "cpsubua1_h_C3", "cpsubua1.h", 32,
3684     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3685   },
3686 /* cpsubla1.h $crqc,$crpc */
3687   {
3688     MEP_INSN_CPSUBLA1_H_C3, "cpsubla1_h_C3", "cpsubla1.h", 32,
3689     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3690   },
3691 /* cpsubaca1u.b $crqc,$crpc */
3692   {
3693     MEP_INSN_CPSUBACA1U_B_C3, "cpsubaca1u_b_C3", "cpsubaca1u.b", 32,
3694     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3695   },
3696 /* cpsubaca1.b $crqc,$crpc */
3697   {
3698     MEP_INSN_CPSUBACA1_B_C3, "cpsubaca1_b_C3", "cpsubaca1.b", 32,
3699     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3700   },
3701 /* cpsubacua1.h $crqc,$crpc */
3702   {
3703     MEP_INSN_CPSUBACUA1_H_C3, "cpsubacua1_h_C3", "cpsubacua1.h", 32,
3704     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3705   },
3706 /* cpsubacla1.h $crqc,$crpc */
3707   {
3708     MEP_INSN_CPSUBACLA1_H_C3, "cpsubacla1_h_C3", "cpsubacla1.h", 32,
3709     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3710   },
3711 /* cpabsa1u.b $crqc,$crpc */
3712   {
3713     MEP_INSN_CPABSA1U_B_C3, "cpabsa1u_b_C3", "cpabsa1u.b", 32,
3714     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3715   },
3716 /* cpabsa1.b $crqc,$crpc */
3717   {
3718     MEP_INSN_CPABSA1_B_C3, "cpabsa1_b_C3", "cpabsa1.b", 32,
3719     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3720   },
3721 /* cpabsua1.h $crqc,$crpc */
3722   {
3723     MEP_INSN_CPABSUA1_H_C3, "cpabsua1_h_C3", "cpabsua1.h", 32,
3724     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3725   },
3726 /* cpabsla1.h $crqc,$crpc */
3727   {
3728     MEP_INSN_CPABSLA1_H_C3, "cpabsla1_h_C3", "cpabsla1.h", 32,
3729     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3730   },
3731 /* cpsada1u.b $crqc,$crpc */
3732   {
3733     MEP_INSN_CPSADA1U_B_C3, "cpsada1u_b_C3", "cpsada1u.b", 32,
3734     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3735   },
3736 /* cpsada1.b $crqc,$crpc */
3737   {
3738     MEP_INSN_CPSADA1_B_C3, "cpsada1_b_C3", "cpsada1.b", 32,
3739     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3740   },
3741 /* cpsadua1.h $crqc,$crpc */
3742   {
3743     MEP_INSN_CPSADUA1_H_C3, "cpsadua1_h_C3", "cpsadua1.h", 32,
3744     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3745   },
3746 /* cpsadla1.h $crqc,$crpc */
3747   {
3748     MEP_INSN_CPSADLA1_H_C3, "cpsadla1_h_C3", "cpsadla1.h", 32,
3749     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3750   },
3751 /* cpseta1.h $crqc,$crpc */
3752   {
3753     MEP_INSN_CPSETA1_H_C3, "cpseta1_h_C3", "cpseta1.h", 32,
3754     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3755   },
3756 /* cpsetua1.w $crqc,$crpc */
3757   {
3758     MEP_INSN_CPSETUA1_W_C3, "cpsetua1_w_C3", "cpsetua1.w", 32,
3759     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3760   },
3761 /* cpsetla1.w $crqc,$crpc */
3762   {
3763     MEP_INSN_CPSETLA1_W_C3, "cpsetla1_w_C3", "cpsetla1.w", 32,
3764     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3765   },
3766 /* cpmova1.b $croc */
3767   {
3768     MEP_INSN_CPMOVA1_B_C3, "cpmova1_b_C3", "cpmova1.b", 32,
3769     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3770   },
3771 /* cpmovua1.h $croc */
3772   {
3773     MEP_INSN_CPMOVUA1_H_C3, "cpmovua1_h_C3", "cpmovua1.h", 32,
3774     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3775   },
3776 /* cpmovla1.h $croc */
3777   {
3778     MEP_INSN_CPMOVLA1_H_C3, "cpmovla1_h_C3", "cpmovla1.h", 32,
3779     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3780   },
3781 /* cpmovuua1.w $croc */
3782   {
3783     MEP_INSN_CPMOVUUA1_W_C3, "cpmovuua1_w_C3", "cpmovuua1.w", 32,
3784     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3785   },
3786 /* cpmovula1.w $croc */
3787   {
3788     MEP_INSN_CPMOVULA1_W_C3, "cpmovula1_w_C3", "cpmovula1.w", 32,
3789     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3790   },
3791 /* cpmovlua1.w $croc */
3792   {
3793     MEP_INSN_CPMOVLUA1_W_C3, "cpmovlua1_w_C3", "cpmovlua1.w", 32,
3794     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3795   },
3796 /* cpmovlla1.w $croc */
3797   {
3798     MEP_INSN_CPMOVLLA1_W_C3, "cpmovlla1_w_C3", "cpmovlla1.w", 32,
3799     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3800   },
3801 /* cppacka1u.b $croc */
3802   {
3803     MEP_INSN_CPPACKA1U_B_C3, "cppacka1u_b_C3", "cppacka1u.b", 32,
3804     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3805   },
3806 /* cppacka1.b $croc */
3807   {
3808     MEP_INSN_CPPACKA1_B_C3, "cppacka1_b_C3", "cppacka1.b", 32,
3809     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3810   },
3811 /* cppackua1.h $croc */
3812   {
3813     MEP_INSN_CPPACKUA1_H_C3, "cppackua1_h_C3", "cppackua1.h", 32,
3814     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3815   },
3816 /* cppackla1.h $croc */
3817   {
3818     MEP_INSN_CPPACKLA1_H_C3, "cppackla1_h_C3", "cppackla1.h", 32,
3819     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3820   },
3821 /* cppackua1.w $croc */
3822   {
3823     MEP_INSN_CPPACKUA1_W_C3, "cppackua1_w_C3", "cppackua1.w", 32,
3824     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3825   },
3826 /* cppackla1.w $croc */
3827   {
3828     MEP_INSN_CPPACKLA1_W_C3, "cppackla1_w_C3", "cppackla1.w", 32,
3829     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3830   },
3831 /* cpmovhua1.w $croc */
3832   {
3833     MEP_INSN_CPMOVHUA1_W_C3, "cpmovhua1_w_C3", "cpmovhua1.w", 32,
3834     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3835   },
3836 /* cpmovhla1.w $croc */
3837   {
3838     MEP_INSN_CPMOVHLA1_W_C3, "cpmovhla1_w_C3", "cpmovhla1.w", 32,
3839     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3840   },
3841 /* cpsrla1 $crqc */
3842   {
3843     MEP_INSN_CPSRLA1_C3, "cpsrla1_C3", "cpsrla1", 32,
3844     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3845   },
3846 /* cpsraa1 $crqc */
3847   {
3848     MEP_INSN_CPSRAA1_C3, "cpsraa1_C3", "cpsraa1", 32,
3849     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3850   },
3851 /* cpslla1 $crqc */
3852   {
3853     MEP_INSN_CPSLLA1_C3, "cpslla1_C3", "cpslla1", 32,
3854     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3855   },
3856 /* cpsrlia1 $imm5p7 */
3857   {
3858     MEP_INSN_CPSRLIA1_P1, "cpsrlia1_P1", "cpsrlia1", 32,
3859     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3860   },
3861 /* cpsraia1 $imm5p7 */
3862   {
3863     MEP_INSN_CPSRAIA1_P1, "cpsraia1_P1", "cpsraia1", 32,
3864     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3865   },
3866 /* cpsllia1 $imm5p7 */
3867   {
3868     MEP_INSN_CPSLLIA1_P1, "cpsllia1_P1", "cpsllia1", 32,
3869     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3870   },
3871 /* cpssqa1u.b $crqc,$crpc */
3872   {
3873     MEP_INSN_CPSSQA1U_B_C3, "cpssqa1u_b_C3", "cpssqa1u.b", 32,
3874     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3875   },
3876 /* cpssqa1.b $crqc,$crpc */
3877   {
3878     MEP_INSN_CPSSQA1_B_C3, "cpssqa1_b_C3", "cpssqa1.b", 32,
3879     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3880   },
3881 /* cpssda1u.b $crqc,$crpc */
3882   {
3883     MEP_INSN_CPSSDA1U_B_C3, "cpssda1u_b_C3", "cpssda1u.b", 32,
3884     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3885   },
3886 /* cpssda1.b $crqc,$crpc */
3887   {
3888     MEP_INSN_CPSSDA1_B_C3, "cpssda1_b_C3", "cpssda1.b", 32,
3889     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3890   },
3891 /* cpmula1u.b $crqc,$crpc */
3892   {
3893     MEP_INSN_CPMULA1U_B_C3, "cpmula1u_b_C3", "cpmula1u.b", 32,
3894     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3895   },
3896 /* cpmula1.b $crqc,$crpc */
3897   {
3898     MEP_INSN_CPMULA1_B_C3, "cpmula1_b_C3", "cpmula1.b", 32,
3899     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3900   },
3901 /* cpmulua1.h $crqc,$crpc */
3902   {
3903     MEP_INSN_CPMULUA1_H_C3, "cpmulua1_h_C3", "cpmulua1.h", 32,
3904     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3905   },
3906 /* cpmulla1.h $crqc,$crpc */
3907   {
3908     MEP_INSN_CPMULLA1_H_C3, "cpmulla1_h_C3", "cpmulla1.h", 32,
3909     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3910   },
3911 /* cpmulua1u.w $crqc,$crpc */
3912   {
3913     MEP_INSN_CPMULUA1U_W_C3, "cpmulua1u_w_C3", "cpmulua1u.w", 32,
3914     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3915   },
3916 /* cpmulla1u.w $crqc,$crpc */
3917   {
3918     MEP_INSN_CPMULLA1U_W_C3, "cpmulla1u_w_C3", "cpmulla1u.w", 32,
3919     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3920   },
3921 /* cpmulua1.w $crqc,$crpc */
3922   {
3923     MEP_INSN_CPMULUA1_W_C3, "cpmulua1_w_C3", "cpmulua1.w", 32,
3924     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3925   },
3926 /* cpmulla1.w $crqc,$crpc */
3927   {
3928     MEP_INSN_CPMULLA1_W_C3, "cpmulla1_w_C3", "cpmulla1.w", 32,
3929     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3930   },
3931 /* cpmada1u.b $crqc,$crpc */
3932   {
3933     MEP_INSN_CPMADA1U_B_C3, "cpmada1u_b_C3", "cpmada1u.b", 32,
3934     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3935   },
3936 /* cpmada1.b $crqc,$crpc */
3937   {
3938     MEP_INSN_CPMADA1_B_C3, "cpmada1_b_C3", "cpmada1.b", 32,
3939     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3940   },
3941 /* cpmadua1.h $crqc,$crpc */
3942   {
3943     MEP_INSN_CPMADUA1_H_C3, "cpmadua1_h_C3", "cpmadua1.h", 32,
3944     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3945   },
3946 /* cpmadla1.h $crqc,$crpc */
3947   {
3948     MEP_INSN_CPMADLA1_H_C3, "cpmadla1_h_C3", "cpmadla1.h", 32,
3949     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3950   },
3951 /* cpmadua1u.w $crqc,$crpc */
3952   {
3953     MEP_INSN_CPMADUA1U_W_C3, "cpmadua1u_w_C3", "cpmadua1u.w", 32,
3954     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3955   },
3956 /* cpmadla1u.w $crqc,$crpc */
3957   {
3958     MEP_INSN_CPMADLA1U_W_C3, "cpmadla1u_w_C3", "cpmadla1u.w", 32,
3959     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3960   },
3961 /* cpmadua1.w $crqc,$crpc */
3962   {
3963     MEP_INSN_CPMADUA1_W_C3, "cpmadua1_w_C3", "cpmadua1.w", 32,
3964     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3965   },
3966 /* cpmadla1.w $crqc,$crpc */
3967   {
3968     MEP_INSN_CPMADLA1_W_C3, "cpmadla1_w_C3", "cpmadla1.w", 32,
3969     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3970   },
3971 /* cpmsbua1.h $crqc,$crpc */
3972   {
3973     MEP_INSN_CPMSBUA1_H_C3, "cpmsbua1_h_C3", "cpmsbua1.h", 32,
3974     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3975   },
3976 /* cpmsbla1.h $crqc,$crpc */
3977   {
3978     MEP_INSN_CPMSBLA1_H_C3, "cpmsbla1_h_C3", "cpmsbla1.h", 32,
3979     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3980   },
3981 /* cpmsbua1u.w $crqc,$crpc */
3982   {
3983     MEP_INSN_CPMSBUA1U_W_C3, "cpmsbua1u_w_C3", "cpmsbua1u.w", 32,
3984     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3985   },
3986 /* cpmsbla1u.w $crqc,$crpc */
3987   {
3988     MEP_INSN_CPMSBLA1U_W_C3, "cpmsbla1u_w_C3", "cpmsbla1u.w", 32,
3989     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3990   },
3991 /* cpmsbua1.w $crqc,$crpc */
3992   {
3993     MEP_INSN_CPMSBUA1_W_C3, "cpmsbua1_w_C3", "cpmsbua1.w", 32,
3994     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
3995   },
3996 /* cpmsbla1.w $crqc,$crpc */
3997   {
3998     MEP_INSN_CPMSBLA1_W_C3, "cpmsbla1_w_C3", "cpmsbla1.w", 32,
3999     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4000   },
4001 /* cpsmadua1.h $crqc,$crpc */
4002   {
4003     MEP_INSN_CPSMADUA1_H_C3, "cpsmadua1_h_C3", "cpsmadua1.h", 32,
4004     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4005   },
4006 /* cpsmadla1.h $crqc,$crpc */
4007   {
4008     MEP_INSN_CPSMADLA1_H_C3, "cpsmadla1_h_C3", "cpsmadla1.h", 32,
4009     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4010   },
4011 /* cpsmadua1.w $crqc,$crpc */
4012   {
4013     MEP_INSN_CPSMADUA1_W_C3, "cpsmadua1_w_C3", "cpsmadua1.w", 32,
4014     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4015   },
4016 /* cpsmadla1.w $crqc,$crpc */
4017   {
4018     MEP_INSN_CPSMADLA1_W_C3, "cpsmadla1_w_C3", "cpsmadla1.w", 32,
4019     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4020   },
4021 /* cpsmsbua1.h $crqc,$crpc */
4022   {
4023     MEP_INSN_CPSMSBUA1_H_C3, "cpsmsbua1_h_C3", "cpsmsbua1.h", 32,
4024     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4025   },
4026 /* cpsmsbla1.h $crqc,$crpc */
4027   {
4028     MEP_INSN_CPSMSBLA1_H_C3, "cpsmsbla1_h_C3", "cpsmsbla1.h", 32,
4029     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4030   },
4031 /* cpsmsbua1.w $crqc,$crpc */
4032   {
4033     MEP_INSN_CPSMSBUA1_W_C3, "cpsmsbua1_w_C3", "cpsmsbua1.w", 32,
4034     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4035   },
4036 /* cpsmsbla1.w $crqc,$crpc */
4037   {
4038     MEP_INSN_CPSMSBLA1_W_C3, "cpsmsbla1_w_C3", "cpsmsbla1.w", 32,
4039     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4040   },
4041 /* cpmulslua1.h $crqc,$crpc */
4042   {
4043     MEP_INSN_CPMULSLUA1_H_C3, "cpmulslua1_h_C3", "cpmulslua1.h", 32,
4044     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4045   },
4046 /* cpmulslla1.h $crqc,$crpc */
4047   {
4048     MEP_INSN_CPMULSLLA1_H_C3, "cpmulslla1_h_C3", "cpmulslla1.h", 32,
4049     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4050   },
4051 /* cpmulslua1.w $crqc,$crpc */
4052   {
4053     MEP_INSN_CPMULSLUA1_W_C3, "cpmulslua1_w_C3", "cpmulslua1.w", 32,
4054     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4055   },
4056 /* cpmulslla1.w $crqc,$crpc */
4057   {
4058     MEP_INSN_CPMULSLLA1_W_C3, "cpmulslla1_w_C3", "cpmulslla1.w", 32,
4059     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4060   },
4061 /* cpsmadslua1.h $crqc,$crpc */
4062   {
4063     MEP_INSN_CPSMADSLUA1_H_C3, "cpsmadslua1_h_C3", "cpsmadslua1.h", 32,
4064     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4065   },
4066 /* cpsmadslla1.h $crqc,$crpc */
4067   {
4068     MEP_INSN_CPSMADSLLA1_H_C3, "cpsmadslla1_h_C3", "cpsmadslla1.h", 32,
4069     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4070   },
4071 /* cpsmadslua1.w $crqc,$crpc */
4072   {
4073     MEP_INSN_CPSMADSLUA1_W_C3, "cpsmadslua1_w_C3", "cpsmadslua1.w", 32,
4074     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4075   },
4076 /* cpsmadslla1.w $crqc,$crpc */
4077   {
4078     MEP_INSN_CPSMADSLLA1_W_C3, "cpsmadslla1_w_C3", "cpsmadslla1.w", 32,
4079     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4080   },
4081 /* cpsmsbslua1.h $crqc,$crpc */
4082   {
4083     MEP_INSN_CPSMSBSLUA1_H_C3, "cpsmsbslua1_h_C3", "cpsmsbslua1.h", 32,
4084     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4085   },
4086 /* cpsmsbslla1.h $crqc,$crpc */
4087   {
4088     MEP_INSN_CPSMSBSLLA1_H_C3, "cpsmsbslla1_h_C3", "cpsmsbslla1.h", 32,
4089     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4090   },
4091 /* cpsmsbslua1.w $crqc,$crpc */
4092   {
4093     MEP_INSN_CPSMSBSLUA1_W_C3, "cpsmsbslua1_w_C3", "cpsmsbslua1.w", 32,
4094     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4095   },
4096 /* cpsmsbslla1.w $crqc,$crpc */
4097   {
4098     MEP_INSN_CPSMSBSLLA1_W_C3, "cpsmsbslla1_w_C3", "cpsmsbslla1.w", 32,
4099     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
4100   },
4101 /* c0nop */
4102   {
4103     MEP_INSN_C0NOP_P0_P0S, "c0nop_P0_P0S", "c0nop", 32,
4104     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x28" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P0S), 0 } } } }
4105   },
4106 /* cpadd3.b $crop,$crqp,$crpp */
4107   {
4108     MEP_INSN_CPADD3_B_P0S_P1, "cpadd3_b_P0S_P1", "cpadd3.b", 32,
4109     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4110   },
4111 /* cpadd3.h $crop,$crqp,$crpp */
4112   {
4113     MEP_INSN_CPADD3_H_P0S_P1, "cpadd3_h_P0S_P1", "cpadd3.h", 32,
4114     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4115   },
4116 /* cpadd3.w $crop,$crqp,$crpp */
4117   {
4118     MEP_INSN_CPADD3_W_P0S_P1, "cpadd3_w_P0S_P1", "cpadd3.w", 32,
4119     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4120   },
4121 /* cpunpacku.b $crop,$crqp,$crpp */
4122   {
4123     MEP_INSN_CPUNPACKU_B_P0S_P1, "cpunpacku_b_P0S_P1", "cpunpacku.b", 32,
4124     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4125   },
4126 /* cpunpacku.h $crop,$crqp,$crpp */
4127   {
4128     MEP_INSN_CPUNPACKU_H_P0S_P1, "cpunpacku_h_P0S_P1", "cpunpacku.h", 32,
4129     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4130   },
4131 /* cpunpacku.w $crop,$crqp,$crpp */
4132   {
4133     MEP_INSN_CPUNPACKU_W_P0S_P1, "cpunpacku_w_P0S_P1", "cpunpacku.w", 32,
4134     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4135   },
4136 /* cpunpackl.b $crop,$crqp,$crpp */
4137   {
4138     MEP_INSN_CPUNPACKL_B_P0S_P1, "cpunpackl_b_P0S_P1", "cpunpackl.b", 32,
4139     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4140   },
4141 /* cpunpackl.h $crop,$crqp,$crpp */
4142   {
4143     MEP_INSN_CPUNPACKL_H_P0S_P1, "cpunpackl_h_P0S_P1", "cpunpackl.h", 32,
4144     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4145   },
4146 /* cpunpackl.w $crop,$crqp,$crpp */
4147   {
4148     MEP_INSN_CPUNPACKL_W_P0S_P1, "cpunpackl_w_P0S_P1", "cpunpackl.w", 32,
4149     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4150   },
4151 /* cpsel $crop,$crqp,$crpp */
4152   {
4153     MEP_INSN_CPSEL_P0S_P1, "cpsel_P0S_P1", "cpsel", 32,
4154     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4155   },
4156 /* cpfsftbs0 $crop,$crqp,$crpp */
4157   {
4158     MEP_INSN_CPFSFTBS0_P0S_P1, "cpfsftbs0_P0S_P1", "cpfsftbs0", 32,
4159     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4160   },
4161 /* cpfsftbs1 $crop,$crqp,$crpp */
4162   {
4163     MEP_INSN_CPFSFTBS1_P0S_P1, "cpfsftbs1_P0S_P1", "cpfsftbs1", 32,
4164     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4165   },
4166 /* cpmov $crop,$crqp */
4167   {
4168     MEP_INSN_CPMOV_P0S_P1, "cpmov_P0S_P1", "cpmov", 32,
4169     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4170   },
4171 /* cpabsz.b $crop,$crqp */
4172   {
4173     MEP_INSN_CPABSZ_B_P0S_P1, "cpabsz_b_P0S_P1", "cpabsz.b", 32,
4174     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4175   },
4176 /* cpabsz.h $crop,$crqp */
4177   {
4178     MEP_INSN_CPABSZ_H_P0S_P1, "cpabsz_h_P0S_P1", "cpabsz.h", 32,
4179     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4180   },
4181 /* cpabsz.w $crop,$crqp */
4182   {
4183     MEP_INSN_CPABSZ_W_P0S_P1, "cpabsz_w_P0S_P1", "cpabsz.w", 32,
4184     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4185   },
4186 /* cpldz.h $crop,$crqp */
4187   {
4188     MEP_INSN_CPLDZ_H_P0S_P1, "cpldz_h_P0S_P1", "cpldz.h", 32,
4189     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4190   },
4191 /* cpldz.w $crop,$crqp */
4192   {
4193     MEP_INSN_CPLDZ_W_P0S_P1, "cpldz_w_P0S_P1", "cpldz.w", 32,
4194     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4195   },
4196 /* cpnorm.h $crop,$crqp */
4197   {
4198     MEP_INSN_CPNORM_H_P0S_P1, "cpnorm_h_P0S_P1", "cpnorm.h", 32,
4199     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4200   },
4201 /* cpnorm.w $crop,$crqp */
4202   {
4203     MEP_INSN_CPNORM_W_P0S_P1, "cpnorm_w_P0S_P1", "cpnorm.w", 32,
4204     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4205   },
4206 /* cphaddu.b $crop,$crqp */
4207   {
4208     MEP_INSN_CPHADDU_B_P0S_P1, "cphaddu_b_P0S_P1", "cphaddu.b", 32,
4209     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4210   },
4211 /* cphadd.b $crop,$crqp */
4212   {
4213     MEP_INSN_CPHADD_B_P0S_P1, "cphadd_b_P0S_P1", "cphadd.b", 32,
4214     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4215   },
4216 /* cphadd.h $crop,$crqp */
4217   {
4218     MEP_INSN_CPHADD_H_P0S_P1, "cphadd_h_P0S_P1", "cphadd.h", 32,
4219     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4220   },
4221 /* cphadd.w $crop,$crqp */
4222   {
4223     MEP_INSN_CPHADD_W_P0S_P1, "cphadd_w_P0S_P1", "cphadd.w", 32,
4224     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4225   },
4226 /* cpccadd.b $crqp */
4227   {
4228     MEP_INSN_CPCCADD_B_P0S_P1, "cpccadd_b_P0S_P1", "cpccadd.b", 32,
4229     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRSTCOPY, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4230   },
4231 /* cpbcast.b $crop,$crqp */
4232   {
4233     MEP_INSN_CPBCAST_B_P0S_P1, "cpbcast_b_P0S_P1", "cpbcast.b", 32,
4234     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4235   },
4236 /* cpbcast.h $crop,$crqp */
4237   {
4238     MEP_INSN_CPBCAST_H_P0S_P1, "cpbcast_h_P0S_P1", "cpbcast.h", 32,
4239     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4240   },
4241 /* cpbcast.w $crop,$crqp */
4242   {
4243     MEP_INSN_CPBCAST_W_P0S_P1, "cpbcast_w_P0S_P1", "cpbcast.w", 32,
4244     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4245   },
4246 /* cpextuu.b $crop,$crqp */
4247   {
4248     MEP_INSN_CPEXTUU_B_P0S_P1, "cpextuu_b_P0S_P1", "cpextuu.b", 32,
4249     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4250   },
4251 /* cpextu.b $crop,$crqp */
4252   {
4253     MEP_INSN_CPEXTU_B_P0S_P1, "cpextu_b_P0S_P1", "cpextu.b", 32,
4254     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4255   },
4256 /* cpextuu.h $crop,$crqp */
4257   {
4258     MEP_INSN_CPEXTUU_H_P0S_P1, "cpextuu_h_P0S_P1", "cpextuu.h", 32,
4259     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4260   },
4261 /* cpextu.h $crop,$crqp */
4262   {
4263     MEP_INSN_CPEXTU_H_P0S_P1, "cpextu_h_P0S_P1", "cpextu.h", 32,
4264     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4265   },
4266 /* cpextlu.b $crop,$crqp */
4267   {
4268     MEP_INSN_CPEXTLU_B_P0S_P1, "cpextlu_b_P0S_P1", "cpextlu.b", 32,
4269     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4270   },
4271 /* cpextl.b $crop,$crqp */
4272   {
4273     MEP_INSN_CPEXTL_B_P0S_P1, "cpextl_b_P0S_P1", "cpextl.b", 32,
4274     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4275   },
4276 /* cpextlu.h $crop,$crqp */
4277   {
4278     MEP_INSN_CPEXTLU_H_P0S_P1, "cpextlu_h_P0S_P1", "cpextlu.h", 32,
4279     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4280   },
4281 /* cpextl.h $crop,$crqp */
4282   {
4283     MEP_INSN_CPEXTL_H_P0S_P1, "cpextl_h_P0S_P1", "cpextl.h", 32,
4284     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4285   },
4286 /* cpcastub.h $crop,$crqp */
4287   {
4288     MEP_INSN_CPCASTUB_H_P0S_P1, "cpcastub_h_P0S_P1", "cpcastub.h", 32,
4289     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4290   },
4291 /* cpcastb.h $crop,$crqp */
4292   {
4293     MEP_INSN_CPCASTB_H_P0S_P1, "cpcastb_h_P0S_P1", "cpcastb.h", 32,
4294     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4295   },
4296 /* cpcastub.w $crop,$crqp */
4297   {
4298     MEP_INSN_CPCASTUB_W_P0S_P1, "cpcastub_w_P0S_P1", "cpcastub.w", 32,
4299     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4300   },
4301 /* cpcastb.w $crop,$crqp */
4302   {
4303     MEP_INSN_CPCASTB_W_P0S_P1, "cpcastb_w_P0S_P1", "cpcastb.w", 32,
4304     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4305   },
4306 /* cpcastuh.w $crop,$crqp */
4307   {
4308     MEP_INSN_CPCASTUH_W_P0S_P1, "cpcastuh_w_P0S_P1", "cpcastuh.w", 32,
4309     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4310   },
4311 /* cpcasth.w $crop,$crqp */
4312   {
4313     MEP_INSN_CPCASTH_W_P0S_P1, "cpcasth_w_P0S_P1", "cpcasth.w", 32,
4314     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4315   },
4316 /* cdcastuw $crop,$crqp */
4317   {
4318     MEP_INSN_CDCASTUW_P0S_P1, "cdcastuw_P0S_P1", "cdcastuw", 32,
4319     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4320   },
4321 /* cdcastw $crop,$crqp */
4322   {
4323     MEP_INSN_CDCASTW_P0S_P1, "cdcastw_P0S_P1", "cdcastw", 32,
4324     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4325   },
4326 /* cpmovfrcsar0 $crop */
4327   {
4328     MEP_INSN_CPMOVFRCSAR0_P0S_P1, "cpmovfrcsar0_P0S_P1", "cpmovfrcsar0", 32,
4329     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4330   },
4331 /* cpmovfrcsar1 $crop */
4332   {
4333     MEP_INSN_CPMOVFRCSAR1_P0S_P1, "cpmovfrcsar1_P0S_P1", "cpmovfrcsar1", 32,
4334     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4335   },
4336 /* cpmovfrcc $crop */
4337   {
4338     MEP_INSN_CPMOVFRCC_P0S_P1, "cpmovfrcc_P0S_P1", "cpmovfrcc", 32,
4339     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4340   },
4341 /* cpmovtocsar0 $crqp */
4342   {
4343     MEP_INSN_CPMOVTOCSAR0_P0S_P1, "cpmovtocsar0_P0S_P1", "cpmovtocsar0", 32,
4344     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4345   },
4346 /* cpmovtocsar1 $crqp */
4347   {
4348     MEP_INSN_CPMOVTOCSAR1_P0S_P1, "cpmovtocsar1_P0S_P1", "cpmovtocsar1", 32,
4349     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4350   },
4351 /* cpmovtocc $crqp */
4352   {
4353     MEP_INSN_CPMOVTOCC_P0S_P1, "cpmovtocc_P0S_P1", "cpmovtocc", 32,
4354     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4355   },
4356 /* cpcmpeqz.b $crqp,$crpp */
4357   {
4358     MEP_INSN_CPCMPEQZ_B_P0S_P1, "cpcmpeqz_b_P0S_P1", "cpcmpeqz.b", 32,
4359     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4360   },
4361 /* cpcmpeq.b $crqp,$crpp */
4362   {
4363     MEP_INSN_CPCMPEQ_B_P0S_P1, "cpcmpeq_b_P0S_P1", "cpcmpeq.b", 32,
4364     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4365   },
4366 /* cpcmpeq.h $crqp,$crpp */
4367   {
4368     MEP_INSN_CPCMPEQ_H_P0S_P1, "cpcmpeq_h_P0S_P1", "cpcmpeq.h", 32,
4369     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4370   },
4371 /* cpcmpeq.w $crqp,$crpp */
4372   {
4373     MEP_INSN_CPCMPEQ_W_P0S_P1, "cpcmpeq_w_P0S_P1", "cpcmpeq.w", 32,
4374     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4375   },
4376 /* cpcmpne.b $crqp,$crpp */
4377   {
4378     MEP_INSN_CPCMPNE_B_P0S_P1, "cpcmpne_b_P0S_P1", "cpcmpne.b", 32,
4379     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4380   },
4381 /* cpcmpne.h $crqp,$crpp */
4382   {
4383     MEP_INSN_CPCMPNE_H_P0S_P1, "cpcmpne_h_P0S_P1", "cpcmpne.h", 32,
4384     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4385   },
4386 /* cpcmpne.w $crqp,$crpp */
4387   {
4388     MEP_INSN_CPCMPNE_W_P0S_P1, "cpcmpne_w_P0S_P1", "cpcmpne.w", 32,
4389     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4390   },
4391 /* cpcmpgtu.b $crqp,$crpp */
4392   {
4393     MEP_INSN_CPCMPGTU_B_P0S_P1, "cpcmpgtu_b_P0S_P1", "cpcmpgtu.b", 32,
4394     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4395   },
4396 /* cpcmpgt.b $crqp,$crpp */
4397   {
4398     MEP_INSN_CPCMPGT_B_P0S_P1, "cpcmpgt_b_P0S_P1", "cpcmpgt.b", 32,
4399     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4400   },
4401 /* cpcmpgt.h $crqp,$crpp */
4402   {
4403     MEP_INSN_CPCMPGT_H_P0S_P1, "cpcmpgt_h_P0S_P1", "cpcmpgt.h", 32,
4404     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4405   },
4406 /* cpcmpgtu.w $crqp,$crpp */
4407   {
4408     MEP_INSN_CPCMPGTU_W_P0S_P1, "cpcmpgtu_w_P0S_P1", "cpcmpgtu.w", 32,
4409     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4410   },
4411 /* cpcmpgt.w $crqp,$crpp */
4412   {
4413     MEP_INSN_CPCMPGT_W_P0S_P1, "cpcmpgt_w_P0S_P1", "cpcmpgt.w", 32,
4414     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4415   },
4416 /* cpcmpgeu.b $crqp,$crpp */
4417   {
4418     MEP_INSN_CPCMPGEU_B_P0S_P1, "cpcmpgeu_b_P0S_P1", "cpcmpgeu.b", 32,
4419     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4420   },
4421 /* cpcmpge.b $crqp,$crpp */
4422   {
4423     MEP_INSN_CPCMPGE_B_P0S_P1, "cpcmpge_b_P0S_P1", "cpcmpge.b", 32,
4424     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4425   },
4426 /* cpcmpge.h $crqp,$crpp */
4427   {
4428     MEP_INSN_CPCMPGE_H_P0S_P1, "cpcmpge_h_P0S_P1", "cpcmpge.h", 32,
4429     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4430   },
4431 /* cpcmpgeu.w $crqp,$crpp */
4432   {
4433     MEP_INSN_CPCMPGEU_W_P0S_P1, "cpcmpgeu_w_P0S_P1", "cpcmpgeu.w", 32,
4434     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4435   },
4436 /* cpcmpge.w $crqp,$crpp */
4437   {
4438     MEP_INSN_CPCMPGE_W_P0S_P1, "cpcmpge_w_P0S_P1", "cpcmpge.w", 32,
4439     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
4440   },
4441 /* cpadda0u.b $crqp,$crpp */
4442   {
4443     MEP_INSN_CPADDA0U_B_P0S, "cpadda0u_b_P0S", "cpadda0u.b", 32,
4444     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4445   },
4446 /* cpadda0.b $crqp,$crpp */
4447   {
4448     MEP_INSN_CPADDA0_B_P0S, "cpadda0_b_P0S", "cpadda0.b", 32,
4449     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4450   },
4451 /* cpaddua0.h $crqp,$crpp */
4452   {
4453     MEP_INSN_CPADDUA0_H_P0S, "cpaddua0_h_P0S", "cpaddua0.h", 32,
4454     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4455   },
4456 /* cpaddla0.h $crqp,$crpp */
4457   {
4458     MEP_INSN_CPADDLA0_H_P0S, "cpaddla0_h_P0S", "cpaddla0.h", 32,
4459     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4460   },
4461 /* cpaddaca0u.b $crqp,$crpp */
4462   {
4463     MEP_INSN_CPADDACA0U_B_P0S, "cpaddaca0u_b_P0S", "cpaddaca0u.b", 32,
4464     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4465   },
4466 /* cpaddaca0.b $crqp,$crpp */
4467   {
4468     MEP_INSN_CPADDACA0_B_P0S, "cpaddaca0_b_P0S", "cpaddaca0.b", 32,
4469     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4470   },
4471 /* cpaddacua0.h $crqp,$crpp */
4472   {
4473     MEP_INSN_CPADDACUA0_H_P0S, "cpaddacua0_h_P0S", "cpaddacua0.h", 32,
4474     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4475   },
4476 /* cpaddacla0.h $crqp,$crpp */
4477   {
4478     MEP_INSN_CPADDACLA0_H_P0S, "cpaddacla0_h_P0S", "cpaddacla0.h", 32,
4479     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4480   },
4481 /* cpsuba0u.b $crqp,$crpp */
4482   {
4483     MEP_INSN_CPSUBA0U_B_P0S, "cpsuba0u_b_P0S", "cpsuba0u.b", 32,
4484     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4485   },
4486 /* cpsuba0.b $crqp,$crpp */
4487   {
4488     MEP_INSN_CPSUBA0_B_P0S, "cpsuba0_b_P0S", "cpsuba0.b", 32,
4489     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4490   },
4491 /* cpsubua0.h $crqp,$crpp */
4492   {
4493     MEP_INSN_CPSUBUA0_H_P0S, "cpsubua0_h_P0S", "cpsubua0.h", 32,
4494     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4495   },
4496 /* cpsubla0.h $crqp,$crpp */
4497   {
4498     MEP_INSN_CPSUBLA0_H_P0S, "cpsubla0_h_P0S", "cpsubla0.h", 32,
4499     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4500   },
4501 /* cpsubaca0u.b $crqp,$crpp */
4502   {
4503     MEP_INSN_CPSUBACA0U_B_P0S, "cpsubaca0u_b_P0S", "cpsubaca0u.b", 32,
4504     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4505   },
4506 /* cpsubaca0.b $crqp,$crpp */
4507   {
4508     MEP_INSN_CPSUBACA0_B_P0S, "cpsubaca0_b_P0S", "cpsubaca0.b", 32,
4509     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4510   },
4511 /* cpsubacua0.h $crqp,$crpp */
4512   {
4513     MEP_INSN_CPSUBACUA0_H_P0S, "cpsubacua0_h_P0S", "cpsubacua0.h", 32,
4514     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4515   },
4516 /* cpsubacla0.h $crqp,$crpp */
4517   {
4518     MEP_INSN_CPSUBACLA0_H_P0S, "cpsubacla0_h_P0S", "cpsubacla0.h", 32,
4519     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4520   },
4521 /* cpabsa0u.b $crqp,$crpp */
4522   {
4523     MEP_INSN_CPABSA0U_B_P0S, "cpabsa0u_b_P0S", "cpabsa0u.b", 32,
4524     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4525   },
4526 /* cpabsa0.b $crqp,$crpp */
4527   {
4528     MEP_INSN_CPABSA0_B_P0S, "cpabsa0_b_P0S", "cpabsa0.b", 32,
4529     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4530   },
4531 /* cpabsua0.h $crqp,$crpp */
4532   {
4533     MEP_INSN_CPABSUA0_H_P0S, "cpabsua0_h_P0S", "cpabsua0.h", 32,
4534     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4535   },
4536 /* cpabsla0.h $crqp,$crpp */
4537   {
4538     MEP_INSN_CPABSLA0_H_P0S, "cpabsla0_h_P0S", "cpabsla0.h", 32,
4539     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4540   },
4541 /* cpsada0u.b $crqp,$crpp */
4542   {
4543     MEP_INSN_CPSADA0U_B_P0S, "cpsada0u_b_P0S", "cpsada0u.b", 32,
4544     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4545   },
4546 /* cpsada0.b $crqp,$crpp */
4547   {
4548     MEP_INSN_CPSADA0_B_P0S, "cpsada0_b_P0S", "cpsada0.b", 32,
4549     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4550   },
4551 /* cpsadua0.h $crqp,$crpp */
4552   {
4553     MEP_INSN_CPSADUA0_H_P0S, "cpsadua0_h_P0S", "cpsadua0.h", 32,
4554     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4555   },
4556 /* cpsadla0.h $crqp,$crpp */
4557   {
4558     MEP_INSN_CPSADLA0_H_P0S, "cpsadla0_h_P0S", "cpsadla0.h", 32,
4559     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4560   },
4561 /* cpseta0.h $crqp,$crpp */
4562   {
4563     MEP_INSN_CPSETA0_H_P0S, "cpseta0_h_P0S", "cpseta0.h", 32,
4564     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4565   },
4566 /* cpsetua0.w $crqp,$crpp */
4567   {
4568     MEP_INSN_CPSETUA0_W_P0S, "cpsetua0_w_P0S", "cpsetua0.w", 32,
4569     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4570   },
4571 /* cpsetla0.w $crqp,$crpp */
4572   {
4573     MEP_INSN_CPSETLA0_W_P0S, "cpsetla0_w_P0S", "cpsetla0.w", 32,
4574     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4575   },
4576 /* cpmova0.b $crop */
4577   {
4578     MEP_INSN_CPMOVA0_B_P0S, "cpmova0_b_P0S", "cpmova0.b", 32,
4579     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4580   },
4581 /* cpmovua0.h $crop */
4582   {
4583     MEP_INSN_CPMOVUA0_H_P0S, "cpmovua0_h_P0S", "cpmovua0.h", 32,
4584     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4585   },
4586 /* cpmovla0.h $crop */
4587   {
4588     MEP_INSN_CPMOVLA0_H_P0S, "cpmovla0_h_P0S", "cpmovla0.h", 32,
4589     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4590   },
4591 /* cpmovuua0.w $crop */
4592   {
4593     MEP_INSN_CPMOVUUA0_W_P0S, "cpmovuua0_w_P0S", "cpmovuua0.w", 32,
4594     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4595   },
4596 /* cpmovula0.w $crop */
4597   {
4598     MEP_INSN_CPMOVULA0_W_P0S, "cpmovula0_w_P0S", "cpmovula0.w", 32,
4599     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4600   },
4601 /* cpmovlua0.w $crop */
4602   {
4603     MEP_INSN_CPMOVLUA0_W_P0S, "cpmovlua0_w_P0S", "cpmovlua0.w", 32,
4604     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4605   },
4606 /* cpmovlla0.w $crop */
4607   {
4608     MEP_INSN_CPMOVLLA0_W_P0S, "cpmovlla0_w_P0S", "cpmovlla0.w", 32,
4609     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4610   },
4611 /* cppacka0u.b $crop */
4612   {
4613     MEP_INSN_CPPACKA0U_B_P0S, "cppacka0u_b_P0S", "cppacka0u.b", 32,
4614     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4615   },
4616 /* cppacka0.b $crop */
4617   {
4618     MEP_INSN_CPPACKA0_B_P0S, "cppacka0_b_P0S", "cppacka0.b", 32,
4619     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4620   },
4621 /* cppackua0.h $crop */
4622   {
4623     MEP_INSN_CPPACKUA0_H_P0S, "cppackua0_h_P0S", "cppackua0.h", 32,
4624     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4625   },
4626 /* cppackla0.h $crop */
4627   {
4628     MEP_INSN_CPPACKLA0_H_P0S, "cppackla0_h_P0S", "cppackla0.h", 32,
4629     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4630   },
4631 /* cppackua0.w $crop */
4632   {
4633     MEP_INSN_CPPACKUA0_W_P0S, "cppackua0_w_P0S", "cppackua0.w", 32,
4634     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4635   },
4636 /* cppackla0.w $crop */
4637   {
4638     MEP_INSN_CPPACKLA0_W_P0S, "cppackla0_w_P0S", "cppackla0.w", 32,
4639     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4640   },
4641 /* cpmovhua0.w $crop */
4642   {
4643     MEP_INSN_CPMOVHUA0_W_P0S, "cpmovhua0_w_P0S", "cpmovhua0.w", 32,
4644     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4645   },
4646 /* cpmovhla0.w $crop */
4647   {
4648     MEP_INSN_CPMOVHLA0_W_P0S, "cpmovhla0_w_P0S", "cpmovhla0.w", 32,
4649     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4650   },
4651 /* cpacsuma0 */
4652   {
4653     MEP_INSN_CPACSUMA0_P0S, "cpacsuma0_P0S", "cpacsuma0", 32,
4654     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4655   },
4656 /* cpaccpa0 */
4657   {
4658     MEP_INSN_CPACCPA0_P0S, "cpaccpa0_P0S", "cpaccpa0", 32,
4659     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4660   },
4661 /* cpsrla0 $crqp */
4662   {
4663     MEP_INSN_CPSRLA0_P0S, "cpsrla0_P0S", "cpsrla0", 32,
4664     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4665   },
4666 /* cpsraa0 $crqp */
4667   {
4668     MEP_INSN_CPSRAA0_P0S, "cpsraa0_P0S", "cpsraa0", 32,
4669     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4670   },
4671 /* cpslla0 $crqp */
4672   {
4673     MEP_INSN_CPSLLA0_P0S, "cpslla0_P0S", "cpslla0", 32,
4674     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4675   },
4676 /* cpsrlia0 $imm5p23 */
4677   {
4678     MEP_INSN_CPSRLIA0_P0S, "cpsrlia0_P0S", "cpsrlia0", 32,
4679     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4680   },
4681 /* cpsraia0 $imm5p23 */
4682   {
4683     MEP_INSN_CPSRAIA0_P0S, "cpsraia0_P0S", "cpsraia0", 32,
4684     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4685   },
4686 /* cpsllia0 $imm5p23 */
4687   {
4688     MEP_INSN_CPSLLIA0_P0S, "cpsllia0_P0S", "cpsllia0", 32,
4689     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4690   },
4691 /* cpfsftba0s0u.b $crqp,$crpp */
4692   {
4693     MEP_INSN_CPFSFTBA0S0U_B_P0S, "cpfsftba0s0u_b_P0S", "cpfsftba0s0u.b", 32,
4694     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4695   },
4696 /* cpfsftba0s0.b $crqp,$crpp */
4697   {
4698     MEP_INSN_CPFSFTBA0S0_B_P0S, "cpfsftba0s0_b_P0S", "cpfsftba0s0.b", 32,
4699     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4700   },
4701 /* cpfsftbua0s0.h $crqp,$crpp */
4702   {
4703     MEP_INSN_CPFSFTBUA0S0_H_P0S, "cpfsftbua0s0_h_P0S", "cpfsftbua0s0.h", 32,
4704     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4705   },
4706 /* cpfsftbla0s0.h $crqp,$crpp */
4707   {
4708     MEP_INSN_CPFSFTBLA0S0_H_P0S, "cpfsftbla0s0_h_P0S", "cpfsftbla0s0.h", 32,
4709     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4710   },
4711 /* cpfaca0s0u.b $crqp,$crpp */
4712   {
4713     MEP_INSN_CPFACA0S0U_B_P0S, "cpfaca0s0u_b_P0S", "cpfaca0s0u.b", 32,
4714     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4715   },
4716 /* cpfaca0s0.b $crqp,$crpp */
4717   {
4718     MEP_INSN_CPFACA0S0_B_P0S, "cpfaca0s0_b_P0S", "cpfaca0s0.b", 32,
4719     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4720   },
4721 /* cpfacua0s0.h $crqp,$crpp */
4722   {
4723     MEP_INSN_CPFACUA0S0_H_P0S, "cpfacua0s0_h_P0S", "cpfacua0s0.h", 32,
4724     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4725   },
4726 /* cpfacla0s0.h $crqp,$crpp */
4727   {
4728     MEP_INSN_CPFACLA0S0_H_P0S, "cpfacla0s0_h_P0S", "cpfacla0s0.h", 32,
4729     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4730   },
4731 /* cpfsftba0s1u.b $crqp,$crpp */
4732   {
4733     MEP_INSN_CPFSFTBA0S1U_B_P0S, "cpfsftba0s1u_b_P0S", "cpfsftba0s1u.b", 32,
4734     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4735   },
4736 /* cpfsftba0s1.b $crqp,$crpp */
4737   {
4738     MEP_INSN_CPFSFTBA0S1_B_P0S, "cpfsftba0s1_b_P0S", "cpfsftba0s1.b", 32,
4739     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4740   },
4741 /* cpfsftbua0s1.h $crqp,$crpp */
4742   {
4743     MEP_INSN_CPFSFTBUA0S1_H_P0S, "cpfsftbua0s1_h_P0S", "cpfsftbua0s1.h", 32,
4744     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4745   },
4746 /* cpfsftbla0s1.h $crqp,$crpp */
4747   {
4748     MEP_INSN_CPFSFTBLA0S1_H_P0S, "cpfsftbla0s1_h_P0S", "cpfsftbla0s1.h", 32,
4749     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4750   },
4751 /* cpfaca0s1u.b $crqp,$crpp */
4752   {
4753     MEP_INSN_CPFACA0S1U_B_P0S, "cpfaca0s1u_b_P0S", "cpfaca0s1u.b", 32,
4754     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4755   },
4756 /* cpfaca0s1.b $crqp,$crpp */
4757   {
4758     MEP_INSN_CPFACA0S1_B_P0S, "cpfaca0s1_b_P0S", "cpfaca0s1.b", 32,
4759     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4760   },
4761 /* cpfacua0s1.h $crqp,$crpp */
4762   {
4763     MEP_INSN_CPFACUA0S1_H_P0S, "cpfacua0s1_h_P0S", "cpfacua0s1.h", 32,
4764     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4765   },
4766 /* cpfacla0s1.h $crqp,$crpp */
4767   {
4768     MEP_INSN_CPFACLA0S1_H_P0S, "cpfacla0s1_h_P0S", "cpfacla0s1.h", 32,
4769     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
4770   },
4771 /* cpfsftbi $crop,$crqp,$crpp,$imm3p5 */
4772   {
4773     MEP_INSN_CPFSFTBI_P0_P1, "cpfsftbi_P0_P1", "cpfsftbi", 32,
4774     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4775   },
4776 /* cpacmpeq.b $crqp,$crpp */
4777   {
4778     MEP_INSN_CPACMPEQ_B_P0_P1, "cpacmpeq_b_P0_P1", "cpacmpeq.b", 32,
4779     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4780   },
4781 /* cpacmpeq.h $crqp,$crpp */
4782   {
4783     MEP_INSN_CPACMPEQ_H_P0_P1, "cpacmpeq_h_P0_P1", "cpacmpeq.h", 32,
4784     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4785   },
4786 /* cpacmpeq.w $crqp,$crpp */
4787   {
4788     MEP_INSN_CPACMPEQ_W_P0_P1, "cpacmpeq_w_P0_P1", "cpacmpeq.w", 32,
4789     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4790   },
4791 /* cpacmpne.b $crqp,$crpp */
4792   {
4793     MEP_INSN_CPACMPNE_B_P0_P1, "cpacmpne_b_P0_P1", "cpacmpne.b", 32,
4794     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4795   },
4796 /* cpacmpne.h $crqp,$crpp */
4797   {
4798     MEP_INSN_CPACMPNE_H_P0_P1, "cpacmpne_h_P0_P1", "cpacmpne.h", 32,
4799     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4800   },
4801 /* cpacmpne.w $crqp,$crpp */
4802   {
4803     MEP_INSN_CPACMPNE_W_P0_P1, "cpacmpne_w_P0_P1", "cpacmpne.w", 32,
4804     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4805   },
4806 /* cpacmpgtu.b $crqp,$crpp */
4807   {
4808     MEP_INSN_CPACMPGTU_B_P0_P1, "cpacmpgtu_b_P0_P1", "cpacmpgtu.b", 32,
4809     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4810   },
4811 /* cpacmpgt.b $crqp,$crpp */
4812   {
4813     MEP_INSN_CPACMPGT_B_P0_P1, "cpacmpgt_b_P0_P1", "cpacmpgt.b", 32,
4814     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4815   },
4816 /* cpacmpgt.h $crqp,$crpp */
4817   {
4818     MEP_INSN_CPACMPGT_H_P0_P1, "cpacmpgt_h_P0_P1", "cpacmpgt.h", 32,
4819     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4820   },
4821 /* cpacmpgtu.w $crqp,$crpp */
4822   {
4823     MEP_INSN_CPACMPGTU_W_P0_P1, "cpacmpgtu_w_P0_P1", "cpacmpgtu.w", 32,
4824     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4825   },
4826 /* cpacmpgt.w $crqp,$crpp */
4827   {
4828     MEP_INSN_CPACMPGT_W_P0_P1, "cpacmpgt_w_P0_P1", "cpacmpgt.w", 32,
4829     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4830   },
4831 /* cpacmpgeu.b $crqp,$crpp */
4832   {
4833     MEP_INSN_CPACMPGEU_B_P0_P1, "cpacmpgeu_b_P0_P1", "cpacmpgeu.b", 32,
4834     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4835   },
4836 /* cpacmpge.b $crqp,$crpp */
4837   {
4838     MEP_INSN_CPACMPGE_B_P0_P1, "cpacmpge_b_P0_P1", "cpacmpge.b", 32,
4839     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4840   },
4841 /* cpacmpge.h $crqp,$crpp */
4842   {
4843     MEP_INSN_CPACMPGE_H_P0_P1, "cpacmpge_h_P0_P1", "cpacmpge.h", 32,
4844     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4845   },
4846 /* cpacmpgeu.w $crqp,$crpp */
4847   {
4848     MEP_INSN_CPACMPGEU_W_P0_P1, "cpacmpgeu_w_P0_P1", "cpacmpgeu.w", 32,
4849     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4850   },
4851 /* cpacmpge.w $crqp,$crpp */
4852   {
4853     MEP_INSN_CPACMPGE_W_P0_P1, "cpacmpge_w_P0_P1", "cpacmpge.w", 32,
4854     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4855   },
4856 /* cpocmpeq.b $crqp,$crpp */
4857   {
4858     MEP_INSN_CPOCMPEQ_B_P0_P1, "cpocmpeq_b_P0_P1", "cpocmpeq.b", 32,
4859     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4860   },
4861 /* cpocmpeq.h $crqp,$crpp */
4862   {
4863     MEP_INSN_CPOCMPEQ_H_P0_P1, "cpocmpeq_h_P0_P1", "cpocmpeq.h", 32,
4864     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4865   },
4866 /* cpocmpeq.w $crqp,$crpp */
4867   {
4868     MEP_INSN_CPOCMPEQ_W_P0_P1, "cpocmpeq_w_P0_P1", "cpocmpeq.w", 32,
4869     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4870   },
4871 /* cpocmpne.b $crqp,$crpp */
4872   {
4873     MEP_INSN_CPOCMPNE_B_P0_P1, "cpocmpne_b_P0_P1", "cpocmpne.b", 32,
4874     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4875   },
4876 /* cpocmpne.h $crqp,$crpp */
4877   {
4878     MEP_INSN_CPOCMPNE_H_P0_P1, "cpocmpne_h_P0_P1", "cpocmpne.h", 32,
4879     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4880   },
4881 /* cpocmpne.w $crqp,$crpp */
4882   {
4883     MEP_INSN_CPOCMPNE_W_P0_P1, "cpocmpne_w_P0_P1", "cpocmpne.w", 32,
4884     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4885   },
4886 /* cpocmpgtu.b $crqp,$crpp */
4887   {
4888     MEP_INSN_CPOCMPGTU_B_P0_P1, "cpocmpgtu_b_P0_P1", "cpocmpgtu.b", 32,
4889     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4890   },
4891 /* cpocmpgt.b $crqp,$crpp */
4892   {
4893     MEP_INSN_CPOCMPGT_B_P0_P1, "cpocmpgt_b_P0_P1", "cpocmpgt.b", 32,
4894     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4895   },
4896 /* cpocmpgt.h $crqp,$crpp */
4897   {
4898     MEP_INSN_CPOCMPGT_H_P0_P1, "cpocmpgt_h_P0_P1", "cpocmpgt.h", 32,
4899     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4900   },
4901 /* cpocmpgtu.w $crqp,$crpp */
4902   {
4903     MEP_INSN_CPOCMPGTU_W_P0_P1, "cpocmpgtu_w_P0_P1", "cpocmpgtu.w", 32,
4904     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4905   },
4906 /* cpocmpgt.w $crqp,$crpp */
4907   {
4908     MEP_INSN_CPOCMPGT_W_P0_P1, "cpocmpgt_w_P0_P1", "cpocmpgt.w", 32,
4909     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4910   },
4911 /* cpocmpgeu.b $crqp,$crpp */
4912   {
4913     MEP_INSN_CPOCMPGEU_B_P0_P1, "cpocmpgeu_b_P0_P1", "cpocmpgeu.b", 32,
4914     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4915   },
4916 /* cpocmpge.b $crqp,$crpp */
4917   {
4918     MEP_INSN_CPOCMPGE_B_P0_P1, "cpocmpge_b_P0_P1", "cpocmpge.b", 32,
4919     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4920   },
4921 /* cpocmpge.h $crqp,$crpp */
4922   {
4923     MEP_INSN_CPOCMPGE_H_P0_P1, "cpocmpge_h_P0_P1", "cpocmpge.h", 32,
4924     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4925   },
4926 /* cpocmpgeu.w $crqp,$crpp */
4927   {
4928     MEP_INSN_CPOCMPGEU_W_P0_P1, "cpocmpgeu_w_P0_P1", "cpocmpgeu.w", 32,
4929     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4930   },
4931 /* cpocmpge.w $crqp,$crpp */
4932   {
4933     MEP_INSN_CPOCMPGE_W_P0_P1, "cpocmpge_w_P0_P1", "cpocmpge.w", 32,
4934     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4935   },
4936 /* cdadd3 $crop,$crqp,$crpp */
4937   {
4938     MEP_INSN_CDADD3_P0_P1, "cdadd3_P0_P1", "cdadd3", 32,
4939     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4940   },
4941 /* cpsub3.b $crop,$crqp,$crpp */
4942   {
4943     MEP_INSN_CPSUB3_B_P0_P1, "cpsub3_b_P0_P1", "cpsub3.b", 32,
4944     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4945   },
4946 /* cpsub3.h $crop,$crqp,$crpp */
4947   {
4948     MEP_INSN_CPSUB3_H_P0_P1, "cpsub3_h_P0_P1", "cpsub3.h", 32,
4949     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4950   },
4951 /* cpsub3.w $crop,$crqp,$crpp */
4952   {
4953     MEP_INSN_CPSUB3_W_P0_P1, "cpsub3_w_P0_P1", "cpsub3.w", 32,
4954     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4955   },
4956 /* cdsub3 $crop,$crqp,$crpp */
4957   {
4958     MEP_INSN_CDSUB3_P0_P1, "cdsub3_P0_P1", "cdsub3", 32,
4959     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4960   },
4961 /* cpsadd3.h $crop,$crqp,$crpp */
4962   {
4963     MEP_INSN_CPSADD3_H_P0_P1, "cpsadd3_h_P0_P1", "cpsadd3.h", 32,
4964     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4965   },
4966 /* cpsadd3.w $crop,$crqp,$crpp */
4967   {
4968     MEP_INSN_CPSADD3_W_P0_P1, "cpsadd3_w_P0_P1", "cpsadd3.w", 32,
4969     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4970   },
4971 /* cpssub3.h $crop,$crqp,$crpp */
4972   {
4973     MEP_INSN_CPSSUB3_H_P0_P1, "cpssub3_h_P0_P1", "cpssub3.h", 32,
4974     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4975   },
4976 /* cpssub3.w $crop,$crqp,$crpp */
4977   {
4978     MEP_INSN_CPSSUB3_W_P0_P1, "cpssub3_w_P0_P1", "cpssub3.w", 32,
4979     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4980   },
4981 /* cpextuaddu3.b $crop,$crqp,$crpp */
4982   {
4983     MEP_INSN_CPEXTUADDU3_B_P0_P1, "cpextuaddu3_b_P0_P1", "cpextuaddu3.b", 32,
4984     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4985   },
4986 /* cpextuadd3.b $crop,$crqp,$crpp */
4987   {
4988     MEP_INSN_CPEXTUADD3_B_P0_P1, "cpextuadd3_b_P0_P1", "cpextuadd3.b", 32,
4989     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4990   },
4991 /* cpextladdu3.b $crop,$crqp,$crpp */
4992   {
4993     MEP_INSN_CPEXTLADDU3_B_P0_P1, "cpextladdu3_b_P0_P1", "cpextladdu3.b", 32,
4994     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
4995   },
4996 /* cpextladd3.b $crop,$crqp,$crpp */
4997   {
4998     MEP_INSN_CPEXTLADD3_B_P0_P1, "cpextladd3_b_P0_P1", "cpextladd3.b", 32,
4999     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5000   },
5001 /* cpextusubu3.b $crop,$crqp,$crpp */
5002   {
5003     MEP_INSN_CPEXTUSUBU3_B_P0_P1, "cpextusubu3_b_P0_P1", "cpextusubu3.b", 32,
5004     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5005   },
5006 /* cpextusub3.b $crop,$crqp,$crpp */
5007   {
5008     MEP_INSN_CPEXTUSUB3_B_P0_P1, "cpextusub3_b_P0_P1", "cpextusub3.b", 32,
5009     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5010   },
5011 /* cpextlsubu3.b $crop,$crqp,$crpp */
5012   {
5013     MEP_INSN_CPEXTLSUBU3_B_P0_P1, "cpextlsubu3_b_P0_P1", "cpextlsubu3.b", 32,
5014     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5015   },
5016 /* cpextlsub3.b $crop,$crqp,$crpp */
5017   {
5018     MEP_INSN_CPEXTLSUB3_B_P0_P1, "cpextlsub3_b_P0_P1", "cpextlsub3.b", 32,
5019     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5020   },
5021 /* cpaveu3.b $crop,$crqp,$crpp */
5022   {
5023     MEP_INSN_CPAVEU3_B_P0_P1, "cpaveu3_b_P0_P1", "cpaveu3.b", 32,
5024     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5025   },
5026 /* cpave3.b $crop,$crqp,$crpp */
5027   {
5028     MEP_INSN_CPAVE3_B_P0_P1, "cpave3_b_P0_P1", "cpave3.b", 32,
5029     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5030   },
5031 /* cpave3.h $crop,$crqp,$crpp */
5032   {
5033     MEP_INSN_CPAVE3_H_P0_P1, "cpave3_h_P0_P1", "cpave3.h", 32,
5034     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5035   },
5036 /* cpave3.w $crop,$crqp,$crpp */
5037   {
5038     MEP_INSN_CPAVE3_W_P0_P1, "cpave3_w_P0_P1", "cpave3.w", 32,
5039     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5040   },
5041 /* cpaddsru3.b $crop,$crqp,$crpp */
5042   {
5043     MEP_INSN_CPADDSRU3_B_P0_P1, "cpaddsru3_b_P0_P1", "cpaddsru3.b", 32,
5044     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5045   },
5046 /* cpaddsr3.b $crop,$crqp,$crpp */
5047   {
5048     MEP_INSN_CPADDSR3_B_P0_P1, "cpaddsr3_b_P0_P1", "cpaddsr3.b", 32,
5049     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5050   },
5051 /* cpaddsr3.h $crop,$crqp,$crpp */
5052   {
5053     MEP_INSN_CPADDSR3_H_P0_P1, "cpaddsr3_h_P0_P1", "cpaddsr3.h", 32,
5054     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5055   },
5056 /* cpaddsr3.w $crop,$crqp,$crpp */
5057   {
5058     MEP_INSN_CPADDSR3_W_P0_P1, "cpaddsr3_w_P0_P1", "cpaddsr3.w", 32,
5059     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5060   },
5061 /* cpabsu3.b $crop,$crqp,$crpp */
5062   {
5063     MEP_INSN_CPABSU3_B_P0_P1, "cpabsu3_b_P0_P1", "cpabsu3.b", 32,
5064     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5065   },
5066 /* cpabs3.b $crop,$crqp,$crpp */
5067   {
5068     MEP_INSN_CPABS3_B_P0_P1, "cpabs3_b_P0_P1", "cpabs3.b", 32,
5069     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5070   },
5071 /* cpabs3.h $crop,$crqp,$crpp */
5072   {
5073     MEP_INSN_CPABS3_H_P0_P1, "cpabs3_h_P0_P1", "cpabs3.h", 32,
5074     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5075   },
5076 /* cpand3 $crop,$crqp,$crpp */
5077   {
5078     MEP_INSN_CPAND3_P0_P1, "cpand3_P0_P1", "cpand3", 32,
5079     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5080   },
5081 /* cpor3 $crop,$crqp,$crpp */
5082   {
5083     MEP_INSN_CPOR3_P0_P1, "cpor3_P0_P1", "cpor3", 32,
5084     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5085   },
5086 /* cpnor3 $crop,$crqp,$crpp */
5087   {
5088     MEP_INSN_CPNOR3_P0_P1, "cpnor3_P0_P1", "cpnor3", 32,
5089     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5090   },
5091 /* cpxor3 $crop,$crqp,$crpp */
5092   {
5093     MEP_INSN_CPXOR3_P0_P1, "cpxor3_P0_P1", "cpxor3", 32,
5094     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5095   },
5096 /* cppacku.b $crop,$crqp,$crpp */
5097   {
5098     MEP_INSN_CPPACKU_B_P0_P1, "cppacku_b_P0_P1", "cppacku.b", 32,
5099     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5100   },
5101 /* cppack.b $crop,$crqp,$crpp */
5102   {
5103     MEP_INSN_CPPACK_B_P0_P1, "cppack_b_P0_P1", "cppack.b", 32,
5104     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5105   },
5106 /* cppack.h $crop,$crqp,$crpp */
5107   {
5108     MEP_INSN_CPPACK_H_P0_P1, "cppack_h_P0_P1", "cppack.h", 32,
5109     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5110   },
5111 /* cpmaxu3.b $crop,$crqp,$crpp */
5112   {
5113     MEP_INSN_CPMAXU3_B_P0_P1, "cpmaxu3_b_P0_P1", "cpmaxu3.b", 32,
5114     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5115   },
5116 /* cpmax3.b $crop,$crqp,$crpp */
5117   {
5118     MEP_INSN_CPMAX3_B_P0_P1, "cpmax3_b_P0_P1", "cpmax3.b", 32,
5119     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5120   },
5121 /* cpmax3.h $crop,$crqp,$crpp */
5122   {
5123     MEP_INSN_CPMAX3_H_P0_P1, "cpmax3_h_P0_P1", "cpmax3.h", 32,
5124     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5125   },
5126 /* cpmaxu3.w $crop,$crqp,$crpp */
5127   {
5128     MEP_INSN_CPMAXU3_W_P0_P1, "cpmaxu3_w_P0_P1", "cpmaxu3.w", 32,
5129     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5130   },
5131 /* cpmax3.w $crop,$crqp,$crpp */
5132   {
5133     MEP_INSN_CPMAX3_W_P0_P1, "cpmax3_w_P0_P1", "cpmax3.w", 32,
5134     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5135   },
5136 /* cpminu3.b $crop,$crqp,$crpp */
5137   {
5138     MEP_INSN_CPMINU3_B_P0_P1, "cpminu3_b_P0_P1", "cpminu3.b", 32,
5139     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5140   },
5141 /* cpmin3.b $crop,$crqp,$crpp */
5142   {
5143     MEP_INSN_CPMIN3_B_P0_P1, "cpmin3_b_P0_P1", "cpmin3.b", 32,
5144     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5145   },
5146 /* cpmin3.h $crop,$crqp,$crpp */
5147   {
5148     MEP_INSN_CPMIN3_H_P0_P1, "cpmin3_h_P0_P1", "cpmin3.h", 32,
5149     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5150   },
5151 /* cpminu3.w $crop,$crqp,$crpp */
5152   {
5153     MEP_INSN_CPMINU3_W_P0_P1, "cpminu3_w_P0_P1", "cpminu3.w", 32,
5154     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5155   },
5156 /* cpmin3.w $crop,$crqp,$crpp */
5157   {
5158     MEP_INSN_CPMIN3_W_P0_P1, "cpmin3_w_P0_P1", "cpmin3.w", 32,
5159     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5160   },
5161 /* cpsrl3.b $crop,$crqp,$crpp */
5162   {
5163     MEP_INSN_CPSRL3_B_P0_P1, "cpsrl3_b_P0_P1", "cpsrl3.b", 32,
5164     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5165   },
5166 /* cpssrl3.b $crop,$crqp,$crpp */
5167   {
5168     MEP_INSN_CPSSRL3_B_P0_P1, "cpssrl3_b_P0_P1", "cpssrl3.b", 32,
5169     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5170   },
5171 /* cpsrl3.h $crop,$crqp,$crpp */
5172   {
5173     MEP_INSN_CPSRL3_H_P0_P1, "cpsrl3_h_P0_P1", "cpsrl3.h", 32,
5174     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5175   },
5176 /* cpssrl3.h $crop,$crqp,$crpp */
5177   {
5178     MEP_INSN_CPSSRL3_H_P0_P1, "cpssrl3_h_P0_P1", "cpssrl3.h", 32,
5179     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5180   },
5181 /* cpsrl3.w $crop,$crqp,$crpp */
5182   {
5183     MEP_INSN_CPSRL3_W_P0_P1, "cpsrl3_w_P0_P1", "cpsrl3.w", 32,
5184     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5185   },
5186 /* cpssrl3.w $crop,$crqp,$crpp */
5187   {
5188     MEP_INSN_CPSSRL3_W_P0_P1, "cpssrl3_w_P0_P1", "cpssrl3.w", 32,
5189     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5190   },
5191 /* cdsrl3 $crop,$crqp,$crpp */
5192   {
5193     MEP_INSN_CDSRL3_P0_P1, "cdsrl3_P0_P1", "cdsrl3", 32,
5194     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5195   },
5196 /* cpsra3.b $crop,$crqp,$crpp */
5197   {
5198     MEP_INSN_CPSRA3_B_P0_P1, "cpsra3_b_P0_P1", "cpsra3.b", 32,
5199     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5200   },
5201 /* cpssra3.b $crop,$crqp,$crpp */
5202   {
5203     MEP_INSN_CPSSRA3_B_P0_P1, "cpssra3_b_P0_P1", "cpssra3.b", 32,
5204     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5205   },
5206 /* cpsra3.h $crop,$crqp,$crpp */
5207   {
5208     MEP_INSN_CPSRA3_H_P0_P1, "cpsra3_h_P0_P1", "cpsra3.h", 32,
5209     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5210   },
5211 /* cpssra3.h $crop,$crqp,$crpp */
5212   {
5213     MEP_INSN_CPSSRA3_H_P0_P1, "cpssra3_h_P0_P1", "cpssra3.h", 32,
5214     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5215   },
5216 /* cpsra3.w $crop,$crqp,$crpp */
5217   {
5218     MEP_INSN_CPSRA3_W_P0_P1, "cpsra3_w_P0_P1", "cpsra3.w", 32,
5219     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5220   },
5221 /* cpssra3.w $crop,$crqp,$crpp */
5222   {
5223     MEP_INSN_CPSSRA3_W_P0_P1, "cpssra3_w_P0_P1", "cpssra3.w", 32,
5224     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5225   },
5226 /* cdsra3 $crop,$crqp,$crpp */
5227   {
5228     MEP_INSN_CDSRA3_P0_P1, "cdsra3_P0_P1", "cdsra3", 32,
5229     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5230   },
5231 /* cpsll3.b $crop,$crqp,$crpp */
5232   {
5233     MEP_INSN_CPSLL3_B_P0_P1, "cpsll3_b_P0_P1", "cpsll3.b", 32,
5234     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5235   },
5236 /* cpssll3.b $crop,$crqp,$crpp */
5237   {
5238     MEP_INSN_CPSSLL3_B_P0_P1, "cpssll3_b_P0_P1", "cpssll3.b", 32,
5239     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5240   },
5241 /* cpsll3.h $crop,$crqp,$crpp */
5242   {
5243     MEP_INSN_CPSLL3_H_P0_P1, "cpsll3_h_P0_P1", "cpsll3.h", 32,
5244     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5245   },
5246 /* cpssll3.h $crop,$crqp,$crpp */
5247   {
5248     MEP_INSN_CPSSLL3_H_P0_P1, "cpssll3_h_P0_P1", "cpssll3.h", 32,
5249     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5250   },
5251 /* cpsll3.w $crop,$crqp,$crpp */
5252   {
5253     MEP_INSN_CPSLL3_W_P0_P1, "cpsll3_w_P0_P1", "cpsll3.w", 32,
5254     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5255   },
5256 /* cpssll3.w $crop,$crqp,$crpp */
5257   {
5258     MEP_INSN_CPSSLL3_W_P0_P1, "cpssll3_w_P0_P1", "cpssll3.w", 32,
5259     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5260   },
5261 /* cdsll3 $crop,$crqp,$crpp */
5262   {
5263     MEP_INSN_CDSLL3_P0_P1, "cdsll3_P0_P1", "cdsll3", 32,
5264     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5265   },
5266 /* cpsla3.h $crop,$crqp,$crpp */
5267   {
5268     MEP_INSN_CPSLA3_H_P0_P1, "cpsla3_h_P0_P1", "cpsla3.h", 32,
5269     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5270   },
5271 /* cpsla3.w $crop,$crqp,$crpp */
5272   {
5273     MEP_INSN_CPSLA3_W_P0_P1, "cpsla3_w_P0_P1", "cpsla3.w", 32,
5274     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5275   },
5276 /* cpsrli3.b $crop,$crqp,$imm3p5 */
5277   {
5278     MEP_INSN_CPSRLI3_B_P0_P1, "cpsrli3_b_P0_P1", "cpsrli3.b", 32,
5279     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5280   },
5281 /* cpsrli3.h $crop,$crqp,$imm4p4 */
5282   {
5283     MEP_INSN_CPSRLI3_H_P0_P1, "cpsrli3_h_P0_P1", "cpsrli3.h", 32,
5284     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5285   },
5286 /* cpsrli3.w $crop,$crqp,$imm5p3 */
5287   {
5288     MEP_INSN_CPSRLI3_W_P0_P1, "cpsrli3_w_P0_P1", "cpsrli3.w", 32,
5289     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5290   },
5291 /* cdsrli3 $crop,$crqp,$imm6p2 */
5292   {
5293     MEP_INSN_CDSRLI3_P0_P1, "cdsrli3_P0_P1", "cdsrli3", 32,
5294     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5295   },
5296 /* cpsrai3.b $crop,$crqp,$imm3p5 */
5297   {
5298     MEP_INSN_CPSRAI3_B_P0_P1, "cpsrai3_b_P0_P1", "cpsrai3.b", 32,
5299     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5300   },
5301 /* cpsrai3.h $crop,$crqp,$imm4p4 */
5302   {
5303     MEP_INSN_CPSRAI3_H_P0_P1, "cpsrai3_h_P0_P1", "cpsrai3.h", 32,
5304     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5305   },
5306 /* cpsrai3.w $crop,$crqp,$imm5p3 */
5307   {
5308     MEP_INSN_CPSRAI3_W_P0_P1, "cpsrai3_w_P0_P1", "cpsrai3.w", 32,
5309     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5310   },
5311 /* cdsrai3 $crop,$crqp,$imm6p2 */
5312   {
5313     MEP_INSN_CDSRAI3_P0_P1, "cdsrai3_P0_P1", "cdsrai3", 32,
5314     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5315   },
5316 /* cpslli3.b $crop,$crqp,$imm3p5 */
5317   {
5318     MEP_INSN_CPSLLI3_B_P0_P1, "cpslli3_b_P0_P1", "cpslli3.b", 32,
5319     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5320   },
5321 /* cpslli3.h $crop,$crqp,$imm4p4 */
5322   {
5323     MEP_INSN_CPSLLI3_H_P0_P1, "cpslli3_h_P0_P1", "cpslli3.h", 32,
5324     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5325   },
5326 /* cpslli3.w $crop,$crqp,$imm5p3 */
5327   {
5328     MEP_INSN_CPSLLI3_W_P0_P1, "cpslli3_w_P0_P1", "cpslli3.w", 32,
5329     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5330   },
5331 /* cdslli3 $crop,$crqp,$imm6p2 */
5332   {
5333     MEP_INSN_CDSLLI3_P0_P1, "cdslli3_P0_P1", "cdslli3", 32,
5334     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5335   },
5336 /* cpslai3.h $crop,$crqp,$imm4p4 */
5337   {
5338     MEP_INSN_CPSLAI3_H_P0_P1, "cpslai3_h_P0_P1", "cpslai3.h", 32,
5339     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5340   },
5341 /* cpslai3.w $crop,$crqp,$imm5p3 */
5342   {
5343     MEP_INSN_CPSLAI3_W_P0_P1, "cpslai3_w_P0_P1", "cpslai3.w", 32,
5344     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5345   },
5346 /* cpclipiu3.w $crop,$crqp,$imm5p3 */
5347   {
5348     MEP_INSN_CPCLIPIU3_W_P0_P1, "cpclipiu3_w_P0_P1", "cpclipiu3.w", 32,
5349     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5350   },
5351 /* cpclipi3.w $crop,$crqp,$imm5p3 */
5352   {
5353     MEP_INSN_CPCLIPI3_W_P0_P1, "cpclipi3_w_P0_P1", "cpclipi3.w", 32,
5354     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5355   },
5356 /* cdclipiu3 $crop,$crqp,$imm6p2 */
5357   {
5358     MEP_INSN_CDCLIPIU3_P0_P1, "cdclipiu3_P0_P1", "cdclipiu3", 32,
5359     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5360   },
5361 /* cdclipi3 $crop,$crqp,$imm6p2 */
5362   {
5363     MEP_INSN_CDCLIPI3_P0_P1, "cdclipi3_P0_P1", "cdclipi3", 32,
5364     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5365   },
5366 /* cpmovi.h $crqp,$simm16p0 */
5367   {
5368     MEP_INSN_CPMOVI_H_P0_P1, "cpmovi_h_P0_P1", "cpmovi.h", 32,
5369     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5370   },
5371 /* cpmoviu.w $crqp,$imm16p0 */
5372   {
5373     MEP_INSN_CPMOVIU_W_P0_P1, "cpmoviu_w_P0_P1", "cpmoviu.w", 32,
5374     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5375   },
5376 /* cpmovi.w $crqp,$simm16p0 */
5377   {
5378     MEP_INSN_CPMOVI_W_P0_P1, "cpmovi_w_P0_P1", "cpmovi.w", 32,
5379     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5380   },
5381 /* cdmoviu $crqp,$imm16p0 */
5382   {
5383     MEP_INSN_CDMOVIU_P0_P1, "cdmoviu_P0_P1", "cdmoviu", 32,
5384     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5385   },
5386 /* cdmovi $crqp,$simm16p0 */
5387   {
5388     MEP_INSN_CDMOVI_P0_P1, "cdmovi_P0_P1", "cdmovi", 32,
5389     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
5390   },
5391 /* c1nop */
5392   {
5393     MEP_INSN_C1NOP_P1, "c1nop_P1", "c1nop", 32,
5394     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5395   },
5396 /* cpmovi.b $crqp,$simm8p20 */
5397   {
5398     MEP_INSN_CPMOVI_B_P0S_P1, "cpmovi_b_P0S_P1", "cpmovi.b", 32,
5399     { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
5400   },
5401 /* cpadda1u.b $crqp,$crpp */
5402   {
5403     MEP_INSN_CPADDA1U_B_P1, "cpadda1u_b_P1", "cpadda1u.b", 32,
5404     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5405   },
5406 /* cpadda1.b $crqp,$crpp */
5407   {
5408     MEP_INSN_CPADDA1_B_P1, "cpadda1_b_P1", "cpadda1.b", 32,
5409     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5410   },
5411 /* cpaddua1.h $crqp,$crpp */
5412   {
5413     MEP_INSN_CPADDUA1_H_P1, "cpaddua1_h_P1", "cpaddua1.h", 32,
5414     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5415   },
5416 /* cpaddla1.h $crqp,$crpp */
5417   {
5418     MEP_INSN_CPADDLA1_H_P1, "cpaddla1_h_P1", "cpaddla1.h", 32,
5419     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5420   },
5421 /* cpaddaca1u.b $crqp,$crpp */
5422   {
5423     MEP_INSN_CPADDACA1U_B_P1, "cpaddaca1u_b_P1", "cpaddaca1u.b", 32,
5424     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5425   },
5426 /* cpaddaca1.b $crqp,$crpp */
5427   {
5428     MEP_INSN_CPADDACA1_B_P1, "cpaddaca1_b_P1", "cpaddaca1.b", 32,
5429     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5430   },
5431 /* cpaddacua1.h $crqp,$crpp */
5432   {
5433     MEP_INSN_CPADDACUA1_H_P1, "cpaddacua1_h_P1", "cpaddacua1.h", 32,
5434     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5435   },
5436 /* cpaddacla1.h $crqp,$crpp */
5437   {
5438     MEP_INSN_CPADDACLA1_H_P1, "cpaddacla1_h_P1", "cpaddacla1.h", 32,
5439     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5440   },
5441 /* cpsuba1u.b $crqp,$crpp */
5442   {
5443     MEP_INSN_CPSUBA1U_B_P1, "cpsuba1u_b_P1", "cpsuba1u.b", 32,
5444     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5445   },
5446 /* cpsuba1.b $crqp,$crpp */
5447   {
5448     MEP_INSN_CPSUBA1_B_P1, "cpsuba1_b_P1", "cpsuba1.b", 32,
5449     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5450   },
5451 /* cpsubua1.h $crqp,$crpp */
5452   {
5453     MEP_INSN_CPSUBUA1_H_P1, "cpsubua1_h_P1", "cpsubua1.h", 32,
5454     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5455   },
5456 /* cpsubla1.h $crqp,$crpp */
5457   {
5458     MEP_INSN_CPSUBLA1_H_P1, "cpsubla1_h_P1", "cpsubla1.h", 32,
5459     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5460   },
5461 /* cpsubaca1u.b $crqp,$crpp */
5462   {
5463     MEP_INSN_CPSUBACA1U_B_P1, "cpsubaca1u_b_P1", "cpsubaca1u.b", 32,
5464     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5465   },
5466 /* cpsubaca1.b $crqp,$crpp */
5467   {
5468     MEP_INSN_CPSUBACA1_B_P1, "cpsubaca1_b_P1", "cpsubaca1.b", 32,
5469     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5470   },
5471 /* cpsubacua1.h $crqp,$crpp */
5472   {
5473     MEP_INSN_CPSUBACUA1_H_P1, "cpsubacua1_h_P1", "cpsubacua1.h", 32,
5474     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5475   },
5476 /* cpsubacla1.h $crqp,$crpp */
5477   {
5478     MEP_INSN_CPSUBACLA1_H_P1, "cpsubacla1_h_P1", "cpsubacla1.h", 32,
5479     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5480   },
5481 /* cpabsa1u.b $crqp,$crpp */
5482   {
5483     MEP_INSN_CPABSA1U_B_P1, "cpabsa1u_b_P1", "cpabsa1u.b", 32,
5484     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5485   },
5486 /* cpabsa1.b $crqp,$crpp */
5487   {
5488     MEP_INSN_CPABSA1_B_P1, "cpabsa1_b_P1", "cpabsa1.b", 32,
5489     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5490   },
5491 /* cpabsua1.h $crqp,$crpp */
5492   {
5493     MEP_INSN_CPABSUA1_H_P1, "cpabsua1_h_P1", "cpabsua1.h", 32,
5494     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5495   },
5496 /* cpabsla1.h $crqp,$crpp */
5497   {
5498     MEP_INSN_CPABSLA1_H_P1, "cpabsla1_h_P1", "cpabsla1.h", 32,
5499     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5500   },
5501 /* cpsada1u.b $crqp,$crpp */
5502   {
5503     MEP_INSN_CPSADA1U_B_P1, "cpsada1u_b_P1", "cpsada1u.b", 32,
5504     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5505   },
5506 /* cpsada1.b $crqp,$crpp */
5507   {
5508     MEP_INSN_CPSADA1_B_P1, "cpsada1_b_P1", "cpsada1.b", 32,
5509     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5510   },
5511 /* cpsadua1.h $crqp,$crpp */
5512   {
5513     MEP_INSN_CPSADUA1_H_P1, "cpsadua1_h_P1", "cpsadua1.h", 32,
5514     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5515   },
5516 /* cpsadla1.h $crqp,$crpp */
5517   {
5518     MEP_INSN_CPSADLA1_H_P1, "cpsadla1_h_P1", "cpsadla1.h", 32,
5519     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5520   },
5521 /* cpseta1.h $crqp,$crpp */
5522   {
5523     MEP_INSN_CPSETA1_H_P1, "cpseta1_h_P1", "cpseta1.h", 32,
5524     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5525   },
5526 /* cpsetua1.w $crqp,$crpp */
5527   {
5528     MEP_INSN_CPSETUA1_W_P1, "cpsetua1_w_P1", "cpsetua1.w", 32,
5529     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5530   },
5531 /* cpsetla1.w $crqp,$crpp */
5532   {
5533     MEP_INSN_CPSETLA1_W_P1, "cpsetla1_w_P1", "cpsetla1.w", 32,
5534     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5535   },
5536 /* cpmova1.b $crop */
5537   {
5538     MEP_INSN_CPMOVA1_B_P1, "cpmova1_b_P1", "cpmova1.b", 32,
5539     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5540   },
5541 /* cpmovua1.h $crop */
5542   {
5543     MEP_INSN_CPMOVUA1_H_P1, "cpmovua1_h_P1", "cpmovua1.h", 32,
5544     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5545   },
5546 /* cpmovla1.h $crop */
5547   {
5548     MEP_INSN_CPMOVLA1_H_P1, "cpmovla1_h_P1", "cpmovla1.h", 32,
5549     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5550   },
5551 /* cpmovuua1.w $crop */
5552   {
5553     MEP_INSN_CPMOVUUA1_W_P1, "cpmovuua1_w_P1", "cpmovuua1.w", 32,
5554     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5555   },
5556 /* cpmovula1.w $crop */
5557   {
5558     MEP_INSN_CPMOVULA1_W_P1, "cpmovula1_w_P1", "cpmovula1.w", 32,
5559     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5560   },
5561 /* cpmovlua1.w $crop */
5562   {
5563     MEP_INSN_CPMOVLUA1_W_P1, "cpmovlua1_w_P1", "cpmovlua1.w", 32,
5564     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5565   },
5566 /* cpmovlla1.w $crop */
5567   {
5568     MEP_INSN_CPMOVLLA1_W_P1, "cpmovlla1_w_P1", "cpmovlla1.w", 32,
5569     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5570   },
5571 /* cppacka1u.b $crop */
5572   {
5573     MEP_INSN_CPPACKA1U_B_P1, "cppacka1u_b_P1", "cppacka1u.b", 32,
5574     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5575   },
5576 /* cppacka1.b $crop */
5577   {
5578     MEP_INSN_CPPACKA1_B_P1, "cppacka1_b_P1", "cppacka1.b", 32,
5579     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5580   },
5581 /* cppackua1.h $crop */
5582   {
5583     MEP_INSN_CPPACKUA1_H_P1, "cppackua1_h_P1", "cppackua1.h", 32,
5584     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5585   },
5586 /* cppackla1.h $crop */
5587   {
5588     MEP_INSN_CPPACKLA1_H_P1, "cppackla1_h_P1", "cppackla1.h", 32,
5589     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5590   },
5591 /* cppackua1.w $crop */
5592   {
5593     MEP_INSN_CPPACKUA1_W_P1, "cppackua1_w_P1", "cppackua1.w", 32,
5594     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5595   },
5596 /* cppackla1.w $crop */
5597   {
5598     MEP_INSN_CPPACKLA1_W_P1, "cppackla1_w_P1", "cppackla1.w", 32,
5599     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5600   },
5601 /* cpmovhua1.w $crop */
5602   {
5603     MEP_INSN_CPMOVHUA1_W_P1, "cpmovhua1_w_P1", "cpmovhua1.w", 32,
5604     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5605   },
5606 /* cpmovhla1.w $crop */
5607   {
5608     MEP_INSN_CPMOVHLA1_W_P1, "cpmovhla1_w_P1", "cpmovhla1.w", 32,
5609     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5610   },
5611 /* cpacsuma1 */
5612   {
5613     MEP_INSN_CPACSUMA1_P1, "cpacsuma1_P1", "cpacsuma1", 32,
5614     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5615   },
5616 /* cpaccpa1 */
5617   {
5618     MEP_INSN_CPACCPA1_P1, "cpaccpa1_P1", "cpaccpa1", 32,
5619     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5620   },
5621 /* cpacswp */
5622   {
5623     MEP_INSN_CPACSWP_P1, "cpacswp_P1", "cpacswp", 32,
5624     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5625   },
5626 /* cpsrla1 $crqp */
5627   {
5628     MEP_INSN_CPSRLA1_P1, "cpsrla1_P1", "cpsrla1", 32,
5629     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5630   },
5631 /* cpsraa1 $crqp */
5632   {
5633     MEP_INSN_CPSRAA1_P1, "cpsraa1_P1", "cpsraa1", 32,
5634     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5635   },
5636 /* cpslla1 $crqp */
5637   {
5638     MEP_INSN_CPSLLA1_P1, "cpslla1_P1", "cpslla1", 32,
5639     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5640   },
5641 /* cpsrlia1 $imm5p23 */
5642   {
5643     MEP_INSN_CPSRLIA1_1_P1, "cpsrlia1_1_p1", "cpsrlia1", 32,
5644     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5645   },
5646 /* cpsraia1 $imm5p23 */
5647   {
5648     MEP_INSN_CPSRAIA1_1_P1, "cpsraia1_1_p1", "cpsraia1", 32,
5649     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5650   },
5651 /* cpsllia1 $imm5p23 */
5652   {
5653     MEP_INSN_CPSLLIA1_1_P1, "cpsllia1_1_p1", "cpsllia1", 32,
5654     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5655   },
5656 /* cpfmulia1s0u.b $crqp,$crpp,$simm8p0 */
5657   {
5658     MEP_INSN_CPFMULIA1S0U_B_P1, "cpfmulia1s0u_b_P1", "cpfmulia1s0u.b", 32,
5659     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5660   },
5661 /* cpfmulia1s0.b $crqp,$crpp,$simm8p0 */
5662   {
5663     MEP_INSN_CPFMULIA1S0_B_P1, "cpfmulia1s0_b_P1", "cpfmulia1s0.b", 32,
5664     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5665   },
5666 /* cpfmuliua1s0.h $crqp,$crpp,$simm8p0 */
5667   {
5668     MEP_INSN_CPFMULIUA1S0_H_P1, "cpfmuliua1s0_h_P1", "cpfmuliua1s0.h", 32,
5669     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5670   },
5671 /* cpfmulila1s0.h $crqp,$crpp,$simm8p0 */
5672   {
5673     MEP_INSN_CPFMULILA1S0_H_P1, "cpfmulila1s0_h_P1", "cpfmulila1s0.h", 32,
5674     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5675   },
5676 /* cpfmadia1s0u.b $crqp,$crpp,$simm8p0 */
5677   {
5678     MEP_INSN_CPFMADIA1S0U_B_P1, "cpfmadia1s0u_b_P1", "cpfmadia1s0u.b", 32,
5679     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5680   },
5681 /* cpfmadia1s0.b $crqp,$crpp,$simm8p0 */
5682   {
5683     MEP_INSN_CPFMADIA1S0_B_P1, "cpfmadia1s0_b_P1", "cpfmadia1s0.b", 32,
5684     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5685   },
5686 /* cpfmadiua1s0.h $crqp,$crpp,$simm8p0 */
5687   {
5688     MEP_INSN_CPFMADIUA1S0_H_P1, "cpfmadiua1s0_h_P1", "cpfmadiua1s0.h", 32,
5689     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5690   },
5691 /* cpfmadila1s0.h $crqp,$crpp,$simm8p0 */
5692   {
5693     MEP_INSN_CPFMADILA1S0_H_P1, "cpfmadila1s0_h_P1", "cpfmadila1s0.h", 32,
5694     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5695   },
5696 /* cpfmulia1s1u.b $crqp,$crpp,$simm8p0 */
5697   {
5698     MEP_INSN_CPFMULIA1S1U_B_P1, "cpfmulia1s1u_b_P1", "cpfmulia1s1u.b", 32,
5699     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5700   },
5701 /* cpfmulia1s1.b $crqp,$crpp,$simm8p0 */
5702   {
5703     MEP_INSN_CPFMULIA1S1_B_P1, "cpfmulia1s1_b_P1", "cpfmulia1s1.b", 32,
5704     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5705   },
5706 /* cpfmuliua1s1.h $crqp,$crpp,$simm8p0 */
5707   {
5708     MEP_INSN_CPFMULIUA1S1_H_P1, "cpfmuliua1s1_h_P1", "cpfmuliua1s1.h", 32,
5709     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5710   },
5711 /* cpfmulila1s1.h $crqp,$crpp,$simm8p0 */
5712   {
5713     MEP_INSN_CPFMULILA1S1_H_P1, "cpfmulila1s1_h_P1", "cpfmulila1s1.h", 32,
5714     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5715   },
5716 /* cpfmadia1s1u.b $crqp,$crpp,$simm8p0 */
5717   {
5718     MEP_INSN_CPFMADIA1S1U_B_P1, "cpfmadia1s1u_b_P1", "cpfmadia1s1u.b", 32,
5719     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5720   },
5721 /* cpfmadia1s1.b $crqp,$crpp,$simm8p0 */
5722   {
5723     MEP_INSN_CPFMADIA1S1_B_P1, "cpfmadia1s1_b_P1", "cpfmadia1s1.b", 32,
5724     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5725   },
5726 /* cpfmadiua1s1.h $crqp,$crpp,$simm8p0 */
5727   {
5728     MEP_INSN_CPFMADIUA1S1_H_P1, "cpfmadiua1s1_h_P1", "cpfmadiua1s1.h", 32,
5729     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5730   },
5731 /* cpfmadila1s1.h $crqp,$crpp,$simm8p0 */
5732   {
5733     MEP_INSN_CPFMADILA1S1_H_P1, "cpfmadila1s1_h_P1", "cpfmadila1s1.h", 32,
5734     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5735   },
5736 /* cpamulia1u.b $crqp,$crpp,$simm8p0 */
5737   {
5738     MEP_INSN_CPAMULIA1U_B_P1, "cpamulia1u_b_P1", "cpamulia1u.b", 32,
5739     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5740   },
5741 /* cpamulia1.b $crqp,$crpp,$simm8p0 */
5742   {
5743     MEP_INSN_CPAMULIA1_B_P1, "cpamulia1_b_P1", "cpamulia1.b", 32,
5744     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5745   },
5746 /* cpamuliua1.h $crqp,$crpp,$simm8p0 */
5747   {
5748     MEP_INSN_CPAMULIUA1_H_P1, "cpamuliua1_h_P1", "cpamuliua1.h", 32,
5749     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5750   },
5751 /* cpamulila1.h $crqp,$crpp,$simm8p0 */
5752   {
5753     MEP_INSN_CPAMULILA1_H_P1, "cpamulila1_h_P1", "cpamulila1.h", 32,
5754     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5755   },
5756 /* cpamadia1u.b $crqp,$crpp,$simm8p0 */
5757   {
5758     MEP_INSN_CPAMADIA1U_B_P1, "cpamadia1u_b_P1", "cpamadia1u.b", 32,
5759     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5760   },
5761 /* cpamadia1.b $crqp,$crpp,$simm8p0 */
5762   {
5763     MEP_INSN_CPAMADIA1_B_P1, "cpamadia1_b_P1", "cpamadia1.b", 32,
5764     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5765   },
5766 /* cpamadiua1.h $crqp,$crpp,$simm8p0 */
5767   {
5768     MEP_INSN_CPAMADIUA1_H_P1, "cpamadiua1_h_P1", "cpamadiua1.h", 32,
5769     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5770   },
5771 /* cpamadila1.h $crqp,$crpp,$simm8p0 */
5772   {
5773     MEP_INSN_CPAMADILA1_H_P1, "cpamadila1_h_P1", "cpamadila1.h", 32,
5774     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5775   },
5776 /* cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */
5777   {
5778     MEP_INSN_CPFMULIA1U_B_P1, "cpfmulia1u_b_P1", "cpfmulia1u.b", 32,
5779     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5780   },
5781 /* cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0 */
5782   {
5783     MEP_INSN_CPFMULIA1_B_P1, "cpfmulia1_b_P1", "cpfmulia1.b", 32,
5784     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5785   },
5786 /* cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5787   {
5788     MEP_INSN_CPFMULIUA1_H_P1, "cpfmuliua1_h_P1", "cpfmuliua1.h", 32,
5789     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5790   },
5791 /* cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5792   {
5793     MEP_INSN_CPFMULILA1_H_P1, "cpfmulila1_h_P1", "cpfmulila1.h", 32,
5794     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5795   },
5796 /* cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */
5797   {
5798     MEP_INSN_CPFMADIA1U_B_P1, "cpfmadia1u_b_P1", "cpfmadia1u.b", 32,
5799     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5800   },
5801 /* cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0 */
5802   {
5803     MEP_INSN_CPFMADIA1_B_P1, "cpfmadia1_b_P1", "cpfmadia1.b", 32,
5804     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5805   },
5806 /* cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5807   {
5808     MEP_INSN_CPFMADIUA1_H_P1, "cpfmadiua1_h_P1", "cpfmadiua1.h", 32,
5809     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5810   },
5811 /* cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0 */
5812   {
5813     MEP_INSN_CPFMADILA1_H_P1, "cpfmadila1_h_P1", "cpfmadila1.h", 32,
5814     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5815   },
5816 /* cpssqa1u.b $crqp,$crpp */
5817   {
5818     MEP_INSN_CPSSQA1U_B_P1, "cpssqa1u_b_P1", "cpssqa1u.b", 32,
5819     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5820   },
5821 /* cpssqa1.b $crqp,$crpp */
5822   {
5823     MEP_INSN_CPSSQA1_B_P1, "cpssqa1_b_P1", "cpssqa1.b", 32,
5824     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5825   },
5826 /* cpssda1u.b $crqp,$crpp */
5827   {
5828     MEP_INSN_CPSSDA1U_B_P1, "cpssda1u_b_P1", "cpssda1u.b", 32,
5829     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5830   },
5831 /* cpssda1.b $crqp,$crpp */
5832   {
5833     MEP_INSN_CPSSDA1_B_P1, "cpssda1_b_P1", "cpssda1.b", 32,
5834     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5835   },
5836 /* cpmula1u.b $crqp,$crpp */
5837   {
5838     MEP_INSN_CPMULA1U_B_P1, "cpmula1u_b_P1", "cpmula1u.b", 32,
5839     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5840   },
5841 /* cpmula1.b $crqp,$crpp */
5842   {
5843     MEP_INSN_CPMULA1_B_P1, "cpmula1_b_P1", "cpmula1.b", 32,
5844     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5845   },
5846 /* cpmulua1.h $crqp,$crpp */
5847   {
5848     MEP_INSN_CPMULUA1_H_P1, "cpmulua1_h_P1", "cpmulua1.h", 32,
5849     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5850   },
5851 /* cpmulla1.h $crqp,$crpp */
5852   {
5853     MEP_INSN_CPMULLA1_H_P1, "cpmulla1_h_P1", "cpmulla1.h", 32,
5854     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5855   },
5856 /* cpmulua1u.w $crqp,$crpp */
5857   {
5858     MEP_INSN_CPMULUA1U_W_P1, "cpmulua1u_w_P1", "cpmulua1u.w", 32,
5859     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5860   },
5861 /* cpmulla1u.w $crqp,$crpp */
5862   {
5863     MEP_INSN_CPMULLA1U_W_P1, "cpmulla1u_w_P1", "cpmulla1u.w", 32,
5864     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5865   },
5866 /* cpmulua1.w $crqp,$crpp */
5867   {
5868     MEP_INSN_CPMULUA1_W_P1, "cpmulua1_w_P1", "cpmulua1.w", 32,
5869     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5870   },
5871 /* cpmulla1.w $crqp,$crpp */
5872   {
5873     MEP_INSN_CPMULLA1_W_P1, "cpmulla1_w_P1", "cpmulla1.w", 32,
5874     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5875   },
5876 /* cpmada1u.b $crqp,$crpp */
5877   {
5878     MEP_INSN_CPMADA1U_B_P1, "cpmada1u_b_P1", "cpmada1u.b", 32,
5879     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5880   },
5881 /* cpmada1.b $crqp,$crpp */
5882   {
5883     MEP_INSN_CPMADA1_B_P1, "cpmada1_b_P1", "cpmada1.b", 32,
5884     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5885   },
5886 /* cpmadua1.h $crqp,$crpp */
5887   {
5888     MEP_INSN_CPMADUA1_H_P1, "cpmadua1_h_P1", "cpmadua1.h", 32,
5889     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5890   },
5891 /* cpmadla1.h $crqp,$crpp */
5892   {
5893     MEP_INSN_CPMADLA1_H_P1, "cpmadla1_h_P1", "cpmadla1.h", 32,
5894     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5895   },
5896 /* cpmadua1u.w $crqp,$crpp */
5897   {
5898     MEP_INSN_CPMADUA1U_W_P1, "cpmadua1u_w_P1", "cpmadua1u.w", 32,
5899     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5900   },
5901 /* cpmadla1u.w $crqp,$crpp */
5902   {
5903     MEP_INSN_CPMADLA1U_W_P1, "cpmadla1u_w_P1", "cpmadla1u.w", 32,
5904     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5905   },
5906 /* cpmadua1.w $crqp,$crpp */
5907   {
5908     MEP_INSN_CPMADUA1_W_P1, "cpmadua1_w_P1", "cpmadua1.w", 32,
5909     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5910   },
5911 /* cpmadla1.w $crqp,$crpp */
5912   {
5913     MEP_INSN_CPMADLA1_W_P1, "cpmadla1_w_P1", "cpmadla1.w", 32,
5914     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5915   },
5916 /* cpmsbua1.h $crqp,$crpp */
5917   {
5918     MEP_INSN_CPMSBUA1_H_P1, "cpmsbua1_h_P1", "cpmsbua1.h", 32,
5919     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5920   },
5921 /* cpmsbla1.h $crqp,$crpp */
5922   {
5923     MEP_INSN_CPMSBLA1_H_P1, "cpmsbla1_h_P1", "cpmsbla1.h", 32,
5924     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5925   },
5926 /* cpmsbua1u.w $crqp,$crpp */
5927   {
5928     MEP_INSN_CPMSBUA1U_W_P1, "cpmsbua1u_w_P1", "cpmsbua1u.w", 32,
5929     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5930   },
5931 /* cpmsbla1u.w $crqp,$crpp */
5932   {
5933     MEP_INSN_CPMSBLA1U_W_P1, "cpmsbla1u_w_P1", "cpmsbla1u.w", 32,
5934     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5935   },
5936 /* cpmsbua1.w $crqp,$crpp */
5937   {
5938     MEP_INSN_CPMSBUA1_W_P1, "cpmsbua1_w_P1", "cpmsbua1.w", 32,
5939     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5940   },
5941 /* cpmsbla1.w $crqp,$crpp */
5942   {
5943     MEP_INSN_CPMSBLA1_W_P1, "cpmsbla1_w_P1", "cpmsbla1.w", 32,
5944     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5945   },
5946 /* cpsmadua1.h $crqp,$crpp */
5947   {
5948     MEP_INSN_CPSMADUA1_H_P1, "cpsmadua1_h_P1", "cpsmadua1.h", 32,
5949     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5950   },
5951 /* cpsmadla1.h $crqp,$crpp */
5952   {
5953     MEP_INSN_CPSMADLA1_H_P1, "cpsmadla1_h_P1", "cpsmadla1.h", 32,
5954     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5955   },
5956 /* cpsmadua1.w $crqp,$crpp */
5957   {
5958     MEP_INSN_CPSMADUA1_W_P1, "cpsmadua1_w_P1", "cpsmadua1.w", 32,
5959     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5960   },
5961 /* cpsmadla1.w $crqp,$crpp */
5962   {
5963     MEP_INSN_CPSMADLA1_W_P1, "cpsmadla1_w_P1", "cpsmadla1.w", 32,
5964     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5965   },
5966 /* cpsmsbua1.h $crqp,$crpp */
5967   {
5968     MEP_INSN_CPSMSBUA1_H_P1, "cpsmsbua1_h_P1", "cpsmsbua1.h", 32,
5969     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5970   },
5971 /* cpsmsbla1.h $crqp,$crpp */
5972   {
5973     MEP_INSN_CPSMSBLA1_H_P1, "cpsmsbla1_h_P1", "cpsmsbla1.h", 32,
5974     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5975   },
5976 /* cpsmsbua1.w $crqp,$crpp */
5977   {
5978     MEP_INSN_CPSMSBUA1_W_P1, "cpsmsbua1_w_P1", "cpsmsbua1.w", 32,
5979     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5980   },
5981 /* cpsmsbla1.w $crqp,$crpp */
5982   {
5983     MEP_INSN_CPSMSBLA1_W_P1, "cpsmsbla1_w_P1", "cpsmsbla1.w", 32,
5984     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5985   },
5986 /* cpmulslua1.h $crqp,$crpp */
5987   {
5988     MEP_INSN_CPMULSLUA1_H_P1, "cpmulslua1_h_P1", "cpmulslua1.h", 32,
5989     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5990   },
5991 /* cpmulslla1.h $crqp,$crpp */
5992   {
5993     MEP_INSN_CPMULSLLA1_H_P1, "cpmulslla1_h_P1", "cpmulslla1.h", 32,
5994     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
5995   },
5996 /* cpmulslua1.w $crqp,$crpp */
5997   {
5998     MEP_INSN_CPMULSLUA1_W_P1, "cpmulslua1_w_P1", "cpmulslua1.w", 32,
5999     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6000   },
6001 /* cpmulslla1.w $crqp,$crpp */
6002   {
6003     MEP_INSN_CPMULSLLA1_W_P1, "cpmulslla1_w_P1", "cpmulslla1.w", 32,
6004     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6005   },
6006 /* cpsmadslua1.h $crqp,$crpp */
6007   {
6008     MEP_INSN_CPSMADSLUA1_H_P1, "cpsmadslua1_h_P1", "cpsmadslua1.h", 32,
6009     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6010   },
6011 /* cpsmadslla1.h $crqp,$crpp */
6012   {
6013     MEP_INSN_CPSMADSLLA1_H_P1, "cpsmadslla1_h_P1", "cpsmadslla1.h", 32,
6014     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6015   },
6016 /* cpsmadslua1.w $crqp,$crpp */
6017   {
6018     MEP_INSN_CPSMADSLUA1_W_P1, "cpsmadslua1_w_P1", "cpsmadslua1.w", 32,
6019     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6020   },
6021 /* cpsmadslla1.w $crqp,$crpp */
6022   {
6023     MEP_INSN_CPSMADSLLA1_W_P1, "cpsmadslla1_w_P1", "cpsmadslla1.w", 32,
6024     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6025   },
6026 /* cpsmsbslua1.h $crqp,$crpp */
6027   {
6028     MEP_INSN_CPSMSBSLUA1_H_P1, "cpsmsbslua1_h_P1", "cpsmsbslua1.h", 32,
6029     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6030   },
6031 /* cpsmsbslla1.h $crqp,$crpp */
6032   {
6033     MEP_INSN_CPSMSBSLLA1_H_P1, "cpsmsbslla1_h_P1", "cpsmsbslla1.h", 32,
6034     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6035   },
6036 /* cpsmsbslua1.w $crqp,$crpp */
6037   {
6038     MEP_INSN_CPSMSBSLUA1_W_P1, "cpsmsbslua1_w_P1", "cpsmsbslua1.w", 32,
6039     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6040   },
6041 /* cpsmsbslla1.w $crqp,$crpp */
6042   {
6043     MEP_INSN_CPSMSBSLLA1_W_P1, "cpsmsbslla1_w_P1", "cpsmsbslla1.w", 32,
6044     { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
6045   },
6046 };
6047 
6048 #undef OP
6049 #undef A
6050 
6051 /* Initialize anything needed to be done once, before any cpu_open call.  */
6052 
6053 static void
init_tables(void)6054 init_tables (void)
6055 {
6056 }
6057 
6058 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
6059 static void build_hw_table      (CGEN_CPU_TABLE *);
6060 static void build_ifield_table  (CGEN_CPU_TABLE *);
6061 static void build_operand_table (CGEN_CPU_TABLE *);
6062 static void build_insn_table    (CGEN_CPU_TABLE *);
6063 static void mep_cgen_rebuild_tables (CGEN_CPU_TABLE *);
6064 
6065 /* Subroutine of mep_cgen_cpu_open to look up a mach via its bfd name.  */
6066 
6067 static const CGEN_MACH *
lookup_mach_via_bfd_name(const CGEN_MACH * table,const char * name)6068 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
6069 {
6070   while (table->name)
6071     {
6072       if (strcmp (name, table->bfd_name) == 0)
6073 	return table;
6074       ++table;
6075     }
6076   abort ();
6077 }
6078 
6079 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
6080 
6081 static void
build_hw_table(CGEN_CPU_TABLE * cd)6082 build_hw_table (CGEN_CPU_TABLE *cd)
6083 {
6084   int i;
6085   int machs = cd->machs;
6086   const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0];
6087   /* MAX_HW is only an upper bound on the number of selected entries.
6088      However each entry is indexed by it's enum so there can be holes in
6089      the table.  */
6090   const CGEN_HW_ENTRY **selected =
6091     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
6092 
6093   cd->hw_table.init_entries = init;
6094   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
6095   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
6096   /* ??? For now we just use machs to determine which ones we want.  */
6097   for (i = 0; init[i].name != NULL; ++i)
6098     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
6099 	& machs)
6100       selected[init[i].type] = &init[i];
6101   cd->hw_table.entries = selected;
6102   cd->hw_table.num_entries = MAX_HW;
6103 }
6104 
6105 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
6106 
6107 static void
build_ifield_table(CGEN_CPU_TABLE * cd)6108 build_ifield_table (CGEN_CPU_TABLE *cd)
6109 {
6110   cd->ifld_table = & mep_cgen_ifld_table[0];
6111 }
6112 
6113 /* Subroutine of mep_cgen_cpu_open to build the hardware table.  */
6114 
6115 static void
build_operand_table(CGEN_CPU_TABLE * cd)6116 build_operand_table (CGEN_CPU_TABLE *cd)
6117 {
6118   int i;
6119   int machs = cd->machs;
6120   const CGEN_OPERAND *init = & mep_cgen_operand_table[0];
6121   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
6122      However each entry is indexed by it's enum so there can be holes in
6123      the table.  */
6124   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
6125 
6126   cd->operand_table.init_entries = init;
6127   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
6128   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6129   /* ??? For now we just use mach to determine which ones we want.  */
6130   for (i = 0; init[i].name != NULL; ++i)
6131     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
6132 	& machs)
6133       selected[init[i].type] = &init[i];
6134   cd->operand_table.entries = selected;
6135   cd->operand_table.num_entries = MAX_OPERANDS;
6136 }
6137 
6138 /* Subroutine of mep_cgen_cpu_open to build the hardware table.
6139    ??? This could leave out insns not supported by the specified mach/isa,
6140    but that would cause errors like "foo only supported by bar" to become
6141    "unknown insn", so for now we include all insns and require the app to
6142    do the checking later.
6143    ??? On the other hand, parsing of such insns may require their hardware or
6144    operand elements to be in the table [which they mightn't be].  */
6145 
6146 static void
build_insn_table(CGEN_CPU_TABLE * cd)6147 build_insn_table (CGEN_CPU_TABLE *cd)
6148 {
6149   int i;
6150   const CGEN_IBASE *ib = & mep_cgen_insn_table[0];
6151   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
6152 
6153   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
6154   for (i = 0; i < MAX_INSNS; ++i)
6155     insns[i].base = &ib[i];
6156   cd->insn_table.init_entries = insns;
6157   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
6158   cd->insn_table.num_init_entries = MAX_INSNS;
6159 }
6160 
6161 /* Subroutine of mep_cgen_cpu_open to rebuild the tables.  */
6162 
6163 static void
mep_cgen_rebuild_tables(CGEN_CPU_TABLE * cd)6164 mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
6165 {
6166   int i;
6167   CGEN_BITSET *isas = cd->isas;
6168   unsigned int machs = cd->machs;
6169 
6170   cd->int_insn_p = CGEN_INT_INSN_P;
6171 
6172   /* Data derived from the isa spec.  */
6173 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
6174   cd->default_insn_bitsize = UNSET;
6175   cd->base_insn_bitsize = UNSET;
6176   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
6177   cd->max_insn_bitsize = 0;
6178   for (i = 0; i < MAX_ISAS; ++i)
6179     if (cgen_bitset_contains (isas, i))
6180       {
6181 	const CGEN_ISA *isa = & mep_cgen_isa_table[i];
6182 
6183 	/* Default insn sizes of all selected isas must be
6184 	   equal or we set the result to 0, meaning "unknown".  */
6185 	if (cd->default_insn_bitsize == UNSET)
6186 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
6187 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
6188 	  ; /* This is ok.  */
6189 	else
6190 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
6191 
6192 	/* Base insn sizes of all selected isas must be equal
6193 	   or we set the result to 0, meaning "unknown".  */
6194 	if (cd->base_insn_bitsize == UNSET)
6195 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
6196 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
6197 	  ; /* This is ok.  */
6198 	else
6199 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
6200 
6201 	/* Set min,max insn sizes.  */
6202 	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
6203 	  cd->min_insn_bitsize = isa->min_insn_bitsize;
6204 	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
6205 	  cd->max_insn_bitsize = isa->max_insn_bitsize;
6206       }
6207 
6208   /* Data derived from the mach spec.  */
6209   for (i = 0; i < MAX_MACHS; ++i)
6210     if (((1 << i) & machs) != 0)
6211       {
6212 	const CGEN_MACH *mach = & mep_cgen_mach_table[i];
6213 
6214 	if (mach->insn_chunk_bitsize != 0)
6215 	{
6216 	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
6217 	    {
6218 	      fprintf (stderr, "mep_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
6219 		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
6220 	      abort ();
6221 	    }
6222 
6223  	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
6224 	}
6225       }
6226 
6227   /* Determine which hw elements are used by MACH.  */
6228   build_hw_table (cd);
6229 
6230   /* Build the ifield table.  */
6231   build_ifield_table (cd);
6232 
6233   /* Determine which operands are used by MACH/ISA.  */
6234   build_operand_table (cd);
6235 
6236   /* Build the instruction table.  */
6237   build_insn_table (cd);
6238 }
6239 
6240 /* Initialize a cpu table and return a descriptor.
6241    It's much like opening a file, and must be the first function called.
6242    The arguments are a set of (type/value) pairs, terminated with
6243    CGEN_CPU_OPEN_END.
6244 
6245    Currently supported values:
6246    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
6247    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
6248    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
6249    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
6250    CGEN_CPU_OPEN_END:     terminates arguments
6251 
6252    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
6253    precluded.  */
6254 
6255 CGEN_CPU_DESC
mep_cgen_cpu_open(enum cgen_cpu_open_arg arg_type,...)6256 mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
6257 {
6258   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
6259   static int init_p;
6260   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
6261   unsigned int machs = 0; /* 0 = "unspecified" */
6262   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
6263   va_list ap;
6264 
6265   if (! init_p)
6266     {
6267       init_tables ();
6268       init_p = 1;
6269     }
6270 
6271   memset (cd, 0, sizeof (*cd));
6272 
6273   va_start (ap, arg_type);
6274   while (arg_type != CGEN_CPU_OPEN_END)
6275     {
6276       switch (arg_type)
6277 	{
6278 	case CGEN_CPU_OPEN_ISAS :
6279 	  isas = va_arg (ap, CGEN_BITSET *);
6280 	  break;
6281 	case CGEN_CPU_OPEN_MACHS :
6282 	  machs = va_arg (ap, unsigned int);
6283 	  break;
6284 	case CGEN_CPU_OPEN_BFDMACH :
6285 	  {
6286 	    const char *name = va_arg (ap, const char *);
6287 	    const CGEN_MACH *mach =
6288 	      lookup_mach_via_bfd_name (mep_cgen_mach_table, name);
6289 
6290 	    machs |= 1 << mach->num;
6291 	    break;
6292 	  }
6293 	case CGEN_CPU_OPEN_ENDIAN :
6294 	  endian = va_arg (ap, enum cgen_endian);
6295 	  break;
6296 	default :
6297 	  fprintf (stderr, "mep_cgen_cpu_open: unsupported argument `%d'\n",
6298 		   arg_type);
6299 	  abort (); /* ??? return NULL? */
6300 	}
6301       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
6302     }
6303   va_end (ap);
6304 
6305   /* Mach unspecified means "all".  */
6306   if (machs == 0)
6307     machs = (1 << MAX_MACHS) - 1;
6308   /* Base mach is always selected.  */
6309   machs |= 1;
6310   if (endian == CGEN_ENDIAN_UNKNOWN)
6311     {
6312       /* ??? If target has only one, could have a default.  */
6313       fprintf (stderr, "mep_cgen_cpu_open: no endianness specified\n");
6314       abort ();
6315     }
6316 
6317   cd->isas = cgen_bitset_copy (isas);
6318   cd->machs = machs;
6319   cd->endian = endian;
6320   /* FIXME: for the sparc case we can determine insn-endianness statically.
6321      The worry here is where both data and insn endian can be independently
6322      chosen, in which case this function will need another argument.
6323      Actually, will want to allow for more arguments in the future anyway.  */
6324   cd->insn_endian = endian;
6325 
6326   /* Table (re)builder.  */
6327   cd->rebuild_tables = mep_cgen_rebuild_tables;
6328   mep_cgen_rebuild_tables (cd);
6329 
6330   /* Default to not allowing signed overflow.  */
6331   cd->signed_overflow_ok_p = 0;
6332 
6333   return (CGEN_CPU_DESC) cd;
6334 }
6335 
6336 /* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
6337    MACH_NAME is the bfd name of the mach.  */
6338 
6339 CGEN_CPU_DESC
mep_cgen_cpu_open_1(const char * mach_name,enum cgen_endian endian)6340 mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
6341 {
6342   return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
6343 			       CGEN_CPU_OPEN_ENDIAN, endian,
6344 			       CGEN_CPU_OPEN_END);
6345 }
6346 
6347 /* Close a cpu table.
6348    ??? This can live in a machine independent file, but there's currently
6349    no place to put this file (there's no libcgen).  libopcodes is the wrong
6350    place as some simulator ports use this but they don't use libopcodes.  */
6351 
6352 void
mep_cgen_cpu_close(CGEN_CPU_DESC cd)6353 mep_cgen_cpu_close (CGEN_CPU_DESC cd)
6354 {
6355   unsigned int i;
6356   const CGEN_INSN *insns;
6357 
6358   if (cd->macro_insn_table.init_entries)
6359     {
6360       insns = cd->macro_insn_table.init_entries;
6361       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
6362 	if (CGEN_INSN_RX ((insns)))
6363 	  regfree (CGEN_INSN_RX (insns));
6364     }
6365 
6366   if (cd->insn_table.init_entries)
6367     {
6368       insns = cd->insn_table.init_entries;
6369       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
6370 	if (CGEN_INSN_RX (insns))
6371 	  regfree (CGEN_INSN_RX (insns));
6372     }
6373 
6374   if (cd->macro_insn_table.init_entries)
6375     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
6376 
6377   if (cd->insn_table.init_entries)
6378     free ((CGEN_INSN *) cd->insn_table.init_entries);
6379 
6380   if (cd->hw_table.entries)
6381     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
6382 
6383   if (cd->operand_table.entries)
6384     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
6385 
6386   free (cd);
6387 }
6388 
6389