1 /* Copyright (c) 2009 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iom128rfa1.h 2477 2015-06-19 13:22:24Z pitchumani $ */ 32 33 /* avr/iom128rfa1.h - definitions for ATmega128RFA1 */ 34 35 #ifndef _AVR_IOM128RFA1_H_ 36 #define _AVR_IOM128RFA1_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "iom128rfa1.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 #include <avr/sfr_defs.h> 51 52 #ifndef __ASSEMBLER__ 53 # define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) 54 # define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) 55 # define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) 56 #endif /* __ASSEMBLER__ */ 57 58 /* 59 * USAGE: 60 * 61 * simple register assignment: 62 * TIFR1 = 0x17 63 * subregister assignment: 64 * TIFR1_struct.ocf1a = 1 65 * (subregister names are converted to small letters) 66 */ 67 68 69 /* Port A Input Pins Address */ 70 #define PINA _SFR_IO8(0x00) 71 72 /* PINA */ 73 74 #define PINA0 0 75 #define PINA1 1 76 #define PINA2 2 77 #define PINA3 3 78 #define PINA4 4 79 #define PINA5 5 80 #define PINA6 6 81 #define PINA7 7 82 83 /* Port A Data Direction Register */ 84 #define DDRA _SFR_IO8(0x01) 85 86 /* DDRA */ 87 88 #define DDA0 0 89 #define DDA1 1 90 #define DDA2 2 91 #define DDA3 3 92 #define DDA4 4 93 #define DDA5 5 94 #define DDA6 6 95 #define DDA7 7 96 97 /* Port A Data Register */ 98 #define PORTA _SFR_IO8(0x02) 99 100 /* PORTA */ 101 102 #define PORTA0 0 103 #define PA0 0 104 #define PORTA1 1 105 #define PA1 1 106 #define PORTA2 2 107 #define PA2 2 108 #define PORTA3 3 109 #define PA3 3 110 #define PORTA4 4 111 #define PA4 4 112 #define PORTA5 5 113 #define PA5 5 114 #define PORTA6 6 115 #define PA6 6 116 #define PORTA7 7 117 #define PA7 7 118 119 /* Port B Input Pins Address */ 120 #define PINB _SFR_IO8(0x03) 121 122 /* PINB */ 123 124 #define PINB0 0 125 #define PINB1 1 126 #define PINB2 2 127 #define PINB3 3 128 #define PINB4 4 129 #define PINB5 5 130 #define PINB6 6 131 #define PINB7 7 132 133 /* Port B Data Direction Register */ 134 #define DDRB _SFR_IO8(0x04) 135 136 /* DDRB */ 137 138 #define DDB0 0 139 #define DDB1 1 140 #define DDB2 2 141 #define DDB3 3 142 #define DDB4 4 143 #define DDB5 5 144 #define DDB6 6 145 #define DDB7 7 146 147 /* Port B Data Register */ 148 #define PORTB _SFR_IO8(0x05) 149 150 /* PORTB */ 151 152 #define PORTB0 0 153 #define PB0 0 154 #define PORTB1 1 155 #define PB1 1 156 #define PORTB2 2 157 #define PB2 2 158 #define PORTB3 3 159 #define PB3 3 160 #define PORTB4 4 161 #define PB4 4 162 #define PORTB5 5 163 #define PB5 5 164 #define PORTB6 6 165 #define PB6 6 166 #define PORTB7 7 167 #define PB7 7 168 169 /* Port C Input Pins Address */ 170 #define PINC _SFR_IO8(0x06) 171 172 /* PINC */ 173 174 #define PINC0 0 175 #define PINC1 1 176 #define PINC2 2 177 #define PINC3 3 178 #define PINC4 4 179 #define PINC5 5 180 #define PINC6 6 181 #define PINC7 7 182 183 /* Port C Data Direction Register */ 184 #define DDRC _SFR_IO8(0x07) 185 186 /* DDRC */ 187 188 #define DDC0 0 189 #define DDC1 1 190 #define DDC2 2 191 #define DDC3 3 192 #define DDC4 4 193 #define DDC5 5 194 #define DDC6 6 195 #define DDC7 7 196 197 /* Port C Data Register */ 198 #define PORTC _SFR_IO8(0x08) 199 200 /* PORTC */ 201 202 #define PORTC0 0 203 #define PC0 0 204 #define PORTC1 1 205 #define PC1 1 206 #define PORTC2 2 207 #define PC2 2 208 #define PORTC3 3 209 #define PC3 3 210 #define PORTC4 4 211 #define PC4 4 212 #define PORTC5 5 213 #define PC5 5 214 #define PORTC6 6 215 #define PC6 6 216 #define PORTC7 7 217 #define PC7 7 218 219 /* Port D Input Pins Address */ 220 #define PIND _SFR_IO8(0x09) 221 222 /* PIND */ 223 224 #define PIND0 0 225 #define PIND1 1 226 #define PIND2 2 227 #define PIND3 3 228 #define PIND4 4 229 #define PIND5 5 230 #define PIND6 6 231 #define PIND7 7 232 233 /* Port D Data Direction Register */ 234 #define DDRD _SFR_IO8(0x0A) 235 236 /* DDRD */ 237 238 #define DDD0 0 239 #define DDD1 1 240 #define DDD2 2 241 #define DDD3 3 242 #define DDD4 4 243 #define DDD5 5 244 #define DDD6 6 245 #define DDD7 7 246 247 /* Port D Data Register */ 248 #define PORTD _SFR_IO8(0x0B) 249 250 /* PORTD */ 251 252 #define PORTD0 0 253 #define PD0 0 254 #define PORTD1 1 255 #define PD1 1 256 #define PORTD2 2 257 #define PD2 2 258 #define PORTD3 3 259 #define PD3 3 260 #define PORTD4 4 261 #define PD4 4 262 #define PORTD5 5 263 #define PD5 5 264 #define PORTD6 6 265 #define PD6 6 266 #define PORTD7 7 267 #define PD7 7 268 269 /* Port E Input Pins Address */ 270 #define PINE _SFR_IO8(0x0C) 271 272 /* PINE */ 273 274 #define PINE0 0 275 #define PINE1 1 276 #define PINE2 2 277 #define PINE3 3 278 #define PINE4 4 279 #define PINE5 5 280 #define PINE6 6 281 #define PINE7 7 282 283 /* Port E Data Direction Register */ 284 #define DDRE _SFR_IO8(0x0D) 285 286 /* DDRE */ 287 288 #define DDE0 0 289 #define DDE1 1 290 #define DDE2 2 291 #define DDE3 3 292 #define DDE4 4 293 #define DDE5 5 294 #define DDE6 6 295 #define DDE7 7 296 297 /* Port E Data Register */ 298 #define PORTE _SFR_IO8(0x0E) 299 300 /* PORTE */ 301 302 #define PORTE0 0 303 #define PE0 0 304 #define PORTE1 1 305 #define PE1 1 306 #define PORTE2 2 307 #define PE2 2 308 #define PORTE3 3 309 #define PE3 3 310 #define PORTE4 4 311 #define PE4 4 312 #define PORTE5 5 313 #define PE5 5 314 #define PORTE6 6 315 #define PE6 6 316 #define PORTE7 7 317 #define PE7 7 318 319 /* Port F Input Pins Address */ 320 #define PINF _SFR_IO8(0x0F) 321 322 /* PINF */ 323 324 #define PINF0 0 325 #define PINF1 1 326 #define PINF2 2 327 #define PINF3 3 328 #define PINF4 4 329 #define PINF5 5 330 #define PINF6 6 331 #define PINF7 7 332 333 /* Port F Data Direction Register */ 334 #define DDRF _SFR_IO8(0x10) 335 336 /* DDRF */ 337 338 #define DDF0 0 339 #define DDF1 1 340 #define DDF2 2 341 #define DDF3 3 342 #define DDF4 4 343 #define DDF5 5 344 #define DDF6 6 345 #define DDF7 7 346 347 /* Port F Data Register */ 348 #define PORTF _SFR_IO8(0x11) 349 350 /* PORTF */ 351 352 #define PORTF0 0 353 #define PF0 0 354 #define PORTF1 1 355 #define PF1 1 356 #define PORTF2 2 357 #define PF2 2 358 #define PORTF3 3 359 #define PF3 3 360 #define PORTF4 4 361 #define PF4 4 362 #define PORTF5 5 363 #define PF5 5 364 #define PORTF6 6 365 #define PF6 6 366 #define PORTF7 7 367 #define PF7 7 368 369 /* Port G Input Pins Address */ 370 #define PING _SFR_IO8(0x12) 371 372 /* PING */ 373 374 #define PING0 0 375 #define PING1 1 376 #define PING2 2 377 #define PING3 3 378 #define PING4 4 379 #define PING5 5 380 381 /* Port G Data Direction Register */ 382 #define DDRG _SFR_IO8(0x13) 383 384 /* DDRG */ 385 386 #define DDG0 0 387 #define DDG1 1 388 #define DDG2 2 389 #define DDG3 3 390 #define DDG4 4 391 #define DDG5 5 392 393 /* Port G Data Register */ 394 #define PORTG _SFR_IO8(0x14) 395 396 /* PORTG */ 397 398 #define PORTG0 0 399 #define PG0 0 400 #define PORTG1 1 401 #define PG1 1 402 #define PORTG2 2 403 #define PG2 2 404 #define PORTG3 3 405 #define PG3 3 406 #define PORTG4 4 407 #define PG4 4 408 #define PORTG5 5 409 #define PG5 5 410 411 /* Timer/Counter0 Interrupt Flag Register */ 412 #define TIFR0 _SFR_IO8(0x15) 413 414 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 415 416 struct __reg_TIFR0 { 417 unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ 418 unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ 419 unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ 420 unsigned int : 5; 421 }; 422 423 #define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) 424 425 #endif /* __ASSEMBLER__ */ 426 427 /* TIFR0 */ 428 429 #define TOV0 0 430 #define OCF0A 1 431 #define OCF0B 2 432 433 /* Timer/Counter1 Interrupt Flag Register */ 434 #define TIFR1 _SFR_IO8(0x16) 435 436 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 437 438 struct __reg_TIFR1 { 439 unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ 440 unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ 441 unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ 442 unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ 443 unsigned int : 1; 444 unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ 445 unsigned int : 2; 446 }; 447 448 #define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) 449 450 #endif /* __ASSEMBLER__ */ 451 452 /* TIFR1 */ 453 454 #define TOV1 0 455 #define OCF1A 1 456 #define OCF1B 2 457 #define OCF1C 3 458 #define ICF1 5 459 460 /* Timer/Counter Interrupt Flag Register */ 461 #define TIFR2 _SFR_IO8(0x17) 462 463 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 464 465 struct __reg_TIFR2 { 466 unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ 467 unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ 468 unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ 469 unsigned int : 5; 470 }; 471 472 #define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) 473 474 #endif /* __ASSEMBLER__ */ 475 476 /* TIFR2 */ 477 478 #define TOV2 0 479 #define OCF2A 1 480 #define OCF2B 2 481 482 /* Timer/Counter3 Interrupt Flag Register */ 483 #define TIFR3 _SFR_IO8(0x18) 484 485 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 486 487 struct __reg_TIFR3 { 488 unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ 489 unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ 490 unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ 491 unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ 492 unsigned int : 1; 493 unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ 494 unsigned int : 2; 495 }; 496 497 #define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) 498 499 #endif /* __ASSEMBLER__ */ 500 501 /* TIFR3 */ 502 503 #define TOV3 0 504 #define OCF3A 1 505 #define OCF3B 2 506 #define OCF3C 3 507 #define ICF3 5 508 509 /* Timer/Counter4 Interrupt Flag Register */ 510 #define TIFR4 _SFR_IO8(0x19) 511 512 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 513 514 struct __reg_TIFR4 { 515 unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ 516 unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ 517 unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ 518 unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ 519 unsigned int : 1; 520 unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ 521 unsigned int : 2; 522 }; 523 524 #define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) 525 526 #endif /* __ASSEMBLER__ */ 527 528 /* TIFR4 */ 529 530 #define TOV4 0 531 #define OCF4A 1 532 #define OCF4B 2 533 #define OCF4C 3 534 #define ICF4 5 535 536 /* Timer/Counter5 Interrupt Flag Register */ 537 #define TIFR5 _SFR_IO8(0x1A) 538 539 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 540 541 struct __reg_TIFR5 { 542 unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ 543 unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ 544 unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ 545 unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ 546 unsigned int : 1; 547 unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ 548 unsigned int : 2; 549 }; 550 551 #define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) 552 553 #endif /* __ASSEMBLER__ */ 554 555 /* TIFR5 */ 556 557 #define TOV5 0 558 #define OCF5A 1 559 #define OCF5B 2 560 #define OCF5C 3 561 #define ICF5 5 562 563 /* Pin Change Interrupt Flag Register */ 564 #define PCIFR _SFR_IO8(0x1B) 565 566 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 567 568 struct __reg_PCIFR { 569 unsigned int pcif : 3; /* Pin Change Interrupt Flag 2 */ 570 unsigned int : 5; 571 }; 572 573 #define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) 574 575 #endif /* __ASSEMBLER__ */ 576 577 /* PCIFR */ 578 579 #define PCIF0 0 580 #define PCIF1 1 581 #define PCIF2 2 582 583 /* External Interrupt Flag Register */ 584 #define EIFR _SFR_IO8(0x1C) 585 586 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 587 588 struct __reg_EIFR { 589 unsigned int intf : 8; /* External Interrupt Flag */ 590 }; 591 592 #define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) 593 594 #endif /* __ASSEMBLER__ */ 595 596 /* EIFR */ 597 598 #define INTF0 0 599 #define INTF1 1 600 #define INTF2 2 601 #define INTF3 3 602 #define INTF4 4 603 #define INTF5 5 604 #define INTF6 6 605 #define INTF7 7 606 607 /* External Interrupt Mask Register */ 608 #define EIMSK _SFR_IO8(0x1D) 609 610 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 611 612 struct __reg_EIMSK { 613 unsigned int intm : 8; /* External Interrupt Request Enable */ 614 }; 615 616 #define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) 617 618 #endif /* __ASSEMBLER__ */ 619 620 /* EIMSK */ 621 622 #define INT0 0 623 #define INT1 1 624 #define INT2 2 625 #define INT3 3 626 #define INT4 4 627 #define INT5 5 628 #define INT6 6 629 #define INT7 7 630 631 /* General Purpose IO Register 0 */ 632 #define GPIOR0 _SFR_IO8(0x1E) 633 634 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 635 636 struct __reg_GPIOR0 { 637 unsigned int gpior0 : 8; /* General Purpose I/O Register 0 Value */ 638 }; 639 640 #define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) 641 642 #endif /* __ASSEMBLER__ */ 643 644 /* GPIOR0 */ 645 646 #define GPIOR00 0 647 #define GPIOR01 1 648 #define GPIOR02 2 649 #define GPIOR03 3 650 #define GPIOR04 4 651 #define GPIOR05 5 652 #define GPIOR06 6 653 #define GPIOR07 7 654 655 /* 6-char sequence denoting where to find the EEPROM registers in memory space. 656 Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM 657 subroutines. 658 First two letters: EECR address. 659 Second two letters: EEDR address. 660 Last two letters: EEAR address. */ 661 662 #define __EEPROM_REG_LOCATIONS__ 1F2021 663 664 /* EEPROM Control Register */ 665 #define EECR _SFR_IO8(0x1F) 666 667 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 668 669 struct __reg_EECR { 670 unsigned int eere : 1; /* EEPROM Read Enable */ 671 unsigned int eepe : 1; /* EEPROM Programming Enable */ 672 unsigned int eempe : 1; /* EEPROM Master Write Enable */ 673 unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ 674 unsigned int eepm : 2; /* EEPROM Programming Mode */ 675 unsigned int : 2; 676 }; 677 678 #define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) 679 680 #endif /* __ASSEMBLER__ */ 681 682 /* EECR */ 683 684 #define EERE 0 685 #define EEPE 1 686 #define EEMPE 2 687 #define EERIE 3 688 #define EEPM0 4 689 #define EEPM1 5 690 691 /* EEPROM Data Register */ 692 #define EEDR _SFR_IO8(0x20) 693 694 /* EEDR */ 695 696 #define EEDR0 0 697 #define EEDR1 1 698 #define EEDR2 2 699 #define EEDR3 3 700 #define EEDR4 4 701 #define EEDR5 5 702 #define EEDR6 6 703 #define EEDR7 7 704 705 /* EEPROM Address Register Bytes */ 706 #define EEAR _SFR_IO16(0x21) 707 #define EEARL _SFR_IO8(0x21) 708 #define EEARH _SFR_IO8(0x22) 709 710 /* General Timer/Counter Control Register */ 711 #define GTCCR _SFR_IO8(0x23) 712 713 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 714 715 struct __reg_GTCCR { 716 unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ 717 unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ 718 unsigned int : 5; 719 unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ 720 }; 721 722 #define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) 723 724 #endif /* __ASSEMBLER__ */ 725 726 /* GTCCR */ 727 728 #define PSRSYNC 0 729 #define PSR10 0 730 #define PSRASY 1 731 #define PSR2 1 732 #define TSM 7 733 734 /* Timer/Counter0 Control Register A */ 735 #define TCCR0A _SFR_IO8(0x24) 736 737 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 738 739 struct __reg_TCCR0A { 740 unsigned int wgm0 : 2; /* Waveform Generation Mode */ 741 unsigned int : 2; 742 unsigned int com0b : 2; /* Compare Match Output B Mode */ 743 unsigned int com0a : 2; /* Compare Match Output A Mode */ 744 }; 745 746 #define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) 747 748 #endif /* __ASSEMBLER__ */ 749 750 /* TCCR0A */ 751 752 #define WGM00 0 753 #define WGM01 1 754 #define COM0B0 4 755 #define COM0B1 5 756 #define COM0A0 6 757 #define COM0A1 7 758 759 /* Timer/Counter0 Control Register B */ 760 #define TCCR0B _SFR_IO8(0x25) 761 762 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 763 764 struct __reg_TCCR0B { 765 unsigned int cs0 : 3; /* Clock Select */ 766 unsigned int wgm02 : 1; /* */ 767 unsigned int : 2; 768 unsigned int foc0b : 1; /* Force Output Compare B */ 769 unsigned int foc0a : 1; /* Force Output Compare A */ 770 }; 771 772 #define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) 773 774 #endif /* __ASSEMBLER__ */ 775 776 /* TCCR0B */ 777 778 #define CS00 0 779 #define CS01 1 780 #define CS02 2 781 #define WGM02 3 782 #define FOC0B 6 783 #define FOC0A 7 784 785 /* Timer/Counter0 Register */ 786 #define TCNT0 _SFR_IO8(0x26) 787 788 /* TCNT0 */ 789 790 #define TCNT0_0 0 791 #define TCNT0_1 1 792 #define TCNT0_2 2 793 #define TCNT0_3 3 794 #define TCNT0_4 4 795 #define TCNT0_5 5 796 #define TCNT0_6 6 797 #define TCNT0_7 7 798 799 /* Timer/Counter0 Output Compare Register */ 800 #define OCR0A _SFR_IO8(0x27) 801 802 /* OCR0A */ 803 804 #define OCR0A_0 0 805 #define OCR0A_1 1 806 #define OCR0A_2 2 807 #define OCR0A_3 3 808 #define OCR0A_4 4 809 #define OCR0A_5 5 810 #define OCR0A_6 6 811 #define OCR0A_7 7 812 813 /* Timer/Counter0 Output Compare Register B */ 814 #define OCR0B _SFR_IO8(0x28) 815 816 /* OCR0B */ 817 818 #define OCR0B_0 0 819 #define OCR0B_1 1 820 #define OCR0B_2 2 821 #define OCR0B_3 3 822 #define OCR0B_4 4 823 #define OCR0B_5 5 824 #define OCR0B_6 6 825 #define OCR0B_7 7 826 827 /* General Purpose IO Register 1 */ 828 #define GPIOR1 _SFR_IO8(0x2A) 829 830 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 831 832 struct __reg_GPIOR1 { 833 unsigned int gpior1 : 8; /* General Purpose I/O Register 1 Value */ 834 }; 835 836 #define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) 837 838 #endif /* __ASSEMBLER__ */ 839 840 /* GPIOR1 */ 841 842 #define GPIOR10 0 843 #define GPIOR11 1 844 #define GPIOR12 2 845 #define GPIOR13 3 846 #define GPIOR14 4 847 #define GPIOR15 5 848 #define GPIOR16 6 849 #define GPIOR17 7 850 851 /* General Purpose I/O Register 2 */ 852 #define GPIOR2 _SFR_IO8(0x2B) 853 854 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 855 856 struct __reg_GPIOR2 { 857 unsigned int gpior2 : 8; /* General Purpose I/O Register 2 Value */ 858 }; 859 860 #define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) 861 862 #endif /* __ASSEMBLER__ */ 863 864 /* GPIOR2 */ 865 866 #define GPIOR20 0 867 #define GPIOR21 1 868 #define GPIOR22 2 869 #define GPIOR23 3 870 #define GPIOR24 4 871 #define GPIOR25 5 872 #define GPIOR26 6 873 #define GPIOR27 7 874 875 /* SPI Control Register */ 876 #define SPCR _SFR_IO8(0x2C) 877 878 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 879 880 struct __reg_SPCR { 881 unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ 882 unsigned int cpha : 1; /* Clock Phase */ 883 unsigned int cpol : 1; /* Clock polarity */ 884 unsigned int mstr : 1; /* Master/Slave Select */ 885 unsigned int dord : 1; /* Data Order */ 886 unsigned int spe : 1; /* SPI Enable */ 887 unsigned int spie : 1; /* SPI Interrupt Enable */ 888 }; 889 890 #define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) 891 892 #endif /* __ASSEMBLER__ */ 893 894 /* SPCR */ 895 896 #define SPR0 0 897 #define SPR1 1 898 #define CPHA 2 899 #define CPOL 3 900 #define MSTR 4 901 #define DORD 5 902 #define SPE 6 903 #define SPIE 7 904 905 /* SPI Status Register */ 906 #define SPSR _SFR_IO8(0x2D) 907 908 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 909 910 struct __reg_SPSR { 911 unsigned int spi2x : 1; /* Double SPI Speed Bit */ 912 unsigned int : 5; 913 unsigned int wcol : 1; /* Write Collision Flag */ 914 unsigned int spif : 1; /* SPI Interrupt Flag */ 915 }; 916 917 #define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) 918 919 #endif /* __ASSEMBLER__ */ 920 921 /* SPSR */ 922 923 #define SPI2X 0 924 #define WCOL 6 925 #define SPIF 7 926 927 /* SPI Data Register */ 928 #define SPDR _SFR_IO8(0x2E) 929 930 /* SPDR */ 931 932 #define SPDR0 0 933 #define SPDR1 1 934 #define SPDR2 2 935 #define SPDR3 3 936 #define SPDR4 4 937 #define SPDR5 5 938 #define SPDR6 6 939 #define SPDR7 7 940 941 /* Analog Comparator Control And Status Register */ 942 #define ACSR _SFR_IO8(0x30) 943 944 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 945 946 struct __reg_ACSR { 947 unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ 948 unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ 949 unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ 950 unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ 951 unsigned int aco : 1; /* Analog Compare Output */ 952 unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ 953 unsigned int acd : 1; /* Analog Comparator Disable */ 954 }; 955 956 #define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) 957 958 #endif /* __ASSEMBLER__ */ 959 960 /* ACSR */ 961 962 #define ACIS0 0 963 #define ACIS1 1 964 #define ACIC 2 965 #define ACIE 3 966 #define ACI 4 967 #define ACO 5 968 #define ACBG 6 969 #define ACD 7 970 971 /* On-Chip Debug Register */ 972 #define OCDR _SFR_IO8(0x31) 973 974 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 975 976 struct __reg_OCDR { 977 unsigned int ocdr : 8; /* On-Chip Debug Register Data */ 978 }; 979 980 #define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) 981 982 #endif /* __ASSEMBLER__ */ 983 984 /* OCDR */ 985 986 #define OCDR0 0 987 #define OCDR1 1 988 #define OCDR2 2 989 #define OCDR3 3 990 #define OCDR4 4 991 #define OCDR5 5 992 #define OCDR6 6 993 #define OCDR7 7 994 #define IDRD 7 995 996 /* Sleep Mode Control Register */ 997 #define SMCR _SFR_IO8(0x33) 998 999 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1000 1001 struct __reg_SMCR { 1002 unsigned int se : 1; /* Sleep Enable */ 1003 unsigned int sm : 3; /* Sleep Mode Select bits */ 1004 unsigned int : 4; 1005 }; 1006 1007 #define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) 1008 1009 #endif /* __ASSEMBLER__ */ 1010 1011 /* SMCR */ 1012 1013 #define SE 0 1014 #define SM0 1 1015 #define SM1 2 1016 #define SM2 3 1017 1018 /* MCU Status Register */ 1019 #define MCUSR _SFR_IO8(0x34) 1020 1021 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1022 1023 struct __reg_MCUSR { 1024 unsigned int porf : 1; /* Power-on Reset Flag */ 1025 unsigned int extrf : 1; /* External Reset Flag */ 1026 unsigned int borf : 1; /* Brown-out Reset Flag */ 1027 unsigned int wdrf : 1; /* Watchdog Reset Flag */ 1028 unsigned int jtrf : 1; /* JTAG Reset Flag */ 1029 unsigned int : 3; 1030 }; 1031 1032 #define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) 1033 1034 #endif /* __ASSEMBLER__ */ 1035 1036 /* MCUSR */ 1037 1038 #define PORF 0 1039 #define EXTRF 1 1040 #define BORF 2 1041 #define WDRF 3 1042 #define JTRF 4 1043 1044 /* MCU Control Register */ 1045 #define MCUCR _SFR_IO8(0x35) 1046 1047 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1048 1049 struct __reg_MCUCR { 1050 unsigned int ivce : 1; /* Interrupt Vector Change Enable */ 1051 unsigned int ivsel : 1; /* Interrupt Vector Select */ 1052 unsigned int : 2; 1053 unsigned int pud : 1; /* Pull-up Disable */ 1054 unsigned int : 2; 1055 unsigned int jtd : 1; /* JTAG Interface Disable */ 1056 }; 1057 1058 #define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) 1059 1060 #endif /* __ASSEMBLER__ */ 1061 1062 /* MCUCR */ 1063 1064 #define IVCE 0 1065 #define IVSEL 1 1066 #define PUD 4 1067 #define JTD 7 1068 1069 /* Store Program Memory Control Register */ 1070 #define SPMCSR _SFR_IO8(0x37) 1071 1072 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1073 1074 struct __reg_SPMCSR { 1075 unsigned int spmen : 1; /* Store Program Memory Enable */ 1076 unsigned int pgers : 1; /* Page Erase */ 1077 unsigned int pgwrt : 1; /* Page Write */ 1078 unsigned int blbset : 1; /* Boot Lock Bit Set */ 1079 unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ 1080 unsigned int sigrd : 1; /* Signature Row Read */ 1081 unsigned int rwwsb : 1; /* Read While Write Section Busy */ 1082 unsigned int spmie : 1; /* SPM Interrupt Enable */ 1083 }; 1084 1085 #define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) 1086 1087 #endif /* __ASSEMBLER__ */ 1088 1089 /* SPMCSR */ 1090 1091 #define SPMEN 0 1092 #define PGERS 1 1093 #define PGWRT 2 1094 #define BLBSET 3 1095 #define RWWSRE 4 1096 #define SIGRD 5 1097 #define RWWSB 6 1098 #define SPMIE 7 1099 1100 /* Extended Z-pointer Register for ELPM/SPM */ 1101 #define RAMPZ _SFR_IO8(0x3B) 1102 1103 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1104 1105 struct __reg_RAMPZ { 1106 unsigned int rampz : 2; /* Extended Z-Pointer Value */ 1107 unsigned int : 6; 1108 }; 1109 1110 #define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) 1111 1112 #endif /* __ASSEMBLER__ */ 1113 1114 /* RAMPZ */ 1115 1116 #define RAMPZ0 0 1117 #define RAMPZ1 1 1118 1119 /* Stack Pointer */ 1120 #define SP _SFR_IO16(0x3D) 1121 #define SPL _SFR_IO8(0x3D) 1122 #define SPH _SFR_IO8(0x3E) 1123 1124 /* Status Register */ 1125 #define SREG _SFR_IO8(0x3F) 1126 1127 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1128 1129 struct __reg_SREG { 1130 unsigned int c : 1; /* Carry Flag */ 1131 unsigned int z : 1; /* Zero Flag */ 1132 unsigned int n : 1; /* Negative Flag */ 1133 unsigned int v : 1; /* Two's Complement Overflow Flag */ 1134 unsigned int s : 1; /* Sign Bit */ 1135 unsigned int h : 1; /* Half Carry Flag */ 1136 unsigned int t : 1; /* Bit Copy Storage */ 1137 unsigned int i : 1; /* Global Interrupt Enable */ 1138 }; 1139 1140 #define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) 1141 1142 #endif /* __ASSEMBLER__ */ 1143 1144 /* SREG */ 1145 1146 #define SREG_C 0 1147 #define SREG_Z 1 1148 #define SREG_N 2 1149 #define SREG_V 3 1150 #define SREG_S 4 1151 #define SREG_H 5 1152 #define SREG_T 6 1153 #define SREG_I 7 1154 1155 /* Watchdog Timer Control Register */ 1156 #define WDTCSR _SFR_MEM8(0x60) 1157 1158 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1159 1160 struct __reg_WDTCSR { 1161 unsigned int wdp : 3; /* Watchdog Timer Prescaler bits */ 1162 unsigned int wde : 1; /* Watch Dog Enable */ 1163 unsigned int wdce : 1; /* Watchdog Change Enable */ 1164 unsigned int : 1; 1165 unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ 1166 unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ 1167 }; 1168 1169 #define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) 1170 1171 #endif /* __ASSEMBLER__ */ 1172 1173 /* WDTCSR */ 1174 1175 #define WDP0 0 1176 #define WDP1 1 1177 #define WDP2 2 1178 #define WDE 3 1179 #define WDCE 4 1180 #define WDP3 5 1181 #define WDIE 6 1182 #define WDIF 7 1183 1184 /* Clock Prescale Register */ 1185 #define CLKPR _SFR_MEM8(0x61) 1186 1187 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1188 1189 struct __reg_CLKPR { 1190 unsigned int clkps : 4; /* Clock Prescaler Select Bits */ 1191 unsigned int : 3; 1192 unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ 1193 }; 1194 1195 #define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) 1196 1197 #endif /* __ASSEMBLER__ */ 1198 1199 /* CLKPR */ 1200 1201 #define CLKPS0 0 1202 #define CLKPS1 1 1203 #define CLKPS2 2 1204 #define CLKPS3 3 1205 #define CLKPCE 7 1206 1207 /* Power Reduction Register 2 */ 1208 #define PRR2 _SFR_MEM8(0x63) 1209 1210 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1211 1212 struct __reg_PRR2 { 1213 unsigned int prram : 4; /* Power Reduction SRAM 3 */ 1214 unsigned int : 4; 1215 }; 1216 1217 #define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) 1218 1219 #endif /* __ASSEMBLER__ */ 1220 1221 /* PRR2 */ 1222 1223 #define PRRAM0 0 1224 #define PRRAM1 1 1225 #define PRRAM2 2 1226 #define PRRAM3 3 1227 1228 #define __AVR_HAVE_PRR2 ((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3)) 1229 #define __AVR_HAVE_PRR2_PRRAM0 1230 #define __AVR_HAVE_PRR2_PRRAM1 1231 #define __AVR_HAVE_PRR2_PRRAM2 1232 #define __AVR_HAVE_PRR2_PRRAM3 1233 1234 /* Power Reduction Register0 */ 1235 #define PRR0 _SFR_MEM8(0x64) 1236 1237 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1238 1239 struct __reg_PRR0 { 1240 unsigned int pradc : 1; /* Power Reduction ADC */ 1241 unsigned int prusart0 : 1; /* Power Reduction USART */ 1242 unsigned int prspi : 1; /* Power Reduction Serial Peripheral Interface */ 1243 unsigned int prtim1 : 1; /* Power Reduction Timer/Counter1 */ 1244 unsigned int prpga : 1; /* Power Reduction PGA */ 1245 unsigned int prtim0 : 1; /* Power Reduction Timer/Counter0 */ 1246 unsigned int prtim2 : 1; /* Power Reduction Timer/Counter2 */ 1247 unsigned int prtwi : 1; /* Power Reduction TWI */ 1248 }; 1249 1250 #define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0) 1251 1252 #endif /* __ASSEMBLER__ */ 1253 1254 /* PRR0 */ 1255 1256 #define PRADC 0 1257 #define PRUSART0 1 1258 #define PRSPI 2 1259 #define PRTIM1 3 1260 #define PRPGA 4 1261 #define PRTIM0 5 1262 #define PRTIM2 6 1263 #define PRTWI 7 1264 1265 #define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)) 1266 #define __AVR_HAVE_PRR0_PRADC 1267 #define __AVR_HAVE_PRR0_PRUSART0 1268 #define __AVR_HAVE_PRR0_PRSPI 1269 #define __AVR_HAVE_PRR0_PRTIM1 1270 #define __AVR_HAVE_PRR0_PRPGA 1271 #define __AVR_HAVE_PRR0_PRTIM0 1272 #define __AVR_HAVE_PRR0_PRTIM2 1273 #define __AVR_HAVE_PRR0_PRTWI 1274 1275 /* Power Reduction Register 1 */ 1276 #define PRR1 _SFR_MEM8(0x65) 1277 1278 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1279 1280 struct __reg_PRR1 { 1281 unsigned int prusart : 3; /* Reserved */ 1282 unsigned int prtim3 : 1; /* Power Reduction Timer/Counter3 */ 1283 unsigned int prtim4 : 1; /* Power Reduction Timer/Counter4 */ 1284 unsigned int prtim5 : 1; /* Power Reduction Timer/Counter5 */ 1285 unsigned int prtrx24 : 1; /* Power Reduction Transceiver */ 1286 unsigned int : 1; 1287 }; 1288 1289 #define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1) 1290 1291 #endif /* __ASSEMBLER__ */ 1292 1293 /* PRR1 */ 1294 1295 #define PRUSART1 0 1296 #define PRUSART2 1 1297 #define PRUSART3 2 1298 #define PRTIM3 3 1299 #define PRTIM4 4 1300 #define PRTIM5 5 1301 #define PRTRX24 6 1302 1303 #define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRUSART2)|(1<<PRUSART3)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24)) 1304 #define __AVR_HAVE_PRR1_PRUSART1 1305 #define __AVR_HAVE_PRR1_PRUSART2 1306 #define __AVR_HAVE_PRR1_PRUSART3 1307 #define __AVR_HAVE_PRR1_PRTIM3 1308 #define __AVR_HAVE_PRR1_PRTIM4 1309 #define __AVR_HAVE_PRR1_PRTIM5 1310 #define __AVR_HAVE_PRR1_PRTRX24 1311 1312 /* Oscillator Calibration Value */ 1313 #define OSCCAL _SFR_MEM8(0x66) 1314 1315 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1316 1317 struct __reg_OSCCAL { 1318 unsigned int cal : 8; /* Oscillator Calibration Tuning Value */ 1319 }; 1320 1321 #define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL) 1322 1323 #endif /* __ASSEMBLER__ */ 1324 1325 /* OSCCAL */ 1326 1327 #define CAL0 0 1328 #define CAL1 1 1329 #define CAL2 2 1330 #define CAL3 3 1331 #define CAL4 4 1332 #define CAL5 5 1333 #define CAL6 6 1334 #define CAL7 7 1335 1336 /* Reference Voltage Calibration Register */ 1337 #define BGCR _SFR_MEM8(0x67) 1338 1339 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1340 1341 struct __reg_BGCR { 1342 unsigned int bgcal : 3; /* Coarse Calibration Bits */ 1343 unsigned int bgcal_fine : 4; /* Fine Calibration Bits */ 1344 unsigned int : 1; 1345 }; 1346 1347 #define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR) 1348 1349 #endif /* __ASSEMBLER__ */ 1350 1351 /* BGCR */ 1352 1353 #define BGCAL0 0 1354 #define BGCAL1 1 1355 #define BGCAL2 2 1356 #define BGCAL_FINE0 3 1357 #define BGCAL_FINE1 4 1358 #define BGCAL_FINE2 5 1359 #define BGCAL_FINE3 6 1360 1361 /* Pin Change Interrupt Control Register */ 1362 #define PCICR _SFR_MEM8(0x68) 1363 1364 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1365 1366 struct __reg_PCICR { 1367 unsigned int pcie : 3; /* Pin Change Interrupt Enable 2 */ 1368 unsigned int : 5; 1369 }; 1370 1371 #define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR) 1372 1373 #endif /* __ASSEMBLER__ */ 1374 1375 /* PCICR */ 1376 1377 #define PCIE0 0 1378 #define PCIE1 1 1379 #define PCIE2 2 1380 1381 /* External Interrupt Control Register A */ 1382 #define EICRA _SFR_MEM8(0x69) 1383 1384 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1385 1386 struct __reg_EICRA { 1387 unsigned int isc0 : 2; /* External Interrupt 0 Sense Control Bit */ 1388 unsigned int isc1 : 2; /* External Interrupt 1 Sense Control Bit */ 1389 unsigned int isc2 : 2; /* External Interrupt 2 Sense Control Bit */ 1390 unsigned int isc3 : 2; /* External Interrupt 3 Sense Control Bit */ 1391 }; 1392 1393 #define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA) 1394 1395 #endif /* __ASSEMBLER__ */ 1396 1397 /* EICRA */ 1398 1399 #define ISC00 0 1400 #define ISC01 1 1401 #define ISC10 2 1402 #define ISC11 3 1403 #define ISC20 4 1404 #define ISC21 5 1405 #define ISC30 6 1406 #define ISC31 7 1407 1408 /* External Interrupt Control Register B */ 1409 #define EICRB _SFR_MEM8(0x6A) 1410 1411 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1412 1413 struct __reg_EICRB { 1414 unsigned int isc4 : 2; /* External Interrupt 4 Sense Control Bit */ 1415 unsigned int isc5 : 2; /* External Interrupt 5 Sense Control Bit */ 1416 unsigned int isc6 : 2; /* External Interrupt 6 Sense Control Bit */ 1417 unsigned int isc7 : 2; /* External Interrupt 7 Sense Control Bit */ 1418 }; 1419 1420 #define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB) 1421 1422 #endif /* __ASSEMBLER__ */ 1423 1424 /* EICRB */ 1425 1426 #define ISC40 0 1427 #define ISC41 1 1428 #define ISC50 2 1429 #define ISC51 3 1430 #define ISC60 4 1431 #define ISC61 5 1432 #define ISC70 6 1433 #define ISC71 7 1434 1435 /* Pin Change Mask Register 0 */ 1436 #define PCMSK0 _SFR_MEM8(0x6B) 1437 1438 /* PCMSK0 */ 1439 1440 #define PCINT0 0 1441 #define PCINT1 1 1442 #define PCINT2 2 1443 #define PCINT3 3 1444 #define PCINT4 4 1445 #define PCINT5 5 1446 #define PCINT6 6 1447 #define PCINT7 7 1448 1449 /* Pin Change Mask Register 1 */ 1450 #define PCMSK1 _SFR_MEM8(0x6C) 1451 1452 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1453 1454 struct __reg_PCMSK1 { 1455 unsigned int pcint : 2; /* Pin Change Enable Mask */ 1456 unsigned int pcint1 : 6; /* Pin Change Enable Mask */ 1457 }; 1458 1459 #define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1) 1460 1461 #endif /* __ASSEMBLER__ */ 1462 1463 /* PCMSK1 */ 1464 1465 #define PCINT8 0 1466 #define PCINT9 1 1467 #define PCINT10 2 1468 #define PCINT11 3 1469 #define PCINT12 4 1470 #define PCINT13 5 1471 #define PCINT14 6 1472 #define PCINT15 7 1473 1474 /* Pin Change Mask Register 2 */ 1475 #define PCMSK2 _SFR_MEM8(0x6D) 1476 1477 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1478 1479 struct __reg_PCMSK2 { 1480 unsigned int pcint1 : 4; /* Pin Change Enable Mask */ 1481 unsigned int pcint2 : 4; /* Pin Change Enable Mask */ 1482 }; 1483 1484 #define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2) 1485 1486 #endif /* __ASSEMBLER__ */ 1487 1488 /* PCMSK2 */ 1489 1490 #define PCINT16 0 1491 #define PCINT17 1 1492 #define PCINT18 2 1493 #define PCINT19 3 1494 #define PCINT20 4 1495 #define PCINT21 5 1496 #define PCINT22 6 1497 #define PCINT23 7 1498 1499 /* Timer/Counter0 Interrupt Mask Register */ 1500 #define TIMSK0 _SFR_MEM8(0x6E) 1501 1502 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1503 1504 struct __reg_TIMSK0 { 1505 unsigned int toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */ 1506 unsigned int ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */ 1507 unsigned int ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */ 1508 unsigned int : 5; 1509 }; 1510 1511 #define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0) 1512 1513 #endif /* __ASSEMBLER__ */ 1514 1515 /* TIMSK0 */ 1516 1517 #define TOIE0 0 1518 #define OCIE0A 1 1519 #define OCIE0B 2 1520 1521 /* Timer/Counter1 Interrupt Mask Register */ 1522 #define TIMSK1 _SFR_MEM8(0x6F) 1523 1524 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1525 1526 struct __reg_TIMSK1 { 1527 unsigned int toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */ 1528 unsigned int ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */ 1529 unsigned int ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */ 1530 unsigned int ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */ 1531 unsigned int : 1; 1532 unsigned int icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */ 1533 unsigned int : 2; 1534 }; 1535 1536 #define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1) 1537 1538 #endif /* __ASSEMBLER__ */ 1539 1540 /* TIMSK1 */ 1541 1542 #define TOIE1 0 1543 #define OCIE1A 1 1544 #define OCIE1B 2 1545 #define OCIE1C 3 1546 #define ICIE1 5 1547 1548 /* Timer/Counter Interrupt Mask register */ 1549 #define TIMSK2 _SFR_MEM8(0x70) 1550 1551 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1552 1553 struct __reg_TIMSK2 { 1554 unsigned int toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */ 1555 unsigned int ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */ 1556 unsigned int ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */ 1557 unsigned int : 5; 1558 }; 1559 1560 #define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2) 1561 1562 #endif /* __ASSEMBLER__ */ 1563 1564 /* TIMSK2 */ 1565 1566 #define TOIE2 0 1567 #define TOIE2A 0 1568 #define OCIE2A 1 1569 #define OCIE2B 2 1570 1571 /* Timer/Counter3 Interrupt Mask Register */ 1572 #define TIMSK3 _SFR_MEM8(0x71) 1573 1574 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1575 1576 struct __reg_TIMSK3 { 1577 unsigned int toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */ 1578 unsigned int ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */ 1579 unsigned int ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */ 1580 unsigned int ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */ 1581 unsigned int : 1; 1582 unsigned int icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */ 1583 unsigned int : 2; 1584 }; 1585 1586 #define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3) 1587 1588 #endif /* __ASSEMBLER__ */ 1589 1590 /* TIMSK3 */ 1591 1592 #define TOIE3 0 1593 #define OCIE3A 1 1594 #define OCIE3B 2 1595 #define OCIE3C 3 1596 #define ICIE3 5 1597 1598 /* Timer/Counter4 Interrupt Mask Register */ 1599 #define TIMSK4 _SFR_MEM8(0x72) 1600 1601 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1602 1603 struct __reg_TIMSK4 { 1604 unsigned int toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */ 1605 unsigned int ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */ 1606 unsigned int ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */ 1607 unsigned int ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */ 1608 unsigned int : 1; 1609 unsigned int icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */ 1610 unsigned int : 2; 1611 }; 1612 1613 #define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4) 1614 1615 #endif /* __ASSEMBLER__ */ 1616 1617 /* TIMSK4 */ 1618 1619 #define TOIE4 0 1620 #define OCIE4A 1 1621 #define OCIE4B 2 1622 #define OCIE4C 3 1623 #define ICIE4 5 1624 1625 /* Timer/Counter5 Interrupt Mask Register */ 1626 #define TIMSK5 _SFR_MEM8(0x73) 1627 1628 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1629 1630 struct __reg_TIMSK5 { 1631 unsigned int toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */ 1632 unsigned int ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */ 1633 unsigned int ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */ 1634 unsigned int ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */ 1635 unsigned int : 1; 1636 unsigned int icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */ 1637 unsigned int : 2; 1638 }; 1639 1640 #define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5) 1641 1642 #endif /* __ASSEMBLER__ */ 1643 1644 /* TIMSK5 */ 1645 1646 #define TOIE5 0 1647 #define OCIE5A 1 1648 #define OCIE5B 2 1649 #define OCIE5C 3 1650 #define ICIE5 5 1651 1652 /* Flash Extended-Mode Control-Register */ 1653 #define NEMCR _SFR_MEM8(0x75) 1654 1655 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1656 1657 struct __reg_NEMCR { 1658 unsigned int : 4; 1659 unsigned int aeam : 2; /* Address for Extended Address Mode of Extra Rows */ 1660 unsigned int eneam : 1; /* Enable Extended Address Mode for Extra Rows */ 1661 unsigned int : 1; 1662 }; 1663 1664 #define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR) 1665 1666 #endif /* __ASSEMBLER__ */ 1667 1668 /* NEMCR */ 1669 1670 #define AEAM0 4 1671 #define AEAM1 5 1672 #define ENEAM 6 1673 1674 /* The ADC Control and Status Register C */ 1675 #define ADCSRC _SFR_MEM8(0x77) 1676 1677 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1678 1679 struct __reg_ADCSRC { 1680 unsigned int adsut : 5; /* ADC Start-up Time */ 1681 unsigned int res0 : 1; /* Reserved */ 1682 unsigned int adtht : 2; /* ADC Track-and-Hold Time */ 1683 }; 1684 1685 #define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC) 1686 1687 #endif /* __ASSEMBLER__ */ 1688 1689 /* ADCSRC */ 1690 1691 #define ADSUT0 0 1692 #define ADSUT1 1 1693 #define ADSUT2 2 1694 #define ADSUT3 3 1695 #define ADSUT4 4 1696 #define ADTHT0 6 1697 #define ADTHT1 7 1698 1699 /* ADC Data Register Bytes */ 1700 #ifndef __ASSEMBLER__ 1701 #define ADC _SFR_MEM16(0x78) 1702 #define ADCL _SFR_MEM8(0x78) 1703 #define ADCH _SFR_MEM8(0x79) 1704 #endif /* __ASSEMBLER__ */ 1705 #define ADCW _SFR_MEM16(0x78) 1706 #define ADCWL _SFR_MEM8(0x78) 1707 #define ADCWH _SFR_MEM8(0x79) 1708 1709 /* The ADC Control and Status Register A */ 1710 #define ADCSRA _SFR_MEM8(0x7A) 1711 1712 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1713 1714 struct __reg_ADCSRA { 1715 unsigned int adps : 3; /* ADC Prescaler Select Bits */ 1716 unsigned int adie : 1; /* ADC Interrupt Enable */ 1717 unsigned int adif : 1; /* ADC Interrupt Flag */ 1718 unsigned int adate : 1; /* ADC Auto Trigger Enable */ 1719 unsigned int adsc : 1; /* ADC Start Conversion */ 1720 unsigned int aden : 1; /* ADC Enable */ 1721 }; 1722 1723 #define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA) 1724 1725 #endif /* __ASSEMBLER__ */ 1726 1727 /* ADCSRA */ 1728 1729 #define ADPS0 0 1730 #define ADPS1 1 1731 #define ADPS2 2 1732 #define ADIE 3 1733 #define ADIF 4 1734 #define ADATE 5 1735 #define ADSC 6 1736 #define ADEN 7 1737 1738 /* ADC Control and Status Register B */ 1739 #define ADCSRB _SFR_MEM8(0x7B) 1740 1741 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1742 1743 struct __reg_ADCSRB { 1744 unsigned int adts : 3; /* ADC Auto Trigger Source */ 1745 unsigned int mux5 : 1; /* Analog Channel and Gain Selection Bits */ 1746 unsigned int acch : 1; /* Analog Channel Change */ 1747 unsigned int refok : 1; /* Reference Voltage OK */ 1748 unsigned int acme : 1; /* Analog Comparator Multiplexer Enable */ 1749 unsigned int avddok : 1; /* AVDD Supply Voltage OK */ 1750 }; 1751 1752 #define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB) 1753 1754 #endif /* __ASSEMBLER__ */ 1755 1756 /* ADCSRB */ 1757 1758 #define ADTS0 0 1759 #define ADTS1 1 1760 #define ADTS2 2 1761 #define MUX5 3 1762 #define ACCH 4 1763 #define REFOK 5 1764 #define ACME 6 1765 #define AVDDOK 7 1766 1767 /* The ADC Multiplexer Selection Register */ 1768 #define ADMUX _SFR_MEM8(0x7C) 1769 1770 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1771 1772 struct __reg_ADMUX { 1773 unsigned int mux : 5; /* Analog Channel and Gain Selection Bits */ 1774 unsigned int adlar : 1; /* ADC Left Adjust Result */ 1775 unsigned int refs : 2; /* Reference Selection Bits */ 1776 }; 1777 1778 #define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX) 1779 1780 #endif /* __ASSEMBLER__ */ 1781 1782 /* ADMUX */ 1783 1784 #define MUX0 0 1785 #define MUX1 1 1786 #define MUX2 2 1787 #define MUX3 3 1788 #define MUX4 4 1789 #define ADLAR 5 1790 #define REFS0 6 1791 #define REFS1 7 1792 1793 /* Digital Input Disable Register 2 */ 1794 #define DIDR2 _SFR_MEM8(0x7D) 1795 1796 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1797 1798 struct __reg_DIDR2 { 1799 unsigned int adc8d : 1; /* Reserved Bits */ 1800 unsigned int adc9d : 1; /* Reserved Bits */ 1801 unsigned int adc10d : 1; /* Reserved Bits */ 1802 unsigned int adc11d : 1; /* Reserved Bits */ 1803 unsigned int adc12d : 1; /* Reserved Bits */ 1804 unsigned int adc13d : 1; /* Reserved Bits */ 1805 unsigned int adc14d : 1; /* Reserved Bits */ 1806 unsigned int adc15d : 1; /* Reserved Bits */ 1807 }; 1808 1809 #define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2) 1810 1811 #endif /* __ASSEMBLER__ */ 1812 1813 /* DIDR2 */ 1814 1815 #define ADC8D 0 1816 #define ADC9D 1 1817 #define ADC10D 2 1818 #define ADC11D 3 1819 #define ADC12D 4 1820 #define ADC13D 5 1821 #define ADC14D 6 1822 #define ADC15D 7 1823 1824 /* Digital Input Disable Register 0 */ 1825 #define DIDR0 _SFR_MEM8(0x7E) 1826 1827 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1828 1829 struct __reg_DIDR0 { 1830 unsigned int adc0d : 1; /* Disable ADC7:0 Digital Input */ 1831 unsigned int adc1d : 1; /* Disable ADC7:0 Digital Input */ 1832 unsigned int adc2d : 1; /* Disable ADC7:0 Digital Input */ 1833 unsigned int adc3d : 1; /* Disable ADC7:0 Digital Input */ 1834 unsigned int adc4d : 1; /* Disable ADC7:0 Digital Input */ 1835 unsigned int adc5d : 1; /* Disable ADC7:0 Digital Input */ 1836 unsigned int adc6d : 1; /* Disable ADC7:0 Digital Input */ 1837 unsigned int adc7d : 1; /* Disable ADC7:0 Digital Input */ 1838 }; 1839 1840 #define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0) 1841 1842 #endif /* __ASSEMBLER__ */ 1843 1844 /* DIDR0 */ 1845 1846 #define ADC0D 0 1847 #define ADC1D 1 1848 #define ADC2D 2 1849 #define ADC3D 3 1850 #define ADC4D 4 1851 #define ADC5D 5 1852 #define ADC6D 6 1853 #define ADC7D 7 1854 1855 /* Digital Input Disable Register 1 */ 1856 #define DIDR1 _SFR_MEM8(0x7F) 1857 1858 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1859 1860 struct __reg_DIDR1 { 1861 unsigned int ain0d : 1; /* AIN0 Digital Input Disable */ 1862 unsigned int ain1d : 1; /* AIN1 Digital Input Disable */ 1863 unsigned int : 6; 1864 }; 1865 1866 #define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1) 1867 1868 #endif /* __ASSEMBLER__ */ 1869 1870 /* DIDR1 */ 1871 1872 #define AIN0D 0 1873 #define AIN1D 1 1874 1875 /* Timer/Counter1 Control Register A */ 1876 #define TCCR1A _SFR_MEM8(0x80) 1877 1878 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1879 1880 struct __reg_TCCR1A { 1881 unsigned int wgm1 : 2; /* Waveform Generation Mode */ 1882 unsigned int com1c : 2; /* Compare Output Mode for Channel C */ 1883 unsigned int com1b : 2; /* Compare Output Mode for Channel B */ 1884 unsigned int com1a : 2; /* Compare Output Mode for Channel A */ 1885 }; 1886 1887 #define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A) 1888 1889 #endif /* __ASSEMBLER__ */ 1890 1891 /* TCCR1A */ 1892 1893 #define WGM10 0 1894 #define WGM11 1 1895 #define COM1C0 2 1896 #define COM1C1 3 1897 #define COM1B0 4 1898 #define COM1B1 5 1899 #define COM1A0 6 1900 #define COM1A1 7 1901 1902 /* Timer/Counter1 Control Register B */ 1903 #define TCCR1B _SFR_MEM8(0x81) 1904 1905 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1906 1907 struct __reg_TCCR1B { 1908 unsigned int cs1 : 3; /* Clock Select */ 1909 unsigned int wgm1 : 2; /* Waveform Generation Mode */ 1910 unsigned int : 1; 1911 unsigned int ices1 : 1; /* Input Capture 1 Edge Select */ 1912 unsigned int icnc1 : 1; /* Input Capture 1 Noise Canceller */ 1913 }; 1914 1915 #define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B) 1916 1917 #endif /* __ASSEMBLER__ */ 1918 1919 /* TCCR1B */ 1920 1921 #define CS10 0 1922 #define CS11 1 1923 #define CS12 2 1924 #define WGM12 3 1925 #define WGM13 4 1926 #define ICES1 6 1927 #define ICNC1 7 1928 1929 /* Timer/Counter1 Control Register C */ 1930 #define TCCR1C _SFR_MEM8(0x82) 1931 1932 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1933 1934 struct __reg_TCCR1C { 1935 unsigned int : 5; 1936 unsigned int foc1c : 1; /* Force Output Compare for Channel C */ 1937 unsigned int foc1b : 1; /* Force Output Compare for Channel B */ 1938 unsigned int foc1a : 1; /* Force Output Compare for Channel A */ 1939 }; 1940 1941 #define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C) 1942 1943 #endif /* __ASSEMBLER__ */ 1944 1945 /* TCCR1C */ 1946 1947 #define FOC1C 5 1948 #define FOC1B 6 1949 #define FOC1A 7 1950 1951 /* Timer/Counter1 Bytes */ 1952 #define TCNT1 _SFR_MEM16(0x84) 1953 #define TCNT1L _SFR_MEM8(0x84) 1954 #define TCNT1H _SFR_MEM8(0x85) 1955 1956 /* Timer/Counter1 Input Capture Register Bytes */ 1957 #define ICR1 _SFR_MEM16(0x86) 1958 #define ICR1L _SFR_MEM8(0x86) 1959 #define ICR1H _SFR_MEM8(0x87) 1960 1961 /* Timer/Counter1 Output Compare Register A Bytes */ 1962 #define OCR1A _SFR_MEM16(0x88) 1963 #define OCR1AL _SFR_MEM8(0x88) 1964 #define OCR1AH _SFR_MEM8(0x89) 1965 1966 /* Timer/Counter1 Output Compare Register B Bytes */ 1967 #define OCR1B _SFR_MEM16(0x8A) 1968 #define OCR1BL _SFR_MEM8(0x8A) 1969 #define OCR1BH _SFR_MEM8(0x8B) 1970 1971 /* Timer/Counter1 Output Compare Register C Bytes */ 1972 #define OCR1C _SFR_MEM16(0x8C) 1973 #define OCR1CL _SFR_MEM8(0x8C) 1974 #define OCR1CH _SFR_MEM8(0x8D) 1975 1976 /* Timer/Counter3 Control Register A */ 1977 #define TCCR3A _SFR_MEM8(0x90) 1978 1979 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1980 1981 struct __reg_TCCR3A { 1982 unsigned int wgm3 : 2; /* Waveform Generation Mode */ 1983 unsigned int com3c : 2; /* Compare Output Mode for Channel C */ 1984 unsigned int com3b : 2; /* Compare Output Mode for Channel B */ 1985 unsigned int com3a : 2; /* Compare Output Mode for Channel A */ 1986 }; 1987 1988 #define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A) 1989 1990 #endif /* __ASSEMBLER__ */ 1991 1992 /* TCCR3A */ 1993 1994 #define WGM30 0 1995 #define WGM31 1 1996 #define COM3C0 2 1997 #define COM3C1 3 1998 #define COM3B0 4 1999 #define COM3B1 5 2000 #define COM3A0 6 2001 #define COM3A1 7 2002 2003 /* Timer/Counter3 Control Register B */ 2004 #define TCCR3B _SFR_MEM8(0x91) 2005 2006 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2007 2008 struct __reg_TCCR3B { 2009 unsigned int cs3 : 3; /* Clock Select */ 2010 unsigned int wgm3 : 2; /* Waveform Generation Mode */ 2011 unsigned int : 1; 2012 unsigned int ices3 : 1; /* Input Capture 3 Edge Select */ 2013 unsigned int icnc3 : 1; /* Input Capture 3 Noise Canceller */ 2014 }; 2015 2016 #define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B) 2017 2018 #endif /* __ASSEMBLER__ */ 2019 2020 /* TCCR3B */ 2021 2022 #define CS30 0 2023 #define CS31 1 2024 #define CS32 2 2025 #define WGM32 3 2026 #define WGM33 4 2027 #define ICES3 6 2028 #define ICNC3 7 2029 2030 /* Timer/Counter3 Control Register C */ 2031 #define TCCR3C _SFR_MEM8(0x92) 2032 2033 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2034 2035 struct __reg_TCCR3C { 2036 unsigned int : 5; 2037 unsigned int foc3c : 1; /* Force Output Compare for Channel C */ 2038 unsigned int foc3b : 1; /* Force Output Compare for Channel B */ 2039 unsigned int foc3a : 1; /* Force Output Compare for Channel A */ 2040 }; 2041 2042 #define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C) 2043 2044 #endif /* __ASSEMBLER__ */ 2045 2046 /* TCCR3C */ 2047 2048 #define FOC3C 5 2049 #define FOC3B 6 2050 #define FOC3A 7 2051 2052 /* Timer/Counter3 Bytes */ 2053 #define TCNT3 _SFR_MEM16(0x94) 2054 #define TCNT3L _SFR_MEM8(0x94) 2055 #define TCNT3H _SFR_MEM8(0x95) 2056 2057 /* Timer/Counter3 Input Capture Register Bytes */ 2058 #define ICR3 _SFR_MEM16(0x96) 2059 #define ICR3L _SFR_MEM8(0x96) 2060 #define ICR3H _SFR_MEM8(0x97) 2061 2062 /* Timer/Counter3 Output Compare Register A Bytes */ 2063 #define OCR3A _SFR_MEM16(0x98) 2064 #define OCR3AL _SFR_MEM8(0x98) 2065 #define OCR3AH _SFR_MEM8(0x99) 2066 2067 /* Timer/Counter3 Output Compare Register B Bytes */ 2068 #define OCR3B _SFR_MEM16(0x9A) 2069 #define OCR3BL _SFR_MEM8(0x9A) 2070 #define OCR3BH _SFR_MEM8(0x9B) 2071 2072 /* Timer/Counter3 Output Compare Register C Bytes */ 2073 #define OCR3C _SFR_MEM16(0x9C) 2074 #define OCR3CL _SFR_MEM8(0x9C) 2075 #define OCR3CH _SFR_MEM8(0x9D) 2076 2077 /* Timer/Counter4 Control Register A */ 2078 #define TCCR4A _SFR_MEM8(0xA0) 2079 2080 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2081 2082 struct __reg_TCCR4A { 2083 unsigned int wgm4 : 2; /* Waveform Generation Mode */ 2084 unsigned int com4c : 2; /* Compare Output Mode for Channel C */ 2085 unsigned int com4b : 2; /* Compare Output Mode for Channel B */ 2086 unsigned int com4a : 2; /* Compare Output Mode for Channel A */ 2087 }; 2088 2089 #define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A) 2090 2091 #endif /* __ASSEMBLER__ */ 2092 2093 /* TCCR4A */ 2094 2095 #define WGM40 0 2096 #define WGM41 1 2097 #define COM4C0 2 2098 #define COM4C1 3 2099 #define COM4B0 4 2100 #define COM4B1 5 2101 #define COM4A0 6 2102 #define COM4A1 7 2103 2104 /* Timer/Counter4 Control Register B */ 2105 #define TCCR4B _SFR_MEM8(0xA1) 2106 2107 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2108 2109 struct __reg_TCCR4B { 2110 unsigned int cs4 : 3; /* Clock Select */ 2111 unsigned int wgm4 : 2; /* Waveform Generation Mode */ 2112 unsigned int : 1; 2113 unsigned int ices4 : 1; /* Input Capture 4 Edge Select */ 2114 unsigned int icnc4 : 1; /* Input Capture 4 Noise Canceller */ 2115 }; 2116 2117 #define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B) 2118 2119 #endif /* __ASSEMBLER__ */ 2120 2121 /* TCCR4B */ 2122 2123 #define CS40 0 2124 #define CS41 1 2125 #define CS42 2 2126 #define WGM42 3 2127 #define WGM43 4 2128 #define ICES4 6 2129 #define ICNC4 7 2130 2131 /* Timer/Counter4 Control Register C */ 2132 #define TCCR4C _SFR_MEM8(0xA2) 2133 2134 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2135 2136 struct __reg_TCCR4C { 2137 unsigned int : 5; 2138 unsigned int foc4c : 1; /* Force Output Compare for Channel C */ 2139 unsigned int foc4b : 1; /* Force Output Compare for Channel B */ 2140 unsigned int foc4a : 1; /* Force Output Compare for Channel A */ 2141 }; 2142 2143 #define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C) 2144 2145 #endif /* __ASSEMBLER__ */ 2146 2147 /* TCCR4C */ 2148 2149 #define FOC4C 5 2150 #define FOC4B 6 2151 #define FOC4A 7 2152 2153 /* Timer/Counter4 Bytes */ 2154 #define TCNT4 _SFR_MEM16(0xA4) 2155 #define TCNT4L _SFR_MEM8(0xA4) 2156 #define TCNT4H _SFR_MEM8(0xA5) 2157 2158 /* Timer/Counter4 Input Capture Register Bytes */ 2159 #define ICR4 _SFR_MEM16(0xA6) 2160 #define ICR4L _SFR_MEM8(0xA6) 2161 #define ICR4H _SFR_MEM8(0xA7) 2162 2163 /* Timer/Counter4 Output Compare Register A Bytes */ 2164 #define OCR4A _SFR_MEM16(0xA8) 2165 #define OCR4AL _SFR_MEM8(0xA8) 2166 #define OCR4AH _SFR_MEM8(0xA9) 2167 2168 /* Timer/Counter4 Output Compare Register B Bytes */ 2169 #define OCR4B _SFR_MEM16(0xAA) 2170 #define OCR4BL _SFR_MEM8(0xAA) 2171 #define OCR4BH _SFR_MEM8(0xAB) 2172 2173 /* Timer/Counter4 Output Compare Register C Bytes */ 2174 #define OCR4C _SFR_MEM16(0xAC) 2175 #define OCR4CL _SFR_MEM8(0xAC) 2176 #define OCR4CH _SFR_MEM8(0xAD) 2177 2178 /* Timer/Counter2 Control Register A */ 2179 #define TCCR2A _SFR_MEM8(0xB0) 2180 2181 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2182 2183 struct __reg_TCCR2A { 2184 unsigned int wgm2 : 2; /* Waveform Generation Mode */ 2185 unsigned int : 2; 2186 unsigned int com2b : 2; /* Compare Match Output B Mode */ 2187 unsigned int com2a : 2; /* Compare Match Output A Mode */ 2188 }; 2189 2190 #define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A) 2191 2192 #endif /* __ASSEMBLER__ */ 2193 2194 /* TCCR2A */ 2195 2196 #define WGM20 0 2197 #define WGM21 1 2198 #define COM2B0 4 2199 #define COM2B1 5 2200 #define COM2A0 6 2201 #define COM2A1 7 2202 2203 /* Timer/Counter2 Control Register B */ 2204 #define TCCR2B _SFR_MEM8(0xB1) 2205 2206 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2207 2208 struct __reg_TCCR2B { 2209 unsigned int cs2 : 3; /* Clock Select */ 2210 unsigned int wgm22 : 1; /* Waveform Generation Mode */ 2211 unsigned int : 2; 2212 unsigned int foc2b : 1; /* Force Output Compare B */ 2213 unsigned int foc2a : 1; /* Force Output Compare A */ 2214 }; 2215 2216 #define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B) 2217 2218 #endif /* __ASSEMBLER__ */ 2219 2220 /* TCCR2B */ 2221 2222 #define CS20 0 2223 #define CS21 1 2224 #define CS22 2 2225 #define WGM22 3 2226 #define FOC2B 6 2227 #define FOC2A 7 2228 2229 /* Timer/Counter2 */ 2230 #define TCNT2 _SFR_MEM8(0xB2) 2231 2232 /* TCNT2 */ 2233 2234 #define TCNT20 0 2235 #define TCNT21 1 2236 #define TCNT22 2 2237 #define TCNT23 3 2238 #define TCNT24 4 2239 #define TCNT25 5 2240 #define TCNT26 6 2241 #define TCNT27 7 2242 2243 /* Timer/Counter2 Output Compare Register A */ 2244 #define OCR2A _SFR_MEM8(0xB3) 2245 2246 /* OCR2A */ 2247 2248 #define OCR2A0 0 2249 #define OCR2A1 1 2250 #define OCR2A2 2 2251 #define OCR2A3 3 2252 #define OCR2A4 4 2253 #define OCR2A5 5 2254 #define OCR2A6 6 2255 #define OCR2A7 7 2256 2257 /* Timer/Counter2 Output Compare Register B */ 2258 #define OCR2B _SFR_MEM8(0xB4) 2259 2260 /* OCR2B */ 2261 2262 #define OCR2B0 0 2263 #define OCR2B1 1 2264 #define OCR2B2 2 2265 #define OCR2B3 3 2266 #define OCR2B4 4 2267 #define OCR2B5 5 2268 #define OCR2B6 6 2269 #define OCR2B7 7 2270 2271 /* Asynchronous Status Register */ 2272 #define ASSR _SFR_MEM8(0xB6) 2273 2274 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2275 2276 struct __reg_ASSR { 2277 unsigned int tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */ 2278 unsigned int tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */ 2279 unsigned int ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */ 2280 unsigned int ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */ 2281 unsigned int tcn2ub : 1; /* Timer/Counter2 Update Busy */ 2282 unsigned int as2 : 1; /* Timer/Counter2 Asynchronous Mode */ 2283 unsigned int exclk : 1; /* Enable External Clock Input */ 2284 unsigned int exclkamr : 1; /* Enable External Clock Input for AMR */ 2285 }; 2286 2287 #define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR) 2288 2289 #endif /* __ASSEMBLER__ */ 2290 2291 /* ASSR */ 2292 2293 #define TCR2BUB 0 2294 #define TCR2AUB 1 2295 #define OCR2BUB 2 2296 #define OCR2AUB 3 2297 #define TCN2UB 4 2298 #define AS2 5 2299 #define EXCLK 6 2300 #define EXCLKAMR 7 2301 2302 /* TWI Bit Rate Register */ 2303 #define TWBR _SFR_MEM8(0xB8) 2304 2305 /* TWBR */ 2306 2307 #define TWBR0 0 2308 #define TWBR1 1 2309 #define TWBR2 2 2310 #define TWBR3 3 2311 #define TWBR4 4 2312 #define TWBR5 5 2313 #define TWBR6 6 2314 #define TWBR7 7 2315 2316 /* TWI Status Register */ 2317 #define TWSR _SFR_MEM8(0xB9) 2318 2319 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2320 2321 struct __reg_TWSR { 2322 unsigned int twps : 2; /* TWI Prescaler Bits */ 2323 unsigned int : 1; 2324 unsigned int tws : 5; /* TWI Status */ 2325 }; 2326 2327 #define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR) 2328 2329 #endif /* __ASSEMBLER__ */ 2330 2331 /* TWSR */ 2332 2333 #define TWPS0 0 2334 #define TWPS1 1 2335 #define TWS3 3 2336 #define TWS4 4 2337 #define TWS5 5 2338 #define TWS6 6 2339 #define TWS7 7 2340 2341 /* TWI (Slave) Address Register */ 2342 #define TWAR _SFR_MEM8(0xBA) 2343 2344 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2345 2346 struct __reg_TWAR { 2347 unsigned int twgce : 1; /* TWI General Call Recognition Enable Bit */ 2348 unsigned int twa : 7; /* TWI (Slave) Address */ 2349 }; 2350 2351 #define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR) 2352 2353 #endif /* __ASSEMBLER__ */ 2354 2355 /* TWAR */ 2356 2357 #define TWGCE 0 2358 #define TWA0 1 2359 #define TWA1 2 2360 #define TWA2 3 2361 #define TWA3 4 2362 #define TWA4 5 2363 #define TWA5 6 2364 #define TWA6 7 2365 2366 /* TWI Data Register */ 2367 #define TWDR _SFR_MEM8(0xBB) 2368 2369 /* TWDR */ 2370 2371 #define TWD0 0 2372 #define TWD1 1 2373 #define TWD2 2 2374 #define TWD3 3 2375 #define TWD4 4 2376 #define TWD5 5 2377 #define TWD6 6 2378 #define TWD7 7 2379 2380 /* TWI Control Register */ 2381 #define TWCR _SFR_MEM8(0xBC) 2382 2383 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2384 2385 struct __reg_TWCR { 2386 unsigned int twie : 1; /* TWI Interrupt Enable */ 2387 unsigned int : 1; 2388 unsigned int twen : 1; /* TWI Enable Bit */ 2389 unsigned int twwc : 1; /* TWI Write Collision Flag */ 2390 unsigned int twsto : 1; /* TWI STOP Condition Bit */ 2391 unsigned int twsta : 1; /* TWI START Condition Bit */ 2392 unsigned int twea : 1; /* TWI Enable Acknowledge Bit */ 2393 unsigned int twint : 1; /* TWI Interrupt Flag */ 2394 }; 2395 2396 #define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR) 2397 2398 #endif /* __ASSEMBLER__ */ 2399 2400 /* TWCR */ 2401 2402 #define TWIE 0 2403 #define TWEN 2 2404 #define TWWC 3 2405 #define TWSTO 4 2406 #define TWSTA 5 2407 #define TWEA 6 2408 #define TWINT 7 2409 2410 /* TWI (Slave) Address Mask Register */ 2411 #define TWAMR _SFR_MEM8(0xBD) 2412 2413 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2414 2415 struct __reg_TWAMR { 2416 unsigned int : 1; 2417 unsigned int twam : 7; /* TWI Address Mask */ 2418 }; 2419 2420 #define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR) 2421 2422 #endif /* __ASSEMBLER__ */ 2423 2424 /* TWAMR */ 2425 2426 #define TWAM0 1 2427 #define TWAMR0 1 2428 #define TWAM1 2 2429 #define TWAMR1 2 2430 #define TWAM2 3 2431 #define TWAMR2 3 2432 #define TWAM3 4 2433 #define TWAMR3 4 2434 #define TWAM4 5 2435 #define TWAMR4 5 2436 #define TWAM5 6 2437 #define TWAMR5 6 2438 #define TWAM6 7 2439 #define TWAMR6 7 2440 2441 /* USART0 Control and Status Register A */ 2442 #define UCSR0A _SFR_MEM8(0xC0) 2443 2444 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2445 2446 struct __reg_UCSR0A { 2447 unsigned int mpcm0 : 1; /* Multi-processor Communication Mode */ 2448 unsigned int u2x0 : 1; /* Double the USART Transmission Speed */ 2449 unsigned int upe0 : 1; /* USART Parity Error */ 2450 unsigned int dor0 : 1; /* Data OverRun */ 2451 unsigned int fe0 : 1; /* Frame Error */ 2452 unsigned int udre0 : 1; /* USART Data Register Empty */ 2453 unsigned int txc0 : 1; /* USART Transmit Complete */ 2454 unsigned int rxc0 : 1; /* USART Receive Complete */ 2455 }; 2456 2457 #define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A) 2458 2459 #endif /* __ASSEMBLER__ */ 2460 2461 /* UCSR0A */ 2462 2463 #define MPCM0 0 2464 #define U2X0 1 2465 #define UPE0 2 2466 #define DOR0 3 2467 #define FE0 4 2468 #define UDRE0 5 2469 #define TXC0 6 2470 #define RXC0 7 2471 2472 /* USART0 Control and Status Register B */ 2473 #define UCSR0B _SFR_MEM8(0xC1) 2474 2475 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2476 2477 struct __reg_UCSR0B { 2478 unsigned int txb80 : 1; /* Transmit Data Bit 8 */ 2479 unsigned int rxb80 : 1; /* Receive Data Bit 8 */ 2480 unsigned int ucsz02 : 1; /* Character Size */ 2481 unsigned int txen0 : 1; /* Transmitter Enable */ 2482 unsigned int rxen0 : 1; /* Receiver Enable */ 2483 unsigned int udrie0 : 1; /* USART Data Register Empty Interrupt Enable */ 2484 unsigned int txcie0 : 1; /* TX Complete Interrupt Enable */ 2485 unsigned int rxcie0 : 1; /* RX Complete Interrupt Enable */ 2486 }; 2487 2488 #define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B) 2489 2490 #endif /* __ASSEMBLER__ */ 2491 2492 /* UCSR0B */ 2493 2494 #define TXB80 0 2495 #define RXB80 1 2496 #define UCSZ02 2 2497 #define TXEN0 3 2498 #define RXEN0 4 2499 #define UDRIE0 5 2500 #define TXCIE0 6 2501 #define RXCIE0 7 2502 2503 /* USART0 Control and Status Register C */ 2504 #define UCSR0C _SFR_MEM8(0xC2) 2505 2506 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2507 2508 struct __reg_UCSR0C { 2509 unsigned int ucpol0 : 1; /* Clock Polarity */ 2510 unsigned int ucsz0 : 2; /* Character Size */ 2511 unsigned int usbs0 : 1; /* Stop Bit Select */ 2512 unsigned int upm0 : 2; /* Parity Mode */ 2513 unsigned int umsel0 : 2; /* USART Mode Select */ 2514 }; 2515 /* NOTE: UCSR0C in SPI mode have only lower three bits. 2516 UCORD1 Data Order 2517 UCPHA1 Clock Phase 2518 UCPOL1 Clock Polarity 2519 */ 2520 2521 #define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C) 2522 2523 #endif /* __ASSEMBLER__ */ 2524 2525 /* UCSR0C */ 2526 2527 #define UCPOL0 0 2528 #define UCPHA0 1 2529 #define UCSZ00 1 2530 #define UDORD0 2 2531 #define UCSZ01 2 2532 #define USBS0 3 2533 #define UPM00 4 2534 #define UPM01 5 2535 #define UMSEL00 6 2536 #define UMSEL0 6 2537 #define UMSEL01 7 2538 #define UMSEL1 7 2539 2540 /* USART0 Baud Rate Register Bytes */ 2541 #define UBRR0 _SFR_MEM16(0xC4) 2542 #define UBRR0L _SFR_MEM8(0xC4) 2543 #define UBRR0H _SFR_MEM8(0xC5) 2544 2545 /* USART0 I/O Data Register */ 2546 #define UDR0 _SFR_MEM8(0xC6) 2547 2548 /* UDR0 */ 2549 2550 #define UDR00 0 2551 #define UDR01 1 2552 #define UDR02 2 2553 #define UDR03 3 2554 #define UDR04 4 2555 #define UDR05 5 2556 #define UDR06 6 2557 #define UDR07 7 2558 2559 /* USART1 Control and Status Register A */ 2560 #define UCSR1A _SFR_MEM8(0xC8) 2561 2562 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2563 2564 struct __reg_UCSR1A { 2565 unsigned int mpcm1 : 1; /* Multi-processor Communication Mode */ 2566 unsigned int u2x1 : 1; /* Double the USART Transmission Speed */ 2567 unsigned int upe1 : 1; /* USART Parity Error */ 2568 unsigned int dor1 : 1; /* Data OverRun */ 2569 unsigned int fe1 : 1; /* Frame Error */ 2570 unsigned int udre1 : 1; /* USART Data Register Empty */ 2571 unsigned int txc1 : 1; /* USART Transmit Complete */ 2572 unsigned int rxc1 : 1; /* USART Receive Complete */ 2573 }; 2574 2575 #define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A) 2576 2577 #endif /* __ASSEMBLER__ */ 2578 2579 /* UCSR1A */ 2580 2581 #define MPCM1 0 2582 #define U2X1 1 2583 #define UPE1 2 2584 #define DOR1 3 2585 #define FE1 4 2586 #define UDRE1 5 2587 #define TXC1 6 2588 #define RXC1 7 2589 2590 /* USART1 Control and Status Register B */ 2591 #define UCSR1B _SFR_MEM8(0xC9) 2592 2593 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2594 2595 struct __reg_UCSR1B { 2596 unsigned int txb81 : 1; /* Transmit Data Bit 8 */ 2597 unsigned int rxb81 : 1; /* Receive Data Bit 8 */ 2598 unsigned int ucsz12 : 1; /* Character Size */ 2599 unsigned int txen1 : 1; /* Transmitter Enable */ 2600 unsigned int rxen1 : 1; /* Receiver Enable */ 2601 unsigned int udrie1 : 1; /* USART Data Register Empty Interrupt Enable */ 2602 unsigned int txcie1 : 1; /* TX Complete Interrupt Enable */ 2603 unsigned int rxcie1 : 1; /* RX Complete Interrupt Enable */ 2604 }; 2605 2606 #define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B) 2607 2608 #endif /* __ASSEMBLER__ */ 2609 2610 /* UCSR1B */ 2611 2612 #define TXB81 0 2613 #define RXB81 1 2614 #define UCSZ12 2 2615 #define TXEN1 3 2616 #define RXEN1 4 2617 #define UDRIE1 5 2618 #define TXCIE1 6 2619 #define RXCIE1 7 2620 2621 /* USART1 Control and Status Register C */ 2622 #define UCSR1C _SFR_MEM8(0xCA) 2623 2624 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2625 2626 struct __reg_UCSR1C { 2627 unsigned int ucpol1 : 1; /* Clock Polarity */ 2628 unsigned int ucsz1 : 2; /* Character Size */ 2629 unsigned int usbs1 : 1; /* Stop Bit Select */ 2630 unsigned int upm1 : 2; /* Parity Mode */ 2631 unsigned int umsel1 : 2; /* USART Mode Select */ 2632 }; 2633 /* NOTE: UCSR1C in SPI mode have only lower three bits. 2634 UCORD1 Data Order 2635 UCPHA1 Clock Phase 2636 UCPOL1 Clock Polarity 2637 */ 2638 #define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C) 2639 2640 #endif /* __ASSEMBLER__ */ 2641 2642 /* UCSR1C */ 2643 2644 #define UCPOL1 0 2645 #define UCPHA1 1 2646 #define UCSZ10 1 2647 #define UDORD1 2 2648 #define UCSZ11 2 2649 #define USBS1 3 2650 #define UPM10 4 2651 #define UPM11 5 2652 #define UMSEL10 6 2653 #define UMSEL11 7 2654 2655 /* USART1 Baud Rate Register Bytes */ 2656 #define UBRR1 _SFR_MEM16(0xCC) 2657 #define UBRR1L _SFR_MEM8(0xCC) 2658 #define UBRR1H _SFR_MEM8(0xCD) 2659 2660 /* USART1 I/O Data Register */ 2661 #define UDR1 _SFR_MEM8(0xCE) 2662 2663 /* UDR1 */ 2664 2665 #define UDR10 0 2666 #define UDR11 1 2667 #define UDR12 2 2668 #define UDR13 3 2669 #define UDR14 4 2670 #define UDR15 5 2671 #define UDR16 6 2672 #define UDR17 7 2673 2674 /* Symbol Counter Control Register 0 */ 2675 #define SCCR0 _SFR_MEM8(0xDC) 2676 2677 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2678 2679 struct __reg_SCCR0 { 2680 unsigned int sccmp : 3; /* Symbol Counter Compare Unit 3 Mode select */ 2681 unsigned int sctse : 1; /* Symbol Counter Automatic Timestamping enable */ 2682 unsigned int sccksel : 1; /* Symbol Counter Clock Source select */ 2683 unsigned int scen : 1; /* Symbol Counter enable */ 2684 unsigned int scmbts : 1; /* Manual Beacon Timestamp */ 2685 unsigned int scres : 1; /* Symbol Counter Synchronization */ 2686 }; 2687 2688 #define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0) 2689 2690 #endif /* __ASSEMBLER__ */ 2691 2692 /* SCCR0 */ 2693 2694 #define SCCMP1 0 2695 #define SCCMP2 1 2696 #define SCCMP3 2 2697 #define SCTSE 3 2698 #define SCCKSEL 4 2699 #define SCEN 5 2700 #define SCMBTS 6 2701 #define SCRES 7 2702 2703 /* Symbol Counter Control Register 1 */ 2704 #define SCCR1 _SFR_MEM8(0xDD) 2705 2706 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2707 2708 struct __reg_SCCR1 { 2709 unsigned int scenbo : 1; /* Backoff Slot Counter enable */ 2710 unsigned int : 7; 2711 }; 2712 2713 #define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1) 2714 2715 #endif /* __ASSEMBLER__ */ 2716 2717 /* SCCR1 */ 2718 2719 #define SCENBO 0 2720 2721 /* Symbol Counter Status Register */ 2722 #define SCSR _SFR_MEM8(0xDE) 2723 2724 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2725 2726 struct __reg_SCSR { 2727 unsigned int scbsy : 1; /* Symbol Counter busy */ 2728 unsigned int : 7; 2729 }; 2730 2731 #define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR) 2732 2733 #endif /* __ASSEMBLER__ */ 2734 2735 /* SCSR */ 2736 2737 #define SCBSY 0 2738 2739 /* Symbol Counter Interrupt Mask Register */ 2740 #define SCIRQM _SFR_MEM8(0xDF) 2741 2742 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2743 2744 struct __reg_SCIRQM { 2745 unsigned int irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */ 2746 unsigned int irqmof : 1; /* Symbol Counter Overflow IRQ enable */ 2747 unsigned int irqmbo : 1; /* Backoff Slot Counter IRQ enable */ 2748 unsigned int : 3; 2749 }; 2750 2751 #define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM) 2752 2753 #endif /* __ASSEMBLER__ */ 2754 2755 /* SCIRQM */ 2756 2757 #define IRQMCP1 0 2758 #define IRQMCP2 1 2759 #define IRQMCP3 2 2760 #define IRQMOF 3 2761 #define IRQMBO 4 2762 2763 /* Symbol Counter Interrupt Status Register */ 2764 #define SCIRQS _SFR_MEM8(0xE0) 2765 2766 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2767 2768 struct __reg_SCIRQS { 2769 unsigned int irqscp : 3; /* Compare Unit 3 Compare Match IRQ */ 2770 unsigned int irqsof : 1; /* Symbol Counter Overflow IRQ */ 2771 unsigned int irqsbo : 1; /* Backoff Slot Counter IRQ */ 2772 unsigned int : 3; 2773 }; 2774 2775 #define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS) 2776 2777 #endif /* __ASSEMBLER__ */ 2778 2779 /* SCIRQS */ 2780 2781 #define IRQSCP1 0 2782 #define IRQSCP2 1 2783 #define IRQSCP3 2 2784 #define IRQSOF 3 2785 #define IRQSBO 4 2786 2787 /* Symbol Counter Register LL-Byte */ 2788 #define SCCNTLL _SFR_MEM8(0xE1) 2789 2790 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2791 2792 struct __reg_SCCNTLL { 2793 unsigned int sccntll : 8; /* Symbol Counter Register LL-Byte */ 2794 }; 2795 2796 #define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL) 2797 2798 #endif /* __ASSEMBLER__ */ 2799 2800 /* SCCNTLL */ 2801 2802 #define SCCNTLL0 0 2803 #define SCCNTLL1 1 2804 #define SCCNTLL2 2 2805 #define SCCNTLL3 3 2806 #define SCCNTLL4 4 2807 #define SCCNTLL5 5 2808 #define SCCNTLL6 6 2809 #define SCCNTLL7 7 2810 2811 /* Symbol Counter Register LH-Byte */ 2812 #define SCCNTLH _SFR_MEM8(0xE2) 2813 2814 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2815 2816 struct __reg_SCCNTLH { 2817 unsigned int sccntlh : 8; /* Symbol Counter Register LH-Byte */ 2818 }; 2819 2820 #define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH) 2821 2822 #endif /* __ASSEMBLER__ */ 2823 2824 /* SCCNTLH */ 2825 2826 #define SCCNTLH0 0 2827 #define SCCNTLH1 1 2828 #define SCCNTLH2 2 2829 #define SCCNTLH3 3 2830 #define SCCNTLH4 4 2831 #define SCCNTLH5 5 2832 #define SCCNTLH6 6 2833 #define SCCNTLH7 7 2834 2835 /* Symbol Counter Register HL-Byte */ 2836 #define SCCNTHL _SFR_MEM8(0xE3) 2837 2838 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2839 2840 struct __reg_SCCNTHL { 2841 unsigned int sccnthl : 8; /* Symbol Counter Register HL-Byte */ 2842 }; 2843 2844 #define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL) 2845 2846 #endif /* __ASSEMBLER__ */ 2847 2848 /* SCCNTHL */ 2849 2850 #define SCCNTHL0 0 2851 #define SCCNTHL1 1 2852 #define SCCNTHL2 2 2853 #define SCCNTHL3 3 2854 #define SCCNTHL4 4 2855 #define SCCNTHL5 5 2856 #define SCCNTHL6 6 2857 #define SCCNTHL7 7 2858 2859 /* Symbol Counter Register HH-Byte */ 2860 #define SCCNTHH _SFR_MEM8(0xE4) 2861 2862 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2863 2864 struct __reg_SCCNTHH { 2865 unsigned int sccnthh : 8; /* Symbol Counter Register HH-Byte */ 2866 }; 2867 2868 #define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH) 2869 2870 #endif /* __ASSEMBLER__ */ 2871 2872 /* SCCNTHH */ 2873 2874 #define SCCNTHH0 0 2875 #define SCCNTHH1 1 2876 #define SCCNTHH2 2 2877 #define SCCNTHH3 3 2878 #define SCCNTHH4 4 2879 #define SCCNTHH5 5 2880 #define SCCNTHH6 6 2881 #define SCCNTHH7 7 2882 2883 /* Symbol Counter Beacon Timestamp Register LL-Byte */ 2884 #define SCBTSRLL _SFR_MEM8(0xE5) 2885 2886 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2887 2888 struct __reg_SCBTSRLL { 2889 unsigned int scbtsrll : 8; /* Symbol Counter Beacon Timestamp Register LL-Byte */ 2890 }; 2891 2892 #define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL) 2893 2894 #endif /* __ASSEMBLER__ */ 2895 2896 /* SCBTSRLL */ 2897 2898 #define SCBTSRLL0 0 2899 #define SCBTSRLL1 1 2900 #define SCBTSRLL2 2 2901 #define SCBTSRLL3 3 2902 #define SCBTSRLL4 4 2903 #define SCBTSRLL5 5 2904 #define SCBTSRLL6 6 2905 #define SCBTSRLL7 7 2906 2907 /* Symbol Counter Beacon Timestamp Register LH-Byte */ 2908 #define SCBTSRLH _SFR_MEM8(0xE6) 2909 2910 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2911 2912 struct __reg_SCBTSRLH { 2913 unsigned int scbtsrlh : 8; /* Symbol Counter Beacon Timestamp Register LH-Byte */ 2914 }; 2915 2916 #define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH) 2917 2918 #endif /* __ASSEMBLER__ */ 2919 2920 /* SCBTSRLH */ 2921 2922 #define SCBTSRLH0 0 2923 #define SCBTSRLH1 1 2924 #define SCBTSRLH2 2 2925 #define SCBTSRLH3 3 2926 #define SCBTSRLH4 4 2927 #define SCBTSRLH5 5 2928 #define SCBTSRLH6 6 2929 #define SCBTSRLH7 7 2930 2931 /* Symbol Counter Beacon Timestamp Register HL-Byte */ 2932 #define SCBTSRHL _SFR_MEM8(0xE7) 2933 2934 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2935 2936 struct __reg_SCBTSRHL { 2937 unsigned int scbtsrhl : 8; /* Symbol Counter Beacon Timestamp Register HL-Byte */ 2938 }; 2939 2940 #define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL) 2941 2942 #endif /* __ASSEMBLER__ */ 2943 2944 /* SCBTSRHL */ 2945 2946 #define SCBTSRHL0 0 2947 #define SCBTSRHL1 1 2948 #define SCBTSRHL2 2 2949 #define SCBTSRHL3 3 2950 #define SCBTSRHL4 4 2951 #define SCBTSRHL5 5 2952 #define SCBTSRHL6 6 2953 #define SCBTSRHL7 7 2954 2955 /* Symbol Counter Beacon Timestamp Register HH-Byte */ 2956 #define SCBTSRHH _SFR_MEM8(0xE8) 2957 2958 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2959 2960 struct __reg_SCBTSRHH { 2961 unsigned int scbtsrhh : 8; /* Symbol Counter Beacon Timestamp Register HH-Byte */ 2962 }; 2963 2964 #define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH) 2965 2966 #endif /* __ASSEMBLER__ */ 2967 2968 /* SCBTSRHH */ 2969 2970 #define SCBTSRHH0 0 2971 #define SCBTSRHH1 1 2972 #define SCBTSRHH2 2 2973 #define SCBTSRHH3 3 2974 #define SCBTSRHH4 4 2975 #define SCBTSRHH5 5 2976 #define SCBTSRHH6 6 2977 #define SCBTSRHH7 7 2978 2979 /* Symbol Counter Frame Timestamp Register LL-Byte */ 2980 #define SCTSRLL _SFR_MEM8(0xE9) 2981 2982 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2983 2984 struct __reg_SCTSRLL { 2985 unsigned int sctsrll : 8; /* Symbol Counter Frame Timestamp Register LL-Byte */ 2986 }; 2987 2988 #define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL) 2989 2990 #endif /* __ASSEMBLER__ */ 2991 2992 /* SCTSRLL */ 2993 2994 #define SCTSRLL0 0 2995 #define SCTSRLL1 1 2996 #define SCTSRLL2 2 2997 #define SCTSRLL3 3 2998 #define SCTSRLL4 4 2999 #define SCTSRLL5 5 3000 #define SCTSRLL6 6 3001 #define SCTSRLL7 7 3002 3003 /* Symbol Counter Frame Timestamp Register LH-Byte */ 3004 #define SCTSRLH _SFR_MEM8(0xEA) 3005 3006 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3007 3008 struct __reg_SCTSRLH { 3009 unsigned int sctsrlh : 8; /* Symbol Counter Frame Timestamp Register LH-Byte */ 3010 }; 3011 3012 #define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH) 3013 3014 #endif /* __ASSEMBLER__ */ 3015 3016 /* SCTSRLH */ 3017 3018 #define SCTSRLH0 0 3019 #define SCTSRLH1 1 3020 #define SCTSRLH2 2 3021 #define SCTSRLH3 3 3022 #define SCTSRLH4 4 3023 #define SCTSRLH5 5 3024 #define SCTSRLH6 6 3025 #define SCTSRLH7 7 3026 3027 /* Symbol Counter Frame Timestamp Register HL-Byte */ 3028 #define SCTSRHL _SFR_MEM8(0xEB) 3029 3030 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3031 3032 struct __reg_SCTSRHL { 3033 unsigned int sctsrhl : 8; /* Symbol Counter Frame Timestamp Register HL-Byte */ 3034 }; 3035 3036 #define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL) 3037 3038 #endif /* __ASSEMBLER__ */ 3039 3040 /* SCTSRHL */ 3041 3042 #define SCTSRHL0 0 3043 #define SCTSRHL1 1 3044 #define SCTSRHL2 2 3045 #define SCTSRHL3 3 3046 #define SCTSRHL4 4 3047 #define SCTSRHL5 5 3048 #define SCTSRHL6 6 3049 #define SCTSRHL7 7 3050 3051 /* Symbol Counter Frame Timestamp Register HH-Byte */ 3052 #define SCTSRHH _SFR_MEM8(0xEC) 3053 3054 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3055 3056 struct __reg_SCTSRHH { 3057 unsigned int sctsrhh : 8; /* Symbol Counter Frame Timestamp Register HH-Byte */ 3058 }; 3059 3060 #define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH) 3061 3062 #endif /* __ASSEMBLER__ */ 3063 3064 /* SCTSRHH */ 3065 3066 #define SCTSRHH0 0 3067 #define SCTSRHH1 1 3068 #define SCTSRHH2 2 3069 #define SCTSRHH3 3 3070 #define SCTSRHH4 4 3071 #define SCTSRHH5 5 3072 #define SCTSRHH6 6 3073 #define SCTSRHH7 7 3074 3075 /* Symbol Counter Output Compare Register 3 LL-Byte */ 3076 #define SCOCR3LL _SFR_MEM8(0xED) 3077 3078 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3079 3080 struct __reg_SCOCR3LL { 3081 unsigned int scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte */ 3082 }; 3083 3084 #define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL) 3085 3086 #endif /* __ASSEMBLER__ */ 3087 3088 /* SCOCR3LL */ 3089 3090 #define SCOCR3LL0 0 3091 #define SCOCR3LL1 1 3092 #define SCOCR3LL2 2 3093 #define SCOCR3LL3 3 3094 #define SCOCR3LL4 4 3095 #define SCOCR3LL5 5 3096 #define SCOCR3LL6 6 3097 #define SCOCR3LL7 7 3098 3099 /* Symbol Counter Output Compare Register 3 LH-Byte */ 3100 #define SCOCR3LH _SFR_MEM8(0xEE) 3101 3102 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3103 3104 struct __reg_SCOCR3LH { 3105 unsigned int scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte */ 3106 }; 3107 3108 #define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH) 3109 3110 #endif /* __ASSEMBLER__ */ 3111 3112 /* SCOCR3LH */ 3113 3114 #define SCOCR3LH0 0 3115 #define SCOCR3LH1 1 3116 #define SCOCR3LH2 2 3117 #define SCOCR3LH3 3 3118 #define SCOCR3LH4 4 3119 #define SCOCR3LH5 5 3120 #define SCOCR3LH6 6 3121 #define SCOCR3LH7 7 3122 3123 /* Symbol Counter Output Compare Register 3 HL-Byte */ 3124 #define SCOCR3HL _SFR_MEM8(0xEF) 3125 3126 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3127 3128 struct __reg_SCOCR3HL { 3129 unsigned int scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte */ 3130 }; 3131 3132 #define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL) 3133 3134 #endif /* __ASSEMBLER__ */ 3135 3136 /* SCOCR3HL */ 3137 3138 #define SCOCR3HL0 0 3139 #define SCOCR3HL1 1 3140 #define SCOCR3HL2 2 3141 #define SCOCR3HL3 3 3142 #define SCOCR3HL4 4 3143 #define SCOCR3HL5 5 3144 #define SCOCR3HL6 6 3145 #define SCOCR3HL7 7 3146 3147 /* Symbol Counter Output Compare Register 3 HH-Byte */ 3148 #define SCOCR3HH _SFR_MEM8(0xF0) 3149 3150 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3151 3152 struct __reg_SCOCR3HH { 3153 unsigned int scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte */ 3154 }; 3155 3156 #define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH) 3157 3158 #endif /* __ASSEMBLER__ */ 3159 3160 /* SCOCR3HH */ 3161 3162 #define SCOCR3HH0 0 3163 #define SCOCR3HH1 1 3164 #define SCOCR3HH2 2 3165 #define SCOCR3HH3 3 3166 #define SCOCR3HH4 4 3167 #define SCOCR3HH5 5 3168 #define SCOCR3HH6 6 3169 #define SCOCR3HH7 7 3170 3171 /* Symbol Counter Output Compare Register 2 LL-Byte */ 3172 #define SCOCR2LL _SFR_MEM8(0xF1) 3173 3174 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3175 3176 struct __reg_SCOCR2LL { 3177 unsigned int scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte */ 3178 }; 3179 3180 #define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL) 3181 3182 #endif /* __ASSEMBLER__ */ 3183 3184 /* SCOCR2LL */ 3185 3186 #define SCOCR2LL0 0 3187 #define SCOCR2LL1 1 3188 #define SCOCR2LL2 2 3189 #define SCOCR2LL3 3 3190 #define SCOCR2LL4 4 3191 #define SCOCR2LL5 5 3192 #define SCOCR2LL6 6 3193 #define SCOCR2LL7 7 3194 3195 /* Symbol Counter Output Compare Register 2 LH-Byte */ 3196 #define SCOCR2LH _SFR_MEM8(0xF2) 3197 3198 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3199 3200 struct __reg_SCOCR2LH { 3201 unsigned int scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte */ 3202 }; 3203 3204 #define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH) 3205 3206 #endif /* __ASSEMBLER__ */ 3207 3208 /* SCOCR2LH */ 3209 3210 #define SCOCR2LH0 0 3211 #define SCOCR2LH1 1 3212 #define SCOCR2LH2 2 3213 #define SCOCR2LH3 3 3214 #define SCOCR2LH4 4 3215 #define SCOCR2LH5 5 3216 #define SCOCR2LH6 6 3217 #define SCOCR2LH7 7 3218 3219 /* Symbol Counter Output Compare Register 2 HL-Byte */ 3220 #define SCOCR2HL _SFR_MEM8(0xF3) 3221 3222 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3223 3224 struct __reg_SCOCR2HL { 3225 unsigned int scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte */ 3226 }; 3227 3228 #define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL) 3229 3230 #endif /* __ASSEMBLER__ */ 3231 3232 /* SCOCR2HL */ 3233 3234 #define SCOCR2HL0 0 3235 #define SCOCR2HL1 1 3236 #define SCOCR2HL2 2 3237 #define SCOCR2HL3 3 3238 #define SCOCR2HL4 4 3239 #define SCOCR2HL5 5 3240 #define SCOCR2HL6 6 3241 #define SCOCR2HL7 7 3242 3243 /* Symbol Counter Output Compare Register 2 HH-Byte */ 3244 #define SCOCR2HH _SFR_MEM8(0xF4) 3245 3246 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3247 3248 struct __reg_SCOCR2HH { 3249 unsigned int scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte */ 3250 }; 3251 3252 #define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH) 3253 3254 #endif /* __ASSEMBLER__ */ 3255 3256 /* SCOCR2HH */ 3257 3258 #define SCOCR2HH0 0 3259 #define SCOCR2HH1 1 3260 #define SCOCR2HH2 2 3261 #define SCOCR2HH3 3 3262 #define SCOCR2HH4 4 3263 #define SCOCR2HH5 5 3264 #define SCOCR2HH6 6 3265 #define SCOCR2HH7 7 3266 3267 /* Symbol Counter Output Compare Register 1 LL-Byte */ 3268 #define SCOCR1LL _SFR_MEM8(0xF5) 3269 3270 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3271 3272 struct __reg_SCOCR1LL { 3273 unsigned int scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte */ 3274 }; 3275 3276 #define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL) 3277 3278 #endif /* __ASSEMBLER__ */ 3279 3280 /* SCOCR1LL */ 3281 3282 #define SCOCR1LL0 0 3283 #define SCOCR1LL1 1 3284 #define SCOCR1LL2 2 3285 #define SCOCR1LL3 3 3286 #define SCOCR1LL4 4 3287 #define SCOCR1LL5 5 3288 #define SCOCR1LL6 6 3289 #define SCOCR1LL7 7 3290 3291 /* Symbol Counter Output Compare Register 1 LH-Byte */ 3292 #define SCOCR1LH _SFR_MEM8(0xF6) 3293 3294 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3295 3296 struct __reg_SCOCR1LH { 3297 unsigned int scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte */ 3298 }; 3299 3300 #define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH) 3301 3302 #endif /* __ASSEMBLER__ */ 3303 3304 /* SCOCR1LH */ 3305 3306 #define SCOCR1LH0 0 3307 #define SCOCR1LH1 1 3308 #define SCOCR1LH2 2 3309 #define SCOCR1LH3 3 3310 #define SCOCR1LH4 4 3311 #define SCOCR1LH5 5 3312 #define SCOCR1LH6 6 3313 #define SCOCR1LH7 7 3314 3315 /* Symbol Counter Output Compare Register 1 HL-Byte */ 3316 #define SCOCR1HL _SFR_MEM8(0xF7) 3317 3318 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3319 3320 struct __reg_SCOCR1HL { 3321 unsigned int scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte */ 3322 }; 3323 3324 #define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL) 3325 3326 #endif /* __ASSEMBLER__ */ 3327 3328 /* SCOCR1HL */ 3329 3330 #define SCOCR1HL0 0 3331 #define SCOCR1HL1 1 3332 #define SCOCR1HL2 2 3333 #define SCOCR1HL3 3 3334 #define SCOCR1HL4 4 3335 #define SCOCR1HL5 5 3336 #define SCOCR1HL6 6 3337 #define SCOCR1HL7 7 3338 3339 /* Symbol Counter Output Compare Register 1 HH-Byte */ 3340 #define SCOCR1HH _SFR_MEM8(0xF8) 3341 3342 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3343 3344 struct __reg_SCOCR1HH { 3345 unsigned int scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte */ 3346 }; 3347 3348 #define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH) 3349 3350 #endif /* __ASSEMBLER__ */ 3351 3352 /* SCOCR1HH */ 3353 3354 #define SCOCR1HH0 0 3355 #define SCOCR1HH1 1 3356 #define SCOCR1HH2 2 3357 #define SCOCR1HH3 3 3358 #define SCOCR1HH4 4 3359 #define SCOCR1HH5 5 3360 #define SCOCR1HH6 6 3361 #define SCOCR1HH7 7 3362 3363 /* Timer/Counter5 Control Register A */ 3364 #define TCCR5A _SFR_MEM8(0x120) 3365 3366 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3367 3368 struct __reg_TCCR5A { 3369 unsigned int wgm5 : 2; /* Waveform Generation Mode */ 3370 unsigned int com5c : 2; /* Compare Output Mode for Channel C */ 3371 unsigned int com5b : 2; /* Compare Output Mode for Channel B */ 3372 unsigned int com5a : 2; /* Compare Output Mode for Channel A */ 3373 }; 3374 3375 #define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A) 3376 3377 #endif /* __ASSEMBLER__ */ 3378 3379 /* TCCR5A */ 3380 3381 #define WGM50 0 3382 #define WGM51 1 3383 #define COM5C0 2 3384 #define COM5C1 3 3385 #define COM5B0 4 3386 #define COM5B1 5 3387 #define COM5A0 6 3388 #define COM5A1 7 3389 3390 /* Timer/Counter5 Control Register B */ 3391 #define TCCR5B _SFR_MEM8(0x121) 3392 3393 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3394 3395 struct __reg_TCCR5B { 3396 unsigned int cs5 : 3; /* Clock Select */ 3397 unsigned int wgm5 : 2; /* Waveform Generation Mode */ 3398 unsigned int : 1; 3399 unsigned int ices5 : 1; /* Input Capture 5 Edge Select */ 3400 unsigned int icnc5 : 1; /* Input Capture 5 Noise Canceller */ 3401 }; 3402 3403 #define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B) 3404 3405 #endif /* __ASSEMBLER__ */ 3406 3407 /* TCCR5B */ 3408 3409 #define CS50 0 3410 #define CS51 1 3411 #define CS52 2 3412 #define WGM52 3 3413 #define WGM53 4 3414 #define ICES5 6 3415 #define ICNC5 7 3416 3417 /* Timer/Counter5 Control Register C */ 3418 #define TCCR5C _SFR_MEM8(0x122) 3419 3420 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3421 3422 struct __reg_TCCR5C { 3423 unsigned int : 5; 3424 unsigned int foc5c : 1; /* Force Output Compare for Channel C */ 3425 unsigned int foc5b : 1; /* Force Output Compare for Channel B */ 3426 unsigned int foc5a : 1; /* Force Output Compare for Channel A */ 3427 }; 3428 3429 #define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C) 3430 3431 #endif /* __ASSEMBLER__ */ 3432 3433 /* TCCR5C */ 3434 3435 #define FOC5C 5 3436 #define FOC5B 6 3437 #define FOC5A 7 3438 3439 /* Timer/Counter5 Bytes */ 3440 #define TCNT5 _SFR_MEM16(0x124) 3441 #define TCNT5L _SFR_MEM8(0x124) 3442 #define TCNT5H _SFR_MEM8(0x125) 3443 3444 /* Timer/Counter5 Input Capture Register Bytes */ 3445 #define ICR5 _SFR_MEM16(0x126) 3446 #define ICR5L _SFR_MEM8(0x126) 3447 #define ICR5H _SFR_MEM8(0x127) 3448 3449 /* Timer/Counter5 Output Compare Register A Bytes */ 3450 #define OCR5A _SFR_MEM16(0x128) 3451 #define OCR5AL _SFR_MEM8(0x128) 3452 #define OCR5AH _SFR_MEM8(0x129) 3453 3454 /* Timer/Counter5 Output Compare Register B Bytes */ 3455 #define OCR5B _SFR_MEM16(0x12A) 3456 #define OCR5BL _SFR_MEM8(0x12A) 3457 #define OCR5BH _SFR_MEM8(0x12B) 3458 3459 /* Timer/Counter5 Output Compare Register C Bytes */ 3460 #define OCR5C _SFR_MEM16(0x12C) 3461 #define OCR5CL _SFR_MEM8(0x12C) 3462 #define OCR5CH _SFR_MEM8(0x12D) 3463 3464 /* Low Leakage Voltage Regulator Control Register */ 3465 #define LLCR _SFR_MEM8(0x12F) 3466 3467 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3468 3469 struct __reg_LLCR { 3470 unsigned int llencal : 1; /* Enable Automatic Calibration */ 3471 unsigned int llshort : 1; /* Short Lower Calibration Circuit */ 3472 unsigned int lltco : 1; /* Temperature Coefficient of Current Source */ 3473 unsigned int llcal : 1; /* Calibration Active */ 3474 unsigned int llcomp : 1; /* Comparator Output */ 3475 unsigned int lldone : 1; /* Calibration Done */ 3476 unsigned int : 2; 3477 }; 3478 3479 #define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR) 3480 3481 #endif /* __ASSEMBLER__ */ 3482 3483 /* LLCR */ 3484 3485 #define LLENCAL 0 3486 #define LLSHORT 1 3487 #define LLTCO 2 3488 #define LLCAL 3 3489 #define LLCOMP 4 3490 #define LLDONE 5 3491 3492 /* Low Leakage Voltage Regulator Data Register (Low-Byte) */ 3493 #define LLDRL _SFR_MEM8(0x130) 3494 3495 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3496 3497 struct __reg_LLDRL { 3498 unsigned int lldrl : 4; /* Low-Byte Data Register Bits */ 3499 unsigned int : 4; 3500 }; 3501 3502 #define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL) 3503 3504 #endif /* __ASSEMBLER__ */ 3505 3506 /* LLDRL */ 3507 3508 #define LLDRL0 0 3509 #define LLDRL1 1 3510 #define LLDRL2 2 3511 #define LLDRL3 3 3512 3513 /* Low Leakage Voltage Regulator Data Register (High-Byte) */ 3514 #define LLDRH _SFR_MEM8(0x131) 3515 3516 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3517 3518 struct __reg_LLDRH { 3519 unsigned int lldrh : 5; /* High-Byte Data Register Bits */ 3520 unsigned int : 3; 3521 }; 3522 3523 #define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH) 3524 3525 #endif /* __ASSEMBLER__ */ 3526 3527 /* LLDRH */ 3528 3529 #define LLDRH0 0 3530 #define LLDRH1 1 3531 #define LLDRH2 2 3532 #define LLDRH3 3 3533 #define LLDRH4 4 3534 3535 /* Data Retention Configuration Register of SRAM 3 */ 3536 #define DRTRAM3 _SFR_MEM8(0x132) 3537 3538 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3539 3540 struct __reg_DRTRAM3 { 3541 unsigned int : 4; 3542 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 3543 unsigned int drtswok : 1; /* DRT Switch OK */ 3544 unsigned int : 2; 3545 }; 3546 3547 #define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3) 3548 3549 #endif /* __ASSEMBLER__ */ 3550 3551 /* DRTRAM3 */ 3552 3553 #define ENDRT 4 3554 #define DRTSWOK 5 3555 3556 /* Data Retention Configuration Register of SRAM 2 */ 3557 #define DRTRAM2 _SFR_MEM8(0x133) 3558 3559 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3560 3561 struct __reg_DRTRAM2 { 3562 unsigned int : 4; 3563 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 3564 unsigned int drtswok : 1; /* DRT Switch OK */ 3565 unsigned int : 2; 3566 }; 3567 3568 #define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2) 3569 3570 #endif /* __ASSEMBLER__ */ 3571 3572 /* DRTRAM2 */ 3573 3574 #define ENDRT 4 3575 #define DRTSWOK 5 3576 3577 /* Data Retention Configuration Register of SRAM 1 */ 3578 #define DRTRAM1 _SFR_MEM8(0x134) 3579 3580 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3581 3582 struct __reg_DRTRAM1 { 3583 unsigned int : 4; 3584 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 3585 unsigned int drtswok : 1; /* DRT Switch OK */ 3586 unsigned int : 2; 3587 }; 3588 3589 #define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1) 3590 3591 #endif /* __ASSEMBLER__ */ 3592 3593 /* DRTRAM1 */ 3594 3595 #define ENDRT 4 3596 #define DRTSWOK 5 3597 3598 /* Data Retention Configuration Register of SRAM 0 */ 3599 #define DRTRAM0 _SFR_MEM8(0x135) 3600 3601 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3602 3603 struct __reg_DRTRAM0 { 3604 unsigned int : 4; 3605 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 3606 unsigned int drtswok : 1; /* DRT Switch OK */ 3607 unsigned int : 2; 3608 }; 3609 3610 #define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0) 3611 3612 #endif /* __ASSEMBLER__ */ 3613 3614 /* DRTRAM0 */ 3615 3616 #define ENDRT 4 3617 #define DRTSWOK 5 3618 3619 /* Port Driver Strength Register 0 */ 3620 #define DPDS0 _SFR_MEM8(0x136) 3621 3622 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3623 3624 struct __reg_DPDS0 { 3625 unsigned int pbdrv : 2; /* Driver Strength Port B */ 3626 unsigned int pddrv : 2; /* Driver Strength Port D */ 3627 unsigned int pedrv : 2; /* Driver Strength Port E */ 3628 unsigned int pfdrv : 2; /* Driver Strength Port F */ 3629 }; 3630 3631 #define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0) 3632 3633 #endif /* __ASSEMBLER__ */ 3634 3635 /* DPDS0 */ 3636 3637 #define PBDRV0 0 3638 #define PBDRV1 1 3639 #define PDDRV0 2 3640 #define PDDRV1 3 3641 #define PEDRV0 4 3642 #define PEDRV1 5 3643 #define PFDRV0 6 3644 #define PFDRV1 7 3645 3646 /* Port Driver Strength Register 1 */ 3647 #define DPDS1 _SFR_MEM8(0x137) 3648 3649 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3650 3651 struct __reg_DPDS1 { 3652 unsigned int pgdrv : 2; /* Driver Strength Port G */ 3653 unsigned int : 6; 3654 }; 3655 3656 #define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1) 3657 3658 #endif /* __ASSEMBLER__ */ 3659 3660 /* DPDS1 */ 3661 3662 #define PGDRV0 0 3663 #define PGDRV1 1 3664 3665 /* Transceiver Pin Register */ 3666 #define TRXPR _SFR_MEM8(0x139) 3667 3668 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3669 3670 struct __reg_TRXPR { 3671 unsigned int trxrst : 1; /* Force Transceiver Reset */ 3672 unsigned int slptr : 1; /* Multi-purpose Transceiver Control Bit */ 3673 unsigned int : 6; 3674 }; 3675 3676 #define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR) 3677 3678 #endif /* __ASSEMBLER__ */ 3679 3680 /* TRXPR */ 3681 3682 #define TRXRST 0 3683 #define SLPTR 1 3684 3685 /* AES Control Register */ 3686 #define AES_CTRL _SFR_MEM8(0x13C) 3687 3688 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3689 3690 struct __reg_AES_CTRL { 3691 unsigned int : 2; 3692 unsigned int aes_im : 1; /* AES Interrupt Enable */ 3693 unsigned int aes_dir : 1; /* Set AES Operation Direction */ 3694 unsigned int : 1; 3695 unsigned int aes_mode : 1; /* Set AES Operation Mode */ 3696 unsigned int : 1; 3697 unsigned int aes_request : 1; /* Request AES Operation. */ 3698 }; 3699 3700 #define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL) 3701 3702 /* symbolic names */ 3703 3704 #define AES_DIR_ENC 0 3705 #define AES_DIR_DEC 1 3706 #define AES_MODE_ECB 0 3707 #define AES_MODE_CBC 1 3708 3709 #endif /* __ASSEMBLER__ */ 3710 3711 /* AES_CTRL */ 3712 3713 #define AES_IM 2 3714 #define AES_DIR 3 3715 #define AES_MODE 5 3716 #define AES_REQUEST 7 3717 3718 /* AES Status Register */ 3719 #define AES_STATUS _SFR_MEM8(0x13D) 3720 3721 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3722 3723 struct __reg_AES_STATUS { 3724 unsigned int aes_done : 1; /* AES Operation Finished with Success */ 3725 unsigned int : 6; 3726 unsigned int aes_er : 1; /* AES Operation Finished with Error */ 3727 }; 3728 3729 #define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS) 3730 3731 #endif /* __ASSEMBLER__ */ 3732 3733 /* AES_STATUS */ 3734 3735 #define AES_DONE 0 3736 #define AES_ER 7 3737 3738 /* AES Plain and Cipher Text Buffer Register */ 3739 #define AES_STATE _SFR_MEM8(0x13E) 3740 3741 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3742 3743 struct __reg_AES_STATE { 3744 unsigned int aes_state : 8; /* AES Plain and Cipher Text Buffer */ 3745 }; 3746 3747 #define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE) 3748 3749 #endif /* __ASSEMBLER__ */ 3750 3751 /* AES_STATE */ 3752 3753 #define AES_STATE0 0 3754 #define AES_STATE1 1 3755 #define AES_STATE2 2 3756 #define AES_STATE3 3 3757 #define AES_STATE4 4 3758 #define AES_STATE5 5 3759 #define AES_STATE6 6 3760 #define AES_STATE7 7 3761 3762 /* AES Encryption and Decryption Key Buffer Register */ 3763 #define AES_KEY _SFR_MEM8(0x13F) 3764 3765 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3766 3767 struct __reg_AES_KEY { 3768 unsigned int aes_key : 8; /* AES Encryption/Decryption Key Buffer */ 3769 }; 3770 3771 #define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY) 3772 3773 #endif /* __ASSEMBLER__ */ 3774 3775 /* AES_KEY */ 3776 3777 #define AES_KEY0 0 3778 #define AES_KEY1 1 3779 #define AES_KEY2 2 3780 #define AES_KEY3 3 3781 #define AES_KEY4 4 3782 #define AES_KEY5 5 3783 #define AES_KEY6 6 3784 #define AES_KEY7 7 3785 3786 /* Transceiver Status Register */ 3787 #define TRX_STATUS _SFR_MEM8(0x141) 3788 3789 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3790 3791 struct __reg_TRX_STATUS { 3792 unsigned int trx_status : 5; /* Transceiver Main Status */ 3793 unsigned int tst_status : 1; /* Test mode status */ 3794 unsigned int cca_status : 1; /* CCA Status Result */ 3795 unsigned int cca_done : 1; /* CCA Algorithm Status */ 3796 }; 3797 3798 #define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS) 3799 3800 /* symbolic names */ 3801 3802 #define P_ON 0 3803 #define BUSY_RX 1 3804 #define BUSY_TX 2 3805 #define RX_ON 6 3806 #define TRX_OFF 8 3807 #define PLL_ON 9 3808 #define SLEEP 15 3809 #define BUSY_RX_AACK 17 3810 #define BUSY_TX_ARET 18 3811 #define RX_AACK_ON 22 3812 #define TX_ARET_ON 25 3813 #define STATE_TRANSITION_IN_PROGRESS 31 3814 #define TST_DISABLED 0 3815 #define TST_ENABLED 1 3816 #define CCA_BUSY 0 3817 #define CCA_IDLE 1 3818 #define CCA_NOT_FIN 0 3819 #define CCA_FIN 1 3820 3821 #endif /* __ASSEMBLER__ */ 3822 3823 /* TRX_STATUS */ 3824 3825 #define TRX_STATUS0 0 3826 #define TRX_STATUS1 1 3827 #define TRX_STATUS2 2 3828 #define TRX_STATUS3 3 3829 #define TRX_STATUS4 4 3830 #define TST_STATUS 5 3831 #define CCA_STATUS 6 3832 #define CCA_DONE 7 3833 3834 /* Transceiver State Control Register */ 3835 #define TRX_STATE _SFR_MEM8(0x142) 3836 3837 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3838 3839 struct __reg_TRX_STATE { 3840 unsigned int trx_cmd : 5; /* State Control Command */ 3841 unsigned int trac_status : 3; /* Transaction Status */ 3842 }; 3843 3844 #define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE) 3845 3846 /* symbolic names */ 3847 3848 #define CMD_NOP 0 3849 #define CMD_TX_START 2 3850 #define CMD_FORCE_TRX_OFF 3 3851 #define CMD_FORCE_PLL_ON 4 3852 #define CMD_RX_ON 6 3853 #define CMD_TRX_OFF 8 3854 #define CMD_PLL_ON 9 3855 #define CMD_RX_AACK_ON 22 3856 #define CMD_TX_ARET_ON 25 3857 #define TRAC_SUCCESS 0 3858 #define TRAC_SUCCESS_DATA_PENDING 1 3859 #define TRAC_SUCCESS_WAIT_FOR_ACK 2 3860 #define TRAC_CHANNEL_ACCESS_FAILURE 3 3861 #define TRAC_NO_ACK 5 3862 #define TRAC_INVALID 7 3863 3864 #endif /* __ASSEMBLER__ */ 3865 3866 /* TRX_STATE */ 3867 3868 #define TRX_CMD0 0 3869 #define TRX_CMD1 1 3870 #define TRX_CMD2 2 3871 #define TRX_CMD3 3 3872 #define TRX_CMD4 4 3873 #define TRAC_STATUS0 5 3874 #define TRAC_STATUS1 6 3875 #define TRAC_STATUS2 7 3876 3877 /* Reserved */ 3878 #define TRX_CTRL_0 _SFR_MEM8(0x143) 3879 3880 /* Transceiver Control Register 1 */ 3881 #define TRX_CTRL_1 _SFR_MEM8(0x144) 3882 3883 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3884 3885 struct __reg_TRX_CTRL_1 { 3886 unsigned int : 5; 3887 unsigned int tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */ 3888 unsigned int irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */ 3889 unsigned int pa_ext_en : 1; /* External PA support enable */ 3890 }; 3891 3892 #define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1) 3893 3894 #endif /* __ASSEMBLER__ */ 3895 3896 /* TRX_CTRL_1 */ 3897 3898 #define TX_AUTO_CRC_ON 5 3899 #define IRQ_2_EXT_EN 6 3900 #define PA_EXT_EN 7 3901 3902 /* Transceiver Transmit Power Control Register */ 3903 #define PHY_TX_PWR _SFR_MEM8(0x145) 3904 3905 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3906 3907 struct __reg_PHY_TX_PWR { 3908 unsigned int tx_pwr : 4; /* Transmit Power Setting */ 3909 unsigned int pa_lt : 2; /* Power Amplifier Lead Time */ 3910 unsigned int pa_buf_lt : 2; /* Power Amplifier Buffer Lead Time */ 3911 }; 3912 3913 #define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR) 3914 3915 /* symbolic names */ 3916 3917 #define PA_LT_2US 0 3918 #define PA_LT_4US 1 3919 #define PA_LT_6US 2 3920 #define PA_LT_8US 3 3921 #define PA_BUF_LT_0US 0 3922 #define PA_BUF_LT_2US 1 3923 #define PA_BUF_LT_4US 2 3924 #define PA_BUF_LT_6US 3 3925 3926 #endif /* __ASSEMBLER__ */ 3927 3928 /* PHY_TX_PWR */ 3929 3930 #define TX_PWR0 0 3931 #define TX_PWR1 1 3932 #define TX_PWR2 2 3933 #define TX_PWR3 3 3934 #define PA_LT0 4 3935 #define PA_LT1 5 3936 #define PA_BUF_LT0 6 3937 #define PA_BUF_LT1 7 3938 3939 /* Receiver Signal Strength Indicator Register */ 3940 #define PHY_RSSI _SFR_MEM8(0x146) 3941 3942 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3943 3944 struct __reg_PHY_RSSI { 3945 unsigned int rssi : 5; /* Receiver Signal Strength Indicator */ 3946 unsigned int rnd_value : 2; /* Random Value */ 3947 unsigned int rx_crc_valid : 1; /* Received Frame CRC Status */ 3948 }; 3949 3950 #define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI) 3951 3952 /* symbolic names */ 3953 3954 #define RSSI_MIN 0 3955 #define RSSI_MIN_PLUS_3dB 1 3956 #define RSSI_MAX 28 3957 #define CRC_INVALID 0 3958 #define CRC_VALID 1 3959 3960 #endif /* __ASSEMBLER__ */ 3961 3962 /* PHY_RSSI */ 3963 3964 #define RSSI0 0 3965 #define RSSI1 1 3966 #define RSSI2 2 3967 #define RSSI3 3 3968 #define RSSI4 4 3969 #define RND_VALUE0 5 3970 #define RND_VALUE1 6 3971 #define RX_CRC_VALID 7 3972 3973 /* Transceiver Energy Detection Level Register */ 3974 #define PHY_ED_LEVEL _SFR_MEM8(0x147) 3975 3976 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3977 3978 struct __reg_PHY_ED_LEVEL { 3979 unsigned int ed_level : 8; /* Energy Detection Level */ 3980 }; 3981 3982 #define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL) 3983 3984 /* symbolic names */ 3985 3986 #define ED_MIN 0 3987 #define ED_MIN_PLUS_1dB 1 3988 #define ED_MAX 84 3989 #define ED_RESET 255 3990 3991 #endif /* __ASSEMBLER__ */ 3992 3993 /* PHY_ED_LEVEL */ 3994 3995 #define ED_LEVEL0 0 3996 #define ED_LEVEL1 1 3997 #define ED_LEVEL2 2 3998 #define ED_LEVEL3 3 3999 #define ED_LEVEL4 4 4000 #define ED_LEVEL5 5 4001 #define ED_LEVEL6 6 4002 #define ED_LEVEL7 7 4003 4004 /* Transceiver Clear Channel Assessment (CCA) Control Register */ 4005 #define PHY_CC_CCA _SFR_MEM8(0x148) 4006 4007 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4008 4009 struct __reg_PHY_CC_CCA { 4010 unsigned int channel : 5; /* RX/TX Channel Selection */ 4011 unsigned int cca_mode : 2; /* Select CCA Measurement Mode */ 4012 unsigned int cca_request : 1; /* Manual CCA Measurement Request */ 4013 }; 4014 4015 #define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA) 4016 4017 /* symbolic names */ 4018 4019 #define F_2405MHZ 11 4020 #define F_2410MHZ 12 4021 #define F_2415MHZ 13 4022 #define F_2420MHZ 14 4023 #define F_2425MHZ 15 4024 #define F_2430MHZ 16 4025 #define F_2435MHZ 17 4026 #define F_2440MHZ 18 4027 #define F_2445MHZ 19 4028 #define F_2450MHZ 20 4029 #define F_2455MHZ 21 4030 #define F_2460MHZ 22 4031 #define F_2465MHZ 23 4032 #define F_2470MHZ 24 4033 #define F_2475MHZ 25 4034 #define F_2480MHZ 26 4035 #define CCA_CS_OR_ED 0 4036 #define CCA_ED 1 4037 #define CCA_CS 2 4038 #define CCA_CS_AND_ED 3 4039 4040 #endif /* __ASSEMBLER__ */ 4041 4042 /* PHY_CC_CCA */ 4043 4044 #define CHANNEL0 0 4045 #define CHANNEL1 1 4046 #define CHANNEL2 2 4047 #define CHANNEL3 3 4048 #define CHANNEL4 4 4049 #define CCA_MODE0 5 4050 #define CCA_MODE1 6 4051 #define CCA_REQUEST 7 4052 4053 /* Transceiver CCA Threshold Setting Register */ 4054 #define CCA_THRES _SFR_MEM8(0x149) 4055 4056 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4057 4058 struct __reg_CCA_THRES { 4059 unsigned int cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */ 4060 unsigned int cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */ 4061 }; 4062 4063 #define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES) 4064 4065 #endif /* __ASSEMBLER__ */ 4066 4067 /* CCA_THRES */ 4068 4069 #define CCA_ED_THRES0 0 4070 #define CCA_ED_THRES1 1 4071 #define CCA_ED_THRES2 2 4072 #define CCA_ED_THRES3 3 4073 #define CCA_CS_THRES0 4 4074 #define CCA_CS_THRES1 5 4075 #define CCA_CS_THRES2 6 4076 #define CCA_CS_THRES3 7 4077 4078 /* Transceiver Receive Control Register */ 4079 #define RX_CTRL _SFR_MEM8(0x14A) 4080 4081 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4082 4083 struct __reg_RX_CTRL { 4084 unsigned int pdt_thres : 4; /* Receiver Sensitivity Control */ 4085 unsigned int : 4; 4086 }; 4087 4088 #define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL) 4089 4090 /* symbolic names */ 4091 4092 #define PDT_THRES_ANT_DIV_OFF 7 4093 #define PDT_THRES_ANT_DIV_ON 3 4094 4095 #endif /* __ASSEMBLER__ */ 4096 4097 /* RX_CTRL */ 4098 4099 #define PDT_THRES0 0 4100 #define PDT_THRES1 1 4101 #define PDT_THRES2 2 4102 #define PDT_THRES3 3 4103 4104 /* Start of Frame Delimiter Value Register */ 4105 #define SFD_VALUE _SFR_MEM8(0x14B) 4106 4107 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4108 4109 struct __reg_SFD_VALUE { 4110 unsigned int sfd_value : 8; /* Start of Frame Delimiter Value */ 4111 }; 4112 4113 #define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE) 4114 4115 /* symbolic names */ 4116 4117 #define IEEE_SFD 167 4118 4119 #endif /* __ASSEMBLER__ */ 4120 4121 /* SFD_VALUE */ 4122 4123 #define SFD_VALUE0 0 4124 #define SFD_VALUE1 1 4125 #define SFD_VALUE2 2 4126 #define SFD_VALUE3 3 4127 #define SFD_VALUE4 4 4128 #define SFD_VALUE5 5 4129 #define SFD_VALUE6 6 4130 #define SFD_VALUE7 7 4131 4132 /* Transceiver Control Register 2 */ 4133 #define TRX_CTRL_2 _SFR_MEM8(0x14C) 4134 4135 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4136 4137 struct __reg_TRX_CTRL_2 { 4138 unsigned int oqpsk_data_rate : 2; /* Data Rate Selection */ 4139 unsigned int : 5; 4140 unsigned int rx_safe_mode : 1; /* RX Safe Mode */ 4141 }; 4142 4143 #define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2) 4144 4145 /* symbolic names */ 4146 4147 #define RATE_250KB 0 4148 #define RATE_500KB 1 4149 #define RATE_1000KB 2 4150 #define RATE_2000KB 3 4151 4152 #endif /* __ASSEMBLER__ */ 4153 4154 /* TRX_CTRL_2 */ 4155 4156 #define OQPSK_DATA_RATE0 0 4157 #define OQPSK_DATA_RATE1 1 4158 #define RX_SAFE_MODE 7 4159 4160 /* Antenna Diversity Control Register */ 4161 #define ANT_DIV _SFR_MEM8(0x14D) 4162 4163 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4164 4165 struct __reg_ANT_DIV { 4166 unsigned int ant_ctrl : 2; /* Static Antenna Diversity Switch Control */ 4167 unsigned int ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */ 4168 unsigned int ant_div_en : 1; /* Enable Antenna Diversity */ 4169 unsigned int : 3; 4170 unsigned int ant_sel : 1; /* Antenna Diversity Antenna Status */ 4171 }; 4172 4173 #define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV) 4174 4175 /* symbolic names */ 4176 4177 #define ANT_1 1 4178 #define ANT_0 2 4179 #define ANT_RESET 3 4180 #define ANT_DIV_EXT_SW_DIS 0 4181 #define ANT_DIV_EXT_SW_EN 1 4182 #define ANTENNA_0 0 4183 #define ANTENNA_1 1 4184 4185 #endif /* __ASSEMBLER__ */ 4186 4187 /* ANT_DIV */ 4188 4189 #define ANT_CTRL0 0 4190 #define ANT_CTRL1 1 4191 #define ANT_EXT_SW_EN 2 4192 #define ANT_DIV_EN 3 4193 #define ANT_SEL 7 4194 4195 /* Transceiver Interrupt Enable Register */ 4196 #define IRQ_MASK _SFR_MEM8(0x14E) 4197 4198 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4199 4200 struct __reg_IRQ_MASK { 4201 unsigned int pll_lock_en : 1; /* PLL Lock Interrupt Enable */ 4202 unsigned int pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */ 4203 unsigned int rx_start_en : 1; /* RX_START Interrupt Enable */ 4204 unsigned int rx_end_en : 1; /* RX_END Interrupt Enable */ 4205 unsigned int cca_ed_done_en : 1; /* End of ED Measurement Interrupt Enable */ 4206 unsigned int ami_en : 1; /* Address Match Interrupt Enable */ 4207 unsigned int tx_end_en : 1; /* TX_END Interrupt Enable */ 4208 unsigned int awake_en : 1; /* Awake Interrupt Enable */ 4209 }; 4210 4211 #define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK) 4212 4213 #endif /* __ASSEMBLER__ */ 4214 4215 /* IRQ_MASK */ 4216 4217 #define PLL_LOCK_EN 0 4218 #define PLL_UNLOCK_EN 1 4219 #define RX_START_EN 2 4220 #define RX_END_EN 3 4221 #define CCA_ED_DONE_EN 4 4222 #define AMI_EN 5 4223 #define TX_END_EN 6 4224 #define AWAKE_EN 7 4225 4226 /* Transceiver Interrupt Status Register */ 4227 #define IRQ_STATUS _SFR_MEM8(0x14F) 4228 4229 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4230 4231 struct __reg_IRQ_STATUS { 4232 unsigned int pll_lock : 1; /* PLL Lock Interrupt Status */ 4233 unsigned int pll_unlock : 1; /* PLL Unlock Interrupt Status */ 4234 unsigned int rx_start : 1; /* RX_START Interrupt Status */ 4235 unsigned int rx_end : 1; /* RX_END Interrupt Status */ 4236 unsigned int cca_ed_done : 1; /* End of ED Measurement Interrupt Status */ 4237 unsigned int ami : 1; /* Address Match Interrupt Status */ 4238 unsigned int tx_end : 1; /* TX_END Interrupt Status */ 4239 unsigned int awake : 1; /* Awake Interrupt Status */ 4240 }; 4241 4242 #define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS) 4243 4244 #endif /* __ASSEMBLER__ */ 4245 4246 /* IRQ_STATUS */ 4247 4248 #define PLL_LOCK 0 4249 #define PLL_UNLOCK 1 4250 #define RX_START 2 4251 #define RX_END 3 4252 #define CCA_ED_DONE 4 4253 #define AMI 5 4254 #define TX_END 6 4255 #define AWAKE 7 4256 4257 /* Voltage Regulator Control and Status Register */ 4258 #define VREG_CTRL _SFR_MEM8(0x150) 4259 4260 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4261 4262 struct __reg_VREG_CTRL { 4263 unsigned int : 2; 4264 unsigned int dvdd_ok : 1; /* DVDD Supply Voltage Valid */ 4265 unsigned int dvreg_ext : 1; /* Use External DVDD Regulator */ 4266 unsigned int : 2; 4267 unsigned int avdd_ok : 1; /* AVDD Supply Voltage Valid */ 4268 unsigned int avreg_ext : 1; /* Use External AVDD Regulator */ 4269 }; 4270 4271 #define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL) 4272 4273 /* symbolic names */ 4274 4275 #define DVDD_INT 0 4276 #define DVDD_EXT 1 4277 #define AVDD_INT 0 4278 #define AVDD_EXT 1 4279 4280 #endif /* __ASSEMBLER__ */ 4281 4282 /* VREG_CTRL */ 4283 4284 #define DVDD_OK 2 4285 #define DVREG_EXT 3 4286 #define AVDD_OK 6 4287 #define AVREG_EXT 7 4288 4289 /* Battery Monitor Control and Status Register */ 4290 #define BATMON _SFR_MEM8(0x151) 4291 4292 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4293 4294 struct __reg_BATMON { 4295 unsigned int batmon_vth : 4; /* Battery Monitor Threshold Voltage */ 4296 unsigned int batmon_hr : 1; /* Battery Monitor Voltage Range */ 4297 unsigned int batmon_ok : 1; /* Battery Monitor Status */ 4298 unsigned int bat_low_en : 1; /* Battery Monitor Interrupt Enable */ 4299 unsigned int bat_low : 1; /* Battery Monitor Interrupt Status */ 4300 }; 4301 4302 #define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON) 4303 4304 /* symbolic names */ 4305 4306 #define BATMON_HR_DIS 0 4307 #define BATMON_HR_EN 1 4308 4309 #endif /* __ASSEMBLER__ */ 4310 4311 /* BATMON */ 4312 4313 #define BATMON_VTH0 0 4314 #define BATMON_VTH1 1 4315 #define BATMON_VTH2 2 4316 #define BATMON_VTH3 3 4317 #define BATMON_HR 4 4318 #define BATMON_OK 5 4319 #define BAT_LOW_EN 6 4320 #define BAT_LOW 7 4321 4322 /* Crystal Oscillator Control Register */ 4323 #define XOSC_CTRL _SFR_MEM8(0x152) 4324 4325 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4326 4327 struct __reg_XOSC_CTRL { 4328 unsigned int xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */ 4329 unsigned int xtal_mode : 4; /* Crystal Oscillator Operating Mode */ 4330 }; 4331 4332 #define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL) 4333 4334 /* symbolic names */ 4335 4336 #define XTAL_TRIM_MIN 0 4337 #define XTAL_TRIM_MAX 15 4338 4339 #endif /* __ASSEMBLER__ */ 4340 4341 /* XOSC_CTRL */ 4342 4343 #define XTAL_TRIM0 0 4344 #define XTAL_TRIM1 1 4345 #define XTAL_TRIM2 2 4346 #define XTAL_TRIM3 3 4347 #define XTAL_MODE0 4 4348 #define XTAL_MODE1 5 4349 #define XTAL_MODE2 6 4350 #define XTAL_MODE3 7 4351 4352 /* Transceiver Receiver Sensitivity Control Register */ 4353 #define RX_SYN _SFR_MEM8(0x155) 4354 4355 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4356 4357 struct __reg_RX_SYN { 4358 unsigned int rx_pdt_level : 4; /* Reduce Receiver Sensitivity */ 4359 unsigned int : 3; 4360 unsigned int rx_pdt_dis : 1; /* Prevent Frame Reception */ 4361 }; 4362 4363 #define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN) 4364 4365 /* symbolic names */ 4366 4367 #define RX_PDT_LEVEL_MIN 0 4368 #define RX_PDT_LEVEL_MAX 15 4369 4370 #endif /* __ASSEMBLER__ */ 4371 4372 /* RX_SYN */ 4373 4374 #define RX_PDT_LEVEL0 0 4375 #define RX_PDT_LEVEL1 1 4376 #define RX_PDT_LEVEL2 2 4377 #define RX_PDT_LEVEL3 3 4378 #define RX_PDT_DIS 7 4379 4380 /* Transceiver Acknowledgment Frame Control Register 1 */ 4381 #define XAH_CTRL_1 _SFR_MEM8(0x157) 4382 4383 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4384 4385 struct __reg_XAH_CTRL_1 { 4386 unsigned int : 1; 4387 unsigned int aack_prom_mode : 1; /* Enable Promiscuous Mode */ 4388 unsigned int aack_ack_time : 1; /* Reduce Acknowledgment Time */ 4389 unsigned int : 1; 4390 unsigned int aack_upld_res_ft : 1; /* Process Reserved Frames */ 4391 unsigned int aack_fltr_res_ft : 1; /* Filter Reserved Frames */ 4392 unsigned int : 2; 4393 }; 4394 4395 #define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1) 4396 4397 /* symbolic names */ 4398 4399 #define AACK_ACK_TIME_12_SYM 0 4400 #define AACK_ACK_TIME_2_SYM 1 4401 4402 #endif /* __ASSEMBLER__ */ 4403 4404 /* XAH_CTRL_1 */ 4405 4406 #define AACK_PROM_MODE 1 4407 #define AACK_ACK_TIME 2 4408 #define AACK_UPLD_RES_FT 4 4409 #define AACK_FLTR_RES_FT 5 4410 4411 /* Transceiver Filter Tuning Control Register */ 4412 #define FTN_CTRL _SFR_MEM8(0x158) 4413 4414 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4415 4416 struct __reg_FTN_CTRL { 4417 unsigned int : 7; 4418 unsigned int ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */ 4419 }; 4420 4421 #define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL) 4422 4423 #endif /* __ASSEMBLER__ */ 4424 4425 /* FTN_CTRL */ 4426 4427 #define FTN_START 7 4428 4429 /* Transceiver Center Frequency Calibration Control Register */ 4430 #define PLL_CF _SFR_MEM8(0x15A) 4431 4432 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4433 4434 struct __reg_PLL_CF { 4435 unsigned int : 7; 4436 unsigned int pll_cf_start : 1; /* Start Center Frequency Calibration */ 4437 }; 4438 4439 #define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF) 4440 4441 #endif /* __ASSEMBLER__ */ 4442 4443 /* PLL_CF */ 4444 4445 #define PLL_CF_START 7 4446 4447 /* Transceiver Delay Cell Calibration Control Register */ 4448 #define PLL_DCU _SFR_MEM8(0x15B) 4449 4450 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4451 4452 struct __reg_PLL_DCU { 4453 unsigned int : 7; 4454 unsigned int pll_dcu_start : 1; /* Start Delay Cell Calibration */ 4455 }; 4456 4457 #define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU) 4458 4459 #endif /* __ASSEMBLER__ */ 4460 4461 /* PLL_DCU */ 4462 4463 #define PLL_DCU_START 7 4464 4465 /* Device Identification Register (Part Number) */ 4466 #define PART_NUM _SFR_MEM8(0x15C) 4467 4468 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4469 4470 struct __reg_PART_NUM { 4471 unsigned int part_num : 8; /* Part Number */ 4472 }; 4473 4474 #define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM) 4475 4476 /* symbolic names */ 4477 4478 #define P_ATmega128RFA1 131 4479 4480 #endif /* __ASSEMBLER__ */ 4481 4482 /* PART_NUM */ 4483 4484 #define PART_NUM0 0 4485 #define PART_NUM1 1 4486 #define PART_NUM2 2 4487 #define PART_NUM3 3 4488 #define PART_NUM4 4 4489 #define PART_NUM5 5 4490 #define PART_NUM6 6 4491 #define PART_NUM7 7 4492 4493 /* Device Identification Register (Version Number) */ 4494 #define VERSION_NUM _SFR_MEM8(0x15D) 4495 4496 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4497 4498 struct __reg_VERSION_NUM { 4499 unsigned int version_num : 8; /* Version Number */ 4500 }; 4501 4502 #define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM) 4503 4504 /* symbolic names */ 4505 4506 #define REV_A 2 4507 #define REV_B 3 4508 4509 #endif /* __ASSEMBLER__ */ 4510 4511 /* VERSION_NUM */ 4512 4513 #define VERSION_NUM0 0 4514 #define VERSION_NUM1 1 4515 #define VERSION_NUM2 2 4516 #define VERSION_NUM3 3 4517 #define VERSION_NUM4 4 4518 #define VERSION_NUM5 5 4519 #define VERSION_NUM6 6 4520 #define VERSION_NUM7 7 4521 4522 /* Device Identification Register (Manufacture ID Low Byte) */ 4523 #define MAN_ID_0 _SFR_MEM8(0x15E) 4524 4525 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4526 4527 struct __reg_MAN_ID_0 { 4528 unsigned int man_id_0 : 8; /* Manufacturer ID (Low Byte) */ 4529 }; 4530 4531 #define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0) 4532 4533 /* symbolic names */ 4534 4535 #define ATMEL_BYTE_0 31 4536 4537 #endif /* __ASSEMBLER__ */ 4538 4539 /* MAN_ID_0 */ 4540 4541 #define MAN_ID_00 0 4542 #define MAN_ID_01 1 4543 #define MAN_ID_02 2 4544 #define MAN_ID_03 3 4545 #define MAN_ID_04 4 4546 #define MAN_ID_05 5 4547 #define MAN_ID_06 6 4548 #define MAN_ID_07 7 4549 4550 /* Device Identification Register (Manufacture ID High Byte) */ 4551 #define MAN_ID_1 _SFR_MEM8(0x15F) 4552 4553 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4554 4555 struct __reg_MAN_ID_1 { 4556 unsigned int man_id_1 : 8; /* Manufacturer ID (High Byte) */ 4557 }; 4558 4559 #define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1) 4560 4561 /* symbolic names */ 4562 4563 #define ATMEL_BYTE_1 0 4564 4565 #endif /* __ASSEMBLER__ */ 4566 4567 /* MAN_ID_1 */ 4568 4569 #define MAN_ID_10 0 4570 #define MAN_ID_11 1 4571 #define MAN_ID_12 2 4572 #define MAN_ID_13 3 4573 #define MAN_ID_14 4 4574 #define MAN_ID_15 5 4575 #define MAN_ID_16 6 4576 #define MAN_ID_17 7 4577 4578 /* Transceiver MAC Short Address Register (Low Byte) */ 4579 #define SHORT_ADDR_0 _SFR_MEM8(0x160) 4580 4581 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4582 4583 struct __reg_SHORT_ADDR_0 { 4584 unsigned int short_addr_0 : 8; /* MAC Short Address */ 4585 }; 4586 4587 #define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0) 4588 4589 #endif /* __ASSEMBLER__ */ 4590 4591 /* SHORT_ADDR_0 */ 4592 4593 #define SHORT_ADDR_00 0 4594 #define SHORT_ADDR_01 1 4595 #define SHORT_ADDR_02 2 4596 #define SHORT_ADDR_03 3 4597 #define SHORT_ADDR_04 4 4598 #define SHORT_ADDR_05 5 4599 #define SHORT_ADDR_06 6 4600 #define SHORT_ADDR_07 7 4601 4602 /* Transceiver MAC Short Address Register (High Byte) */ 4603 #define SHORT_ADDR_1 _SFR_MEM8(0x161) 4604 4605 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4606 4607 struct __reg_SHORT_ADDR_1 { 4608 unsigned int short_addr_1 : 8; /* MAC Short Address */ 4609 }; 4610 4611 #define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1) 4612 4613 #endif /* __ASSEMBLER__ */ 4614 4615 /* SHORT_ADDR_1 */ 4616 4617 #define SHORT_ADDR_10 0 4618 #define SHORT_ADDR_11 1 4619 #define SHORT_ADDR_12 2 4620 #define SHORT_ADDR_13 3 4621 #define SHORT_ADDR_14 4 4622 #define SHORT_ADDR_15 5 4623 #define SHORT_ADDR_16 6 4624 #define SHORT_ADDR_17 7 4625 4626 /* Transceiver Personal Area Network ID Register (Low Byte) */ 4627 #define PAN_ID_0 _SFR_MEM8(0x162) 4628 4629 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4630 4631 struct __reg_PAN_ID_0 { 4632 unsigned int pan_id_0 : 8; /* MAC Personal Area Network ID */ 4633 }; 4634 4635 #define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0) 4636 4637 #endif /* __ASSEMBLER__ */ 4638 4639 /* PAN_ID_0 */ 4640 4641 #define PAN_ID_00 0 4642 #define PAN_ID_01 1 4643 #define PAN_ID_02 2 4644 #define PAN_ID_03 3 4645 #define PAN_ID_04 4 4646 #define PAN_ID_05 5 4647 #define PAN_ID_06 6 4648 #define PAN_ID_07 7 4649 4650 /* Transceiver Personal Area Network ID Register (High Byte) */ 4651 #define PAN_ID_1 _SFR_MEM8(0x163) 4652 4653 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4654 4655 struct __reg_PAN_ID_1 { 4656 unsigned int pan_id_1 : 8; /* MAC Personal Area Network ID */ 4657 }; 4658 4659 #define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1) 4660 4661 #endif /* __ASSEMBLER__ */ 4662 4663 /* PAN_ID_1 */ 4664 4665 #define PAN_ID_10 0 4666 #define PAN_ID_11 1 4667 #define PAN_ID_12 2 4668 #define PAN_ID_13 3 4669 #define PAN_ID_14 4 4670 #define PAN_ID_15 5 4671 #define PAN_ID_16 6 4672 #define PAN_ID_17 7 4673 4674 /* Transceiver MAC IEEE Address Register 0 */ 4675 #define IEEE_ADDR_0 _SFR_MEM8(0x164) 4676 4677 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4678 4679 struct __reg_IEEE_ADDR_0 { 4680 unsigned int ieee_addr_0 : 8; /* MAC IEEE Address */ 4681 }; 4682 4683 #define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0) 4684 4685 #endif /* __ASSEMBLER__ */ 4686 4687 /* IEEE_ADDR_0 */ 4688 4689 #define IEEE_ADDR_00 0 4690 #define IEEE_ADDR_01 1 4691 #define IEEE_ADDR_02 2 4692 #define IEEE_ADDR_03 3 4693 #define IEEE_ADDR_04 4 4694 #define IEEE_ADDR_05 5 4695 #define IEEE_ADDR_06 6 4696 #define IEEE_ADDR_07 7 4697 4698 /* Transceiver MAC IEEE Address Register 1 */ 4699 #define IEEE_ADDR_1 _SFR_MEM8(0x165) 4700 4701 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4702 4703 struct __reg_IEEE_ADDR_1 { 4704 unsigned int ieee_addr_1 : 8; /* MAC IEEE Address */ 4705 }; 4706 4707 #define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1) 4708 4709 #endif /* __ASSEMBLER__ */ 4710 4711 /* IEEE_ADDR_1 */ 4712 4713 #define IEEE_ADDR_10 0 4714 #define IEEE_ADDR_11 1 4715 #define IEEE_ADDR_12 2 4716 #define IEEE_ADDR_13 3 4717 #define IEEE_ADDR_14 4 4718 #define IEEE_ADDR_15 5 4719 #define IEEE_ADDR_16 6 4720 #define IEEE_ADDR_17 7 4721 4722 /* Transceiver MAC IEEE Address Register 2 */ 4723 #define IEEE_ADDR_2 _SFR_MEM8(0x166) 4724 4725 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4726 4727 struct __reg_IEEE_ADDR_2 { 4728 unsigned int ieee_addr_2 : 8; /* MAC IEEE Address */ 4729 }; 4730 4731 #define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2) 4732 4733 #endif /* __ASSEMBLER__ */ 4734 4735 /* IEEE_ADDR_2 */ 4736 4737 #define IEEE_ADDR_20 0 4738 #define IEEE_ADDR_21 1 4739 #define IEEE_ADDR_22 2 4740 #define IEEE_ADDR_23 3 4741 #define IEEE_ADDR_24 4 4742 #define IEEE_ADDR_25 5 4743 #define IEEE_ADDR_26 6 4744 #define IEEE_ADDR_27 7 4745 4746 /* Transceiver MAC IEEE Address Register 3 */ 4747 #define IEEE_ADDR_3 _SFR_MEM8(0x167) 4748 4749 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4750 4751 struct __reg_IEEE_ADDR_3 { 4752 unsigned int ieee_addr_3 : 8; /* MAC IEEE Address */ 4753 }; 4754 4755 #define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3) 4756 4757 #endif /* __ASSEMBLER__ */ 4758 4759 /* IEEE_ADDR_3 */ 4760 4761 #define IEEE_ADDR_30 0 4762 #define IEEE_ADDR_31 1 4763 #define IEEE_ADDR_32 2 4764 #define IEEE_ADDR_33 3 4765 #define IEEE_ADDR_34 4 4766 #define IEEE_ADDR_35 5 4767 #define IEEE_ADDR_36 6 4768 #define IEEE_ADDR_37 7 4769 4770 /* Transceiver MAC IEEE Address Register 4 */ 4771 #define IEEE_ADDR_4 _SFR_MEM8(0x168) 4772 4773 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4774 4775 struct __reg_IEEE_ADDR_4 { 4776 unsigned int ieee_addr_4 : 8; /* MAC IEEE Address */ 4777 }; 4778 4779 #define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4) 4780 4781 #endif /* __ASSEMBLER__ */ 4782 4783 /* IEEE_ADDR_4 */ 4784 4785 #define IEEE_ADDR_40 0 4786 #define IEEE_ADDR_41 1 4787 #define IEEE_ADDR_42 2 4788 #define IEEE_ADDR_43 3 4789 #define IEEE_ADDR_44 4 4790 #define IEEE_ADDR_45 5 4791 #define IEEE_ADDR_46 6 4792 #define IEEE_ADDR_47 7 4793 4794 /* Transceiver MAC IEEE Address Register 5 */ 4795 #define IEEE_ADDR_5 _SFR_MEM8(0x169) 4796 4797 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4798 4799 struct __reg_IEEE_ADDR_5 { 4800 unsigned int ieee_addr_5 : 8; /* MAC IEEE Address */ 4801 }; 4802 4803 #define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5) 4804 4805 #endif /* __ASSEMBLER__ */ 4806 4807 /* IEEE_ADDR_5 */ 4808 4809 #define IEEE_ADDR_50 0 4810 #define IEEE_ADDR_51 1 4811 #define IEEE_ADDR_52 2 4812 #define IEEE_ADDR_53 3 4813 #define IEEE_ADDR_54 4 4814 #define IEEE_ADDR_55 5 4815 #define IEEE_ADDR_56 6 4816 #define IEEE_ADDR_57 7 4817 4818 /* Transceiver MAC IEEE Address Register 6 */ 4819 #define IEEE_ADDR_6 _SFR_MEM8(0x16A) 4820 4821 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4822 4823 struct __reg_IEEE_ADDR_6 { 4824 unsigned int ieee_addr_6 : 8; /* MAC IEEE Address */ 4825 }; 4826 4827 #define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6) 4828 4829 #endif /* __ASSEMBLER__ */ 4830 4831 /* IEEE_ADDR_6 */ 4832 4833 #define IEEE_ADDR_60 0 4834 #define IEEE_ADDR_61 1 4835 #define IEEE_ADDR_62 2 4836 #define IEEE_ADDR_63 3 4837 #define IEEE_ADDR_64 4 4838 #define IEEE_ADDR_65 5 4839 #define IEEE_ADDR_66 6 4840 #define IEEE_ADDR_67 7 4841 4842 /* Transceiver MAC IEEE Address Register 7 */ 4843 #define IEEE_ADDR_7 _SFR_MEM8(0x16B) 4844 4845 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4846 4847 struct __reg_IEEE_ADDR_7 { 4848 unsigned int ieee_addr_7 : 8; /* MAC IEEE Address */ 4849 }; 4850 4851 #define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7) 4852 4853 #endif /* __ASSEMBLER__ */ 4854 4855 /* IEEE_ADDR_7 */ 4856 4857 #define IEEE_ADDR_70 0 4858 #define IEEE_ADDR_71 1 4859 #define IEEE_ADDR_72 2 4860 #define IEEE_ADDR_73 3 4861 #define IEEE_ADDR_74 4 4862 #define IEEE_ADDR_75 5 4863 #define IEEE_ADDR_76 6 4864 #define IEEE_ADDR_77 7 4865 4866 /* Transceiver Extended Operating Mode Control Register */ 4867 #define XAH_CTRL_0 _SFR_MEM8(0x16C) 4868 4869 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4870 4871 struct __reg_XAH_CTRL_0 { 4872 unsigned int slotted_operation : 1; /* Set Slotted Acknowledgment */ 4873 unsigned int max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */ 4874 unsigned int max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */ 4875 }; 4876 4877 #define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0) 4878 4879 /* symbolic names */ 4880 4881 #define SLOTTED_OP_DIS 0 4882 #define SLOTTED_OP_EN 1 4883 4884 #endif /* __ASSEMBLER__ */ 4885 4886 /* XAH_CTRL_0 */ 4887 4888 #define SLOTTED_OPERATION 0 4889 #define MAX_CSMA_RETRIES0 1 4890 #define MAX_CSMA_RETRIES1 2 4891 #define MAX_CSMA_RETRIES2 3 4892 #define MAX_FRAME_RETRIES0 4 4893 #define MAX_FRAME_RETRIES1 5 4894 #define MAX_FRAME_RETRIES2 6 4895 #define MAX_FRAME_RETRIES3 7 4896 4897 /* Transceiver CSMA-CA Random Number Generator Seed Register */ 4898 #define CSMA_SEED_0 _SFR_MEM8(0x16D) 4899 4900 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4901 4902 struct __reg_CSMA_SEED_0 { 4903 unsigned int csma_seed_0 : 8; /* Seed Value for CSMA Random Number Generator */ 4904 }; 4905 4906 #define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0) 4907 4908 #endif /* __ASSEMBLER__ */ 4909 4910 /* CSMA_SEED_0 */ 4911 4912 #define CSMA_SEED_00 0 4913 #define CSMA_SEED_01 1 4914 #define CSMA_SEED_02 2 4915 #define CSMA_SEED_03 3 4916 #define CSMA_SEED_04 4 4917 #define CSMA_SEED_05 5 4918 #define CSMA_SEED_06 6 4919 #define CSMA_SEED_07 7 4920 4921 /* Transceiver Acknowledgment Frame Control Register 2 */ 4922 #define CSMA_SEED_1 _SFR_MEM8(0x16E) 4923 4924 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4925 4926 struct __reg_CSMA_SEED_1 { 4927 unsigned int csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */ 4928 unsigned int aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */ 4929 unsigned int aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */ 4930 unsigned int aack_set_pd : 1; /* Set Frame Pending Sub-field */ 4931 unsigned int aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */ 4932 }; 4933 4934 #define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1) 4935 4936 #endif /* __ASSEMBLER__ */ 4937 4938 /* CSMA_SEED_1 */ 4939 4940 #define CSMA_SEED_10 0 4941 #define CSMA_SEED_11 1 4942 #define CSMA_SEED_12 2 4943 #define AACK_I_AM_COORD 3 4944 #define AACK_DIS_ACK 4 4945 #define AACK_SET_PD 5 4946 #define AACK_FVN_MODE0 6 4947 #define AACK_FVN_MODE1 7 4948 4949 /* Transceiver CSMA-CA Back-off Exponent Control Register */ 4950 #define CSMA_BE _SFR_MEM8(0x16F) 4951 4952 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4953 4954 struct __reg_CSMA_BE { 4955 unsigned int min_be : 4; /* Minimum Back-off Exponent */ 4956 unsigned int max_be : 4; /* Maximum Back-off Exponent */ 4957 }; 4958 4959 #define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE) 4960 4961 #endif /* __ASSEMBLER__ */ 4962 4963 /* CSMA_BE */ 4964 4965 #define MIN_BE0 0 4966 #define MIN_BE1 1 4967 #define MIN_BE2 2 4968 #define MIN_BE3 3 4969 #define MAX_BE0 4 4970 #define MAX_BE1 5 4971 #define MAX_BE2 6 4972 #define MAX_BE3 7 4973 4974 /* Transceiver Digital Test Control Register */ 4975 #define TST_CTRL_DIGI _SFR_MEM8(0x176) 4976 4977 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4978 4979 struct __reg_TST_CTRL_DIGI { 4980 unsigned int tst_ctrl_dig : 4; /* Digital Test Controller Register */ 4981 unsigned int : 4; 4982 }; 4983 4984 #define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI) 4985 4986 #endif /* __ASSEMBLER__ */ 4987 4988 /* TST_CTRL_DIGI */ 4989 4990 #define TST_CTRL_DIG0 0 4991 #define TST_CTRL_DIG1 1 4992 #define TST_CTRL_DIG2 2 4993 #define TST_CTRL_DIG3 3 4994 4995 /* Transceiver Received Frame Length Register */ 4996 #define TST_RX_LENGTH _SFR_MEM8(0x17B) 4997 4998 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4999 5000 struct __reg_TST_RX_LENGTH { 5001 unsigned int rx_length : 8; /* Received Frame Length */ 5002 }; 5003 5004 #define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH) 5005 5006 #endif /* __ASSEMBLER__ */ 5007 5008 /* TST_RX_LENGTH */ 5009 5010 #define RX_LENGTH0 0 5011 #define RX_LENGTH1 1 5012 #define RX_LENGTH2 2 5013 #define RX_LENGTH3 3 5014 #define RX_LENGTH4 4 5015 #define RX_LENGTH5 5 5016 #define RX_LENGTH6 6 5017 #define RX_LENGTH7 7 5018 5019 /* Start of frame buffer */ 5020 #define TRXFBST _SFR_MEM8(0x180) 5021 5022 /* TRXFBST */ 5023 5024 #define TRXFBST0 0 5025 #define TRXFBST1 1 5026 #define TRXFBST2 2 5027 #define TRXFBST3 3 5028 #define TRXFBST4 4 5029 #define TRXFBST5 5 5030 #define TRXFBST6 6 5031 #define TRXFBST7 7 5032 5033 /* End of frame buffer */ 5034 #define TRXFBEND _SFR_MEM8(0x1FF) 5035 5036 /* TRXFBEND */ 5037 5038 #define TRXFBEND0 0 5039 #define TRXFBEND1 1 5040 #define TRXFBEND2 2 5041 #define TRXFBEND3 3 5042 #define TRXFBEND4 4 5043 #define TRXFBEND5 5 5044 #define TRXFBEND6 6 5045 #define TRXFBEND7 7 5046 5047 5048 /* Interrupt vectors */ 5049 /* Vector 0 is the reset vector */ 5050 5051 #define _VECTORS_SIZE 288 5052 5053 /* External Interrupt Request 0 */ 5054 #define INT0_vect _VECTOR(1) 5055 #define INT0_vect_num 1 5056 5057 /* External Interrupt Request 1 */ 5058 #define INT1_vect _VECTOR(2) 5059 #define INT1_vect_num 2 5060 5061 /* External Interrupt Request 2 */ 5062 #define INT2_vect _VECTOR(3) 5063 #define INT2_vect_num 3 5064 5065 /* External Interrupt Request 3 */ 5066 #define INT3_vect _VECTOR(4) 5067 #define INT3_vect_num 4 5068 5069 /* External Interrupt Request 4 */ 5070 #define INT4_vect _VECTOR(5) 5071 #define INT4_vect_num 5 5072 5073 /* External Interrupt Request 5 */ 5074 #define INT5_vect _VECTOR(6) 5075 #define INT5_vect_num 6 5076 5077 /* External Interrupt Request 6 */ 5078 #define INT6_vect _VECTOR(7) 5079 #define INT6_vect_num 7 5080 5081 /* External Interrupt Request 7 */ 5082 #define INT7_vect _VECTOR(8) 5083 #define INT7_vect_num 8 5084 5085 /* Pin Change Interrupt Request 0 */ 5086 #define PCINT0_vect _VECTOR(9) 5087 #define PCINT0_vect_num 9 5088 5089 /* Pin Change Interrupt Request 1 */ 5090 #define PCINT1_vect _VECTOR(10) 5091 #define PCINT1_vect_num 10 5092 5093 /* Pin Change Interrupt Request 2 */ 5094 #define PCINT2_vect _VECTOR(11) 5095 #define PCINT2_vect_num 11 5096 5097 /* Watchdog Time-out Interrupt */ 5098 #define WDT_vect _VECTOR(12) 5099 #define WDT_vect_num 12 5100 5101 /* Timer/Counter2 Compare Match A */ 5102 #define TIMER2_COMPA_vect _VECTOR(13) 5103 #define TIMER2_COMPA_vect_num 13 5104 5105 /* Timer/Counter2 Compare Match B */ 5106 #define TIMER2_COMPB_vect _VECTOR(14) 5107 #define TIMER2_COMPB_vect_num 14 5108 5109 /* Timer/Counter2 Overflow */ 5110 #define TIMER2_OVF_vect _VECTOR(15) 5111 #define TIMER2_OVF_vect_num 15 5112 5113 /* Timer/Counter1 Capture Event */ 5114 #define TIMER1_CAPT_vect _VECTOR(16) 5115 #define TIMER1_CAPT_vect_num 16 5116 5117 /* Timer/Counter1 Compare Match A */ 5118 #define TIMER1_COMPA_vect _VECTOR(17) 5119 #define TIMER1_COMPA_vect_num 17 5120 5121 /* Timer/Counter1 Compare Match B */ 5122 #define TIMER1_COMPB_vect _VECTOR(18) 5123 #define TIMER1_COMPB_vect_num 18 5124 5125 /* Timer/Counter1 Compare Match C */ 5126 #define TIMER1_COMPC_vect _VECTOR(19) 5127 #define TIMER1_COMPC_vect_num 19 5128 5129 /* Timer/Counter1 Overflow */ 5130 #define TIMER1_OVF_vect _VECTOR(20) 5131 #define TIMER1_OVF_vect_num 20 5132 5133 /* Timer/Counter0 Compare Match A */ 5134 #define TIMER0_COMPA_vect _VECTOR(21) 5135 #define TIMER0_COMPA_vect_num 21 5136 5137 /* Timer/Counter0 Compare Match B */ 5138 #define TIMER0_COMPB_vect _VECTOR(22) 5139 #define TIMER0_COMPB_vect_num 22 5140 5141 /* Timer/Counter0 Overflow */ 5142 #define TIMER0_OVF_vect _VECTOR(23) 5143 #define TIMER0_OVF_vect_num 23 5144 5145 /* SPI Serial Transfer Complete */ 5146 #define SPI_STC_vect _VECTOR(24) 5147 #define SPI_STC_vect_num 24 5148 5149 /* USART0, Rx Complete */ 5150 #define USART0_RX_vect _VECTOR(25) 5151 #define USART0_RX_vect_num 25 5152 5153 /* USART0 Data register Empty */ 5154 #define USART0_UDRE_vect _VECTOR(26) 5155 #define USART0_UDRE_vect_num 26 5156 5157 /* USART0, Tx Complete */ 5158 #define USART0_TX_vect _VECTOR(27) 5159 #define USART0_TX_vect_num 27 5160 5161 /* Analog Comparator */ 5162 #define ANALOG_COMP_vect _VECTOR(28) 5163 #define ANALOG_COMP_vect_num 28 5164 5165 /* ADC Conversion Complete */ 5166 #define ADC_vect _VECTOR(29) 5167 #define ADC_vect_num 29 5168 5169 /* EEPROM Ready */ 5170 #define EE_READY_vect _VECTOR(30) 5171 #define EE_READY_vect_num 30 5172 5173 /* Timer/Counter3 Capture Event */ 5174 #define TIMER3_CAPT_vect _VECTOR(31) 5175 #define TIMER3_CAPT_vect_num 31 5176 5177 /* Timer/Counter3 Compare Match A */ 5178 #define TIMER3_COMPA_vect _VECTOR(32) 5179 #define TIMER3_COMPA_vect_num 32 5180 5181 /* Timer/Counter3 Compare Match B */ 5182 #define TIMER3_COMPB_vect _VECTOR(33) 5183 #define TIMER3_COMPB_vect_num 33 5184 5185 /* Timer/Counter3 Compare Match C */ 5186 #define TIMER3_COMPC_vect _VECTOR(34) 5187 #define TIMER3_COMPC_vect_num 34 5188 5189 /* Timer/Counter3 Overflow */ 5190 #define TIMER3_OVF_vect _VECTOR(35) 5191 #define TIMER3_OVF_vect_num 35 5192 5193 /* USART1, Rx Complete */ 5194 #define USART1_RX_vect _VECTOR(36) 5195 #define USART1_RX_vect_num 36 5196 5197 /* USART1 Data register Empty */ 5198 #define USART1_UDRE_vect _VECTOR(37) 5199 #define USART1_UDRE_vect_num 37 5200 5201 /* USART1, Tx Complete */ 5202 #define USART1_TX_vect _VECTOR(38) 5203 #define USART1_TX_vect_num 38 5204 5205 /* 2-wire Serial Interface */ 5206 #define TWI_vect _VECTOR(39) 5207 #define TWI_vect_num 39 5208 5209 /* Store Program Memory Read */ 5210 #define SPM_READY_vect _VECTOR(40) 5211 #define SPM_READY_vect_num 40 5212 5213 /* Timer/Counter4 Capture Event */ 5214 #define TIMER4_CAPT_vect _VECTOR(41) 5215 #define TIMER4_CAPT_vect_num 41 5216 5217 /* Timer/Counter4 Compare Match A */ 5218 #define TIMER4_COMPA_vect _VECTOR(42) 5219 #define TIMER4_COMPA_vect_num 42 5220 5221 /* Timer/Counter4 Compare Match B */ 5222 #define TIMER4_COMPB_vect _VECTOR(43) 5223 #define TIMER4_COMPB_vect_num 43 5224 5225 /* Timer/Counter4 Compare Match C */ 5226 #define TIMER4_COMPC_vect _VECTOR(44) 5227 #define TIMER4_COMPC_vect_num 44 5228 5229 /* Timer/Counter4 Overflow */ 5230 #define TIMER4_OVF_vect _VECTOR(45) 5231 #define TIMER4_OVF_vect_num 45 5232 5233 /* Timer/Counter5 Capture Event */ 5234 #define TIMER5_CAPT_vect _VECTOR(46) 5235 #define TIMER5_CAPT_vect_num 46 5236 5237 /* Timer/Counter5 Compare Match A */ 5238 #define TIMER5_COMPA_vect _VECTOR(47) 5239 #define TIMER5_COMPA_vect_num 47 5240 5241 /* Timer/Counter5 Compare Match B */ 5242 #define TIMER5_COMPB_vect _VECTOR(48) 5243 #define TIMER5_COMPB_vect_num 48 5244 5245 /* Timer/Counter5 Compare Match C */ 5246 #define TIMER5_COMPC_vect _VECTOR(49) 5247 #define TIMER5_COMPC_vect_num 49 5248 5249 /* Timer/Counter5 Overflow */ 5250 #define TIMER5_OVF_vect _VECTOR(50) 5251 #define TIMER5_OVF_vect_num 50 5252 5253 /* Vectors 51 through 56 are reserved (unimplemented UARTs) */ 5254 5255 /* TRX24 - PLL lock interrupt */ 5256 #define TRX24_PLL_LOCK_vect _VECTOR(57) 5257 #define TRX24_PLL_LOCK_vect_num 57 5258 5259 /* TRX24 - PLL unlock interrupt */ 5260 #define TRX24_PLL_UNLOCK_vect _VECTOR(58) 5261 #define TRX24_PLL_UNLOCK_vect_num 58 5262 5263 /* TRX24 - Receive start interrupt */ 5264 #define TRX24_RX_START_vect _VECTOR(59) 5265 #define TRX24_RX_START_vect_num 59 5266 5267 /* TRX24 - RX_END interrupt */ 5268 #define TRX24_RX_END_vect _VECTOR(60) 5269 #define TRX24_RX_END_vect_num 60 5270 5271 /* TRX24 - CCA/ED done interrupt */ 5272 #define TRX24_CCA_ED_DONE_vect _VECTOR(61) 5273 #define TRX24_CCA_ED_DONE_vect_num 61 5274 5275 /* TRX24 - XAH - AMI */ 5276 #define TRX24_XAH_AMI_vect _VECTOR(62) 5277 #define TRX24_XAH_AMI_vect_num 62 5278 5279 /* TRX24 - TX_END interrupt */ 5280 #define TRX24_TX_END_vect _VECTOR(63) 5281 #define TRX24_TX_END_vect_num 63 5282 5283 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ 5284 #define TRX24_AWAKE_vect _VECTOR(64) 5285 #define TRX24_AWAKE_vect_num 64 5286 5287 /* Symbol counter - compare match 1 interrupt */ 5288 #define SCNT_CMP1_vect _VECTOR(65) 5289 #define SCNT_CMP1_vect_num 65 5290 5291 /* Symbol counter - compare match 2 interrupt */ 5292 #define SCNT_CMP2_vect _VECTOR(66) 5293 #define SCNT_CMP2_vect_num 66 5294 5295 /* Symbol counter - compare match 3 interrupt */ 5296 #define SCNT_CMP3_vect _VECTOR(67) 5297 #define SCNT_CMP3_vect_num 67 5298 5299 /* Symbol counter - overflow interrupt */ 5300 #define SCNT_OVFL_vect _VECTOR(68) 5301 #define SCNT_OVFL_vect_num 68 5302 5303 /* Symbol counter - backoff interrupt */ 5304 #define SCNT_BACKOFF_vect _VECTOR(69) 5305 #define SCNT_BACKOFF_vect_num 69 5306 5307 /* AES engine ready interrupt */ 5308 #define AES_READY_vect _VECTOR(70) 5309 #define AES_READY_vect_num 70 5310 5311 /* Battery monitor indicates supply voltage below threshold */ 5312 #define BAT_LOW_vect _VECTOR(71) 5313 #define BAT_LOW_vect_num 71 5314 5315 5316 /* memory parameters */ 5317 5318 #define SPM_PAGESIZE (256) 5319 #define RAMSTART (0x200) 5320 #define RAMSIZE (0x4000) 5321 #define RAMEND (0x41FF) 5322 #define XRAMSTART (0x0000) 5323 #define XRAMSIZE (0x0000) 5324 #define XRAMEND RAMEND 5325 #define E2END (0xFFF) 5326 #define E2PAGESIZE (0x08) 5327 #define FLASHEND (0x1ffff) 5328 5329 5330 /* Fuses */ 5331 5332 #define FUSE_MEMORY_SIZE 3 5333 5334 /* LFUSE Byte */ 5335 #define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */ 5336 #define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */ 5337 #define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */ 5338 #define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */ 5339 #define FUSE_SUT0 ~_BV(4) /* Select start-up time */ 5340 #define FUSE_SUT1 ~_BV(5) /* Select start-up time */ 5341 #define FUSE_CKOUT ~_BV(6) /* Clock output */ 5342 #define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ 5343 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) 5344 5345 /* HFUSE Byte */ 5346 #define FUSE_BOOTRST ~_BV(0) /* Select Reset Vector */ 5347 #define FUSE_BOOTSZ0 ~_BV(1) /* Select Boot Size */ 5348 #define FUSE_BOOTSZ1 ~_BV(2) /* Select Boot Size */ 5349 #define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ 5350 #define FUSE_WDTON ~_BV(4) /* Watchdog timer always on */ 5351 #define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ 5352 #define FUSE_JTAGEN ~_BV(6) /* Enable JTAG */ 5353 #define FUSE_OCDEN ~_BV(7) /* Enable OCD */ 5354 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) 5355 5356 /* EFUSE Byte */ 5357 #define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */ 5358 #define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */ 5359 #define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector trigger level */ 5360 #define EFUSE_DEFAULT (0xFF) 5361 5362 5363 5364 /* Lock Bits */ 5365 5366 #define __BOOT_LOCK_BITS_0_EXIST 5367 #define __BOOT_LOCK_BITS_1_EXIST 5368 #define __LOCK_BITS_EXIST 5369 5370 5371 /* Signature */ 5372 5373 #define SIGNATURE_0 0x1E 5374 #define SIGNATURE_1 0xA7 5375 #define SIGNATURE_2 0x01 5376 5377 #define SLEEP_MODE_IDLE (0x00<<1) 5378 #define SLEEP_MODE_ADC (0x01<<1) 5379 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 5380 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 5381 #define SLEEP_MODE_STANDBY (0x06<<1) 5382 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 5383 5384 5385 #endif /* _AVR_IOM128RFA1_H_ */ 5386