1 /***************************************************************************** 2 * 3 * Copyright (C) 2014 Atmel Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * * Neither the name of the copyright holders nor the names of 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 ****************************************************************************/ 33 34 35 /* $Id: iom168pa.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 36 37 #ifndef _AVR_ATMEGA168PA_H_INCLUDED 38 #define _AVR_ATMEGA168PA_H_INCLUDED 39 40 41 #ifndef _AVR_IO_H_ 42 # error "Include <avr/io.h> instead of this file." 43 #endif 44 45 #ifndef _AVR_IOXXX_H_ 46 # define _AVR_IOXXX_H_ "iom168pa.h" 47 #else 48 # error "Attempt to include more than one <avr/ioXXX.h> file." 49 #endif 50 51 /* Registers and associated bit numbers */ 52 53 #define PINB _SFR_IO8(0x03) 54 #define PINB7 7 55 #define PINB6 6 56 #define PINB5 5 57 #define PINB4 4 58 #define PINB3 3 59 #define PINB2 2 60 #define PINB1 1 61 #define PINB0 0 62 63 #define DDRB _SFR_IO8(0x04) 64 #define DDRB7 7 65 #define DDRB6 6 66 #define DDRB5 5 67 #define DDRB4 4 68 #define DDRB3 3 69 #define DDRB2 2 70 #define DDRB1 1 71 #define DDRB0 0 72 73 #define PORTB _SFR_IO8(0x05) 74 #define PORTB7 7 75 #define PORTB6 6 76 #define PORTB5 5 77 #define PORTB4 4 78 #define PORTB3 3 79 #define PORTB2 2 80 #define PORTB1 1 81 #define PORTB0 0 82 83 #define PINC _SFR_IO8(0x06) 84 #define PINC6 6 85 #define PINC5 5 86 #define PINC4 4 87 #define PINC3 3 88 #define PINC2 2 89 #define PINC1 1 90 #define PINC0 0 91 92 #define DDRC _SFR_IO8(0x07) 93 #define DDRC6 6 94 #define DDRC5 5 95 #define DDRC4 4 96 #define DDRC3 3 97 #define DDRC2 2 98 #define DDRC1 1 99 #define DDRC0 0 100 101 #define PORTC _SFR_IO8(0x08) 102 #define PORTC6 6 103 #define PORTC5 5 104 #define PORTC4 4 105 #define PORTC3 3 106 #define PORTC2 2 107 #define PORTC1 1 108 #define PORTC0 0 109 110 #define PIND _SFR_IO8(0x09) 111 #define PIND7 7 112 #define PIND6 6 113 #define PIND5 5 114 #define PIND4 4 115 #define PIND3 3 116 #define PIND2 2 117 #define PIND1 1 118 #define PIND0 0 119 120 #define DDRD _SFR_IO8(0x0A) 121 #define DDRD7 7 122 #define DDRD6 6 123 #define DDRD5 5 124 #define DDRD4 4 125 #define DDRD3 3 126 #define DDRD2 2 127 #define DDRD1 1 128 #define DDRD0 0 129 130 #define PORTD _SFR_IO8(0x0B) 131 #define PORTD7 7 132 #define PORTD6 6 133 #define PORTD5 5 134 #define PORTD4 4 135 #define PORTD3 3 136 #define PORTD2 2 137 #define PORTD1 1 138 #define PORTD0 0 139 140 /* Reserved [0x0C..0x14] */ 141 142 #define TIFR0 _SFR_IO8(0x15) 143 #define TOV0 0 144 #define OCF0A 1 145 #define OCF0B 2 146 147 #define TIFR1 _SFR_IO8(0x16) 148 #define TOV1 0 149 #define OCF1A 1 150 #define OCF1B 2 151 #define ICF1 5 152 153 #define TIFR2 _SFR_IO8(0x17) 154 #define TOV2 0 155 #define OCF2A 1 156 #define OCF2B 2 157 158 /* Reserved [0x18..0x1A] */ 159 160 #define PCIFR _SFR_IO8(0x1B) 161 #define PCIF0 0 162 #define PCIF1 1 163 #define PCIF2 2 164 165 #define EIFR _SFR_IO8(0x1C) 166 #define INTF0 0 167 #define INTF1 1 168 169 #define EIMSK _SFR_IO8(0x1D) 170 #define INT0 0 171 #define INT1 1 172 173 #define GPIOR0 _SFR_IO8(0x1E) 174 175 #define EECR _SFR_IO8(0x1F) 176 #define EERE 0 177 #define EEPE 1 178 #define EEMPE 2 179 #define EERIE 3 180 #define EEPM0 4 181 #define EEPM1 5 182 183 #define EEDR _SFR_IO8(0x20) 184 185 /* Combine EEARL and EEARH */ 186 #define EEAR _SFR_IO16(0x21) 187 188 #define EEARL _SFR_IO8(0x21) 189 #define EEARH _SFR_IO8(0x22) 190 191 #define GTCCR _SFR_IO8(0x23) 192 #define PSRSYNC 0 193 #define TSM 7 194 #define PSRASY 1 195 196 #define TCCR0A _SFR_IO8(0x24) 197 #define WGM00 0 198 #define WGM01 1 199 #define COM0B0 4 200 #define COM0B1 5 201 #define COM0A0 6 202 #define COM0A1 7 203 204 #define TCCR0B _SFR_IO8(0x25) 205 #define CS00 0 206 #define CS01 1 207 #define CS02 2 208 #define WGM02 3 209 #define FOC0B 6 210 #define FOC0A 7 211 212 #define TCNT0 _SFR_IO8(0x26) 213 214 #define OCR0A _SFR_IO8(0x27) 215 216 #define OCR0B _SFR_IO8(0x28) 217 218 /* Reserved [0x29] */ 219 220 #define GPIOR1 _SFR_IO8(0x2A) 221 222 #define GPIOR2 _SFR_IO8(0x2B) 223 224 #define SPCR _SFR_IO8(0x2C) 225 #define SPR0 0 226 #define SPR1 1 227 #define CPHA 2 228 #define CPOL 3 229 #define MSTR 4 230 #define DORD 5 231 #define SPE 6 232 #define SPIE 7 233 234 #define SPSR _SFR_IO8(0x2D) 235 #define SPI2X 0 236 #define WCOL 6 237 #define SPIF 7 238 239 #define SPDR _SFR_IO8(0x2E) 240 241 /* Reserved [0x2F] */ 242 243 #define ACSR _SFR_IO8(0x30) 244 #define ACIS0 0 245 #define ACIS1 1 246 #define ACIC 2 247 #define ACIE 3 248 #define ACI 4 249 #define ACO 5 250 #define ACBG 6 251 #define ACD 7 252 253 /* Reserved [0x31..0x32] */ 254 255 #define SMCR _SFR_IO8(0x33) 256 #define SE 0 257 #define SM0 1 258 #define SM1 2 259 #define SM2 3 260 261 #define MCUSR _SFR_IO8(0x34) 262 #define PORF 0 263 #define EXTRF 1 264 #define BORF 2 265 #define WDRF 3 266 267 #define MCUCR _SFR_IO8(0x35) 268 #define IVCE 0 269 #define IVSEL 1 270 #define PUD 4 271 #define BODSE 5 272 #define BODS 6 273 274 /* Reserved [0x36] */ 275 276 #define SPMCSR _SFR_IO8(0x37) 277 #define SELFPRGEN 0 278 #define PGERS 1 279 #define PGWRT 2 280 #define BLBSET 3 281 #define RWWSRE 4 282 #define RWWSB 6 283 #define SPMIE 7 284 285 /* Reserved [0x38..0x3C] */ 286 287 /* SP [0x3D..0x3E] */ 288 289 /* SREG [0x3F] */ 290 291 #define WDTCSR _SFR_MEM8(0x60) 292 #define WDE 3 293 #define WDCE 4 294 #define WDP0 0 295 #define WDP1 1 296 #define WDP2 2 297 #define WDP3 5 298 #define WDIE 6 299 #define WDIF 7 300 301 #define CLKPR _SFR_MEM8(0x61) 302 #define CLKPS0 0 303 #define CLKPS1 1 304 #define CLKPS2 2 305 #define CLKPS3 3 306 #define CLKPCE 7 307 308 /* Reserved [0x62..0x63] */ 309 310 #define PRR _SFR_MEM8(0x64) 311 #define PRADC 0 312 #define PRUSART0 1 313 #define PRSPI 2 314 #define PRTIM1 3 315 #define PRTIM0 5 316 #define PRTIM2 6 317 #define PRTWI 7 318 319 #define __AVR_HAVE_PRR ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)) 320 #define __AVR_HAVE_PRR_PRADC 321 #define __AVR_HAVE_PRR_PRUSART0 322 #define __AVR_HAVE_PRR_PRSPI 323 #define __AVR_HAVE_PRR_PRTIM1 324 #define __AVR_HAVE_PRR_PRTIM0 325 #define __AVR_HAVE_PRR_PRTIM2 326 #define __AVR_HAVE_PRR_PRTWI 327 328 /* Reserved [0x65] */ 329 330 #define OSCCAL _SFR_MEM8(0x66) 331 #define OSCCAL0 0 332 #define OSCCAL1 1 333 #define OSCCAL2 2 334 #define OSCCAL3 3 335 #define OSCCAL4 4 336 #define OSCCAL5 5 337 #define OSCCAL6 6 338 #define OSCCAL7 7 339 340 /* Reserved [0x67] */ 341 342 #define PCICR _SFR_MEM8(0x68) 343 #define PCIE0 0 344 #define PCIE1 1 345 #define PCIE2 2 346 347 #define EICRA _SFR_MEM8(0x69) 348 #define ISC00 0 349 #define ISC01 1 350 #define ISC10 2 351 #define ISC11 3 352 353 /* Reserved [0x6A] */ 354 355 #define PCMSK0 _SFR_MEM8(0x6B) 356 #define PCINT0 0 357 #define PCINT1 1 358 #define PCINT2 2 359 #define PCINT3 3 360 #define PCINT4 4 361 #define PCINT5 5 362 #define PCINT6 6 363 #define PCINT7 7 364 365 #define PCMSK1 _SFR_MEM8(0x6C) 366 #define PCINT8 0 367 #define PCINT9 1 368 #define PCINT10 2 369 #define PCINT11 3 370 #define PCINT12 4 371 #define PCINT13 5 372 #define PCINT14 6 373 374 #define PCMSK2 _SFR_MEM8(0x6D) 375 #define PCINT16 0 376 #define PCINT17 1 377 #define PCINT18 2 378 #define PCINT19 3 379 #define PCINT20 4 380 #define PCINT21 5 381 #define PCINT22 6 382 #define PCINT23 7 383 384 #define TIMSK0 _SFR_MEM8(0x6E) 385 #define TOIE0 0 386 #define OCIE0A 1 387 #define OCIE0B 2 388 389 #define TIMSK1 _SFR_MEM8(0x6F) 390 #define TOIE1 0 391 #define OCIE1A 1 392 #define OCIE1B 2 393 #define ICIE1 5 394 395 #define TIMSK2 _SFR_MEM8(0x70) 396 #define TOIE2 0 397 #define OCIE2A 1 398 #define OCIE2B 2 399 400 /* Reserved [0x71..0x77] */ 401 402 /* Combine ADCL and ADCH */ 403 #ifndef __ASSEMBLER__ 404 #define ADC _SFR_MEM16(0x78) 405 #endif 406 #define ADCW _SFR_MEM16(0x78) 407 408 #define ADCL _SFR_MEM8(0x78) 409 #define ADCH _SFR_MEM8(0x79) 410 411 #define ADCSRA _SFR_MEM8(0x7A) 412 #define ADPS0 0 413 #define ADPS1 1 414 #define ADPS2 2 415 #define ADIE 3 416 #define ADIF 4 417 #define ADATE 5 418 #define ADSC 6 419 #define ADEN 7 420 421 #define ADCSRB _SFR_MEM8(0x7B) 422 #define ADTS0 0 423 #define ADTS1 1 424 #define ADTS2 2 425 #define ACME 6 426 427 #define ADMUX _SFR_MEM8(0x7C) 428 #define MUX0 0 429 #define MUX1 1 430 #define MUX2 2 431 #define MUX3 3 432 #define ADLAR 5 433 #define REFS0 6 434 #define REFS1 7 435 436 /* Reserved [0x7D] */ 437 438 #define DIDR0 _SFR_MEM8(0x7E) 439 #define ADC0D 0 440 #define ADC1D 1 441 #define ADC2D 2 442 #define ADC3D 3 443 #define ADC4D 4 444 #define ADC5D 5 445 446 #define DIDR1 _SFR_MEM8(0x7F) 447 #define AIN0D 0 448 #define AIN1D 1 449 450 #define TCCR1A _SFR_MEM8(0x80) 451 #define WGM10 0 452 #define WGM11 1 453 #define COM1B0 4 454 #define COM1B1 5 455 #define COM1A0 6 456 #define COM1A1 7 457 458 #define TCCR1B _SFR_MEM8(0x81) 459 #define CS10 0 460 #define CS11 1 461 #define CS12 2 462 #define WGM12 3 463 #define WGM13 4 464 #define ICES1 6 465 #define ICNC1 7 466 467 #define TCCR1C _SFR_MEM8(0x82) 468 #define FOC1B 6 469 #define FOC1A 7 470 471 /* Reserved [0x83] */ 472 473 /* Combine TCNT1L and TCNT1H */ 474 #define TCNT1 _SFR_MEM16(0x84) 475 476 #define TCNT1L _SFR_MEM8(0x84) 477 #define TCNT1H _SFR_MEM8(0x85) 478 479 /* Combine ICR1L and ICR1H */ 480 #define ICR1 _SFR_MEM16(0x86) 481 482 #define ICR1L _SFR_MEM8(0x86) 483 #define ICR1H _SFR_MEM8(0x87) 484 485 /* Combine OCR1AL and OCR1AH */ 486 #define OCR1A _SFR_MEM16(0x88) 487 488 #define OCR1AL _SFR_MEM8(0x88) 489 #define OCR1AH _SFR_MEM8(0x89) 490 491 /* Combine OCR1BL and OCR1BH */ 492 #define OCR1B _SFR_MEM16(0x8A) 493 494 #define OCR1BL _SFR_MEM8(0x8A) 495 #define OCR1BH _SFR_MEM8(0x8B) 496 497 /* Reserved [0x8C..0xAF] */ 498 499 #define TCCR2A _SFR_MEM8(0xB0) 500 #define WGM20 0 501 #define WGM21 1 502 #define COM2B0 4 503 #define COM2B1 5 504 #define COM2A0 6 505 #define COM2A1 7 506 507 #define TCCR2B _SFR_MEM8(0xB1) 508 #define CS20 0 509 #define CS21 1 510 #define CS22 2 511 #define WGM22 3 512 #define FOC2B 6 513 #define FOC2A 7 514 515 #define TCNT2 _SFR_MEM8(0xB2) 516 517 #define OCR2A _SFR_MEM8(0xB3) 518 519 #define OCR2B _SFR_MEM8(0xB4) 520 521 /* Reserved [0xB5] */ 522 523 #define ASSR _SFR_MEM8(0xB6) 524 #define TCR2BUB 0 525 #define TCR2AUB 1 526 #define OCR2BUB 2 527 #define OCR2AUB 3 528 #define TCN2UB 4 529 #define AS2 5 530 #define EXCLK 6 531 532 /* Reserved [0xB7] */ 533 534 #define TWBR _SFR_MEM8(0xB8) 535 536 #define TWSR _SFR_MEM8(0xB9) 537 #define TWPS0 0 538 #define TWPS1 1 539 #define TWS3 3 540 #define TWS4 4 541 #define TWS5 5 542 #define TWS6 6 543 #define TWS7 7 544 545 #define TWAR _SFR_MEM8(0xBA) 546 #define TWGCE 0 547 #define TWA0 1 548 #define TWA1 2 549 #define TWA2 3 550 #define TWA3 4 551 #define TWA4 5 552 #define TWA5 6 553 #define TWA6 7 554 555 #define TWDR _SFR_MEM8(0xBB) 556 557 #define TWCR _SFR_MEM8(0xBC) 558 #define TWIE 0 559 #define TWEN 2 560 #define TWWC 3 561 #define TWSTO 4 562 #define TWSTA 5 563 #define TWEA 6 564 #define TWINT 7 565 566 #define TWAMR _SFR_MEM8(0xBD) 567 #define TWAM0 1 568 #define TWAM1 2 569 #define TWAM2 3 570 #define TWAM3 4 571 #define TWAM4 5 572 #define TWAM5 6 573 #define TWAM6 7 574 575 /* Reserved [0xBE..0xBF] */ 576 577 #define UCSR0A _SFR_MEM8(0xC0) 578 #define MPCM0 0 579 #define U2X0 1 580 #define UPE0 2 581 #define DOR0 3 582 #define FE0 4 583 #define UDRE0 5 584 #define TXC0 6 585 #define RXC0 7 586 587 #define UCSR0B _SFR_MEM8(0xC1) 588 #define TXB80 0 589 #define RXB80 1 590 #define UCSZ02 2 591 #define TXEN0 3 592 #define RXEN0 4 593 #define UDRIE0 5 594 #define TXCIE0 6 595 #define RXCIE0 7 596 597 #define UCSR0C _SFR_MEM8(0xC2) 598 #define UCPOL0 0 599 #define UCSZ00 1 600 #define UCSZ01 2 601 #define USBS0 3 602 #define UPM00 4 603 #define UPM01 5 604 #define UMSEL00 6 605 #define UMSEL01 7 606 607 /* Reserved [0xC3] */ 608 609 /* Combine UBRR0L and UBRR0H */ 610 #define UBRR0 _SFR_MEM16(0xC4) 611 612 #define UBRR0L _SFR_MEM8(0xC4) 613 #define UBRR0H _SFR_MEM8(0xC5) 614 615 #define UDR0 _SFR_MEM8(0xC6) 616 617 618 619 /* Interrupt vectors */ 620 /* Vector 0 is the reset vector */ 621 /* External Interrupt Request 0 */ 622 #define INT0_vect _VECTOR(1) 623 #define INT0_vect_num 1 624 625 /* External Interrupt Request 1 */ 626 #define INT1_vect _VECTOR(2) 627 #define INT1_vect_num 2 628 629 /* Pin Change Interrupt Request 0 */ 630 #define PCINT0_vect _VECTOR(3) 631 #define PCINT0_vect_num 3 632 633 /* Pin Change Interrupt Request 0 */ 634 #define PCINT1_vect _VECTOR(4) 635 #define PCINT1_vect_num 4 636 637 /* Pin Change Interrupt Request 1 */ 638 #define PCINT2_vect _VECTOR(5) 639 #define PCINT2_vect_num 5 640 641 /* Watchdog Time-out Interrupt */ 642 #define WDT_vect _VECTOR(6) 643 #define WDT_vect_num 6 644 645 /* Timer/Counter2 Compare Match A */ 646 #define TIMER2_COMPA_vect _VECTOR(7) 647 #define TIMER2_COMPA_vect_num 7 648 649 /* Timer/Counter2 Compare Match A */ 650 #define TIMER2_COMPB_vect _VECTOR(8) 651 #define TIMER2_COMPB_vect_num 8 652 653 /* Timer/Counter2 Overflow */ 654 #define TIMER2_OVF_vect _VECTOR(9) 655 #define TIMER2_OVF_vect_num 9 656 657 /* Timer/Counter1 Capture Event */ 658 #define TIMER1_CAPT_vect _VECTOR(10) 659 #define TIMER1_CAPT_vect_num 10 660 661 /* Timer/Counter1 Compare Match A */ 662 #define TIMER1_COMPA_vect _VECTOR(11) 663 #define TIMER1_COMPA_vect_num 11 664 665 /* Timer/Counter1 Compare Match B */ 666 #define TIMER1_COMPB_vect _VECTOR(12) 667 #define TIMER1_COMPB_vect_num 12 668 669 /* Timer/Counter1 Overflow */ 670 #define TIMER1_OVF_vect _VECTOR(13) 671 #define TIMER1_OVF_vect_num 13 672 673 /* TimerCounter0 Compare Match A */ 674 #define TIMER0_COMPA_vect _VECTOR(14) 675 #define TIMER0_COMPA_vect_num 14 676 677 /* TimerCounter0 Compare Match B */ 678 #define TIMER0_COMPB_vect _VECTOR(15) 679 #define TIMER0_COMPB_vect_num 15 680 681 /* Timer/Couner0 Overflow */ 682 #define TIMER0_OVF_vect _VECTOR(16) 683 #define TIMER0_OVF_vect_num 16 684 685 /* SPI Serial Transfer Complete */ 686 #define SPI_STC_vect _VECTOR(17) 687 #define SPI_STC_vect_num 17 688 689 /* USART Rx Complete */ 690 #define USART_RX_vect _VECTOR(18) 691 #define USART_RX_vect_num 18 692 693 /* USART, Data Register Empty */ 694 #define USART_UDRE_vect _VECTOR(19) 695 #define USART_UDRE_vect_num 19 696 697 /* USART Tx Complete */ 698 #define USART_TX_vect _VECTOR(20) 699 #define USART_TX_vect_num 20 700 701 /* ADC Conversion Complete */ 702 #define ADC_vect _VECTOR(21) 703 #define ADC_vect_num 21 704 705 /* EEPROM Ready */ 706 #define EE_READY_vect _VECTOR(22) 707 #define EE_READY_vect_num 22 708 709 /* Analog Comparator */ 710 #define ANALOG_COMP_vect _VECTOR(23) 711 #define ANALOG_COMP_vect_num 23 712 713 /* Two-wire Serial Interface */ 714 #define TWI_vect _VECTOR(24) 715 #define TWI_vect_num 24 716 717 /* Store Program Memory Read */ 718 #define SPM_Ready_vect _VECTOR(25) 719 #define SPM_Ready_vect_num 25 720 721 #define _VECTORS_SIZE 104 722 723 724 /* Constants */ 725 726 #define SPM_PAGESIZE 128 727 #define FLASHSTART 0x0000 728 #define FLASHEND 0x3FFF 729 #define RAMSTART 0x0100 730 #define RAMSIZE 1024 731 #define RAMEND 0x04FF 732 #define E2START 0 733 #define E2SIZE 512 734 #define E2PAGESIZE 4 735 #define E2END 0x01FF 736 #define XRAMEND RAMEND 737 738 739 /* Fuses */ 740 741 #define FUSE_MEMORY_SIZE 3 742 743 /* Low Fuse Byte */ 744 #define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) 745 #define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) 746 #define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) 747 #define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) 748 #define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) 749 #define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) 750 #define FUSE_CKOUT (unsigned char)~_BV(6) 751 #define FUSE_CKDIV8 (unsigned char)~_BV(7) 752 753 /* High Fuse Byte */ 754 #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) 755 #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) 756 #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) 757 #define FUSE_EESAVE (unsigned char)~_BV(3) 758 #define FUSE_WDTON (unsigned char)~_BV(4) 759 #define FUSE_SPIEN (unsigned char)~_BV(5) 760 #define FUSE_DWEN (unsigned char)~_BV(6) 761 #define FUSE_RSTDISBL (unsigned char)~_BV(7) 762 763 /* Extended Fuse Byte */ 764 #define FUSE_BOOTRST (unsigned char)~_BV(0) 765 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) 766 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) 767 768 769 /* Lock Bits */ 770 #define __LOCK_BITS_EXIST 771 #define __BOOT_LOCK_BITS_0_EXIST 772 #define __BOOT_LOCK_BITS_1_EXIST 773 774 775 /* Signature */ 776 #define SIGNATURE_0 0x1E 777 #define SIGNATURE_1 0x94 778 #define SIGNATURE_2 0x0B 779 780 781 782 #define SLEEP_MODE_IDLE (0x00<<1) 783 #define SLEEP_MODE_ADC (0x01<<1) 784 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 785 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 786 #define SLEEP_MODE_STANDBY (0x06<<1) 787 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 788 789 #endif /* #ifdef _AVR_ATMEGA168PA_H_INCLUDED */ 790 791