1 /***************************************************************************** 2 * 3 * Copyright (C) 2016 Atmel Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * * Neither the name of the copyright holders nor the names of 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 ****************************************************************************/ 33 34 35 #ifndef _AVR_ATMEGA64HVE2_H_INCLUDED 36 #define _AVR_ATMEGA64HVE2_H_INCLUDED 37 38 39 #ifndef _AVR_IO_H_ 40 # error "Include <avr/io.h> instead of this file." 41 #endif 42 43 #ifndef _AVR_IOXXX_H_ 44 # define _AVR_IOXXX_H_ "iom64hve2.h" 45 #else 46 # error "Attempt to include more than one <avr/ioXXX.h> file." 47 #endif 48 49 /* Registers and associated bit numbers */ 50 51 #define PINA _SFR_IO8(0x00) 52 #define PINA1 1 53 #define PINA0 0 54 55 #define DDRA _SFR_IO8(0x01) 56 #define DDRA1 1 57 // Inserted "DDA1" from "DDRA1" due to compatibility 58 #define DDA1 1 59 #define DDRA0 0 60 // Inserted "DDA0" from "DDRA0" due to compatibility 61 #define DDA0 0 62 63 #define PORTA _SFR_IO8(0x02) 64 #define PORTA1 1 65 #define PORTA0 0 66 67 #define PINB _SFR_IO8(0x03) 68 #define PINB7 7 69 #define PINB6 6 70 #define PINB5 5 71 #define PINB4 4 72 #define PINB3 3 73 #define PINB2 2 74 #define PINB1 1 75 #define PINB0 0 76 77 #define DDRB _SFR_IO8(0x04) 78 #define DDRB7 7 79 // Inserted "DDB7" from "DDRB7" due to compatibility 80 #define DDB7 7 81 #define DDRB6 6 82 // Inserted "DDB6" from "DDRB6" due to compatibility 83 #define DDB6 6 84 #define DDRB5 5 85 // Inserted "DDB5" from "DDRB5" due to compatibility 86 #define DDB5 5 87 #define DDRB4 4 88 // Inserted "DDB4" from "DDRB4" due to compatibility 89 #define DDB4 4 90 #define DDRB3 3 91 // Inserted "DDB3" from "DDRB3" due to compatibility 92 #define DDB3 3 93 #define DDRB2 2 94 // Inserted "DDB2" from "DDRB2" due to compatibility 95 #define DDB2 2 96 #define DDRB1 1 97 // Inserted "DDB1" from "DDRB1" due to compatibility 98 #define DDB1 1 99 #define DDRB0 0 100 // Inserted "DDB0" from "DDRB0" due to compatibility 101 #define DDB0 0 102 103 #define PORTB _SFR_IO8(0x05) 104 #define PORTB7 7 105 #define PORTB6 6 106 #define PORTB5 5 107 #define PORTB4 4 108 #define PORTB3 3 109 #define PORTB2 2 110 #define PORTB1 1 111 #define PORTB0 0 112 113 /* Reserved [0x06..0x14] */ 114 115 #define TIFR0 _SFR_IO8(0x15) 116 #define TOV0 0 117 #define OCF0A 1 118 #define OCF0B 2 119 #define ICF0 3 120 121 #define TIFR1 _SFR_IO8(0x16) 122 #define TOV1 0 123 #define OCF1A 1 124 #define OCF1B 2 125 #define ICF1 3 126 127 /* Reserved [0x17..0x1A] */ 128 129 #define PCIFR _SFR_IO8(0x1B) 130 #define PCIF0 0 131 #define PCIF1 1 132 133 #define EIFR _SFR_IO8(0x1C) 134 #define INTF0 0 135 136 #define EIMSK _SFR_IO8(0x1D) 137 #define INT0 0 138 139 #define GPIOR0 _SFR_IO8(0x1E) 140 141 #define EECR _SFR_IO8(0x1F) 142 #define EERE 0 143 #define EEPE 1 144 #define EEMPE 2 145 #define EERIE 3 146 #define EEPM0 4 147 #define EEPM1 5 148 149 #define EEDR _SFR_IO8(0x20) 150 151 /* Combine EEARL and EEARH */ 152 #define EEAR _SFR_IO16(0x21) 153 154 #define EEARL _SFR_IO8(0x21) 155 #define EEARH _SFR_IO8(0x22) 156 157 #define GTCCR _SFR_IO8(0x23) 158 #define PSRSYNC 0 159 #define TSM 7 160 161 #define TCCR0A _SFR_IO8(0x24) 162 #define WGM00 0 163 #define ICS0 3 164 #define ICES0 4 165 #define ICNC0 5 166 #define ICEN0 6 167 #define TCW0 7 168 169 #define TCCR0B _SFR_IO8(0x25) 170 #define CS00 0 171 #define CS01 1 172 #define CS02 2 173 174 /* Combine TCNT0L and TCNT0H */ 175 #define TCNT0 _SFR_IO16(0x26) 176 177 #define TCNT0L _SFR_IO8(0x26) 178 #define TCNT0H _SFR_IO8(0x27) 179 180 #define OCR0A _SFR_IO8(0x28) 181 182 #define OCR0B _SFR_IO8(0x29) 183 184 #define GPIOR1 _SFR_IO8(0x2A) 185 186 #define GPIOR2 _SFR_IO8(0x2B) 187 188 #define SPCR _SFR_IO8(0x2C) 189 #define SPR0 0 190 #define SPR1 1 191 #define CPHA 2 192 #define CPOL 3 193 #define MSTR 4 194 #define DORD 5 195 #define SPE 6 196 #define SPIE 7 197 198 #define SPSR _SFR_IO8(0x2D) 199 #define SPI2X 0 200 #define WCOL 6 201 #define SPIF 7 202 203 #define SPDR _SFR_IO8(0x2E) 204 205 /* Reserved [0x2F..0x32] */ 206 207 #define SMCR _SFR_IO8(0x33) 208 #define SE 0 209 #define SM0 1 210 #define SM1 2 211 #define SM2 3 212 213 #define MCUSR _SFR_IO8(0x34) 214 #define PORF 0 215 #define EXTRF 1 216 #define BODRF 2 217 #define WDRF 3 218 #define OCDRF 4 219 220 #define MCUCR _SFR_IO8(0x35) 221 #define IVCE 0 222 #define IVSEL 1 223 #define PUD 4 224 #define CKOE 5 225 226 /* Reserved [0x36] */ 227 228 #define SPMCSR _SFR_IO8(0x37) 229 #define SPMEN 0 230 #define PGERS 1 231 #define PGWRT 2 232 #define LBSET 3 233 #define RWWSRE 4 234 #define SIGRD 5 235 #define RWWSB 6 236 #define SPMIE 7 237 238 /* Reserved [0x38..0x3C] */ 239 240 /* SP [0x3D..0x3E] */ 241 242 /* SREG [0x3F] */ 243 244 #define WDTCSR _SFR_MEM8(0x60) 245 #define WDE 3 246 #define WDCE 4 247 #define WDP0 0 248 #define WDP1 1 249 #define WDP2 2 250 #define WDP3 5 251 #define WDIE 6 252 #define WDIF 7 253 254 #define CLKPR _SFR_MEM8(0x61) 255 #define CLKPS0 0 256 #define CLKPS1 1 257 #define CLKPCE 7 258 259 #define WUTCSR _SFR_MEM8(0x62) 260 #define WUTP0 0 261 #define WUTP1 1 262 #define WUTP2 2 263 #define WUTE 3 264 #define WUTR 4 265 #define WUTIE 6 266 #define WUTIF 7 267 268 #define WDTCLR _SFR_MEM8(0x63) 269 #define WDCLE 0 270 #define WDCL0 1 271 #define WDCL1 2 272 273 #define PRR0 _SFR_MEM8(0x64) 274 #define PRTIM0 0 275 #define PRTIM1 1 276 #define PRSPI 2 277 #define PRLIN 3 278 279 #define __AVR_HAVE_PRR0 ((1<<PRTIM0)|(1<<PRTIM1)|(1<<PRSPI)|(1<<PRLIN)) 280 #define __AVR_HAVE_PRR0_PRTIM0 281 #define __AVR_HAVE_PRR0_PRTIM1 282 #define __AVR_HAVE_PRR0_PRSPI 283 #define __AVR_HAVE_PRR0_PRLIN 284 285 /* Reserved [0x65] */ 286 287 #define SOSCCALA _SFR_MEM8(0x66) 288 289 #define SOSCCALB _SFR_MEM8(0x67) 290 291 #define PCICR _SFR_MEM8(0x68) 292 #define PCIE0 0 293 #define PCIE1 1 294 295 #define EICRA _SFR_MEM8(0x69) 296 #define ISC00 0 297 #define ISC01 1 298 299 /* Reserved [0x6A] */ 300 301 #define PCMSK0 _SFR_MEM8(0x6B) 302 303 #define PCMSK1 _SFR_MEM8(0x6C) 304 305 /* Reserved [0x6D] */ 306 307 #define TIMSK0 _SFR_MEM8(0x6E) 308 #define TOIE0 0 309 #define OCIE0A 1 310 #define OCIE0B 2 311 #define ICIE0 3 312 313 #define TIMSK1 _SFR_MEM8(0x6F) 314 #define TOIE1 0 315 #define OCIE1A 1 316 #define OCIE1B 2 317 #define ICIE1 3 318 319 /* Reserved [0x70..0x7D] */ 320 321 #define DIDR0 _SFR_MEM8(0x7E) 322 #define PA0DID 0 323 #define PA1DID 1 324 325 /* Reserved [0x7F] */ 326 327 #define TCCR1A _SFR_MEM8(0x80) 328 #define WGM10 0 329 #define ICS1 3 330 #define ICES1 4 331 #define ICNC1 5 332 #define ICEN1 6 333 #define TCW1 7 334 335 #define TCCR1B _SFR_MEM8(0x81) 336 #define CS10 0 337 #define CS11 1 338 #define CS12 2 339 340 /* Reserved [0x82..0x83] */ 341 342 /* Combine TCNT1L and TCNT1H */ 343 #define TCNT1 _SFR_MEM16(0x84) 344 345 #define TCNT1L _SFR_MEM8(0x84) 346 #define TCNT1H _SFR_MEM8(0x85) 347 348 /* Reserved [0x86..0x87] */ 349 350 #define OCR1A _SFR_MEM8(0x88) 351 352 #define OCR1B _SFR_MEM8(0x89) 353 354 /* Reserved [0x8A..0xBF] */ 355 356 #define LINCR _SFR_MEM8(0xC0) 357 #define LCMD0 0 358 #define LCMD1 1 359 #define LCMD2 2 360 #define LENA 3 361 #define LCONF0 4 362 #define LCONF1 5 363 #define LIN13 6 364 #define LSWRES 7 365 366 #define LINSIR _SFR_MEM8(0xC1) 367 #define LRXOK 0 368 #define LTXOK 1 369 #define LIDOK 2 370 #define LERR 3 371 #define LBUSY 4 372 #define LIDST0 5 373 #define LIDST1 6 374 #define LIDST2 7 375 376 #define LINENIR _SFR_MEM8(0xC2) 377 #define LENRXOK 0 378 #define LENTXOK 1 379 #define LENIDOK 2 380 #define LENERR 3 381 382 #define LINERR _SFR_MEM8(0xC3) 383 #define LBERR 0 384 #define LCERR 1 385 #define LPERR 2 386 #define LSERR 3 387 #define LFERR 4 388 #define LOVERR 5 389 #define LTOERR 6 390 #define LABORT 7 391 392 #define LINBTR _SFR_MEM8(0xC4) 393 #define LBT0 0 394 #define LBT1 1 395 #define LBT2 2 396 #define LBT3 3 397 #define LBT4 4 398 #define LBT5 5 399 #define LDISR 7 400 401 #define LINBRRL _SFR_MEM8(0xC5) 402 #define LDIV0 0 403 #define LDIV1 1 404 #define LDIV2 2 405 #define LDIV3 3 406 #define LDIV4 4 407 #define LDIV5 5 408 #define LDIV6 6 409 #define LDIV7 7 410 411 #define LINBRRH _SFR_MEM8(0xC6) 412 #define LDIV8 0 413 #define LDIV9 1 414 #define LDIV10 2 415 #define LDIV11 3 416 417 #define LINDLR _SFR_MEM8(0xC7) 418 #define LRXDL0 0 419 #define LRXDL1 1 420 #define LRXDL2 2 421 #define LRXDL3 3 422 #define LTXDL0 4 423 #define LTXDL1 5 424 #define LTXDL2 6 425 #define LTXDL3 7 426 427 #define LINIDR _SFR_MEM8(0xC8) 428 #define LID0 0 429 #define LID1 1 430 #define LID2 2 431 #define LID3 3 432 #define LID4 4 433 #define LID5 5 434 #define LP0 6 435 #define LP1 7 436 437 #define LINSEL _SFR_MEM8(0xC9) 438 #define LINDX0 0 439 #define LINDX1 1 440 #define LINDX2 2 441 #define LAINC 3 442 443 #define LINDAT _SFR_MEM8(0xCA) 444 #define LDATA0 0 445 #define LDATA1 1 446 #define LDATA2 2 447 #define LDATA3 3 448 #define LDATA4 4 449 #define LDATA5 5 450 #define LDATA6 6 451 #define LDATA7 7 452 453 /* Reserved [0xCB..0xD0] */ 454 455 #define BGCSRA _SFR_MEM8(0xD1) 456 #define BGSC0 0 457 #define BGSC1 1 458 #define BGSC2 2 459 460 #define BGCRB _SFR_MEM8(0xD2) 461 #define BGCL0 0 462 #define BGCL1 1 463 #define BGCL2 2 464 #define BGCL3 3 465 #define BGCL4 4 466 #define BGCL5 5 467 #define BGCL6 6 468 #define BGCL7 7 469 470 #define BGCRA _SFR_MEM8(0xD3) 471 #define BGCN0 0 472 #define BGCN1 1 473 #define BGCN2 2 474 #define BGCN3 3 475 #define BGCN4 4 476 #define BGCN5 5 477 #define BGCN6 6 478 #define BGCN7 7 479 480 #define BGLR _SFR_MEM8(0xD4) 481 #define BGPL 0 482 #define BGPLE 1 483 484 /* Reserved [0xD5..0xD7] */ 485 486 #define PLLCSR _SFR_MEM8(0xD8) 487 #define PLLCIE 0 488 #define PLLCIF 1 489 #define LOCK 4 490 #define SWEN 5 491 492 /* Reserved [0xD9..0xDB] */ 493 494 #define PBOV _SFR_MEM8(0xDC) 495 #define PBOE0 0 496 #define PBOE3 3 497 #define PBOVCE 7 498 499 /* Reserved [0xDD..0xDF] */ 500 501 #define ADSCSRA _SFR_MEM8(0xE0) 502 #define SCMD0 0 503 #define SCMD1 1 504 #define SBSY 2 505 506 #define ADSCSRB _SFR_MEM8(0xE1) 507 #define CADICRB 0 508 #define CADACRB 1 509 #define CADICPS 2 510 #define VADICRB 4 511 #define VADACRB 5 512 #define VADICPS 6 513 514 #define ADCRA _SFR_MEM8(0xE2) 515 #define CKSEL 0 516 #define ADCMS0 1 517 #define ADCMS1 2 518 #define ADPSEL 3 519 520 #define ADCRB _SFR_MEM8(0xE3) 521 #define ADADES0 0 522 #define ADADES1 1 523 #define ADADES2 2 524 #define ADIDES0 3 525 #define ADIDES1 4 526 527 #define ADCRC _SFR_MEM8(0xE4) 528 #define CADRCT0 0 529 #define CADRCT1 1 530 #define CADRCT2 2 531 #define CADRCT3 3 532 #define CADRCM0 4 533 #define CADRCM1 5 534 #define CADEN 7 535 536 #define ADCRD _SFR_MEM8(0xE5) 537 #define CADDSEL 0 538 #define CADPDM0 1 539 #define CADPDM1 2 540 #define CADG0 3 541 #define CADG1 4 542 #define CADG2 5 543 544 #define ADCRE _SFR_MEM8(0xE6) 545 #define VADMUX0 0 546 #define VADMUX1 1 547 #define VADMUX2 2 548 #define VADPDM0 3 549 #define VADPDM1 4 550 #define VADREFS 5 551 #define VADEN 7 552 553 #define ADIFR _SFR_MEM8(0xE7) 554 #define CADICIF 0 555 #define CADACIF 1 556 #define CADRCIF 2 557 #define VADICIF 4 558 #define VADACIF 5 559 560 #define ADIMR _SFR_MEM8(0xE8) 561 #define CADICIE 0 562 #define CADACIE 1 563 #define CADRCIE 2 564 #define VADICIE 4 565 #define VADACIE 5 566 567 /* Combine CADRCLL and CADRCLH */ 568 #define CADRCL _SFR_MEM16(0xE9) 569 570 #define CADRCLL _SFR_MEM8(0xE9) 571 #define CADRCLH _SFR_MEM8(0xEA) 572 573 /* Combine CADICL and CADICH */ 574 #define CADIC _SFR_MEM16(0xEB) 575 576 #define CADICL _SFR_MEM8(0xEB) 577 #define CADICH _SFR_MEM8(0xEC) 578 579 #define CADAC0 _SFR_MEM8(0xED) 580 581 #define CADAC1 _SFR_MEM8(0xEE) 582 583 #define CADAC2 _SFR_MEM8(0xEF) 584 585 #define CADAC3 _SFR_MEM8(0xF0) 586 587 /* Combine VADICL and VADICH */ 588 #define VADIC _SFR_MEM16(0xF1) 589 590 #define VADICL _SFR_MEM8(0xF1) 591 #define VADICH _SFR_MEM8(0xF2) 592 593 #define VADAC0 _SFR_MEM8(0xF3) 594 595 #define VADAC1 _SFR_MEM8(0xF4) 596 597 #define VADAC2 _SFR_MEM8(0xF5) 598 599 #define VADAC3 _SFR_MEM8(0xF6) 600 601 602 603 /* Values and associated defines */ 604 605 606 #define SLEEP_MODE_IDLE (0x00<<1) 607 #define SLEEP_MODE_ADC (0x01<<1) 608 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 609 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 610 #define SLEEP_MODE_STANDBY (0x06<<1) 611 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 612 613 /* Interrupt vectors */ 614 /* Vector 0 is the reset vector */ 615 /* External Interrupt 0 */ 616 #define INT0_vect _VECTOR(1) 617 #define INT0_vect_num 1 618 619 /* Pin Change Interrupt 0 */ 620 #define PCINT0_vect _VECTOR(2) 621 #define PCINT0_vect_num 2 622 623 /* Pin Change Interrupt 1 */ 624 #define PCINT1_vect _VECTOR(3) 625 #define PCINT1_vect_num 3 626 627 /* Watchdog Timeout Interrupt */ 628 #define WDT_vect _VECTOR(4) 629 #define WDT_vect_num 4 630 631 /* Wakeup Timer Overflow */ 632 #define WAKEUP_vect _VECTOR(5) 633 #define WAKEUP_vect_num 5 634 635 /* Timer 1 Input capture */ 636 #define TIMER1_IC_vect _VECTOR(6) 637 #define TIMER1_IC_vect_num 6 638 639 /* Timer 1 Compare Match A */ 640 #define TIMER1_COMPA_vect _VECTOR(7) 641 #define TIMER1_COMPA_vect_num 7 642 643 /* Timer 1 Compare Match B */ 644 #define TIMER1_COMPB_vect _VECTOR(8) 645 #define TIMER1_COMPB_vect_num 8 646 647 /* Timer 1 overflow */ 648 #define TIMER1_OVF_vect _VECTOR(9) 649 #define TIMER1_OVF_vect_num 9 650 651 /* Timer 0 Input Capture */ 652 #define TIMER0_IC_vect _VECTOR(10) 653 #define TIMER0_IC_vect_num 10 654 655 /* Timer 0 Comapre Match A */ 656 #define TIMER0_COMPA_vect _VECTOR(11) 657 #define TIMER0_COMPA_vect_num 11 658 659 /* Timer 0 Compare Match B */ 660 #define TIMER0_COMPB_vect _VECTOR(12) 661 #define TIMER0_COMPB_vect_num 12 662 663 /* Timer 0 Overflow */ 664 #define TIMER0_OVF_vect _VECTOR(13) 665 #define TIMER0_OVF_vect_num 13 666 667 /* LIN Status Interrupt */ 668 #define LIN_STATUS_vect _VECTOR(14) 669 #define LIN_STATUS_vect_num 14 670 671 /* LIN Error Interrupt */ 672 #define LIN_ERROR_vect _VECTOR(15) 673 #define LIN_ERROR_vect_num 15 674 675 /* SPI Serial transfer complete */ 676 #define SPI_STC_vect _VECTOR(16) 677 #define SPI_STC_vect_num 16 678 679 /* Voltage ADC Instantaneous Conversion Complete */ 680 #define VADC_CONV_vect _VECTOR(17) 681 #define VADC_CONV_vect_num 17 682 683 /* Voltage ADC Accumulated Conversion Complete */ 684 #define VADC_ACC_vect _VECTOR(18) 685 #define VADC_ACC_vect_num 18 686 687 /* C-ADC Instantaneous Conversion Complete */ 688 #define CADC_CONV_vect _VECTOR(19) 689 #define CADC_CONV_vect_num 19 690 691 /* C-ADC Regular Current */ 692 #define CADC_REG_CUR_vect _VECTOR(20) 693 #define CADC_REG_CUR_vect_num 20 694 695 /* C-ADC Accumulated Conversion Complete */ 696 #define CADC_ACC_vect _VECTOR(21) 697 #define CADC_ACC_vect_num 21 698 699 /* EEPROM Ready */ 700 #define EE_READY_vect _VECTOR(22) 701 #define EE_READY_vect_num 22 702 703 /* SPM Ready */ 704 #define SPM_vect _VECTOR(23) 705 #define SPM_vect_num 23 706 707 /* PLL Lock Change Interrupt */ 708 #define PLL_vect _VECTOR(24) 709 #define PLL_vect_num 24 710 711 #define _VECTORS_SIZE 100 712 713 714 /* Constants */ 715 716 #define SPM_PAGESIZE 128 717 #define FLASHSTART 0x0000 718 #define FLASHEND 0xFFFF 719 #define RAMSTART 0x0100 720 #define RAMSIZE 4096 721 #define RAMEND 0x10FF 722 #define E2START 0 723 #define E2SIZE 1024 724 #define E2PAGESIZE 4 725 #define E2END 0x03FF 726 #define XRAMEND RAMEND 727 728 729 /* Fuses */ 730 731 #define FUSE_MEMORY_SIZE 2 732 733 /* Low Fuse Byte */ 734 #define FUSE_OSCSEL0 (unsigned char)~_BV(0) 735 #define FUSE_SUT0 (unsigned char)~_BV(1) 736 #define FUSE_SUT1 (unsigned char)~_BV(2) 737 #define FUSE_CKDIV8 (unsigned char)~_BV(3) 738 #define FUSE_BODEN (unsigned char)~_BV(4) 739 #define FUSE_SPIEN (unsigned char)~_BV(5) 740 #define FUSE_EESAVE (unsigned char)~_BV(6) 741 #define FUSE_WDTON (unsigned char)~_BV(7) 742 #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SPIEN) 743 744 745 /* High Fuse Byte */ 746 #define FUSE_BOOTRST (unsigned char)~_BV(0) 747 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1) 748 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2) 749 #define FUSE_DWEN (unsigned char)~_BV(3) 750 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) 751 752 753 754 /* Lock Bits */ 755 #define __LOCK_BITS_EXIST 756 #define __BOOT_LOCK_BITS_0_EXIST 757 #define __BOOT_LOCK_BITS_1_EXIST 758 759 760 /* Signature */ 761 #define SIGNATURE_0 0x1E 762 #define SIGNATURE_1 0x96 763 #define SIGNATURE_2 0x10 764 765 766 #endif /* #ifdef _AVR_ATMEGA64HVE2_H_INCLUDED */ 767 768