1 /* Copyright (c) 2013 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iom64rfr2.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 32 33 /* avr/iom64rfr2.h - definitions for ATmega64RFR2 */ 34 35 #ifndef _AVR_IOM64RFR2_H_ 36 #define _AVR_IOM64RFR2_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "iom64rfr2.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 #include <avr/sfr_defs.h> 51 52 #ifndef __ASSEMBLER__ 53 # define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) 54 # define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) 55 # define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) 56 #endif /* __ASSEMBLER__ */ 57 58 /* 59 * USAGE: 60 * 61 * simple register assignment: 62 * TIFR1 = 0x17 63 * subregister assignment: 64 * TIFR1_struct.ocf1a = 1 65 * (subregister names are converted to small letters) 66 */ 67 68 69 /* Port A Input Pins Address */ 70 #define PINA _SFR_IO8(0x00) 71 72 /* PINA */ 73 74 #define PINA0 0 75 #define PINA1 1 76 #define PINA2 2 77 #define PINA3 3 78 #define PINA4 4 79 #define PINA5 5 80 #define PINA6 6 81 #define PINA7 7 82 83 /* Port A Data Direction Register */ 84 #define DDRA _SFR_IO8(0x01) 85 86 /* DDRA */ 87 88 #define DDA0 0 89 #define DDA1 1 90 #define DDA2 2 91 #define DDA3 3 92 #define DDA4 4 93 #define DDA5 5 94 #define DDA6 6 95 #define DDA7 7 96 97 /* Port A Data Register */ 98 #define PORTA _SFR_IO8(0x02) 99 100 /* PORTA */ 101 102 #define PORTA0 0 103 #define PA0 0 104 #define PORTA1 1 105 #define PA1 1 106 #define PORTA2 2 107 #define PA2 2 108 #define PORTA3 3 109 #define PA3 3 110 #define PORTA4 4 111 #define PA4 4 112 #define PORTA5 5 113 #define PA5 5 114 #define PORTA6 6 115 #define PA6 6 116 #define PORTA7 7 117 #define PA7 7 118 119 /* Port B Input Pins Address */ 120 #define PINB _SFR_IO8(0x03) 121 122 /* PINB */ 123 124 #define PINB0 0 125 #define PINB1 1 126 #define PINB2 2 127 #define PINB3 3 128 #define PINB4 4 129 #define PINB5 5 130 #define PINB6 6 131 #define PINB7 7 132 133 /* Port B Data Direction Register */ 134 #define DDRB _SFR_IO8(0x04) 135 136 /* DDRB */ 137 138 #define DDB0 0 139 #define DDB1 1 140 #define DDB2 2 141 #define DDB3 3 142 #define DDB4 4 143 #define DDB5 5 144 #define DDB6 6 145 #define DDB7 7 146 147 /* Port B Data Register */ 148 #define PORTB _SFR_IO8(0x05) 149 150 /* PORTB */ 151 152 #define PORTB0 0 153 #define PB0 0 154 #define PORTB1 1 155 #define PB1 1 156 #define PORTB2 2 157 #define PB2 2 158 #define PORTB3 3 159 #define PB3 3 160 #define PORTB4 4 161 #define PB4 4 162 #define PORTB5 5 163 #define PB5 5 164 #define PORTB6 6 165 #define PB6 6 166 #define PORTB7 7 167 #define PB7 7 168 169 /* Port C Input Pins Address */ 170 #define PINC _SFR_IO8(0x06) 171 172 /* PINC */ 173 174 #define PINC0 0 175 #define PINC1 1 176 #define PINC2 2 177 #define PINC3 3 178 #define PINC4 4 179 #define PINC5 5 180 #define PINC6 6 181 #define PINC7 7 182 183 /* Port C Data Direction Register */ 184 #define DDRC _SFR_IO8(0x07) 185 186 /* DDRC */ 187 188 #define DDC0 0 189 #define DDC1 1 190 #define DDC2 2 191 #define DDC3 3 192 #define DDC4 4 193 #define DDC5 5 194 #define DDC6 6 195 #define DDC7 7 196 197 /* Port C Data Register */ 198 #define PORTC _SFR_IO8(0x08) 199 200 /* PORTC */ 201 202 #define PORTC0 0 203 #define PC0 0 204 #define PORTC1 1 205 #define PC1 1 206 #define PORTC2 2 207 #define PC2 2 208 #define PORTC3 3 209 #define PC3 3 210 #define PORTC4 4 211 #define PC4 4 212 #define PORTC5 5 213 #define PC5 5 214 #define PORTC6 6 215 #define PC6 6 216 #define PORTC7 7 217 #define PC7 7 218 219 /* Port D Input Pins Address */ 220 #define PIND _SFR_IO8(0x09) 221 222 /* PIND */ 223 224 #define PIND0 0 225 #define PIND1 1 226 #define PIND2 2 227 #define PIND3 3 228 #define PIND4 4 229 #define PIND5 5 230 #define PIND6 6 231 #define PIND7 7 232 233 /* Port D Data Direction Register */ 234 #define DDRD _SFR_IO8(0x0A) 235 236 /* DDRD */ 237 238 #define DDD0 0 239 #define DDD1 1 240 #define DDD2 2 241 #define DDD3 3 242 #define DDD4 4 243 #define DDD5 5 244 #define DDD6 6 245 #define DDD7 7 246 247 /* Port D Data Register */ 248 #define PORTD _SFR_IO8(0x0B) 249 250 /* PORTD */ 251 252 #define PORTD0 0 253 #define PD0 0 254 #define PORTD1 1 255 #define PD1 1 256 #define PORTD2 2 257 #define PD2 2 258 #define PORTD3 3 259 #define PD3 3 260 #define PORTD4 4 261 #define PD4 4 262 #define PORTD5 5 263 #define PD5 5 264 #define PORTD6 6 265 #define PD6 6 266 #define PORTD7 7 267 #define PD7 7 268 269 /* Port E Input Pins Address */ 270 #define PINE _SFR_IO8(0x0C) 271 272 /* PINE */ 273 274 #define PINE0 0 275 #define PINE1 1 276 #define PINE2 2 277 #define PINE3 3 278 #define PINE4 4 279 #define PINE5 5 280 #define PINE6 6 281 #define PINE7 7 282 283 /* Port E Data Direction Register */ 284 #define DDRE _SFR_IO8(0x0D) 285 286 /* DDRE */ 287 288 #define DDE0 0 289 #define DDE1 1 290 #define DDE2 2 291 #define DDE3 3 292 #define DDE4 4 293 #define DDE5 5 294 #define DDE6 6 295 #define DDE7 7 296 297 /* Port E Data Register */ 298 #define PORTE _SFR_IO8(0x0E) 299 300 /* PORTE */ 301 302 #define PORTE0 0 303 #define PE0 0 304 #define PORTE1 1 305 #define PE1 1 306 #define PORTE2 2 307 #define PE2 2 308 #define PORTE3 3 309 #define PE3 3 310 #define PORTE4 4 311 #define PE4 4 312 #define PORTE5 5 313 #define PE5 5 314 #define PORTE6 6 315 #define PE6 6 316 #define PORTE7 7 317 #define PE7 7 318 319 /* Port F Input Pins Address */ 320 #define PINF _SFR_IO8(0x0F) 321 322 /* PINF */ 323 324 #define PINF0 0 325 #define PINF1 1 326 #define PINF2 2 327 #define PINF3 3 328 #define PINF4 4 329 #define PINF5 5 330 #define PINF6 6 331 #define PINF7 7 332 333 /* Port F Data Direction Register */ 334 #define DDRF _SFR_IO8(0x10) 335 336 /* DDRF */ 337 338 #define DDF0 0 339 #define DDF1 1 340 #define DDF2 2 341 #define DDF3 3 342 #define DDF4 4 343 #define DDF5 5 344 #define DDF6 6 345 #define DDF7 7 346 347 /* Port F Data Register */ 348 #define PORTF _SFR_IO8(0x11) 349 350 /* PORTF */ 351 352 #define PORTF0 0 353 #define PF0 0 354 #define PORTF1 1 355 #define PF1 1 356 #define PORTF2 2 357 #define PF2 2 358 #define PORTF3 3 359 #define PF3 3 360 #define PORTF4 4 361 #define PF4 4 362 #define PORTF5 5 363 #define PF5 5 364 #define PORTF6 6 365 #define PF6 6 366 #define PORTF7 7 367 #define PF7 7 368 369 /* Port G Input Pins Address */ 370 #define PING _SFR_IO8(0x12) 371 372 /* PING */ 373 374 #define PING0 0 375 #define PING1 1 376 #define PING2 2 377 #define PING3 3 378 #define PING4 4 379 #define PING5 5 380 381 /* Port G Data Direction Register */ 382 #define DDRG _SFR_IO8(0x13) 383 384 /* DDRG */ 385 386 #define DDG0 0 387 #define DDG1 1 388 #define DDG2 2 389 #define DDG3 3 390 #define DDG4 4 391 #define DDG5 5 392 393 /* Port G Data Register */ 394 #define PORTG _SFR_IO8(0x14) 395 396 /* PORTG */ 397 398 #define PORTG0 0 399 #define PG0 0 400 #define PORTG1 1 401 #define PG1 1 402 #define PORTG2 2 403 #define PG2 2 404 #define PORTG3 3 405 #define PG3 3 406 #define PORTG4 4 407 #define PG4 4 408 #define PORTG5 5 409 #define PG5 5 410 411 /* Timer/Counter0 Interrupt Flag Register */ 412 #define TIFR0 _SFR_IO8(0x15) 413 414 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 415 416 struct __reg_TIFR0 { 417 unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ 418 unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ 419 unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ 420 unsigned int : 5; 421 }; 422 423 #define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) 424 425 #endif /* __ASSEMBLER__ */ 426 427 /* TIFR0 */ 428 429 #define TOV0 0 430 #define OCF0A 1 431 #define OCF0B 2 432 433 /* Timer/Counter1 Interrupt Flag Register */ 434 #define TIFR1 _SFR_IO8(0x16) 435 436 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 437 438 struct __reg_TIFR1 { 439 unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ 440 unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ 441 unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ 442 unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ 443 unsigned int : 1; 444 unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ 445 unsigned int : 2; 446 }; 447 448 #define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) 449 450 #endif /* __ASSEMBLER__ */ 451 452 /* TIFR1 */ 453 454 #define TOV1 0 455 #define OCF1A 1 456 #define OCF1B 2 457 #define OCF1C 3 458 #define ICF1 5 459 460 /* Timer/Counter Interrupt Flag Register */ 461 #define TIFR2 _SFR_IO8(0x17) 462 463 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 464 465 struct __reg_TIFR2 { 466 unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ 467 unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ 468 unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ 469 unsigned int : 5; 470 }; 471 472 #define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) 473 474 #endif /* __ASSEMBLER__ */ 475 476 /* TIFR2 */ 477 478 #define TOV2 0 479 #define OCF2A 1 480 #define OCF2B 2 481 482 /* Timer/Counter3 Interrupt Flag Register */ 483 #define TIFR3 _SFR_IO8(0x18) 484 485 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 486 487 struct __reg_TIFR3 { 488 unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ 489 unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ 490 unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ 491 unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ 492 unsigned int : 1; 493 unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ 494 unsigned int : 2; 495 }; 496 497 #define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) 498 499 #endif /* __ASSEMBLER__ */ 500 501 /* TIFR3 */ 502 503 #define TOV3 0 504 #define OCF3A 1 505 #define OCF3B 2 506 #define OCF3C 3 507 #define ICF3 5 508 509 /* Timer/Counter4 Interrupt Flag Register */ 510 #define TIFR4 _SFR_IO8(0x19) 511 512 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 513 514 struct __reg_TIFR4 { 515 unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ 516 unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ 517 unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ 518 unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ 519 unsigned int : 1; 520 unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ 521 unsigned int : 2; 522 }; 523 524 #define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) 525 526 #endif /* __ASSEMBLER__ */ 527 528 /* TIFR4 */ 529 530 #define TOV4 0 531 #define OCF4A 1 532 #define OCF4B 2 533 #define OCF4C 3 534 #define ICF4 5 535 536 /* Timer/Counter5 Interrupt Flag Register */ 537 #define TIFR5 _SFR_IO8(0x1A) 538 539 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 540 541 struct __reg_TIFR5 { 542 unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ 543 unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ 544 unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ 545 unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ 546 unsigned int : 1; 547 unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ 548 unsigned int : 2; 549 }; 550 551 #define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) 552 553 #endif /* __ASSEMBLER__ */ 554 555 /* TIFR5 */ 556 557 #define TOV5 0 558 #define OCF5A 1 559 #define OCF5B 2 560 #define OCF5C 3 561 #define ICF5 5 562 563 /* Pin Change Interrupt Flag Register */ 564 #define PCIFR _SFR_IO8(0x1B) 565 566 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 567 568 struct __reg_PCIFR { 569 unsigned int pcif : 3; /* Pin Change Interrupt Flags */ 570 unsigned int : 5; 571 }; 572 573 #define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) 574 575 #endif /* __ASSEMBLER__ */ 576 577 /* PCIFR */ 578 579 #define PCIF0 0 580 #define PCIF1 1 581 #define PCIF2 2 582 583 /* External Interrupt Flag Register */ 584 #define EIFR _SFR_IO8(0x1C) 585 586 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 587 588 struct __reg_EIFR { 589 unsigned int intf : 8; /* External Interrupt Flag */ 590 }; 591 592 #define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) 593 594 #endif /* __ASSEMBLER__ */ 595 596 /* EIFR */ 597 598 #define INTF0 0 599 #define INTF1 1 600 #define INTF2 2 601 #define INTF3 3 602 #define INTF4 4 603 #define INTF5 5 604 #define INTF6 6 605 #define INTF7 7 606 607 /* External Interrupt Mask Register */ 608 #define EIMSK _SFR_IO8(0x1D) 609 610 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 611 612 struct __reg_EIMSK { 613 unsigned int intm : 8; /* External Interrupt Request Enable */ 614 }; 615 616 #define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) 617 618 #endif /* __ASSEMBLER__ */ 619 620 /* EIMSK */ 621 622 #define INT0 0 623 #define INT1 1 624 #define INT2 2 625 #define INT3 3 626 #define INT4 4 627 #define INT5 5 628 #define INT6 6 629 #define INT7 7 630 631 /* General Purpose IO Register 0 */ 632 #define GPIOR0 _SFR_IO8(0x1E) 633 634 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 635 636 struct __reg_GPIOR0 { 637 unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ 638 unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ 639 unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ 640 unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ 641 unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ 642 unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ 643 unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ 644 unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ 645 }; 646 647 #define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) 648 649 #endif /* __ASSEMBLER__ */ 650 651 /* GPIOR0 */ 652 653 #define GPIOR00 0 654 #define GPIOR01 1 655 #define GPIOR02 2 656 #define GPIOR03 3 657 #define GPIOR04 4 658 #define GPIOR05 5 659 #define GPIOR06 6 660 #define GPIOR07 7 661 662 /* 6-char sequence denoting where to find the EEPROM registers in memory space. 663 Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM 664 subroutines. 665 First two letters: EECR address. 666 Second two letters: EEDR address. 667 Last two letters: EEAR address. */ 668 669 #define __EEPROM_REG_LOCATIONS__ 1F2021 670 671 /* EEPROM Control Register */ 672 #define EECR _SFR_IO8(0x1F) 673 674 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 675 676 struct __reg_EECR { 677 unsigned int eere : 1; /* EEPROM Read Enable */ 678 unsigned int eepe : 1; /* EEPROM Programming Enable */ 679 unsigned int eempe : 1; /* EEPROM Master Write Enable */ 680 unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ 681 unsigned int eepm : 2; /* EEPROM Programming Mode */ 682 unsigned int : 2; 683 }; 684 685 #define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) 686 687 #endif /* __ASSEMBLER__ */ 688 689 /* EECR */ 690 691 #define EERE 0 692 #define EEPE 1 693 #define EEMPE 2 694 #define EERIE 3 695 #define EEPM0 4 696 #define EEPM1 5 697 698 /* EEPROM Data Register */ 699 #define EEDR _SFR_IO8(0x20) 700 701 /* EEDR */ 702 703 #define EEDR0 0 704 #define EEDR1 1 705 #define EEDR2 2 706 #define EEDR3 3 707 #define EEDR4 4 708 #define EEDR5 5 709 #define EEDR6 6 710 #define EEDR7 7 711 712 /* EEPROM Address Register Bytes */ 713 #define EEAR _SFR_IO16(0x21) 714 #define EEARL _SFR_IO8(0x21) 715 #define EEARH _SFR_IO8(0x22) 716 717 /* General Timer/Counter Control Register */ 718 #define GTCCR _SFR_IO8(0x23) 719 720 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 721 722 struct __reg_GTCCR { 723 unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ 724 unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ 725 unsigned int : 5; 726 unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ 727 }; 728 729 #define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) 730 731 #endif /* __ASSEMBLER__ */ 732 733 /* GTCCR */ 734 735 #define PSRSYNC 0 736 #define PSR10 0 737 #define PSRASY 1 738 #define PSR2 1 739 #define TSM 7 740 741 /* Timer/Counter0 Control Register A */ 742 #define TCCR0A _SFR_IO8(0x24) 743 744 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 745 746 struct __reg_TCCR0A { 747 unsigned int wgm0 : 2; /* Waveform Generation Mode */ 748 unsigned int : 2; 749 unsigned int com0b : 2; /* Compare Match Output B Mode */ 750 unsigned int com0a : 2; /* Compare Match Output A Mode */ 751 }; 752 753 #define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) 754 755 #endif /* __ASSEMBLER__ */ 756 757 /* TCCR0A */ 758 759 #define WGM00 0 760 #define WGM01 1 761 #define COM0B0 4 762 #define COM0B1 5 763 #define COM0A0 6 764 #define COM0A1 7 765 766 /* Timer/Counter0 Control Register B */ 767 #define TCCR0B _SFR_IO8(0x25) 768 769 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 770 771 struct __reg_TCCR0B { 772 unsigned int cs0 : 3; /* Clock Select */ 773 unsigned int wgm02 : 1; /* Waveform Generation Mode */ 774 unsigned int : 2; 775 unsigned int foc0b : 1; /* Force Output Compare B */ 776 unsigned int foc0a : 1; /* Force Output Compare A */ 777 }; 778 779 #define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) 780 781 #endif /* __ASSEMBLER__ */ 782 783 /* TCCR0B */ 784 785 #define CS00 0 786 #define CS01 1 787 #define CS02 2 788 #define WGM02 3 789 #define FOC0B 6 790 #define FOC0A 7 791 792 /* Timer/Counter0 Register */ 793 #define TCNT0 _SFR_IO8(0x26) 794 795 /* TCNT0 */ 796 797 #define TCNT0_0 0 798 #define TCNT0_1 1 799 #define TCNT0_2 2 800 #define TCNT0_3 3 801 #define TCNT0_4 4 802 #define TCNT0_5 5 803 #define TCNT0_6 6 804 #define TCNT0_7 7 805 806 /* Timer/Counter0 Output Compare Register */ 807 #define OCR0A _SFR_IO8(0x27) 808 809 /* OCR0A */ 810 811 #define OCR0A_0 0 812 #define OCR0A_1 1 813 #define OCR0A_2 2 814 #define OCR0A_3 3 815 #define OCR0A_4 4 816 #define OCR0A_5 5 817 #define OCR0A_6 6 818 #define OCR0A_7 7 819 820 /* Timer/Counter0 Output Compare Register B */ 821 #define OCR0B _SFR_IO8(0x28) 822 823 /* OCR0B */ 824 825 #define OCR0B_0 0 826 #define OCR0B_1 1 827 #define OCR0B_2 2 828 #define OCR0B_3 3 829 #define OCR0B_4 4 830 #define OCR0B_5 5 831 #define OCR0B_6 6 832 #define OCR0B_7 7 833 834 /* General Purpose IO Register 1 */ 835 #define GPIOR1 _SFR_IO8(0x2A) 836 837 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 838 839 struct __reg_GPIOR1 { 840 unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ 841 }; 842 843 #define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) 844 845 #endif /* __ASSEMBLER__ */ 846 847 /* GPIOR1 */ 848 849 #define GPIOR10 0 850 #define GPIOR11 1 851 #define GPIOR12 2 852 #define GPIOR13 3 853 #define GPIOR14 4 854 #define GPIOR15 5 855 #define GPIOR16 6 856 #define GPIOR17 7 857 858 /* General Purpose I/O Register 2 */ 859 #define GPIOR2 _SFR_IO8(0x2B) 860 861 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 862 863 struct __reg_GPIOR2 { 864 unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ 865 }; 866 867 #define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) 868 869 #endif /* __ASSEMBLER__ */ 870 871 /* GPIOR2 */ 872 873 #define GPIOR20 0 874 #define GPIOR21 1 875 #define GPIOR22 2 876 #define GPIOR23 3 877 #define GPIOR24 4 878 #define GPIOR25 5 879 #define GPIOR26 6 880 #define GPIOR27 7 881 882 /* SPI Control Register */ 883 #define SPCR _SFR_IO8(0x2C) 884 885 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 886 887 struct __reg_SPCR { 888 unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ 889 unsigned int cpha : 1; /* Clock Phase */ 890 unsigned int cpol : 1; /* Clock polarity */ 891 unsigned int mstr : 1; /* Master/Slave Select */ 892 unsigned int dord : 1; /* Data Order */ 893 unsigned int spe : 1; /* SPI Enable */ 894 unsigned int spie : 1; /* SPI Interrupt Enable */ 895 }; 896 897 #define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) 898 899 #endif /* __ASSEMBLER__ */ 900 901 /* SPCR */ 902 903 #define SPR0 0 904 #define SPR1 1 905 #define CPHA 2 906 #define CPOL 3 907 #define MSTR 4 908 #define DORD 5 909 #define SPE 6 910 #define SPIE 7 911 912 /* SPI Status Register */ 913 #define SPSR _SFR_IO8(0x2D) 914 915 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 916 917 struct __reg_SPSR { 918 unsigned int spi2x : 1; /* Double SPI Speed Bit */ 919 unsigned int : 5; 920 unsigned int wcol : 1; /* Write Collision Flag */ 921 unsigned int spif : 1; /* SPI Interrupt Flag */ 922 }; 923 924 #define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) 925 926 #endif /* __ASSEMBLER__ */ 927 928 /* SPSR */ 929 930 #define SPI2X 0 931 #define WCOL 6 932 #define SPIF 7 933 934 /* SPI Data Register */ 935 #define SPDR _SFR_IO8(0x2E) 936 937 /* SPDR */ 938 939 #define SPDR0 0 940 #define SPDR1 1 941 #define SPDR2 2 942 #define SPDR3 3 943 #define SPDR4 4 944 #define SPDR5 5 945 #define SPDR6 6 946 #define SPDR7 7 947 948 /* Analog Comparator Control And Status Register */ 949 #define ACSR _SFR_IO8(0x30) 950 951 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 952 953 struct __reg_ACSR { 954 unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ 955 unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ 956 unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ 957 unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ 958 unsigned int aco : 1; /* Analog Compare Output */ 959 unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ 960 unsigned int acd : 1; /* Analog Comparator Disable */ 961 }; 962 963 #define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) 964 965 #endif /* __ASSEMBLER__ */ 966 967 /* ACSR */ 968 969 #define ACIS0 0 970 #define ACIS1 1 971 #define ACIC 2 972 #define ACIE 3 973 #define ACI 4 974 #define ACO 5 975 #define ACBG 6 976 #define ACD 7 977 978 /* On-Chip Debug Register */ 979 #define OCDR _SFR_IO8(0x31) 980 981 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 982 983 struct __reg_OCDR { 984 unsigned int ocdr : 8; /* On-Chip Debug Register Data */ 985 }; 986 987 #define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) 988 989 #endif /* __ASSEMBLER__ */ 990 991 /* OCDR */ 992 993 #define OCDR0 0 994 #define OCDR1 1 995 #define OCDR2 2 996 #define OCDR3 3 997 #define OCDR4 4 998 #define OCDR5 5 999 #define OCDR6 6 1000 #define OCDR7 7 1001 #define IDRD 7 1002 1003 /* Sleep Mode Control Register */ 1004 #define SMCR _SFR_IO8(0x33) 1005 1006 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1007 1008 struct __reg_SMCR { 1009 unsigned int se : 1; /* Sleep Enable */ 1010 unsigned int sm : 3; /* Sleep Mode Select bits */ 1011 unsigned int : 4; 1012 }; 1013 1014 #define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) 1015 1016 #endif /* __ASSEMBLER__ */ 1017 1018 /* SMCR */ 1019 1020 #define SE 0 1021 #define SM0 1 1022 #define SM1 2 1023 #define SM2 3 1024 1025 /* MCU Status Register */ 1026 #define MCUSR _SFR_IO8(0x34) 1027 1028 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1029 1030 struct __reg_MCUSR { 1031 unsigned int porf : 1; /* Power-on Reset Flag */ 1032 unsigned int extrf : 1; /* External Reset Flag */ 1033 unsigned int borf : 1; /* Brown-out Reset Flag */ 1034 unsigned int wdrf : 1; /* Watchdog Reset Flag */ 1035 unsigned int jtrf : 1; /* JTAG Reset Flag */ 1036 unsigned int : 3; 1037 }; 1038 1039 #define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) 1040 1041 #endif /* __ASSEMBLER__ */ 1042 1043 /* MCUSR */ 1044 1045 #define PORF 0 1046 #define EXTRF 1 1047 #define BORF 2 1048 #define WDRF 3 1049 #define JTRF 4 1050 1051 /* MCU Control Register */ 1052 #define MCUCR _SFR_IO8(0x35) 1053 1054 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1055 1056 struct __reg_MCUCR { 1057 unsigned int ivce : 1; /* Interrupt Vector Change Enable */ 1058 unsigned int ivsel : 1; /* Interrupt Vector Select */ 1059 unsigned int : 2; 1060 unsigned int pud : 1; /* Pull-up Disable */ 1061 unsigned int : 2; 1062 unsigned int jtd : 1; /* JTAG Interface Disable */ 1063 }; 1064 1065 #define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) 1066 1067 #endif /* __ASSEMBLER__ */ 1068 1069 /* MCUCR */ 1070 1071 #define IVCE 0 1072 #define IVSEL 1 1073 #define PUD 4 1074 #define JTD 7 1075 1076 /* Store Program Memory Control Register */ 1077 #define SPMCSR _SFR_IO8(0x37) 1078 1079 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1080 1081 struct __reg_SPMCSR { 1082 unsigned int spmen : 1; /* Store Program Memory Enable */ 1083 unsigned int pgers : 1; /* Page Erase */ 1084 unsigned int pgwrt : 1; /* Page Write */ 1085 unsigned int blbset : 1; /* Boot Lock Bit Set */ 1086 unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ 1087 unsigned int sigrd : 1; /* Signature Row Read */ 1088 unsigned int rwwsb : 1; /* Read While Write Section Busy */ 1089 unsigned int spmie : 1; /* SPM Interrupt Enable */ 1090 }; 1091 1092 #define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) 1093 1094 #endif /* __ASSEMBLER__ */ 1095 1096 /* SPMCSR */ 1097 1098 #define SPMEN 0 1099 #define PGERS 1 1100 #define PGWRT 2 1101 #define BLBSET 3 1102 #define RWWSRE 4 1103 #define SIGRD 5 1104 #define RWWSB 6 1105 #define SPMIE 7 1106 1107 /* Stack Pointer */ 1108 #define SP _SFR_IO16(0x3D) 1109 #define SPL _SFR_IO8(0x3D) 1110 #define SPH _SFR_IO8(0x3E) 1111 1112 /* Status Register */ 1113 #define SREG _SFR_IO8(0x3F) 1114 1115 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1116 1117 struct __reg_SREG { 1118 unsigned int c : 1; /* Carry Flag */ 1119 unsigned int z : 1; /* Zero Flag */ 1120 unsigned int n : 1; /* Negative Flag */ 1121 unsigned int v : 1; /* Two's Complement Overflow Flag */ 1122 unsigned int s : 1; /* Sign Bit */ 1123 unsigned int h : 1; /* Half Carry Flag */ 1124 unsigned int t : 1; /* Bit Copy Storage */ 1125 unsigned int i : 1; /* Global Interrupt Enable */ 1126 }; 1127 1128 #define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) 1129 1130 #endif /* __ASSEMBLER__ */ 1131 1132 /* SREG */ 1133 1134 #define SREG_C 0 1135 #define SREG_Z 1 1136 #define SREG_N 2 1137 #define SREG_V 3 1138 #define SREG_S 4 1139 #define SREG_H 5 1140 #define SREG_T 6 1141 #define SREG_I 7 1142 1143 /* Watchdog Timer Control Register */ 1144 #define WDTCSR _SFR_MEM8(0x60) 1145 1146 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1147 1148 struct __reg_WDTCSR { 1149 unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ 1150 unsigned int wde : 1; /* Watch Dog Enable */ 1151 unsigned int wdce : 1; /* Watchdog Change Enable */ 1152 unsigned int : 1; 1153 unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ 1154 unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ 1155 }; 1156 1157 #define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) 1158 1159 #endif /* __ASSEMBLER__ */ 1160 1161 /* WDTCSR */ 1162 1163 #define WDP0 0 1164 #define WDP1 1 1165 #define WDP2 2 1166 #define WDE 3 1167 #define WDCE 4 1168 #define WDP3 5 1169 #define WDIE 6 1170 #define WDIF 7 1171 1172 /* Clock Prescale Register */ 1173 #define CLKPR _SFR_MEM8(0x61) 1174 1175 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1176 1177 struct __reg_CLKPR { 1178 unsigned int clkps : 4; /* Clock Prescaler Select Bits */ 1179 unsigned int : 3; 1180 unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ 1181 }; 1182 1183 #define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) 1184 1185 #endif /* __ASSEMBLER__ */ 1186 1187 /* CLKPR */ 1188 1189 #define CLKPS0 0 1190 #define CLKPS1 1 1191 #define CLKPS2 2 1192 #define CLKPS3 3 1193 #define CLKPCE 7 1194 1195 /* Power Reduction Register 2 */ 1196 #define PRR2 _SFR_MEM8(0x63) 1197 1198 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1199 1200 struct __reg_PRR2 { 1201 unsigned int prram : 4; /* Power Reduction SRAMs */ 1202 unsigned int : 4; 1203 }; 1204 1205 #define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) 1206 1207 #endif /* __ASSEMBLER__ */ 1208 1209 /* PRR2 */ 1210 1211 #define PRRAM0 0 1212 #define PRRAM1 1 1213 #define PRRAM2 2 1214 #define PRRAM3 3 1215 1216 #define __AVR_HAVE_PRR2 ((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3)) 1217 #define __AVR_HAVE_PRR2_PRRAM0 1218 #define __AVR_HAVE_PRR2_PRRAM1 1219 #define __AVR_HAVE_PRR2_PRRAM2 1220 #define __AVR_HAVE_PRR2_PRRAM3 1221 1222 /* Power Reduction Register0 */ 1223 #define PRR0 _SFR_MEM8(0x64) 1224 1225 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1226 1227 struct __reg_PRR0 { 1228 unsigned int pradc : 1; /* Power Reduction ADC */ 1229 unsigned int prusart0 : 1; /* Power Reduction USART */ 1230 unsigned int prspi : 1; /* Power Reduction Serial Peripheral Interface */ 1231 unsigned int prtim1 : 1; /* Power Reduction Timer/Counter1 */ 1232 unsigned int prpga : 1; /* Power Reduction PGA */ 1233 unsigned int prtim0 : 1; /* Power Reduction Timer/Counter0 */ 1234 unsigned int prtim2 : 1; /* Power Reduction Timer/Counter2 */ 1235 unsigned int prtwi : 1; /* Power Reduction TWI */ 1236 }; 1237 1238 #define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0) 1239 1240 #endif /* __ASSEMBLER__ */ 1241 1242 /* PRR0 */ 1243 1244 #define PRADC 0 1245 #define PRUSART0 1 1246 #define PRSPI 2 1247 #define PRTIM1 3 1248 #define PRPGA 4 1249 #define PRTIM0 5 1250 #define PRTIM2 6 1251 #define PRTWI 7 1252 1253 #define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)) 1254 #define __AVR_HAVE_PRR0_PRADC 1255 #define __AVR_HAVE_PRR0_PRUSART0 1256 #define __AVR_HAVE_PRR0_PRSPI 1257 #define __AVR_HAVE_PRR0_PRTIM1 1258 #define __AVR_HAVE_PRR0_PRPGA 1259 #define __AVR_HAVE_PRR0_PRTIM0 1260 #define __AVR_HAVE_PRR0_PRTIM2 1261 #define __AVR_HAVE_PRR0_PRTWI 1262 1263 /* Power Reduction Register 1 */ 1264 #define PRR1 _SFR_MEM8(0x65) 1265 1266 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1267 1268 struct __reg_PRR1 { 1269 unsigned int prusart1 : 1; /* Power Reduction USART1 */ 1270 unsigned int : 2; 1271 unsigned int prtim3 : 1; /* Power Reduction Timer/Counter3 */ 1272 unsigned int prtim4 : 1; /* Power Reduction Timer/Counter4 */ 1273 unsigned int prtim5 : 1; /* Power Reduction Timer/Counter5 */ 1274 unsigned int prtrx24 : 1; /* Power Reduction Transceiver */ 1275 unsigned int : 1; 1276 }; 1277 1278 #define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1) 1279 1280 #endif /* __ASSEMBLER__ */ 1281 1282 /* PRR1 */ 1283 1284 #define PRUSART1 0 1285 #define PRTIM3 3 1286 #define PRTIM4 4 1287 #define PRTIM5 5 1288 #define PRTRX24 6 1289 1290 #define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24)) 1291 #define __AVR_HAVE_PRR1_PRUSART1 1292 #define __AVR_HAVE_PRR1_PRTIM3 1293 #define __AVR_HAVE_PRR1_PRTIM4 1294 #define __AVR_HAVE_PRR1_PRTIM5 1295 #define __AVR_HAVE_PRR1_PRTRX24 1296 1297 /* Oscillator Calibration Value */ 1298 #define OSCCAL _SFR_MEM8(0x66) 1299 1300 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1301 1302 struct __reg_OSCCAL { 1303 unsigned int cal : 8; /* Oscillator Calibration Tuning Value */ 1304 }; 1305 1306 #define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL) 1307 1308 #endif /* __ASSEMBLER__ */ 1309 1310 /* OSCCAL */ 1311 1312 #define CAL0 0 1313 #define CAL1 1 1314 #define CAL2 2 1315 #define CAL3 3 1316 #define CAL4 4 1317 #define CAL5 5 1318 #define CAL6 6 1319 #define CAL7 7 1320 1321 /* Reference Voltage Calibration Register */ 1322 #define BGCR _SFR_MEM8(0x67) 1323 1324 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1325 1326 struct __reg_BGCR { 1327 unsigned int bgcal : 3; /* Coarse Calibration Bits */ 1328 unsigned int bgcal_fine : 4; /* Fine Calibration Bits */ 1329 unsigned int : 1; 1330 }; 1331 1332 #define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR) 1333 1334 #endif /* __ASSEMBLER__ */ 1335 1336 /* BGCR */ 1337 1338 #define BGCAL0 0 1339 #define BGCAL1 1 1340 #define BGCAL2 2 1341 #define BGCAL_FINE0 3 1342 #define BGCAL_FINE1 4 1343 #define BGCAL_FINE2 5 1344 #define BGCAL_FINE3 6 1345 1346 /* Pin Change Interrupt Control Register */ 1347 #define PCICR _SFR_MEM8(0x68) 1348 1349 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1350 1351 struct __reg_PCICR { 1352 unsigned int pcie : 3; /* Pin Change Interrupt Enables */ 1353 unsigned int : 5; 1354 }; 1355 1356 #define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR) 1357 1358 #endif /* __ASSEMBLER__ */ 1359 1360 /* PCICR */ 1361 1362 #define PCIE0 0 1363 #define PCIE1 1 1364 #define PCIE2 2 1365 1366 /* External Interrupt Control Register A */ 1367 #define EICRA _SFR_MEM8(0x69) 1368 1369 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1370 1371 struct __reg_EICRA { 1372 unsigned int isc0 : 2; /* External Interrupt 0 Sense Control Bit */ 1373 unsigned int isc1 : 2; /* External Interrupt 1 Sense Control Bit */ 1374 unsigned int isc2 : 2; /* External Interrupt 2 Sense Control Bit */ 1375 unsigned int isc3 : 2; /* External Interrupt 3 Sense Control Bit */ 1376 }; 1377 1378 #define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA) 1379 1380 #endif /* __ASSEMBLER__ */ 1381 1382 /* EICRA */ 1383 1384 #define ISC00 0 1385 #define ISC01 1 1386 #define ISC10 2 1387 #define ISC11 3 1388 #define ISC20 4 1389 #define ISC21 5 1390 #define ISC30 6 1391 #define ISC31 7 1392 1393 /* External Interrupt Control Register B */ 1394 #define EICRB _SFR_MEM8(0x6A) 1395 1396 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1397 1398 struct __reg_EICRB { 1399 unsigned int isc4 : 2; /* External Interrupt 4 Sense Control Bit */ 1400 unsigned int isc5 : 2; /* External Interrupt 5 Sense Control Bit */ 1401 unsigned int isc6 : 2; /* External Interrupt 6 Sense Control Bit */ 1402 unsigned int isc7 : 2; /* External Interrupt 7 Sense Control Bit */ 1403 }; 1404 1405 #define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB) 1406 1407 #endif /* __ASSEMBLER__ */ 1408 1409 /* EICRB */ 1410 1411 #define ISC40 0 1412 #define ISC41 1 1413 #define ISC50 2 1414 #define ISC51 3 1415 #define ISC60 4 1416 #define ISC61 5 1417 #define ISC70 6 1418 #define ISC71 7 1419 1420 /* Pin Change Mask Register 0 */ 1421 #define PCMSK0 _SFR_MEM8(0x6B) 1422 1423 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1424 1425 struct __reg_PCMSK0 { 1426 unsigned int pcint : 8; /* Pin Change Enable Mask */ 1427 }; 1428 1429 #define PCMSK0_struct _SFR_MEM8_STRUCT(0x6b, struct __reg_PCMSK0) 1430 1431 #endif /* __ASSEMBLER__ */ 1432 1433 /* PCMSK0 */ 1434 1435 #define PCINT0 0 1436 #define PCINT1 1 1437 #define PCINT2 2 1438 #define PCINT3 3 1439 #define PCINT4 4 1440 #define PCINT5 5 1441 #define PCINT6 6 1442 #define PCINT7 7 1443 1444 /* Pin Change Mask Register 1 */ 1445 #define PCMSK1 _SFR_MEM8(0x6C) 1446 1447 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1448 1449 struct __reg_PCMSK1 { 1450 unsigned int pcint : 8; /* Pin Change Enable Mask */ 1451 }; 1452 1453 #define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1) 1454 1455 #endif /* __ASSEMBLER__ */ 1456 1457 /* PCMSK1 */ 1458 1459 #define PCINT8 0 1460 #define PCINT9 1 1461 #define PCINT10 2 1462 #define PCINT11 3 1463 #define PCINT12 4 1464 #define PCINT13 5 1465 #define PCINT14 6 1466 #define PCINT15 7 1467 1468 /* Pin Change Mask Register 2 */ 1469 #define PCMSK2 _SFR_MEM8(0x6D) 1470 1471 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1472 1473 struct __reg_PCMSK2 { 1474 unsigned int pcint : 8; /* Pin Change Enable Mask */ 1475 }; 1476 1477 #define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2) 1478 1479 #endif /* __ASSEMBLER__ */ 1480 1481 /* PCMSK2 */ 1482 1483 #define PCINT16 0 1484 #define PCINT17 1 1485 #define PCINT18 2 1486 #define PCINT19 3 1487 #define PCINT20 4 1488 #define PCINT21 5 1489 #define PCINT22 6 1490 #define PCINT23 7 1491 1492 /* Timer/Counter0 Interrupt Mask Register */ 1493 #define TIMSK0 _SFR_MEM8(0x6E) 1494 1495 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1496 1497 struct __reg_TIMSK0 { 1498 unsigned int toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */ 1499 unsigned int ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */ 1500 unsigned int ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */ 1501 unsigned int : 5; 1502 }; 1503 1504 #define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0) 1505 1506 #endif /* __ASSEMBLER__ */ 1507 1508 /* TIMSK0 */ 1509 1510 #define TOIE0 0 1511 #define OCIE0A 1 1512 #define OCIE0B 2 1513 1514 /* Timer/Counter1 Interrupt Mask Register */ 1515 #define TIMSK1 _SFR_MEM8(0x6F) 1516 1517 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1518 1519 struct __reg_TIMSK1 { 1520 unsigned int toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */ 1521 unsigned int ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */ 1522 unsigned int ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */ 1523 unsigned int ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */ 1524 unsigned int : 1; 1525 unsigned int icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */ 1526 unsigned int : 2; 1527 }; 1528 1529 #define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1) 1530 1531 #endif /* __ASSEMBLER__ */ 1532 1533 /* TIMSK1 */ 1534 1535 #define TOIE1 0 1536 #define OCIE1A 1 1537 #define OCIE1B 2 1538 #define OCIE1C 3 1539 #define ICIE1 5 1540 1541 /* Timer/Counter Interrupt Mask register */ 1542 #define TIMSK2 _SFR_MEM8(0x70) 1543 1544 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1545 1546 struct __reg_TIMSK2 { 1547 unsigned int toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */ 1548 unsigned int ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */ 1549 unsigned int ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */ 1550 unsigned int : 5; 1551 }; 1552 1553 #define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2) 1554 1555 #endif /* __ASSEMBLER__ */ 1556 1557 /* TIMSK2 */ 1558 1559 #define TOIE2 0 1560 #define TOIE2A 0 1561 #define OCIE2A 1 1562 #define OCIE2B 2 1563 1564 /* Timer/Counter3 Interrupt Mask Register */ 1565 #define TIMSK3 _SFR_MEM8(0x71) 1566 1567 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1568 1569 struct __reg_TIMSK3 { 1570 unsigned int toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */ 1571 unsigned int ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */ 1572 unsigned int ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */ 1573 unsigned int ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */ 1574 unsigned int : 1; 1575 unsigned int icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */ 1576 unsigned int : 2; 1577 }; 1578 1579 #define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3) 1580 1581 #endif /* __ASSEMBLER__ */ 1582 1583 /* TIMSK3 */ 1584 1585 #define TOIE3 0 1586 #define OCIE3A 1 1587 #define OCIE3B 2 1588 #define OCIE3C 3 1589 #define ICIE3 5 1590 1591 /* Timer/Counter4 Interrupt Mask Register */ 1592 #define TIMSK4 _SFR_MEM8(0x72) 1593 1594 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1595 1596 struct __reg_TIMSK4 { 1597 unsigned int toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */ 1598 unsigned int ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */ 1599 unsigned int ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */ 1600 unsigned int ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */ 1601 unsigned int : 1; 1602 unsigned int icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */ 1603 unsigned int : 2; 1604 }; 1605 1606 #define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4) 1607 1608 #endif /* __ASSEMBLER__ */ 1609 1610 /* TIMSK4 */ 1611 1612 #define TOIE4 0 1613 #define OCIE4A 1 1614 #define OCIE4B 2 1615 #define OCIE4C 3 1616 #define ICIE4 5 1617 1618 /* Timer/Counter5 Interrupt Mask Register */ 1619 #define TIMSK5 _SFR_MEM8(0x73) 1620 1621 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1622 1623 struct __reg_TIMSK5 { 1624 unsigned int toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */ 1625 unsigned int ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */ 1626 unsigned int ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */ 1627 unsigned int ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */ 1628 unsigned int : 1; 1629 unsigned int icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */ 1630 unsigned int : 2; 1631 }; 1632 1633 #define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5) 1634 1635 #endif /* __ASSEMBLER__ */ 1636 1637 /* TIMSK5 */ 1638 1639 #define TOIE5 0 1640 #define OCIE5A 1 1641 #define OCIE5B 2 1642 #define OCIE5C 3 1643 #define ICIE5 5 1644 1645 /* Flash Extended-Mode Control-Register */ 1646 #define NEMCR _SFR_MEM8(0x75) 1647 1648 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1649 1650 struct __reg_NEMCR { 1651 unsigned int : 4; 1652 unsigned int aeam : 2; /* Address for Extended Address Mode of Extra Rows */ 1653 unsigned int eneam : 1; /* Enable Extended Address Mode for Extra Rows */ 1654 unsigned int : 1; 1655 }; 1656 1657 #define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR) 1658 1659 #endif /* __ASSEMBLER__ */ 1660 1661 /* NEMCR */ 1662 1663 #define AEAM0 4 1664 #define AEAM1 5 1665 #define ENEAM 6 1666 1667 /* The ADC Control and Status Register C */ 1668 #define ADCSRC _SFR_MEM8(0x77) 1669 1670 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1671 1672 struct __reg_ADCSRC { 1673 unsigned int adsut : 5; /* ADC Start-up Time */ 1674 unsigned int res0 : 1; /* Reserved */ 1675 unsigned int adtht : 2; /* ADC Track-and-Hold Time */ 1676 }; 1677 1678 #define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC) 1679 1680 #endif /* __ASSEMBLER__ */ 1681 1682 /* ADCSRC */ 1683 1684 #define ADSUT0 0 1685 #define ADSUT1 1 1686 #define ADSUT2 2 1687 #define ADSUT3 3 1688 #define ADSUT4 4 1689 #define ADTHT0 6 1690 #define ADTHT1 7 1691 1692 /* ADC Data Register Bytes */ 1693 #ifndef __ASSEMBLER__ 1694 #define ADC _SFR_MEM16(0x78) 1695 #define ADCL _SFR_MEM8(0x78) 1696 #define ADCH _SFR_MEM8(0x79) 1697 #endif /* __ASSEMBLER__ */ 1698 #define ADCW _SFR_MEM16(0x78) 1699 #define ADCWL _SFR_MEM8(0x78) 1700 #define ADCWH _SFR_MEM8(0x79) 1701 1702 /* The ADC Control and Status Register A */ 1703 #define ADCSRA _SFR_MEM8(0x7A) 1704 1705 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1706 1707 struct __reg_ADCSRA { 1708 unsigned int adps : 3; /* ADC Prescaler Select Bits */ 1709 unsigned int adie : 1; /* ADC Interrupt Enable */ 1710 unsigned int adif : 1; /* ADC Interrupt Flag */ 1711 unsigned int adate : 1; /* ADC Auto Trigger Enable */ 1712 unsigned int adsc : 1; /* ADC Start Conversion */ 1713 unsigned int aden : 1; /* ADC Enable */ 1714 }; 1715 1716 #define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA) 1717 1718 #endif /* __ASSEMBLER__ */ 1719 1720 /* ADCSRA */ 1721 1722 #define ADPS0 0 1723 #define ADPS1 1 1724 #define ADPS2 2 1725 #define ADIE 3 1726 #define ADIF 4 1727 #define ADATE 5 1728 #define ADSC 6 1729 #define ADEN 7 1730 1731 /* ADC Control and Status Register B */ 1732 #define ADCSRB _SFR_MEM8(0x7B) 1733 1734 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1735 1736 struct __reg_ADCSRB { 1737 unsigned int adts : 3; /* ADC Auto Trigger Source */ 1738 unsigned int mux5 : 1; /* Analog Channel and Gain Selection Bits */ 1739 unsigned int acch : 1; /* Analog Channel Change */ 1740 unsigned int refok : 1; /* Reference Voltage OK */ 1741 unsigned int acme : 1; /* Analog Comparator Multiplexer Enable */ 1742 unsigned int avddok : 1; /* AVDD Supply Voltage OK */ 1743 }; 1744 1745 #define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB) 1746 1747 #endif /* __ASSEMBLER__ */ 1748 1749 /* ADCSRB */ 1750 1751 #define ADTS0 0 1752 #define ADTS1 1 1753 #define ADTS2 2 1754 #define MUX5 3 1755 #define ACCH 4 1756 #define REFOK 5 1757 #define ACME 6 1758 #define AVDDOK 7 1759 1760 /* The ADC Multiplexer Selection Register */ 1761 #define ADMUX _SFR_MEM8(0x7C) 1762 1763 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1764 1765 struct __reg_ADMUX { 1766 unsigned int mux : 5; /* Analog Channel and Gain Selection Bits */ 1767 unsigned int adlar : 1; /* ADC Left Adjust Result */ 1768 unsigned int refs : 2; /* Reference Selection Bits */ 1769 }; 1770 1771 #define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX) 1772 1773 #endif /* __ASSEMBLER__ */ 1774 1775 /* ADMUX */ 1776 1777 #define MUX0 0 1778 #define MUX1 1 1779 #define MUX2 2 1780 #define MUX3 3 1781 #define MUX4 4 1782 #define ADLAR 5 1783 #define REFS0 6 1784 #define REFS1 7 1785 1786 /* Digital Input Disable Register 2 */ 1787 #define DIDR2 _SFR_MEM8(0x7D) 1788 1789 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1790 1791 struct __reg_DIDR2 { 1792 unsigned int adc8d : 1; /* Reserved Bits */ 1793 unsigned int adc9d : 1; /* Reserved Bits */ 1794 unsigned int adc10d : 1; /* Reserved Bits */ 1795 unsigned int adc11d : 1; /* Reserved Bits */ 1796 unsigned int adc12d : 1; /* Reserved Bits */ 1797 unsigned int adc13d : 1; /* Reserved Bits */ 1798 unsigned int adc14d : 1; /* Reserved Bits */ 1799 unsigned int adc15d : 1; /* Reserved Bits */ 1800 }; 1801 1802 #define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2) 1803 1804 #endif /* __ASSEMBLER__ */ 1805 1806 /* DIDR2 */ 1807 1808 #define ADC8D 0 1809 #define ADC9D 1 1810 #define ADC10D 2 1811 #define ADC11D 3 1812 #define ADC12D 4 1813 #define ADC13D 5 1814 #define ADC14D 6 1815 #define ADC15D 7 1816 1817 /* Digital Input Disable Register 0 */ 1818 #define DIDR0 _SFR_MEM8(0x7E) 1819 1820 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1821 1822 struct __reg_DIDR0 { 1823 unsigned int adc0d : 1; /* Disable ADC7:0 Digital Input */ 1824 unsigned int adc1d : 1; /* Disable ADC7:0 Digital Input */ 1825 unsigned int adc2d : 1; /* Disable ADC7:0 Digital Input */ 1826 unsigned int adc3d : 1; /* Disable ADC7:0 Digital Input */ 1827 unsigned int adc4d : 1; /* Disable ADC7:0 Digital Input */ 1828 unsigned int adc5d : 1; /* Disable ADC7:0 Digital Input */ 1829 unsigned int adc6d : 1; /* Disable ADC7:0 Digital Input */ 1830 unsigned int adc7d : 1; /* Disable ADC7:0 Digital Input */ 1831 }; 1832 1833 #define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0) 1834 1835 #endif /* __ASSEMBLER__ */ 1836 1837 /* DIDR0 */ 1838 1839 #define ADC0D 0 1840 #define ADC1D 1 1841 #define ADC2D 2 1842 #define ADC3D 3 1843 #define ADC4D 4 1844 #define ADC5D 5 1845 #define ADC6D 6 1846 #define ADC7D 7 1847 1848 /* Digital Input Disable Register 1 */ 1849 #define DIDR1 _SFR_MEM8(0x7F) 1850 1851 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1852 1853 struct __reg_DIDR1 { 1854 unsigned int ain0d : 1; /* AIN0 Digital Input Disable */ 1855 unsigned int ain1d : 1; /* AIN1 Digital Input Disable */ 1856 unsigned int : 6; 1857 }; 1858 1859 #define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1) 1860 1861 #endif /* __ASSEMBLER__ */ 1862 1863 /* DIDR1 */ 1864 1865 #define AIN0D 0 1866 #define AIN1D 1 1867 1868 /* Timer/Counter1 Control Register A */ 1869 #define TCCR1A _SFR_MEM8(0x80) 1870 1871 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1872 1873 struct __reg_TCCR1A { 1874 unsigned int wgm1 : 2; /* Waveform Generation Mode */ 1875 unsigned int com1c : 2; /* Compare Output Mode for Channel C */ 1876 unsigned int com1b : 2; /* Compare Output Mode for Channel B */ 1877 unsigned int com1a : 2; /* Compare Output Mode for Channel A */ 1878 }; 1879 1880 #define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A) 1881 1882 #endif /* __ASSEMBLER__ */ 1883 1884 /* TCCR1A */ 1885 1886 #define WGM10 0 1887 #define WGM11 1 1888 #define COM1C0 2 1889 #define COM1C1 3 1890 #define COM1B0 4 1891 #define COM1B1 5 1892 #define COM1A0 6 1893 #define COM1A1 7 1894 1895 /* Timer/Counter1 Control Register B */ 1896 #define TCCR1B _SFR_MEM8(0x81) 1897 1898 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1899 1900 struct __reg_TCCR1B { 1901 unsigned int cs1 : 3; /* Clock Select */ 1902 unsigned int wgm1 : 2; /* Waveform Generation Mode */ 1903 unsigned int : 1; 1904 unsigned int ices1 : 1; /* Input Capture 1 Edge Select */ 1905 unsigned int icnc1 : 1; /* Input Capture 1 Noise Canceller */ 1906 }; 1907 1908 #define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B) 1909 1910 #endif /* __ASSEMBLER__ */ 1911 1912 /* TCCR1B */ 1913 1914 #define CS10 0 1915 #define CS11 1 1916 #define CS12 2 1917 #define WGM12 3 1918 #define WGM13 4 1919 #define ICES1 6 1920 #define ICNC1 7 1921 1922 /* Timer/Counter1 Control Register C */ 1923 #define TCCR1C _SFR_MEM8(0x82) 1924 1925 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1926 1927 struct __reg_TCCR1C { 1928 unsigned int : 5; 1929 unsigned int foc1c : 1; /* Force Output Compare for Channel C */ 1930 unsigned int foc1b : 1; /* Force Output Compare for Channel B */ 1931 unsigned int foc1a : 1; /* Force Output Compare for Channel A */ 1932 }; 1933 1934 #define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C) 1935 1936 #endif /* __ASSEMBLER__ */ 1937 1938 /* TCCR1C */ 1939 1940 #define FOC1C 5 1941 #define FOC1B 6 1942 #define FOC1A 7 1943 1944 /* Timer/Counter1 Bytes */ 1945 #define TCNT1 _SFR_MEM16(0x84) 1946 #define TCNT1L _SFR_MEM8(0x84) 1947 #define TCNT1H _SFR_MEM8(0x85) 1948 1949 /* Timer/Counter1 Input Capture Register Bytes */ 1950 #define ICR1 _SFR_MEM16(0x86) 1951 #define ICR1L _SFR_MEM8(0x86) 1952 #define ICR1H _SFR_MEM8(0x87) 1953 1954 /* Timer/Counter1 Output Compare Register A Bytes */ 1955 #define OCR1A _SFR_MEM16(0x88) 1956 #define OCR1AL _SFR_MEM8(0x88) 1957 #define OCR1AH _SFR_MEM8(0x89) 1958 1959 /* Timer/Counter1 Output Compare Register B Bytes */ 1960 #define OCR1B _SFR_MEM16(0x8A) 1961 #define OCR1BL _SFR_MEM8(0x8A) 1962 #define OCR1BH _SFR_MEM8(0x8B) 1963 1964 /* Timer/Counter1 Output Compare Register C Bytes */ 1965 #define OCR1C _SFR_MEM16(0x8C) 1966 #define OCR1CL _SFR_MEM8(0x8C) 1967 #define OCR1CH _SFR_MEM8(0x8D) 1968 1969 /* Timer/Counter3 Control Register A */ 1970 #define TCCR3A _SFR_MEM8(0x90) 1971 1972 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1973 1974 struct __reg_TCCR3A { 1975 unsigned int wgm3 : 2; /* Waveform Generation Mode */ 1976 unsigned int com3c : 2; /* Compare Output Mode for Channel C */ 1977 unsigned int com3b : 2; /* Compare Output Mode for Channel B */ 1978 unsigned int com3a : 2; /* Compare Output Mode for Channel A */ 1979 }; 1980 1981 #define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A) 1982 1983 #endif /* __ASSEMBLER__ */ 1984 1985 /* TCCR3A */ 1986 1987 #define WGM30 0 1988 #define WGM31 1 1989 #define COM3C0 2 1990 #define COM3C1 3 1991 #define COM3B0 4 1992 #define COM3B1 5 1993 #define COM3A0 6 1994 #define COM3A1 7 1995 1996 /* Timer/Counter3 Control Register B */ 1997 #define TCCR3B _SFR_MEM8(0x91) 1998 1999 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2000 2001 struct __reg_TCCR3B { 2002 unsigned int cs3 : 3; /* Clock Select */ 2003 unsigned int wgm3 : 2; /* Waveform Generation Mode */ 2004 unsigned int : 1; 2005 unsigned int ices3 : 1; /* Input Capture 3 Edge Select */ 2006 unsigned int icnc3 : 1; /* Input Capture 3 Noise Canceller */ 2007 }; 2008 2009 #define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B) 2010 2011 #endif /* __ASSEMBLER__ */ 2012 2013 /* TCCR3B */ 2014 2015 #define CS30 0 2016 #define CS31 1 2017 #define CS32 2 2018 #define WGM32 3 2019 #define WGM33 4 2020 #define ICES3 6 2021 #define ICNC3 7 2022 2023 /* Timer/Counter3 Control Register C */ 2024 #define TCCR3C _SFR_MEM8(0x92) 2025 2026 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2027 2028 struct __reg_TCCR3C { 2029 unsigned int : 5; 2030 unsigned int foc3c : 1; /* Force Output Compare for Channel C */ 2031 unsigned int foc3b : 1; /* Force Output Compare for Channel B */ 2032 unsigned int foc3a : 1; /* Force Output Compare for Channel A */ 2033 }; 2034 2035 #define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C) 2036 2037 #endif /* __ASSEMBLER__ */ 2038 2039 /* TCCR3C */ 2040 2041 #define FOC3C 5 2042 #define FOC3B 6 2043 #define FOC3A 7 2044 2045 /* Timer/Counter3 Bytes */ 2046 #define TCNT3 _SFR_MEM16(0x94) 2047 #define TCNT3L _SFR_MEM8(0x94) 2048 #define TCNT3H _SFR_MEM8(0x95) 2049 2050 /* Timer/Counter3 Input Capture Register Bytes */ 2051 #define ICR3 _SFR_MEM16(0x96) 2052 #define ICR3L _SFR_MEM8(0x96) 2053 #define ICR3H _SFR_MEM8(0x97) 2054 2055 /* Timer/Counter3 Output Compare Register A Bytes */ 2056 #define OCR3A _SFR_MEM16(0x98) 2057 #define OCR3AL _SFR_MEM8(0x98) 2058 #define OCR3AH _SFR_MEM8(0x99) 2059 2060 /* Timer/Counter3 Output Compare Register B Bytes */ 2061 #define OCR3B _SFR_MEM16(0x9A) 2062 #define OCR3BL _SFR_MEM8(0x9A) 2063 #define OCR3BH _SFR_MEM8(0x9B) 2064 2065 /* Timer/Counter3 Output Compare Register C Bytes */ 2066 #define OCR3C _SFR_MEM16(0x9C) 2067 #define OCR3CL _SFR_MEM8(0x9C) 2068 #define OCR3CH _SFR_MEM8(0x9D) 2069 2070 /* Timer/Counter4 Control Register A */ 2071 #define TCCR4A _SFR_MEM8(0xA0) 2072 2073 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2074 2075 struct __reg_TCCR4A { 2076 unsigned int wgm4 : 2; /* Waveform Generation Mode */ 2077 unsigned int com4c : 2; /* Compare Output Mode for Channel C */ 2078 unsigned int com4b : 2; /* Compare Output Mode for Channel B */ 2079 unsigned int com4a : 2; /* Compare Output Mode for Channel A */ 2080 }; 2081 2082 #define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A) 2083 2084 #endif /* __ASSEMBLER__ */ 2085 2086 /* TCCR4A */ 2087 2088 #define WGM40 0 2089 #define WGM41 1 2090 #define COM4C0 2 2091 #define COM4C1 3 2092 #define COM4B0 4 2093 #define COM4B1 5 2094 #define COM4A0 6 2095 #define COM4A1 7 2096 2097 /* Timer/Counter4 Control Register B */ 2098 #define TCCR4B _SFR_MEM8(0xA1) 2099 2100 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2101 2102 struct __reg_TCCR4B { 2103 unsigned int cs4 : 3; /* Clock Select */ 2104 unsigned int wgm4 : 2; /* Waveform Generation Mode */ 2105 unsigned int : 1; 2106 unsigned int ices4 : 1; /* Input Capture 4 Edge Select */ 2107 unsigned int icnc4 : 1; /* Input Capture 4 Noise Canceller */ 2108 }; 2109 2110 #define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B) 2111 2112 #endif /* __ASSEMBLER__ */ 2113 2114 /* TCCR4B */ 2115 2116 #define CS40 0 2117 #define CS41 1 2118 #define CS42 2 2119 #define WGM42 3 2120 #define WGM43 4 2121 #define ICES4 6 2122 #define ICNC4 7 2123 2124 /* Timer/Counter4 Control Register C */ 2125 #define TCCR4C _SFR_MEM8(0xA2) 2126 2127 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2128 2129 struct __reg_TCCR4C { 2130 unsigned int : 5; 2131 unsigned int foc4c : 1; /* Force Output Compare for Channel C */ 2132 unsigned int foc4b : 1; /* Force Output Compare for Channel B */ 2133 unsigned int foc4a : 1; /* Force Output Compare for Channel A */ 2134 }; 2135 2136 #define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C) 2137 2138 #endif /* __ASSEMBLER__ */ 2139 2140 /* TCCR4C */ 2141 2142 #define FOC4C 5 2143 #define FOC4B 6 2144 #define FOC4A 7 2145 2146 /* Timer/Counter4 Bytes */ 2147 #define TCNT4 _SFR_MEM16(0xA4) 2148 #define TCNT4L _SFR_MEM8(0xA4) 2149 #define TCNT4H _SFR_MEM8(0xA5) 2150 2151 /* Timer/Counter4 Input Capture Register Bytes */ 2152 #define ICR4 _SFR_MEM16(0xA6) 2153 #define ICR4L _SFR_MEM8(0xA6) 2154 #define ICR4H _SFR_MEM8(0xA7) 2155 2156 /* Timer/Counter4 Output Compare Register A Bytes */ 2157 #define OCR4A _SFR_MEM16(0xA8) 2158 #define OCR4AL _SFR_MEM8(0xA8) 2159 #define OCR4AH _SFR_MEM8(0xA9) 2160 2161 /* Timer/Counter4 Output Compare Register B Bytes */ 2162 #define OCR4B _SFR_MEM16(0xAA) 2163 #define OCR4BL _SFR_MEM8(0xAA) 2164 #define OCR4BH _SFR_MEM8(0xAB) 2165 2166 /* Timer/Counter4 Output Compare Register C Bytes */ 2167 #define OCR4C _SFR_MEM16(0xAC) 2168 #define OCR4CL _SFR_MEM8(0xAC) 2169 #define OCR4CH _SFR_MEM8(0xAD) 2170 2171 /* Timer/Counter2 Control Register A */ 2172 #define TCCR2A _SFR_MEM8(0xB0) 2173 2174 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2175 2176 struct __reg_TCCR2A { 2177 unsigned int wgm2 : 2; /* Waveform Generation Mode */ 2178 unsigned int : 2; 2179 unsigned int com2b : 2; /* Compare Match Output B Mode */ 2180 unsigned int com2a : 2; /* Compare Match Output A Mode */ 2181 }; 2182 2183 #define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A) 2184 2185 #endif /* __ASSEMBLER__ */ 2186 2187 /* TCCR2A */ 2188 2189 #define WGM20 0 2190 #define WGM21 1 2191 #define COM2B0 4 2192 #define COM2B1 5 2193 #define COM2A0 6 2194 #define COM2A1 7 2195 2196 /* Timer/Counter2 Control Register B */ 2197 #define TCCR2B _SFR_MEM8(0xB1) 2198 2199 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2200 2201 struct __reg_TCCR2B { 2202 unsigned int cs2 : 3; /* Clock Select */ 2203 unsigned int wgm22 : 1; /* Waveform Generation Mode */ 2204 unsigned int : 2; 2205 unsigned int foc2b : 1; /* Force Output Compare B */ 2206 unsigned int foc2a : 1; /* Force Output Compare A */ 2207 }; 2208 2209 #define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B) 2210 2211 #endif /* __ASSEMBLER__ */ 2212 2213 /* TCCR2B */ 2214 2215 #define CS20 0 2216 #define CS21 1 2217 #define CS22 2 2218 #define WGM22 3 2219 #define FOC2B 6 2220 #define FOC2A 7 2221 2222 /* Timer/Counter2 */ 2223 #define TCNT2 _SFR_MEM8(0xB2) 2224 2225 /* TCNT2 */ 2226 2227 #define TCNT20 0 2228 #define TCNT21 1 2229 #define TCNT22 2 2230 #define TCNT23 3 2231 #define TCNT24 4 2232 #define TCNT25 5 2233 #define TCNT26 6 2234 #define TCNT27 7 2235 2236 /* Timer/Counter2 Output Compare Register A */ 2237 #define OCR2A _SFR_MEM8(0xB3) 2238 2239 /* OCR2A */ 2240 2241 #define OCR2A0 0 2242 #define OCR2A1 1 2243 #define OCR2A2 2 2244 #define OCR2A3 3 2245 #define OCR2A4 4 2246 #define OCR2A5 5 2247 #define OCR2A6 6 2248 #define OCR2A7 7 2249 2250 /* Timer/Counter2 Output Compare Register B */ 2251 #define OCR2B _SFR_MEM8(0xB4) 2252 2253 /* OCR2B */ 2254 2255 #define OCR2B0 0 2256 #define OCR2B1 1 2257 #define OCR2B2 2 2258 #define OCR2B3 3 2259 #define OCR2B4 4 2260 #define OCR2B5 5 2261 #define OCR2B6 6 2262 #define OCR2B7 7 2263 2264 /* Asynchronous Status Register */ 2265 #define ASSR _SFR_MEM8(0xB6) 2266 2267 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2268 2269 struct __reg_ASSR { 2270 unsigned int tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */ 2271 unsigned int tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */ 2272 unsigned int ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */ 2273 unsigned int ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */ 2274 unsigned int tcn2ub : 1; /* Timer/Counter2 Update Busy */ 2275 unsigned int as2 : 1; /* Timer/Counter2 Asynchronous Mode */ 2276 unsigned int exclk : 1; /* Enable External Clock Input */ 2277 unsigned int exclkamr : 1; /* Enable External Clock Input for AMR */ 2278 }; 2279 2280 #define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR) 2281 2282 #endif /* __ASSEMBLER__ */ 2283 2284 /* ASSR */ 2285 2286 #define TCR2BUB 0 2287 #define TCR2AUB 1 2288 #define OCR2BUB 2 2289 #define OCR2AUB 3 2290 #define TCN2UB 4 2291 #define AS2 5 2292 #define EXCLK 6 2293 #define EXCLKAMR 7 2294 2295 /* TWI Bit Rate Register */ 2296 #define TWBR _SFR_MEM8(0xB8) 2297 2298 /* TWBR */ 2299 2300 #define TWBR0 0 2301 #define TWBR1 1 2302 #define TWBR2 2 2303 #define TWBR3 3 2304 #define TWBR4 4 2305 #define TWBR5 5 2306 #define TWBR6 6 2307 #define TWBR7 7 2308 2309 /* TWI Status Register */ 2310 #define TWSR _SFR_MEM8(0xB9) 2311 2312 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2313 2314 struct __reg_TWSR { 2315 unsigned int twps : 2; /* TWI Prescaler Bits */ 2316 unsigned int : 1; 2317 unsigned int tws : 5; /* TWI Status */ 2318 }; 2319 2320 #define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR) 2321 2322 #endif /* __ASSEMBLER__ */ 2323 2324 /* TWSR */ 2325 2326 #define TWPS0 0 2327 #define TWPS1 1 2328 #define TWS3 3 2329 #define TWS4 4 2330 #define TWS5 5 2331 #define TWS6 6 2332 #define TWS7 7 2333 2334 /* TWI (Slave) Address Register */ 2335 #define TWAR _SFR_MEM8(0xBA) 2336 2337 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2338 2339 struct __reg_TWAR { 2340 unsigned int twgce : 1; /* TWI General Call Recognition Enable Bit */ 2341 unsigned int twa : 7; /* TWI (Slave) Address */ 2342 }; 2343 2344 #define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR) 2345 2346 #endif /* __ASSEMBLER__ */ 2347 2348 /* TWAR */ 2349 2350 #define TWGCE 0 2351 #define TWA0 1 2352 #define TWA1 2 2353 #define TWA2 3 2354 #define TWA3 4 2355 #define TWA4 5 2356 #define TWA5 6 2357 #define TWA6 7 2358 2359 /* TWI Data Register */ 2360 #define TWDR _SFR_MEM8(0xBB) 2361 2362 /* TWDR */ 2363 2364 #define TWD0 0 2365 #define TWD1 1 2366 #define TWD2 2 2367 #define TWD3 3 2368 #define TWD4 4 2369 #define TWD5 5 2370 #define TWD6 6 2371 #define TWD7 7 2372 2373 /* TWI Control Register */ 2374 #define TWCR _SFR_MEM8(0xBC) 2375 2376 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2377 2378 struct __reg_TWCR { 2379 unsigned int twie : 1; /* TWI Interrupt Enable */ 2380 unsigned int : 1; 2381 unsigned int twen : 1; /* TWI Enable Bit */ 2382 unsigned int twwc : 1; /* TWI Write Collision Flag */ 2383 unsigned int twsto : 1; /* TWI STOP Condition Bit */ 2384 unsigned int twsta : 1; /* TWI START Condition Bit */ 2385 unsigned int twea : 1; /* TWI Enable Acknowledge Bit */ 2386 unsigned int twint : 1; /* TWI Interrupt Flag */ 2387 }; 2388 2389 #define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR) 2390 2391 #endif /* __ASSEMBLER__ */ 2392 2393 /* TWCR */ 2394 2395 #define TWIE 0 2396 #define TWEN 2 2397 #define TWWC 3 2398 #define TWSTO 4 2399 #define TWSTA 5 2400 #define TWEA 6 2401 #define TWINT 7 2402 2403 /* TWI (Slave) Address Mask Register */ 2404 #define TWAMR _SFR_MEM8(0xBD) 2405 2406 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2407 2408 struct __reg_TWAMR { 2409 unsigned int : 1; 2410 unsigned int twam : 7; /* TWI Address Mask */ 2411 }; 2412 2413 #define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR) 2414 2415 #endif /* __ASSEMBLER__ */ 2416 2417 /* TWAMR */ 2418 2419 #define TWAM0 1 2420 #define TWAMR0 1 2421 #define TWAM1 2 2422 #define TWAMR1 2 2423 #define TWAM2 3 2424 #define TWAMR2 3 2425 #define TWAM3 4 2426 #define TWAMR3 4 2427 #define TWAM4 5 2428 #define TWAMR4 5 2429 #define TWAM5 6 2430 #define TWAMR5 6 2431 #define TWAM6 7 2432 #define TWAMR6 7 2433 2434 /* Transceiver Interrupt Enable Register 1 */ 2435 #define IRQ_MASK1 _SFR_MEM8(0xBE) 2436 2437 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2438 2439 struct __reg_IRQ_MASK1 { 2440 unsigned int tx_start_en : 1; /* Transmit Start Interrupt enable */ 2441 unsigned int maf_0_ami_en : 1; /* Address Match Interrupt enable Address filter 0 */ 2442 unsigned int maf_1_ami_en : 1; /* Address Match Interrupt enable Address filter 1 */ 2443 unsigned int maf_2_ami_en : 1; /* Address Match Interrupt enable Address filter 2 */ 2444 unsigned int maf_3_ami_en : 1; /* Address Match Interrupt enable Address filter 3 */ 2445 unsigned int : 3; 2446 }; 2447 2448 #define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1) 2449 2450 #endif /* __ASSEMBLER__ */ 2451 2452 /* IRQ_MASK1 */ 2453 2454 #define TX_START_EN 0 2455 #define MAF_0_AMI_EN 1 2456 #define MAF_1_AMI_EN 2 2457 #define MAF_2_AMI_EN 3 2458 #define MAF_3_AMI_EN 4 2459 2460 /* Transceiver Interrupt Status Register 1 */ 2461 #define IRQ_STATUS1 _SFR_MEM8(0xBF) 2462 2463 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2464 2465 struct __reg_IRQ_STATUS1 { 2466 unsigned int tx_start : 1; /* Transmit Start Interrupt Status */ 2467 unsigned int maf_0_ami : 1; /* Address Match Interrupt Status Address filter 0 */ 2468 unsigned int maf_1_ami : 1; /* Address Match Interrupt Status Address filter 1 */ 2469 unsigned int maf_2_ami : 1; /* Address Match Interrupt Status Address filter 2 */ 2470 unsigned int maf_3_ami : 1; /* Address Match Interrupt Status Address filter 3 */ 2471 unsigned int : 3; 2472 }; 2473 2474 #define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1) 2475 2476 #endif /* __ASSEMBLER__ */ 2477 2478 /* IRQ_STATUS1 */ 2479 2480 #define TX_START 0 2481 #define MAF_0_AMI 1 2482 #define MAF_1_AMI 2 2483 #define MAF_2_AMI 3 2484 #define MAF_3_AMI 4 2485 2486 /* USART0 Control and Status Register A */ 2487 #define UCSR0A _SFR_MEM8(0xC0) 2488 2489 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2490 2491 struct __reg_UCSR0A { 2492 unsigned int mpcm0 : 1; /* Multi-processor Communication Mode */ 2493 unsigned int u2x0 : 1; /* Double the USART Transmission Speed */ 2494 unsigned int upe0 : 1; /* USART Parity Error */ 2495 unsigned int dor0 : 1; /* Data OverRun */ 2496 unsigned int fe0 : 1; /* Frame Error */ 2497 unsigned int udre0 : 1; /* USART Data Register Empty */ 2498 unsigned int txc0 : 1; /* USART Transmit Complete */ 2499 unsigned int rxc0 : 1; /* USART Receive Complete */ 2500 }; 2501 2502 #define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A) 2503 2504 #endif /* __ASSEMBLER__ */ 2505 2506 /* UCSR0A */ 2507 2508 #define MPCM0 0 2509 #define U2X0 1 2510 #define UPE0 2 2511 #define DOR0 3 2512 #define FE0 4 2513 #define UDRE0 5 2514 #define TXC0 6 2515 #define RXC0 7 2516 2517 /* USART0 Control and Status Register B */ 2518 #define UCSR0B _SFR_MEM8(0xC1) 2519 2520 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2521 2522 struct __reg_UCSR0B { 2523 unsigned int txb80 : 1; /* Transmit Data Bit 8 */ 2524 unsigned int rxb80 : 1; /* Receive Data Bit 8 */ 2525 unsigned int ucsz02 : 1; /* Character Size */ 2526 unsigned int txen0 : 1; /* Transmitter Enable */ 2527 unsigned int rxen0 : 1; /* Receiver Enable */ 2528 unsigned int udrie0 : 1; /* USART Data Register Empty Interrupt Enable */ 2529 unsigned int txcie0 : 1; /* TX Complete Interrupt Enable */ 2530 unsigned int rxcie0 : 1; /* RX Complete Interrupt Enable */ 2531 }; 2532 2533 #define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B) 2534 2535 #endif /* __ASSEMBLER__ */ 2536 2537 /* UCSR0B */ 2538 2539 #define TXB80 0 2540 #define RXB80 1 2541 #define UCSZ02 2 2542 #define TXEN0 3 2543 #define RXEN0 4 2544 #define UDRIE0 5 2545 #define TXCIE0 6 2546 #define RXCIE0 7 2547 2548 /* USART0 Control and Status Register C */ 2549 #define UCSR0C _SFR_MEM8(0xC2) 2550 2551 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2552 2553 struct __reg_UCSR0C { 2554 unsigned int ucpol0 : 1; /* Clock Polarity */ 2555 unsigned int ucsz0 : 2; /* Character Size */ 2556 unsigned int ucpha0 : 1; /* Clock Phase */ 2557 unsigned int udord0 : 1; /* Data Order */ 2558 unsigned int usbs0 : 1; /* Stop Bit Select */ 2559 unsigned int upm0 : 2; /* Parity Mode */ 2560 unsigned int umsel0 : 2; /* USART Mode Select */ 2561 }; 2562 2563 #define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C) 2564 2565 #endif /* __ASSEMBLER__ */ 2566 2567 /* UCSR0C */ 2568 2569 #define UCPOL0 0 2570 #define UCPHA0 1 2571 #define UCPHA0 1 2572 #define UCSZ00 1 2573 #define UDORD0 2 2574 #define UDORD0 2 2575 #define UCSZ01 2 2576 #define USBS0 3 2577 #define UPM00 4 2578 #define UPM01 5 2579 #define UMSEL00 6 2580 #define UMSEL0 6 2581 #define UMSEL01 7 2582 #define UMSEL1 7 2583 2584 /* USART0 Baud Rate Register Bytes */ 2585 #define UBRR0 _SFR_MEM16(0xC4) 2586 #define UBRR0L _SFR_MEM8(0xC4) 2587 #define UBRR0H _SFR_MEM8(0xC5) 2588 2589 /* USART0 I/O Data Register */ 2590 #define UDR0 _SFR_MEM8(0xC6) 2591 2592 /* UDR0 */ 2593 2594 #define UDR00 0 2595 #define UDR01 1 2596 #define UDR02 2 2597 #define UDR03 3 2598 #define UDR04 4 2599 #define UDR05 5 2600 #define UDR06 6 2601 #define UDR07 7 2602 2603 /* USART1 Control and Status Register A */ 2604 #define UCSR1A _SFR_MEM8(0xC8) 2605 2606 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2607 2608 struct __reg_UCSR1A { 2609 unsigned int mpcm1 : 1; /* Multi-processor Communication Mode */ 2610 unsigned int u2x1 : 1; /* Double the USART Transmission Speed */ 2611 unsigned int upe1 : 1; /* USART Parity Error */ 2612 unsigned int dor1 : 1; /* Data OverRun */ 2613 unsigned int fe1 : 1; /* Frame Error */ 2614 unsigned int udre1 : 1; /* USART Data Register Empty */ 2615 unsigned int txc1 : 1; /* USART Transmit Complete */ 2616 unsigned int rxc1 : 1; /* USART Receive Complete */ 2617 }; 2618 2619 #define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A) 2620 2621 #endif /* __ASSEMBLER__ */ 2622 2623 /* UCSR1A */ 2624 2625 #define MPCM1 0 2626 #define U2X1 1 2627 #define UPE1 2 2628 #define DOR1 3 2629 #define FE1 4 2630 #define UDRE1 5 2631 #define TXC1 6 2632 #define RXC1 7 2633 2634 /* USART1 Control and Status Register B */ 2635 #define UCSR1B _SFR_MEM8(0xC9) 2636 2637 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2638 2639 struct __reg_UCSR1B { 2640 unsigned int txb81 : 1; /* Transmit Data Bit 8 */ 2641 unsigned int rxb81 : 1; /* Receive Data Bit 8 */ 2642 unsigned int ucsz12 : 1; /* Character Size */ 2643 unsigned int txen1 : 1; /* Transmitter Enable */ 2644 unsigned int rxen1 : 1; /* Receiver Enable */ 2645 unsigned int udrie1 : 1; /* USART Data Register Empty Interrupt Enable */ 2646 unsigned int txcie1 : 1; /* TX Complete Interrupt Enable */ 2647 unsigned int rxcie1 : 1; /* RX Complete Interrupt Enable */ 2648 }; 2649 2650 #define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B) 2651 2652 #endif /* __ASSEMBLER__ */ 2653 2654 /* UCSR1B */ 2655 2656 #define TXB81 0 2657 #define RXB81 1 2658 #define UCSZ12 2 2659 #define TXEN1 3 2660 #define RXEN1 4 2661 #define UDRIE1 5 2662 #define TXCIE1 6 2663 #define RXCIE1 7 2664 2665 /* USART1 Control and Status Register C */ 2666 #define UCSR1C _SFR_MEM8(0xCA) 2667 2668 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2669 2670 struct __reg_UCSR1C { 2671 unsigned int ucpol1 : 1; /* Clock Polarity */ 2672 unsigned int ucsz1 : 2; /* Character Size */ 2673 unsigned int ucpha1 : 1; /* Clock Phase */ 2674 unsigned int udord1 : 1; /* Data Order */ 2675 unsigned int usbs1 : 1; /* Stop Bit Select */ 2676 unsigned int upm1 : 2; /* Parity Mode */ 2677 unsigned int umsel1 : 2; /* USART Mode Select */ 2678 }; 2679 2680 #define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C) 2681 2682 #endif /* __ASSEMBLER__ */ 2683 2684 /* UCSR1C */ 2685 2686 #define UCPOL1 0 2687 #define UCPHA1 1 2688 #define UCPHA1 1 2689 #define UCSZ10 1 2690 #define UDORD1 2 2691 #define UDORD1 2 2692 #define UCSZ11 2 2693 #define USBS1 3 2694 #define UPM10 4 2695 #define UPM11 5 2696 #define UMSEL10 6 2697 #define UMSEL11 7 2698 2699 /* USART1 Baud Rate Register Bytes */ 2700 #define UBRR1 _SFR_MEM16(0xCC) 2701 #define UBRR1L _SFR_MEM8(0xCC) 2702 #define UBRR1H _SFR_MEM8(0xCD) 2703 2704 /* USART1 I/O Data Register */ 2705 #define UDR1 _SFR_MEM8(0xCE) 2706 2707 /* UDR1 */ 2708 2709 #define UDR10 0 2710 #define UDR11 1 2711 #define UDR12 2 2712 #define UDR13 3 2713 #define UDR14 4 2714 #define UDR15 5 2715 #define UDR16 6 2716 #define UDR17 7 2717 2718 /* Symbol Counter Received Frame Timestamp Register LL-Byte */ 2719 #define SCRSTRLL _SFR_MEM8(0xD7) 2720 2721 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2722 2723 struct __reg_SCRSTRLL { 2724 unsigned int scrstrll : 8; /* Symbol Counter Received Frame Timestamp Register LL-Byte */ 2725 }; 2726 2727 #define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL) 2728 2729 #endif /* __ASSEMBLER__ */ 2730 2731 /* SCRSTRLL */ 2732 2733 #define SCRSTRLL0 0 2734 #define SCRSTRLL1 1 2735 #define SCRSTRLL2 2 2736 #define SCRSTRLL3 3 2737 #define SCRSTRLL4 4 2738 #define SCRSTRLL5 5 2739 #define SCRSTRLL6 6 2740 #define SCRSTRLL7 7 2741 2742 /* Symbol Counter Received Frame Timestamp Register LH-Byte */ 2743 #define SCRSTRLH _SFR_MEM8(0xD8) 2744 2745 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2746 2747 struct __reg_SCRSTRLH { 2748 unsigned int scrstrlh : 8; /* Symbol Counter Received Frame Timestamp Register LH-Byte */ 2749 }; 2750 2751 #define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH) 2752 2753 #endif /* __ASSEMBLER__ */ 2754 2755 /* SCRSTRLH */ 2756 2757 #define SCRSTRLH0 0 2758 #define SCRSTRLH1 1 2759 #define SCRSTRLH2 2 2760 #define SCRSTRLH3 3 2761 #define SCRSTRLH4 4 2762 #define SCRSTRLH5 5 2763 #define SCRSTRLH6 6 2764 #define SCRSTRLH7 7 2765 2766 /* Symbol Counter Received Frame Timestamp Register HL-Byte */ 2767 #define SCRSTRHL _SFR_MEM8(0xD9) 2768 2769 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2770 2771 struct __reg_SCRSTRHL { 2772 unsigned int scrstrhl : 8; /* Symbol Counter Received Frame Timestamp Register HL-Byte */ 2773 }; 2774 2775 #define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL) 2776 2777 #endif /* __ASSEMBLER__ */ 2778 2779 /* SCRSTRHL */ 2780 2781 #define SCRSTRHL0 0 2782 #define SCRSTRHL1 1 2783 #define SCRSTRHL2 2 2784 #define SCRSTRHL3 3 2785 #define SCRSTRHL4 4 2786 #define SCRSTRHL5 5 2787 #define SCRSTRHL6 6 2788 #define SCRSTRHL7 7 2789 2790 /* Symbol Counter Received Frame Timestamp Register HH-Byte */ 2791 #define SCRSTRHH _SFR_MEM8(0xDA) 2792 2793 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2794 2795 struct __reg_SCRSTRHH { 2796 unsigned int scrstrhh : 8; /* Symbol Counter Received Frame Timestamp Register HH-Byte */ 2797 }; 2798 2799 #define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH) 2800 2801 #endif /* __ASSEMBLER__ */ 2802 2803 /* SCRSTRHH */ 2804 2805 #define SCRSTRHH0 0 2806 #define SCRSTRHH1 1 2807 #define SCRSTRHH2 2 2808 #define SCRSTRHH3 3 2809 #define SCRSTRHH4 4 2810 #define SCRSTRHH5 5 2811 #define SCRSTRHH6 6 2812 #define SCRSTRHH7 7 2813 2814 /* Symbol Counter Compare Source Register */ 2815 #define SCCSR _SFR_MEM8(0xDB) 2816 2817 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2818 2819 struct __reg_SCCSR { 2820 unsigned int sccs1 : 2; /* Symbol Counter Compare Source select register for Compare Units */ 2821 unsigned int sccs2 : 2; /* Symbol Counter Compare Source select register for Compare Unit 2 */ 2822 unsigned int sccs3 : 2; /* Symbol Counter Compare Source select register for Compare Unit 3 */ 2823 unsigned int : 2; 2824 }; 2825 2826 #define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR) 2827 2828 #endif /* __ASSEMBLER__ */ 2829 2830 /* SCCSR */ 2831 2832 #define SCCS10 0 2833 #define SCCS11 1 2834 #define SCCS20 2 2835 #define SCCS21 3 2836 #define SCCS30 4 2837 #define SCCS31 5 2838 2839 /* Symbol Counter Control Register 0 */ 2840 #define SCCR0 _SFR_MEM8(0xDC) 2841 2842 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2843 2844 struct __reg_SCCR0 { 2845 unsigned int sccmp : 3; /* Symbol Counter Compare Unit 3 Mode select */ 2846 unsigned int sctse : 1; /* Symbol Counter Automatic Timestamping enable */ 2847 unsigned int sccksel : 1; /* Symbol Counter Clock Source select */ 2848 unsigned int scen : 1; /* Symbol Counter enable */ 2849 unsigned int scmbts : 1; /* Manual Beacon Timestamp */ 2850 unsigned int scres : 1; /* Symbol Counter Synchronization */ 2851 }; 2852 2853 #define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0) 2854 2855 #endif /* __ASSEMBLER__ */ 2856 2857 /* SCCR0 */ 2858 2859 #define SCCMP1 0 2860 #define SCCMP2 1 2861 #define SCCMP3 2 2862 #define SCTSE 3 2863 #define SCCKSEL 4 2864 #define SCEN 5 2865 #define SCMBTS 6 2866 #define SCRES 7 2867 2868 /* Symbol Counter Control Register 1 */ 2869 #define SCCR1 _SFR_MEM8(0xDD) 2870 2871 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2872 2873 struct __reg_SCCR1 { 2874 unsigned int scenbo : 1; /* Backoff Slot Counter enable */ 2875 unsigned int sceeclk : 1; /* Enable External Clock Source on PG2 */ 2876 unsigned int scckdiv : 3; /* Clock divider for synchronous clock source (16MHz Transceiver Clock) */ 2877 unsigned int scbtsm : 1; /* Symbol Counter Beacon Timestamp Mask Register */ 2878 unsigned int : 2; 2879 }; 2880 2881 #define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1) 2882 2883 #endif /* __ASSEMBLER__ */ 2884 2885 /* SCCR1 */ 2886 2887 #define SCENBO 0 2888 #define SCEECLK 1 2889 #define SCCKDIV0 2 2890 #define SCCKDIV1 3 2891 #define SCCKDIV2 4 2892 #define SCBTSM 5 2893 2894 /* Symbol Counter Status Register */ 2895 #define SCSR _SFR_MEM8(0xDE) 2896 2897 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2898 2899 struct __reg_SCSR { 2900 unsigned int scbsy : 1; /* Symbol Counter busy */ 2901 unsigned int : 7; 2902 }; 2903 2904 #define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR) 2905 2906 #endif /* __ASSEMBLER__ */ 2907 2908 /* SCSR */ 2909 2910 #define SCBSY 0 2911 2912 /* Symbol Counter Interrupt Mask Register */ 2913 #define SCIRQM _SFR_MEM8(0xDF) 2914 2915 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2916 2917 struct __reg_SCIRQM { 2918 unsigned int irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */ 2919 unsigned int irqmof : 1; /* Symbol Counter Overflow IRQ enable */ 2920 unsigned int irqmbo : 1; /* Backoff Slot Counter IRQ enable */ 2921 unsigned int : 3; 2922 }; 2923 2924 #define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM) 2925 2926 #endif /* __ASSEMBLER__ */ 2927 2928 /* SCIRQM */ 2929 2930 #define IRQMCP1 0 2931 #define IRQMCP2 1 2932 #define IRQMCP3 2 2933 #define IRQMOF 3 2934 #define IRQMBO 4 2935 2936 /* Symbol Counter Interrupt Status Register */ 2937 #define SCIRQS _SFR_MEM8(0xE0) 2938 2939 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2940 2941 struct __reg_SCIRQS { 2942 unsigned int irqscp : 3; /* Compare Unit 3 Compare Match IRQ */ 2943 unsigned int irqsof : 1; /* Symbol Counter Overflow IRQ */ 2944 unsigned int irqsbo : 1; /* Backoff Slot Counter IRQ */ 2945 unsigned int : 3; 2946 }; 2947 2948 #define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS) 2949 2950 #endif /* __ASSEMBLER__ */ 2951 2952 /* SCIRQS */ 2953 2954 #define IRQSCP1 0 2955 #define IRQSCP2 1 2956 #define IRQSCP3 2 2957 #define IRQSOF 3 2958 #define IRQSBO 4 2959 2960 /* Symbol Counter Register LL-Byte */ 2961 #define SCCNTLL _SFR_MEM8(0xE1) 2962 2963 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2964 2965 struct __reg_SCCNTLL { 2966 unsigned int sccntll : 8; /* Symbol Counter Register LL-Byte */ 2967 }; 2968 2969 #define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL) 2970 2971 #endif /* __ASSEMBLER__ */ 2972 2973 /* SCCNTLL */ 2974 2975 #define SCCNTLL0 0 2976 #define SCCNTLL1 1 2977 #define SCCNTLL2 2 2978 #define SCCNTLL3 3 2979 #define SCCNTLL4 4 2980 #define SCCNTLL5 5 2981 #define SCCNTLL6 6 2982 #define SCCNTLL7 7 2983 2984 /* Symbol Counter Register LH-Byte */ 2985 #define SCCNTLH _SFR_MEM8(0xE2) 2986 2987 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2988 2989 struct __reg_SCCNTLH { 2990 unsigned int sccntlh : 8; /* Symbol Counter Register LH-Byte */ 2991 }; 2992 2993 #define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH) 2994 2995 #endif /* __ASSEMBLER__ */ 2996 2997 /* SCCNTLH */ 2998 2999 #define SCCNTLH0 0 3000 #define SCCNTLH1 1 3001 #define SCCNTLH2 2 3002 #define SCCNTLH3 3 3003 #define SCCNTLH4 4 3004 #define SCCNTLH5 5 3005 #define SCCNTLH6 6 3006 #define SCCNTLH7 7 3007 3008 /* Symbol Counter Register HL-Byte */ 3009 #define SCCNTHL _SFR_MEM8(0xE3) 3010 3011 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3012 3013 struct __reg_SCCNTHL { 3014 unsigned int sccnthl : 8; /* Symbol Counter Register HL-Byte */ 3015 }; 3016 3017 #define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL) 3018 3019 #endif /* __ASSEMBLER__ */ 3020 3021 /* SCCNTHL */ 3022 3023 #define SCCNTHL0 0 3024 #define SCCNTHL1 1 3025 #define SCCNTHL2 2 3026 #define SCCNTHL3 3 3027 #define SCCNTHL4 4 3028 #define SCCNTHL5 5 3029 #define SCCNTHL6 6 3030 #define SCCNTHL7 7 3031 3032 /* Symbol Counter Register HH-Byte */ 3033 #define SCCNTHH _SFR_MEM8(0xE4) 3034 3035 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3036 3037 struct __reg_SCCNTHH { 3038 unsigned int sccnthh : 8; /* Symbol Counter Register HH-Byte */ 3039 }; 3040 3041 #define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH) 3042 3043 #endif /* __ASSEMBLER__ */ 3044 3045 /* SCCNTHH */ 3046 3047 #define SCCNTHH0 0 3048 #define SCCNTHH1 1 3049 #define SCCNTHH2 2 3050 #define SCCNTHH3 3 3051 #define SCCNTHH4 4 3052 #define SCCNTHH5 5 3053 #define SCCNTHH6 6 3054 #define SCCNTHH7 7 3055 3056 /* Symbol Counter Beacon Timestamp Register LL-Byte */ 3057 #define SCBTSRLL _SFR_MEM8(0xE5) 3058 3059 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3060 3061 struct __reg_SCBTSRLL { 3062 unsigned int scbtsrll : 8; /* Symbol Counter Beacon Timestamp Register LL-Byte */ 3063 }; 3064 3065 #define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL) 3066 3067 #endif /* __ASSEMBLER__ */ 3068 3069 /* SCBTSRLL */ 3070 3071 #define SCBTSRLL0 0 3072 #define SCBTSRLL1 1 3073 #define SCBTSRLL2 2 3074 #define SCBTSRLL3 3 3075 #define SCBTSRLL4 4 3076 #define SCBTSRLL5 5 3077 #define SCBTSRLL6 6 3078 #define SCBTSRLL7 7 3079 3080 /* Symbol Counter Beacon Timestamp Register LH-Byte */ 3081 #define SCBTSRLH _SFR_MEM8(0xE6) 3082 3083 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3084 3085 struct __reg_SCBTSRLH { 3086 unsigned int scbtsrlh : 8; /* Symbol Counter Beacon Timestamp Register LH-Byte */ 3087 }; 3088 3089 #define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH) 3090 3091 #endif /* __ASSEMBLER__ */ 3092 3093 /* SCBTSRLH */ 3094 3095 #define SCBTSRLH0 0 3096 #define SCBTSRLH1 1 3097 #define SCBTSRLH2 2 3098 #define SCBTSRLH3 3 3099 #define SCBTSRLH4 4 3100 #define SCBTSRLH5 5 3101 #define SCBTSRLH6 6 3102 #define SCBTSRLH7 7 3103 3104 /* Symbol Counter Beacon Timestamp Register HL-Byte */ 3105 #define SCBTSRHL _SFR_MEM8(0xE7) 3106 3107 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3108 3109 struct __reg_SCBTSRHL { 3110 unsigned int scbtsrhl : 8; /* Symbol Counter Beacon Timestamp Register HL-Byte */ 3111 }; 3112 3113 #define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL) 3114 3115 #endif /* __ASSEMBLER__ */ 3116 3117 /* SCBTSRHL */ 3118 3119 #define SCBTSRHL0 0 3120 #define SCBTSRHL1 1 3121 #define SCBTSRHL2 2 3122 #define SCBTSRHL3 3 3123 #define SCBTSRHL4 4 3124 #define SCBTSRHL5 5 3125 #define SCBTSRHL6 6 3126 #define SCBTSRHL7 7 3127 3128 /* Symbol Counter Beacon Timestamp Register HH-Byte */ 3129 #define SCBTSRHH _SFR_MEM8(0xE8) 3130 3131 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3132 3133 struct __reg_SCBTSRHH { 3134 unsigned int scbtsrhh : 8; /* Symbol Counter Beacon Timestamp Register HH-Byte */ 3135 }; 3136 3137 #define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH) 3138 3139 #endif /* __ASSEMBLER__ */ 3140 3141 /* SCBTSRHH */ 3142 3143 #define SCBTSRHH0 0 3144 #define SCBTSRHH1 1 3145 #define SCBTSRHH2 2 3146 #define SCBTSRHH3 3 3147 #define SCBTSRHH4 4 3148 #define SCBTSRHH5 5 3149 #define SCBTSRHH6 6 3150 #define SCBTSRHH7 7 3151 3152 /* Symbol Counter Frame Timestamp Register LL-Byte */ 3153 #define SCTSRLL _SFR_MEM8(0xE9) 3154 3155 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3156 3157 struct __reg_SCTSRLL { 3158 unsigned int sctsrll : 8; /* Symbol Counter Frame Timestamp Register LL-Byte */ 3159 }; 3160 3161 #define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL) 3162 3163 #endif /* __ASSEMBLER__ */ 3164 3165 /* SCTSRLL */ 3166 3167 #define SCTSRLL0 0 3168 #define SCTSRLL1 1 3169 #define SCTSRLL2 2 3170 #define SCTSRLL3 3 3171 #define SCTSRLL4 4 3172 #define SCTSRLL5 5 3173 #define SCTSRLL6 6 3174 #define SCTSRLL7 7 3175 3176 /* Symbol Counter Frame Timestamp Register LH-Byte */ 3177 #define SCTSRLH _SFR_MEM8(0xEA) 3178 3179 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3180 3181 struct __reg_SCTSRLH { 3182 unsigned int sctsrlh : 8; /* Symbol Counter Frame Timestamp Register LH-Byte */ 3183 }; 3184 3185 #define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH) 3186 3187 #endif /* __ASSEMBLER__ */ 3188 3189 /* SCTSRLH */ 3190 3191 #define SCTSRLH0 0 3192 #define SCTSRLH1 1 3193 #define SCTSRLH2 2 3194 #define SCTSRLH3 3 3195 #define SCTSRLH4 4 3196 #define SCTSRLH5 5 3197 #define SCTSRLH6 6 3198 #define SCTSRLH7 7 3199 3200 /* Symbol Counter Frame Timestamp Register HL-Byte */ 3201 #define SCTSRHL _SFR_MEM8(0xEB) 3202 3203 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3204 3205 struct __reg_SCTSRHL { 3206 unsigned int sctsrhl : 8; /* Symbol Counter Frame Timestamp Register HL-Byte */ 3207 }; 3208 3209 #define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL) 3210 3211 #endif /* __ASSEMBLER__ */ 3212 3213 /* SCTSRHL */ 3214 3215 #define SCTSRHL0 0 3216 #define SCTSRHL1 1 3217 #define SCTSRHL2 2 3218 #define SCTSRHL3 3 3219 #define SCTSRHL4 4 3220 #define SCTSRHL5 5 3221 #define SCTSRHL6 6 3222 #define SCTSRHL7 7 3223 3224 /* Symbol Counter Frame Timestamp Register HH-Byte */ 3225 #define SCTSRHH _SFR_MEM8(0xEC) 3226 3227 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3228 3229 struct __reg_SCTSRHH { 3230 unsigned int sctsrhh : 8; /* Symbol Counter Frame Timestamp Register HH-Byte */ 3231 }; 3232 3233 #define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH) 3234 3235 #endif /* __ASSEMBLER__ */ 3236 3237 /* SCTSRHH */ 3238 3239 #define SCTSRHH0 0 3240 #define SCTSRHH1 1 3241 #define SCTSRHH2 2 3242 #define SCTSRHH3 3 3243 #define SCTSRHH4 4 3244 #define SCTSRHH5 5 3245 #define SCTSRHH6 6 3246 #define SCTSRHH7 7 3247 3248 /* Symbol Counter Output Compare Register 3 LL-Byte */ 3249 #define SCOCR3LL _SFR_MEM8(0xED) 3250 3251 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3252 3253 struct __reg_SCOCR3LL { 3254 unsigned int scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte */ 3255 }; 3256 3257 #define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL) 3258 3259 #endif /* __ASSEMBLER__ */ 3260 3261 /* SCOCR3LL */ 3262 3263 #define SCOCR3LL0 0 3264 #define SCOCR3LL1 1 3265 #define SCOCR3LL2 2 3266 #define SCOCR3LL3 3 3267 #define SCOCR3LL4 4 3268 #define SCOCR3LL5 5 3269 #define SCOCR3LL6 6 3270 #define SCOCR3LL7 7 3271 3272 /* Symbol Counter Output Compare Register 3 LH-Byte */ 3273 #define SCOCR3LH _SFR_MEM8(0xEE) 3274 3275 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3276 3277 struct __reg_SCOCR3LH { 3278 unsigned int scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte */ 3279 }; 3280 3281 #define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH) 3282 3283 #endif /* __ASSEMBLER__ */ 3284 3285 /* SCOCR3LH */ 3286 3287 #define SCOCR3LH0 0 3288 #define SCOCR3LH1 1 3289 #define SCOCR3LH2 2 3290 #define SCOCR3LH3 3 3291 #define SCOCR3LH4 4 3292 #define SCOCR3LH5 5 3293 #define SCOCR3LH6 6 3294 #define SCOCR3LH7 7 3295 3296 /* Symbol Counter Output Compare Register 3 HL-Byte */ 3297 #define SCOCR3HL _SFR_MEM8(0xEF) 3298 3299 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3300 3301 struct __reg_SCOCR3HL { 3302 unsigned int scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte */ 3303 }; 3304 3305 #define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL) 3306 3307 #endif /* __ASSEMBLER__ */ 3308 3309 /* SCOCR3HL */ 3310 3311 #define SCOCR3HL0 0 3312 #define SCOCR3HL1 1 3313 #define SCOCR3HL2 2 3314 #define SCOCR3HL3 3 3315 #define SCOCR3HL4 4 3316 #define SCOCR3HL5 5 3317 #define SCOCR3HL6 6 3318 #define SCOCR3HL7 7 3319 3320 /* Symbol Counter Output Compare Register 3 HH-Byte */ 3321 #define SCOCR3HH _SFR_MEM8(0xF0) 3322 3323 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3324 3325 struct __reg_SCOCR3HH { 3326 unsigned int scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte */ 3327 }; 3328 3329 #define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH) 3330 3331 #endif /* __ASSEMBLER__ */ 3332 3333 /* SCOCR3HH */ 3334 3335 #define SCOCR3HH0 0 3336 #define SCOCR3HH1 1 3337 #define SCOCR3HH2 2 3338 #define SCOCR3HH3 3 3339 #define SCOCR3HH4 4 3340 #define SCOCR3HH5 5 3341 #define SCOCR3HH6 6 3342 #define SCOCR3HH7 7 3343 3344 /* Symbol Counter Output Compare Register 2 LL-Byte */ 3345 #define SCOCR2LL _SFR_MEM8(0xF1) 3346 3347 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3348 3349 struct __reg_SCOCR2LL { 3350 unsigned int scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte */ 3351 }; 3352 3353 #define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL) 3354 3355 #endif /* __ASSEMBLER__ */ 3356 3357 /* SCOCR2LL */ 3358 3359 #define SCOCR2LL0 0 3360 #define SCOCR2LL1 1 3361 #define SCOCR2LL2 2 3362 #define SCOCR2LL3 3 3363 #define SCOCR2LL4 4 3364 #define SCOCR2LL5 5 3365 #define SCOCR2LL6 6 3366 #define SCOCR2LL7 7 3367 3368 /* Symbol Counter Output Compare Register 2 LH-Byte */ 3369 #define SCOCR2LH _SFR_MEM8(0xF2) 3370 3371 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3372 3373 struct __reg_SCOCR2LH { 3374 unsigned int scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte */ 3375 }; 3376 3377 #define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH) 3378 3379 #endif /* __ASSEMBLER__ */ 3380 3381 /* SCOCR2LH */ 3382 3383 #define SCOCR2LH0 0 3384 #define SCOCR2LH1 1 3385 #define SCOCR2LH2 2 3386 #define SCOCR2LH3 3 3387 #define SCOCR2LH4 4 3388 #define SCOCR2LH5 5 3389 #define SCOCR2LH6 6 3390 #define SCOCR2LH7 7 3391 3392 /* Symbol Counter Output Compare Register 2 HL-Byte */ 3393 #define SCOCR2HL _SFR_MEM8(0xF3) 3394 3395 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3396 3397 struct __reg_SCOCR2HL { 3398 unsigned int scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte */ 3399 }; 3400 3401 #define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL) 3402 3403 #endif /* __ASSEMBLER__ */ 3404 3405 /* SCOCR2HL */ 3406 3407 #define SCOCR2HL0 0 3408 #define SCOCR2HL1 1 3409 #define SCOCR2HL2 2 3410 #define SCOCR2HL3 3 3411 #define SCOCR2HL4 4 3412 #define SCOCR2HL5 5 3413 #define SCOCR2HL6 6 3414 #define SCOCR2HL7 7 3415 3416 /* Symbol Counter Output Compare Register 2 HH-Byte */ 3417 #define SCOCR2HH _SFR_MEM8(0xF4) 3418 3419 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3420 3421 struct __reg_SCOCR2HH { 3422 unsigned int scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte */ 3423 }; 3424 3425 #define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH) 3426 3427 #endif /* __ASSEMBLER__ */ 3428 3429 /* SCOCR2HH */ 3430 3431 #define SCOCR2HH0 0 3432 #define SCOCR2HH1 1 3433 #define SCOCR2HH2 2 3434 #define SCOCR2HH3 3 3435 #define SCOCR2HH4 4 3436 #define SCOCR2HH5 5 3437 #define SCOCR2HH6 6 3438 #define SCOCR2HH7 7 3439 3440 /* Symbol Counter Output Compare Register 1 LL-Byte */ 3441 #define SCOCR1LL _SFR_MEM8(0xF5) 3442 3443 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3444 3445 struct __reg_SCOCR1LL { 3446 unsigned int scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte */ 3447 }; 3448 3449 #define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL) 3450 3451 #endif /* __ASSEMBLER__ */ 3452 3453 /* SCOCR1LL */ 3454 3455 #define SCOCR1LL0 0 3456 #define SCOCR1LL1 1 3457 #define SCOCR1LL2 2 3458 #define SCOCR1LL3 3 3459 #define SCOCR1LL4 4 3460 #define SCOCR1LL5 5 3461 #define SCOCR1LL6 6 3462 #define SCOCR1LL7 7 3463 3464 /* Symbol Counter Output Compare Register 1 LH-Byte */ 3465 #define SCOCR1LH _SFR_MEM8(0xF6) 3466 3467 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3468 3469 struct __reg_SCOCR1LH { 3470 unsigned int scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte */ 3471 }; 3472 3473 #define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH) 3474 3475 #endif /* __ASSEMBLER__ */ 3476 3477 /* SCOCR1LH */ 3478 3479 #define SCOCR1LH0 0 3480 #define SCOCR1LH1 1 3481 #define SCOCR1LH2 2 3482 #define SCOCR1LH3 3 3483 #define SCOCR1LH4 4 3484 #define SCOCR1LH5 5 3485 #define SCOCR1LH6 6 3486 #define SCOCR1LH7 7 3487 3488 /* Symbol Counter Output Compare Register 1 HL-Byte */ 3489 #define SCOCR1HL _SFR_MEM8(0xF7) 3490 3491 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3492 3493 struct __reg_SCOCR1HL { 3494 unsigned int scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte */ 3495 }; 3496 3497 #define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL) 3498 3499 #endif /* __ASSEMBLER__ */ 3500 3501 /* SCOCR1HL */ 3502 3503 #define SCOCR1HL0 0 3504 #define SCOCR1HL1 1 3505 #define SCOCR1HL2 2 3506 #define SCOCR1HL3 3 3507 #define SCOCR1HL4 4 3508 #define SCOCR1HL5 5 3509 #define SCOCR1HL6 6 3510 #define SCOCR1HL7 7 3511 3512 /* Symbol Counter Output Compare Register 1 HH-Byte */ 3513 #define SCOCR1HH _SFR_MEM8(0xF8) 3514 3515 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3516 3517 struct __reg_SCOCR1HH { 3518 unsigned int scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte */ 3519 }; 3520 3521 #define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH) 3522 3523 #endif /* __ASSEMBLER__ */ 3524 3525 /* SCOCR1HH */ 3526 3527 #define SCOCR1HH0 0 3528 #define SCOCR1HH1 1 3529 #define SCOCR1HH2 2 3530 #define SCOCR1HH3 3 3531 #define SCOCR1HH4 4 3532 #define SCOCR1HH5 5 3533 #define SCOCR1HH6 6 3534 #define SCOCR1HH7 7 3535 3536 /* Symbol Counter Transmit Frame Timestamp Register LL-Byte */ 3537 #define SCTSTRLL _SFR_MEM8(0xF9) 3538 3539 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3540 3541 struct __reg_SCTSTRLL { 3542 unsigned int sctstrll : 8; /* Symbol Counter Transmit Frame Timestamp Register LL-Byte */ 3543 }; 3544 3545 #define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL) 3546 3547 #endif /* __ASSEMBLER__ */ 3548 3549 /* SCTSTRLL */ 3550 3551 #define SCTSTRLL0 0 3552 #define SCTSTRLL1 1 3553 #define SCTSTRLL2 2 3554 #define SCTSTRLL3 3 3555 #define SCTSTRLL4 4 3556 #define SCTSTRLL5 5 3557 #define SCTSTRLL6 6 3558 #define SCTSTRLL7 7 3559 3560 /* Symbol Counter Transmit Frame Timestamp Register LH-Byte */ 3561 #define SCTSTRLH _SFR_MEM8(0xFA) 3562 3563 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3564 3565 struct __reg_SCTSTRLH { 3566 unsigned int sctstrlh : 8; /* Symbol Counter Transmit Frame Timestamp Register LH-Byte */ 3567 }; 3568 3569 #define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH) 3570 3571 #endif /* __ASSEMBLER__ */ 3572 3573 /* SCTSTRLH */ 3574 3575 #define SCTSTRLH0 0 3576 #define SCTSTRLH1 1 3577 #define SCTSTRLH2 2 3578 #define SCTSTRLH3 3 3579 #define SCTSTRLH4 4 3580 #define SCTSTRLH5 5 3581 #define SCTSTRLH6 6 3582 #define SCTSTRLH7 7 3583 3584 /* Symbol Counter Transmit Frame Timestamp Register HL-Byte */ 3585 #define SCTSTRHL _SFR_MEM8(0xFB) 3586 3587 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3588 3589 struct __reg_SCTSTRHL { 3590 unsigned int sctstrhl : 8; /* Symbol Counter Transmit Frame Timestamp Register HL-Byte */ 3591 }; 3592 3593 #define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL) 3594 3595 #endif /* __ASSEMBLER__ */ 3596 3597 /* SCTSTRHL */ 3598 3599 #define SCTSTRHL0 0 3600 #define SCTSTRHL1 1 3601 #define SCTSTRHL2 2 3602 #define SCTSTRHL3 3 3603 #define SCTSTRHL4 4 3604 #define SCTSTRHL5 5 3605 #define SCTSTRHL6 6 3606 #define SCTSTRHL7 7 3607 3608 /* Symbol Counter Transmit Frame Timestamp Register HH-Byte */ 3609 #define SCTSTRHH _SFR_MEM8(0xFC) 3610 3611 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3612 3613 struct __reg_SCTSTRHH { 3614 unsigned int sctstrhh : 8; /* Symbol Counter Transmit Frame Timestamp Register HH-Byte */ 3615 }; 3616 3617 #define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH) 3618 3619 #endif /* __ASSEMBLER__ */ 3620 3621 /* SCTSTRHH */ 3622 3623 #define SCTSTRHH0 0 3624 #define SCTSTRHH1 1 3625 #define SCTSTRHH2 2 3626 #define SCTSTRHH3 3 3627 #define SCTSTRHH4 4 3628 #define SCTSTRHH5 5 3629 #define SCTSTRHH6 6 3630 #define SCTSTRHH7 7 3631 3632 /* Multiple Address Filter Configuration Register 0 */ 3633 #define MAFCR0 _SFR_MEM8(0x10C) 3634 3635 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3636 3637 struct __reg_MAFCR0 { 3638 unsigned int maf0en : 1; /* Multiple Address Filter 0 Enable */ 3639 unsigned int maf1en : 1; /* Multiple Address Filter 1 Enable */ 3640 unsigned int maf2en : 1; /* Multiple Address Filter 2 Enable */ 3641 unsigned int maf3en : 1; /* Multiple Address Filter 3 Enable */ 3642 unsigned int : 4; 3643 }; 3644 3645 #define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0) 3646 3647 #endif /* __ASSEMBLER__ */ 3648 3649 /* MAFCR0 */ 3650 3651 #define MAF0EN 0 3652 #define MAF1EN 1 3653 #define MAF2EN 2 3654 #define MAF3EN 3 3655 3656 /* Multiple Address Filter Configuration Register 1 */ 3657 #define MAFCR1 _SFR_MEM8(0x10D) 3658 3659 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3660 3661 struct __reg_MAFCR1 { 3662 unsigned int aack_0_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 0. */ 3663 unsigned int aack_0_set_pd : 1; /* Set Data Pending bit for address filter 0. */ 3664 unsigned int aack_1_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 1. */ 3665 unsigned int aack_1_set_pd : 1; /* Set Data Pending bit for address filter 1. */ 3666 unsigned int aack_2_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 2. */ 3667 unsigned int aack_2_set_pd : 1; /* Set Data Pending bit for address filter 2. */ 3668 unsigned int aack_3_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 3. */ 3669 unsigned int aack_3_set_pd : 1; /* Set Data Pending bit for address filter 3. */ 3670 }; 3671 3672 #define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1) 3673 3674 #endif /* __ASSEMBLER__ */ 3675 3676 /* MAFCR1 */ 3677 3678 #define AACK_0_I_AM_COORD 0 3679 #define AACK_0_SET_PD 1 3680 #define AACK_1_I_AM_COORD 2 3681 #define AACK_1_SET_PD 3 3682 #define AACK_2_I_AM_COORD 4 3683 #define AACK_2_SET_PD 5 3684 #define AACK_3_I_AM_COORD 6 3685 #define AACK_3_SET_PD 7 3686 3687 /* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */ 3688 #define MAFSA0L _SFR_MEM8(0x10E) 3689 3690 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3691 3692 struct __reg_MAFSA0L { 3693 unsigned int mafsa0l : 8; /* MAC Short Address low Byte for Frame Filter 0 */ 3694 }; 3695 3696 #define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L) 3697 3698 #endif /* __ASSEMBLER__ */ 3699 3700 /* MAFSA0L */ 3701 3702 #define MAFSA0L0 0 3703 #define MAFSA0L1 1 3704 #define MAFSA0L2 2 3705 #define MAFSA0L3 3 3706 #define MAFSA0L4 4 3707 #define MAFSA0L5 5 3708 #define MAFSA0L6 6 3709 #define MAFSA0L7 7 3710 3711 /* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */ 3712 #define MAFSA0H _SFR_MEM8(0x10F) 3713 3714 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3715 3716 struct __reg_MAFSA0H { 3717 unsigned int mafsa0h : 8; /* MAC Short Address high Byte for Frame Filter 0 */ 3718 }; 3719 3720 #define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H) 3721 3722 #endif /* __ASSEMBLER__ */ 3723 3724 /* MAFSA0H */ 3725 3726 #define MAFSA0H0 0 3727 #define MAFSA0H1 1 3728 #define MAFSA0H2 2 3729 #define MAFSA0H3 3 3730 #define MAFSA0H4 4 3731 #define MAFSA0H5 5 3732 #define MAFSA0H6 6 3733 #define MAFSA0H7 7 3734 3735 /* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */ 3736 #define MAFPA0L _SFR_MEM8(0x110) 3737 3738 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3739 3740 struct __reg_MAFPA0L { 3741 unsigned int mafpa0l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 0 */ 3742 }; 3743 3744 #define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L) 3745 3746 #endif /* __ASSEMBLER__ */ 3747 3748 /* MAFPA0L */ 3749 3750 #define MAFPA0L0 0 3751 #define MAFPA0L1 1 3752 #define MAFPA0L2 2 3753 #define MAFPA0L3 3 3754 #define MAFPA0L4 4 3755 #define MAFPA0L5 5 3756 #define MAFPA0L6 6 3757 #define MAFPA0L7 7 3758 3759 /* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */ 3760 #define MAFPA0H _SFR_MEM8(0x111) 3761 3762 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3763 3764 struct __reg_MAFPA0H { 3765 unsigned int mafpa0h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 0 */ 3766 }; 3767 3768 #define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H) 3769 3770 #endif /* __ASSEMBLER__ */ 3771 3772 /* MAFPA0H */ 3773 3774 #define MAFPA0H0 0 3775 #define MAFPA0H1 1 3776 #define MAFPA0H2 2 3777 #define MAFPA0H3 3 3778 #define MAFPA0H4 4 3779 #define MAFPA0H5 5 3780 #define MAFPA0H6 6 3781 #define MAFPA0H7 7 3782 3783 /* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */ 3784 #define MAFSA1L _SFR_MEM8(0x112) 3785 3786 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3787 3788 struct __reg_MAFSA1L { 3789 unsigned int mafsa1l : 8; /* MAC Short Address low Byte for Frame Filter 1 */ 3790 }; 3791 3792 #define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L) 3793 3794 #endif /* __ASSEMBLER__ */ 3795 3796 /* MAFSA1L */ 3797 3798 #define MAFSA1L0 0 3799 #define MAFSA1L1 1 3800 #define MAFSA1L2 2 3801 #define MAFSA1L3 3 3802 #define MAFSA1L4 4 3803 #define MAFSA1L5 5 3804 #define MAFSA1L6 6 3805 #define MAFSA1L7 7 3806 3807 /* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */ 3808 #define MAFSA1H _SFR_MEM8(0x113) 3809 3810 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3811 3812 struct __reg_MAFSA1H { 3813 unsigned int mafsa1h : 8; /* MAC Short Address high Byte for Frame Filter 1 */ 3814 }; 3815 3816 #define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H) 3817 3818 #endif /* __ASSEMBLER__ */ 3819 3820 /* MAFSA1H */ 3821 3822 #define MAFSA1H0 0 3823 #define MAFSA1H1 1 3824 #define MAFSA1H2 2 3825 #define MAFSA1H3 3 3826 #define MAFSA1H4 4 3827 #define MAFSA1H5 5 3828 #define MAFSA1H6 6 3829 #define MAFSA1H7 7 3830 3831 /* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */ 3832 #define MAFPA1L _SFR_MEM8(0x114) 3833 3834 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3835 3836 struct __reg_MAFPA1L { 3837 unsigned int mafpa1l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 1 */ 3838 }; 3839 3840 #define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L) 3841 3842 #endif /* __ASSEMBLER__ */ 3843 3844 /* MAFPA1L */ 3845 3846 #define MAFPA1L0 0 3847 #define MAFPA1L1 1 3848 #define MAFPA1L2 2 3849 #define MAFPA1L3 3 3850 #define MAFPA1L4 4 3851 #define MAFPA1L5 5 3852 #define MAFPA1L6 6 3853 #define MAFPA1L7 7 3854 3855 /* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */ 3856 #define MAFPA1H _SFR_MEM8(0x115) 3857 3858 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3859 3860 struct __reg_MAFPA1H { 3861 unsigned int mafpa1h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 1 */ 3862 }; 3863 3864 #define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H) 3865 3866 #endif /* __ASSEMBLER__ */ 3867 3868 /* MAFPA1H */ 3869 3870 #define MAFPA1H0 0 3871 #define MAFPA1H1 1 3872 #define MAFPA1H2 2 3873 #define MAFPA1H3 3 3874 #define MAFPA1H4 4 3875 #define MAFPA1H5 5 3876 #define MAFPA1H6 6 3877 #define MAFPA1H7 7 3878 3879 /* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */ 3880 #define MAFSA2L _SFR_MEM8(0x116) 3881 3882 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3883 3884 struct __reg_MAFSA2L { 3885 unsigned int mafsa2l : 8; /* MAC Short Address low Byte for Frame Filter 2 */ 3886 }; 3887 3888 #define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L) 3889 3890 #endif /* __ASSEMBLER__ */ 3891 3892 /* MAFSA2L */ 3893 3894 #define MAFSA2L0 0 3895 #define MAFSA2L1 1 3896 #define MAFSA2L2 2 3897 #define MAFSA2L3 3 3898 #define MAFSA2L4 4 3899 #define MAFSA2L5 5 3900 #define MAFSA2L6 6 3901 #define MAFSA2L7 7 3902 3903 /* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */ 3904 #define MAFSA2H _SFR_MEM8(0x117) 3905 3906 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3907 3908 struct __reg_MAFSA2H { 3909 unsigned int mafsa2h : 8; /* MAC Short Address high Byte for Frame Filter 2 */ 3910 }; 3911 3912 #define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H) 3913 3914 #endif /* __ASSEMBLER__ */ 3915 3916 /* MAFSA2H */ 3917 3918 #define MAFSA2H0 0 3919 #define MAFSA2H1 1 3920 #define MAFSA2H2 2 3921 #define MAFSA2H3 3 3922 #define MAFSA2H4 4 3923 #define MAFSA2H5 5 3924 #define MAFSA2H6 6 3925 #define MAFSA2H7 7 3926 3927 /* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */ 3928 #define MAFPA2L _SFR_MEM8(0x118) 3929 3930 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3931 3932 struct __reg_MAFPA2L { 3933 unsigned int mafpa2l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 2 */ 3934 }; 3935 3936 #define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L) 3937 3938 #endif /* __ASSEMBLER__ */ 3939 3940 /* MAFPA2L */ 3941 3942 #define MAFPA2L0 0 3943 #define MAFPA2L1 1 3944 #define MAFPA2L2 2 3945 #define MAFPA2L3 3 3946 #define MAFPA2L4 4 3947 #define MAFPA2L5 5 3948 #define MAFPA2L6 6 3949 #define MAFPA2L7 7 3950 3951 /* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */ 3952 #define MAFPA2H _SFR_MEM8(0x119) 3953 3954 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3955 3956 struct __reg_MAFPA2H { 3957 unsigned int mafpa2h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 2 */ 3958 }; 3959 3960 #define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H) 3961 3962 #endif /* __ASSEMBLER__ */ 3963 3964 /* MAFPA2H */ 3965 3966 #define MAFPA2H0 0 3967 #define MAFPA2H1 1 3968 #define MAFPA2H2 2 3969 #define MAFPA2H3 3 3970 #define MAFPA2H4 4 3971 #define MAFPA2H5 5 3972 #define MAFPA2H6 6 3973 #define MAFPA2H7 7 3974 3975 /* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */ 3976 #define MAFSA3L _SFR_MEM8(0x11A) 3977 3978 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3979 3980 struct __reg_MAFSA3L { 3981 unsigned int mafsa3l : 8; /* MAC Short Address low Byte for Frame Filter 3 */ 3982 }; 3983 3984 #define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L) 3985 3986 #endif /* __ASSEMBLER__ */ 3987 3988 /* MAFSA3L */ 3989 3990 #define MAFSA3L0 0 3991 #define MAFSA3L1 1 3992 #define MAFSA3L2 2 3993 #define MAFSA3L3 3 3994 #define MAFSA3L4 4 3995 #define MAFSA3L5 5 3996 #define MAFSA3L6 6 3997 #define MAFSA3L7 7 3998 3999 /* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */ 4000 #define MAFSA3H _SFR_MEM8(0x11B) 4001 4002 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4003 4004 struct __reg_MAFSA3H { 4005 unsigned int mafsa3h : 8; /* MAC Short Address high Byte for Frame Filter 3 */ 4006 }; 4007 4008 #define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H) 4009 4010 #endif /* __ASSEMBLER__ */ 4011 4012 /* MAFSA3H */ 4013 4014 #define MAFSA3H0 0 4015 #define MAFSA3H1 1 4016 #define MAFSA3H2 2 4017 #define MAFSA3H3 3 4018 #define MAFSA3H4 4 4019 #define MAFSA3H5 5 4020 #define MAFSA3H6 6 4021 #define MAFSA3H7 7 4022 4023 /* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */ 4024 #define MAFPA3L _SFR_MEM8(0x11C) 4025 4026 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4027 4028 struct __reg_MAFPA3L { 4029 unsigned int mafpa3l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 3 */ 4030 }; 4031 4032 #define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L) 4033 4034 #endif /* __ASSEMBLER__ */ 4035 4036 /* MAFPA3L */ 4037 4038 #define MAFPA3L0 0 4039 #define MAFPA3L1 1 4040 #define MAFPA3L2 2 4041 #define MAFPA3L3 3 4042 #define MAFPA3L4 4 4043 #define MAFPA3L5 5 4044 #define MAFPA3L6 6 4045 #define MAFPA3L7 7 4046 4047 /* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */ 4048 #define MAFPA3H _SFR_MEM8(0x11D) 4049 4050 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4051 4052 struct __reg_MAFPA3H { 4053 unsigned int mafpa3h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 3 */ 4054 }; 4055 4056 #define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H) 4057 4058 #endif /* __ASSEMBLER__ */ 4059 4060 /* MAFPA3H */ 4061 4062 #define MAFPA3H0 0 4063 #define MAFPA3H1 1 4064 #define MAFPA3H2 2 4065 #define MAFPA3H3 3 4066 #define MAFPA3H4 4 4067 #define MAFPA3H5 5 4068 #define MAFPA3H6 6 4069 #define MAFPA3H7 7 4070 4071 /* Timer/Counter5 Control Register A */ 4072 #define TCCR5A _SFR_MEM8(0x120) 4073 4074 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4075 4076 struct __reg_TCCR5A { 4077 unsigned int wgm5 : 2; /* Waveform Generation Mode */ 4078 unsigned int com5c : 2; /* Compare Output Mode for Channel C */ 4079 unsigned int com5b : 2; /* Compare Output Mode for Channel B */ 4080 unsigned int com5a : 2; /* Compare Output Mode for Channel A */ 4081 }; 4082 4083 #define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A) 4084 4085 #endif /* __ASSEMBLER__ */ 4086 4087 /* TCCR5A */ 4088 4089 #define WGM50 0 4090 #define WGM51 1 4091 #define COM5C0 2 4092 #define COM5C1 3 4093 #define COM5B0 4 4094 #define COM5B1 5 4095 #define COM5A0 6 4096 #define COM5A1 7 4097 4098 /* Timer/Counter5 Control Register B */ 4099 #define TCCR5B _SFR_MEM8(0x121) 4100 4101 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4102 4103 struct __reg_TCCR5B { 4104 unsigned int cs5 : 3; /* Clock Select */ 4105 unsigned int wgm5 : 2; /* Waveform Generation Mode */ 4106 unsigned int : 1; 4107 unsigned int ices5 : 1; /* Input Capture 5 Edge Select */ 4108 unsigned int icnc5 : 1; /* Input Capture 5 Noise Canceller */ 4109 }; 4110 4111 #define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B) 4112 4113 #endif /* __ASSEMBLER__ */ 4114 4115 /* TCCR5B */ 4116 4117 #define CS50 0 4118 #define CS51 1 4119 #define CS52 2 4120 #define WGM52 3 4121 #define WGM53 4 4122 #define ICES5 6 4123 #define ICNC5 7 4124 4125 /* Timer/Counter5 Control Register C */ 4126 #define TCCR5C _SFR_MEM8(0x122) 4127 4128 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4129 4130 struct __reg_TCCR5C { 4131 unsigned int : 5; 4132 unsigned int foc5c : 1; /* Force Output Compare for Channel C */ 4133 unsigned int foc5b : 1; /* Force Output Compare for Channel B */ 4134 unsigned int foc5a : 1; /* Force Output Compare for Channel A */ 4135 }; 4136 4137 #define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C) 4138 4139 #endif /* __ASSEMBLER__ */ 4140 4141 /* TCCR5C */ 4142 4143 #define FOC5C 5 4144 #define FOC5B 6 4145 #define FOC5A 7 4146 4147 /* Timer/Counter5 Bytes */ 4148 #define TCNT5 _SFR_MEM16(0x124) 4149 #define TCNT5L _SFR_MEM8(0x124) 4150 #define TCNT5H _SFR_MEM8(0x125) 4151 4152 /* Timer/Counter5 Input Capture Register Bytes */ 4153 #define ICR5 _SFR_MEM16(0x126) 4154 #define ICR5L _SFR_MEM8(0x126) 4155 #define ICR5H _SFR_MEM8(0x127) 4156 4157 /* Timer/Counter5 Output Compare Register A Bytes */ 4158 #define OCR5A _SFR_MEM16(0x128) 4159 #define OCR5AL _SFR_MEM8(0x128) 4160 #define OCR5AH _SFR_MEM8(0x129) 4161 4162 /* Timer/Counter5 Output Compare Register B Bytes */ 4163 #define OCR5B _SFR_MEM16(0x12A) 4164 #define OCR5BL _SFR_MEM8(0x12A) 4165 #define OCR5BH _SFR_MEM8(0x12B) 4166 4167 /* Timer/Counter5 Output Compare Register C Bytes */ 4168 #define OCR5C _SFR_MEM16(0x12C) 4169 #define OCR5CL _SFR_MEM8(0x12C) 4170 #define OCR5CH _SFR_MEM8(0x12D) 4171 4172 /* Low Leakage Voltage Regulator Control Register */ 4173 #define LLCR _SFR_MEM8(0x12F) 4174 4175 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4176 4177 struct __reg_LLCR { 4178 unsigned int llencal : 1; /* Enable Automatic Calibration */ 4179 unsigned int llshort : 1; /* Short Lower Calibration Circuit */ 4180 unsigned int lltco : 1; /* Temperature Coefficient of Current Source */ 4181 unsigned int llcal : 1; /* Calibration Active */ 4182 unsigned int llcomp : 1; /* Comparator Output */ 4183 unsigned int lldone : 1; /* Calibration Done */ 4184 unsigned int : 2; 4185 }; 4186 4187 #define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR) 4188 4189 #endif /* __ASSEMBLER__ */ 4190 4191 /* LLCR */ 4192 4193 #define LLENCAL 0 4194 #define LLSHORT 1 4195 #define LLTCO 2 4196 #define LLCAL 3 4197 #define LLCOMP 4 4198 #define LLDONE 5 4199 4200 /* Low Leakage Voltage Regulator Data Register (Low-Byte) */ 4201 #define LLDRL _SFR_MEM8(0x130) 4202 4203 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4204 4205 struct __reg_LLDRL { 4206 unsigned int lldrl : 4; /* Low-Byte Data Register Bits */ 4207 unsigned int : 4; 4208 }; 4209 4210 #define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL) 4211 4212 #endif /* __ASSEMBLER__ */ 4213 4214 /* LLDRL */ 4215 4216 #define LLDRL0 0 4217 #define LLDRL1 1 4218 #define LLDRL2 2 4219 #define LLDRL3 3 4220 4221 /* Low Leakage Voltage Regulator Data Register (High-Byte) */ 4222 #define LLDRH _SFR_MEM8(0x131) 4223 4224 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4225 4226 struct __reg_LLDRH { 4227 unsigned int lldrh : 5; /* High-Byte Data Register Bits */ 4228 unsigned int : 3; 4229 }; 4230 4231 #define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH) 4232 4233 #endif /* __ASSEMBLER__ */ 4234 4235 /* LLDRH */ 4236 4237 #define LLDRH0 0 4238 #define LLDRH1 1 4239 #define LLDRH2 2 4240 #define LLDRH3 3 4241 #define LLDRH4 4 4242 4243 /* Data Retention Configuration Register #3 */ 4244 #define DRTRAM3 _SFR_MEM8(0x132) 4245 4246 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4247 4248 struct __reg_DRTRAM3 { 4249 unsigned int : 4; 4250 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4251 unsigned int drtswok : 1; /* DRT Switch OK */ 4252 unsigned int : 2; 4253 }; 4254 4255 #define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3) 4256 4257 #endif /* __ASSEMBLER__ */ 4258 4259 /* DRTRAM3 */ 4260 4261 #define ENDRT 4 4262 #define DRTSWOK 5 4263 4264 /* Data Retention Configuration Register #2 */ 4265 #define DRTRAM2 _SFR_MEM8(0x133) 4266 4267 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4268 4269 struct __reg_DRTRAM2 { 4270 unsigned int : 4; 4271 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4272 unsigned int drtswok : 1; /* DRT Switch OK */ 4273 unsigned int : 2; 4274 }; 4275 4276 #define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2) 4277 4278 #endif /* __ASSEMBLER__ */ 4279 4280 /* DRTRAM2 */ 4281 4282 #define ENDRT 4 4283 #define DRTSWOK 5 4284 4285 /* Data Retention Configuration Register #1 */ 4286 #define DRTRAM1 _SFR_MEM8(0x134) 4287 4288 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4289 4290 struct __reg_DRTRAM1 { 4291 unsigned int : 4; 4292 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4293 unsigned int drtswok : 1; /* DRT Switch OK */ 4294 unsigned int : 2; 4295 }; 4296 4297 #define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1) 4298 4299 #endif /* __ASSEMBLER__ */ 4300 4301 /* DRTRAM1 */ 4302 4303 #define ENDRT 4 4304 #define DRTSWOK 5 4305 4306 /* Data Retention Configuration Register #0 */ 4307 #define DRTRAM0 _SFR_MEM8(0x135) 4308 4309 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4310 4311 struct __reg_DRTRAM0 { 4312 unsigned int : 4; 4313 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4314 unsigned int drtswok : 1; /* DRT Switch OK */ 4315 unsigned int : 2; 4316 }; 4317 4318 #define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0) 4319 4320 #endif /* __ASSEMBLER__ */ 4321 4322 /* DRTRAM0 */ 4323 4324 #define ENDRT 4 4325 #define DRTSWOK 5 4326 4327 /* Port Driver Strength Register 0 */ 4328 #define DPDS0 _SFR_MEM8(0x136) 4329 4330 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4331 4332 struct __reg_DPDS0 { 4333 unsigned int pbdrv : 2; /* Driver Strength Port B */ 4334 unsigned int pddrv : 2; /* Driver Strength Port D */ 4335 unsigned int pedrv : 2; /* Driver Strength Port E */ 4336 unsigned int pfdrv : 2; /* Driver Strength Port F */ 4337 }; 4338 4339 #define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0) 4340 4341 #endif /* __ASSEMBLER__ */ 4342 4343 /* DPDS0 */ 4344 4345 #define PBDRV0 0 4346 #define PBDRV1 1 4347 #define PDDRV0 2 4348 #define PDDRV1 3 4349 #define PEDRV0 4 4350 #define PEDRV1 5 4351 #define PFDRV0 6 4352 #define PFDRV1 7 4353 4354 /* Port Driver Strength Register 1 */ 4355 #define DPDS1 _SFR_MEM8(0x137) 4356 4357 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4358 4359 struct __reg_DPDS1 { 4360 unsigned int pgdrv : 2; /* Driver Strength Port G */ 4361 unsigned int : 6; 4362 }; 4363 4364 #define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1) 4365 4366 #endif /* __ASSEMBLER__ */ 4367 4368 /* DPDS1 */ 4369 4370 #define PGDRV0 0 4371 #define PGDRV1 1 4372 4373 /* Power Amplifier Ramp up/down Control Register */ 4374 #define PARCR _SFR_MEM8(0x138) 4375 4376 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4377 4378 struct __reg_PARCR { 4379 unsigned int parufi : 1; /* Power Amplifier Ramp Up Frequency Inversion */ 4380 unsigned int pardfi : 1; /* Power Amplifier Ramp Down Frequency Inversion */ 4381 unsigned int paltu : 3; /* ext. PA Ramp Up Lead Time */ 4382 unsigned int paltd : 3; /* ext. PA Ramp Down Lead Time */ 4383 }; 4384 4385 #define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR) 4386 4387 /* symbolic names */ 4388 4389 #define PALTU_MINUS_3US 0 4390 #define PALTU_MINUS_2US 1 4391 #define PALTU_MINUS_1US 2 4392 #define PALTU_0US 3 4393 #define PALTU_1US 4 4394 #define PALTU_2US 5 4395 #define PALTU_3US 6 4396 #define PALTU_4US 7 4397 #define PALTD_MINUS_3US 0 4398 #define PALTD_MINUS_2US 1 4399 #define PALTD_MINUS_1US 2 4400 #define PALTD_0US 3 4401 #define PALTD_1US 4 4402 #define PALTD_2US 5 4403 #define PALTD_3US 6 4404 #define PALTD_4US 7 4405 4406 #endif /* __ASSEMBLER__ */ 4407 4408 /* PARCR */ 4409 4410 #define PARUFI 0 4411 #define PARDFI 1 4412 #define PALTU0 2 4413 #define PALTU1 3 4414 #define PALTU2 4 4415 #define PALTD0 5 4416 #define PALTD1 6 4417 #define PALTD2 7 4418 4419 /* Transceiver Pin Register */ 4420 #define TRXPR _SFR_MEM8(0x139) 4421 4422 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4423 4424 struct __reg_TRXPR { 4425 unsigned int trxrst : 1; /* Force Transceiver Reset */ 4426 unsigned int slptr : 1; /* Multi-purpose Transceiver Control Bit */ 4427 unsigned int : 6; 4428 }; 4429 4430 #define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR) 4431 4432 #endif /* __ASSEMBLER__ */ 4433 4434 /* TRXPR */ 4435 4436 #define TRXRST 0 4437 #define SLPTR 1 4438 4439 /* AES Control Register */ 4440 #define AES_CTRL _SFR_MEM8(0x13C) 4441 4442 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4443 4444 struct __reg_AES_CTRL { 4445 unsigned int : 2; 4446 unsigned int aes_im : 1; /* AES Interrupt Enable */ 4447 unsigned int aes_dir : 1; /* Set AES Operation Direction */ 4448 unsigned int : 1; 4449 unsigned int aes_mode : 1; /* Set AES Operation Mode */ 4450 unsigned int : 1; 4451 unsigned int aes_request : 1; /* Request AES Operation. */ 4452 }; 4453 4454 #define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL) 4455 4456 /* symbolic names */ 4457 4458 #define AES_DIR_ENC 0 4459 #define AES_DIR_DEC 1 4460 #define AES_MODE_ECB 0 4461 #define AES_MODE_CBC 1 4462 4463 #endif /* __ASSEMBLER__ */ 4464 4465 /* AES_CTRL */ 4466 4467 #define AES_IM 2 4468 #define AES_DIR 3 4469 #define AES_MODE 5 4470 #define AES_REQUEST 7 4471 4472 /* AES Status Register */ 4473 #define AES_STATUS _SFR_MEM8(0x13D) 4474 4475 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4476 4477 struct __reg_AES_STATUS { 4478 unsigned int aes_done : 1; /* AES Operation Finished with Success */ 4479 unsigned int : 6; 4480 unsigned int aes_er : 1; /* AES Operation Finished with Error */ 4481 }; 4482 4483 #define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS) 4484 4485 #endif /* __ASSEMBLER__ */ 4486 4487 /* AES_STATUS */ 4488 4489 #define AES_DONE 0 4490 #define AES_ER 7 4491 4492 /* AES Plain and Cipher Text Buffer Register */ 4493 #define AES_STATE _SFR_MEM8(0x13E) 4494 4495 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4496 4497 struct __reg_AES_STATE { 4498 unsigned int aes_state : 8; /* AES Plain and Cipher Text Buffer */ 4499 }; 4500 4501 #define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE) 4502 4503 #endif /* __ASSEMBLER__ */ 4504 4505 /* AES_STATE */ 4506 4507 #define AES_STATE0 0 4508 #define AES_STATE1 1 4509 #define AES_STATE2 2 4510 #define AES_STATE3 3 4511 #define AES_STATE4 4 4512 #define AES_STATE5 5 4513 #define AES_STATE6 6 4514 #define AES_STATE7 7 4515 4516 /* AES Encryption and Decryption Key Buffer Register */ 4517 #define AES_KEY _SFR_MEM8(0x13F) 4518 4519 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4520 4521 struct __reg_AES_KEY { 4522 unsigned int aes_key : 8; /* AES Encryption/Decryption Key Buffer */ 4523 }; 4524 4525 #define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY) 4526 4527 #endif /* __ASSEMBLER__ */ 4528 4529 /* AES_KEY */ 4530 4531 #define AES_KEY0 0 4532 #define AES_KEY1 1 4533 #define AES_KEY2 2 4534 #define AES_KEY3 3 4535 #define AES_KEY4 4 4536 #define AES_KEY5 5 4537 #define AES_KEY6 6 4538 #define AES_KEY7 7 4539 4540 /* Transceiver Status Register */ 4541 #define TRX_STATUS _SFR_MEM8(0x141) 4542 4543 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4544 4545 struct __reg_TRX_STATUS { 4546 unsigned int trx_status : 5; /* Transceiver Main Status */ 4547 unsigned int tst_status : 1; /* Test mode status */ 4548 unsigned int cca_status : 1; /* CCA Status Result */ 4549 unsigned int cca_done : 1; /* CCA Algorithm Status */ 4550 }; 4551 4552 #define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS) 4553 4554 /* symbolic names */ 4555 4556 #define BUSY_RX 1 4557 #define BUSY_TX 2 4558 #define RX_ON 6 4559 #define TRX_OFF 8 4560 #define PLL_ON 9 4561 #define SLEEP 15 4562 #define BUSY_RX_AACK 17 4563 #define BUSY_TX_ARET 18 4564 #define RX_AACK_ON 22 4565 #define TX_ARET_ON 25 4566 #define STATE_TRANSITION_IN_PROGRESS 31 4567 #define TST_DISABLED 0 4568 #define TST_ENABLED 1 4569 #define CCA_BUSY 0 4570 #define CCA_IDLE 1 4571 #define CCA_NOT_FIN 0 4572 #define CCA_FIN 1 4573 4574 #endif /* __ASSEMBLER__ */ 4575 4576 /* TRX_STATUS */ 4577 4578 #define TRX_STATUS0 0 4579 #define TRX_STATUS1 1 4580 #define TRX_STATUS2 2 4581 #define TRX_STATUS3 3 4582 #define TRX_STATUS4 4 4583 #define TST_STATUS 5 4584 #define CCA_STATUS 6 4585 #define CCA_DONE 7 4586 4587 /* Transceiver State Control Register */ 4588 #define TRX_STATE _SFR_MEM8(0x142) 4589 4590 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4591 4592 struct __reg_TRX_STATE { 4593 unsigned int trx_cmd : 5; /* State Control Command */ 4594 unsigned int trac_status : 3; /* Transaction Status */ 4595 }; 4596 4597 #define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE) 4598 4599 /* symbolic names */ 4600 4601 #define CMD_NOP 0 4602 #define CMD_TX_START 2 4603 #define CMD_FORCE_TRX_OFF 3 4604 #define CMD_FORCE_PLL_ON 4 4605 #define CMD_RX_ON 6 4606 #define CMD_TRX_OFF 8 4607 #define CMD_PLL_ON 9 4608 #define CMD_RX_AACK_ON 22 4609 #define CMD_TX_ARET_ON 25 4610 #define TRAC_SUCCESS 0 4611 #define TRAC_SUCCESS_DATA_PENDING 1 4612 #define TRAC_SUCCESS_WAIT_FOR_ACK 2 4613 #define TRAC_CHANNEL_ACCESS_FAILURE 3 4614 #define TRAC_NO_ACK 5 4615 #define TRAC_INVALID 7 4616 4617 #endif /* __ASSEMBLER__ */ 4618 4619 /* TRX_STATE */ 4620 4621 #define TRX_CMD0 0 4622 #define TRX_CMD1 1 4623 #define TRX_CMD2 2 4624 #define TRX_CMD3 3 4625 #define TRX_CMD4 4 4626 #define TRAC_STATUS0 5 4627 #define TRAC_STATUS1 6 4628 #define TRAC_STATUS2 7 4629 4630 /* Tranceiver Control Register 0 */ 4631 #define TRX_CTRL_0 _SFR_MEM8(0x143) 4632 4633 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4634 4635 struct __reg_TRX_CTRL_0 { 4636 unsigned int : 4; 4637 unsigned int pmu_if_inv : 1; /* PMU IF Inverse */ 4638 unsigned int pmu_start : 1; /* Start of Phase Measurement Unit */ 4639 unsigned int pmu_en : 1; /* Enable Phase Measurement Unit */ 4640 unsigned int res7 : 1; /* Reserved */ 4641 }; 4642 4643 #define TRX_CTRL_0_struct _SFR_MEM8_STRUCT(0x143, struct __reg_TRX_CTRL_0) 4644 4645 #endif /* __ASSEMBLER__ */ 4646 4647 /* TRX_CTRL_0 */ 4648 4649 #define PMU_IF_INV 4 4650 #define PMU_START 5 4651 #define PMU_EN 6 4652 4653 /* Transceiver Control Register 1 */ 4654 #define TRX_CTRL_1 _SFR_MEM8(0x144) 4655 4656 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4657 4658 struct __reg_TRX_CTRL_1 { 4659 unsigned int : 4; 4660 unsigned int pll_tx_flt : 1; /* Enable PLL TX Filter */ 4661 unsigned int tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */ 4662 unsigned int irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */ 4663 unsigned int pa_ext_en : 1; /* External PA support enable */ 4664 }; 4665 4666 #define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1) 4667 4668 #endif /* __ASSEMBLER__ */ 4669 4670 /* TRX_CTRL_1 */ 4671 4672 #define PLL_TX_FLT 4 4673 #define TX_AUTO_CRC_ON 5 4674 #define IRQ_2_EXT_EN 6 4675 #define PA_EXT_EN 7 4676 4677 /* Transceiver Transmit Power Control Register */ 4678 #define PHY_TX_PWR _SFR_MEM8(0x145) 4679 4680 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4681 4682 struct __reg_PHY_TX_PWR { 4683 unsigned int tx_pwr : 4; /* Transmit Power Setting */ 4684 unsigned int : 4; 4685 }; 4686 4687 #define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR) 4688 4689 #endif /* __ASSEMBLER__ */ 4690 4691 /* PHY_TX_PWR */ 4692 4693 #define TX_PWR0 0 4694 #define TX_PWR1 1 4695 #define TX_PWR2 2 4696 #define TX_PWR3 3 4697 4698 /* Receiver Signal Strength Indicator Register */ 4699 #define PHY_RSSI _SFR_MEM8(0x146) 4700 4701 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4702 4703 struct __reg_PHY_RSSI { 4704 unsigned int rssi : 5; /* Receiver Signal Strength Indicator */ 4705 unsigned int rnd_value : 2; /* Random Value */ 4706 unsigned int rx_crc_valid : 1; /* Received Frame CRC Status */ 4707 }; 4708 4709 #define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI) 4710 4711 /* symbolic names */ 4712 4713 #define RSSI_MIN 0 4714 #define RSSI_MIN_PLUS_3dB 1 4715 #define RSSI_MAX 28 4716 #define CRC_INVALID 0 4717 #define CRC_VALID 1 4718 4719 #endif /* __ASSEMBLER__ */ 4720 4721 /* PHY_RSSI */ 4722 4723 #define RSSI0 0 4724 #define RSSI1 1 4725 #define RSSI2 2 4726 #define RSSI3 3 4727 #define RSSI4 4 4728 #define RND_VALUE0 5 4729 #define RND_VALUE1 6 4730 #define RX_CRC_VALID 7 4731 4732 /* Transceiver Energy Detection Level Register */ 4733 #define PHY_ED_LEVEL _SFR_MEM8(0x147) 4734 4735 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4736 4737 struct __reg_PHY_ED_LEVEL { 4738 unsigned int ed_level : 8; /* Energy Detection Level */ 4739 }; 4740 4741 #define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL) 4742 4743 /* symbolic names */ 4744 4745 #define ED_MIN 0 4746 #define ED_MIN_PLUS_1dB 1 4747 #define ED_MAX 83 4748 #define ED_RESET 255 4749 4750 #endif /* __ASSEMBLER__ */ 4751 4752 /* PHY_ED_LEVEL */ 4753 4754 #define ED_LEVEL0 0 4755 #define ED_LEVEL1 1 4756 #define ED_LEVEL2 2 4757 #define ED_LEVEL3 3 4758 #define ED_LEVEL4 4 4759 #define ED_LEVEL5 5 4760 #define ED_LEVEL6 6 4761 #define ED_LEVEL7 7 4762 4763 /* Transceiver Clear Channel Assessment (CCA) Control Register */ 4764 #define PHY_CC_CCA _SFR_MEM8(0x148) 4765 4766 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4767 4768 struct __reg_PHY_CC_CCA { 4769 unsigned int channel : 5; /* RX/TX Channel Selection */ 4770 unsigned int cca_mode : 2; /* Select CCA Measurement Mode */ 4771 unsigned int cca_request : 1; /* Manual CCA Measurement Request */ 4772 }; 4773 4774 #define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA) 4775 4776 /* symbolic names */ 4777 4778 #define F_2405MHZ 11 4779 #define F_2410MHZ 12 4780 #define F_2415MHZ 13 4781 #define F_2420MHZ 14 4782 #define F_2425MHZ 15 4783 #define F_2430MHZ 16 4784 #define F_2435MHZ 17 4785 #define F_2440MHZ 18 4786 #define F_2445MHZ 19 4787 #define F_2450MHZ 20 4788 #define F_2455MHZ 21 4789 #define F_2460MHZ 22 4790 #define F_2465MHZ 23 4791 #define F_2470MHZ 24 4792 #define F_2475MHZ 25 4793 #define F_2480MHZ 26 4794 #define CCA_CS_OR_ED 0 4795 #define CCA_ED 1 4796 #define CCA_CS 2 4797 #define CCA_CS_AND_ED 3 4798 4799 #endif /* __ASSEMBLER__ */ 4800 4801 /* PHY_CC_CCA */ 4802 4803 #define CHANNEL0 0 4804 #define CHANNEL1 1 4805 #define CHANNEL2 2 4806 #define CHANNEL3 3 4807 #define CHANNEL4 4 4808 #define CCA_MODE0 5 4809 #define CCA_MODE1 6 4810 #define CCA_REQUEST 7 4811 4812 /* Transceiver CCA Threshold Setting Register */ 4813 #define CCA_THRES _SFR_MEM8(0x149) 4814 4815 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4816 4817 struct __reg_CCA_THRES { 4818 unsigned int cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */ 4819 unsigned int cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */ 4820 }; 4821 4822 #define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES) 4823 4824 #endif /* __ASSEMBLER__ */ 4825 4826 /* CCA_THRES */ 4827 4828 #define CCA_ED_THRES0 0 4829 #define CCA_ED_THRES1 1 4830 #define CCA_ED_THRES2 2 4831 #define CCA_ED_THRES3 3 4832 #define CCA_CS_THRES0 4 4833 #define CCA_CS_THRES1 5 4834 #define CCA_CS_THRES2 6 4835 #define CCA_CS_THRES3 7 4836 4837 /* Transceiver Receive Control Register */ 4838 #define RX_CTRL _SFR_MEM8(0x14A) 4839 4840 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4841 4842 struct __reg_RX_CTRL { 4843 unsigned int pdt_thres : 4; /* Receiver Sensitivity Control */ 4844 unsigned int : 4; 4845 }; 4846 4847 #define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL) 4848 4849 /* symbolic names */ 4850 4851 #define PDT_THRES_ANT_DIV_OFF 7 4852 #define PDT_THRES_ANT_DIV_ON 3 4853 4854 #endif /* __ASSEMBLER__ */ 4855 4856 /* RX_CTRL */ 4857 4858 #define PDT_THRES0 0 4859 #define PDT_THRES1 1 4860 #define PDT_THRES2 2 4861 #define PDT_THRES3 3 4862 4863 /* Start of Frame Delimiter Value Register */ 4864 #define SFD_VALUE _SFR_MEM8(0x14B) 4865 4866 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4867 4868 struct __reg_SFD_VALUE { 4869 unsigned int sfd_value : 8; /* Start of Frame Delimiter Value */ 4870 }; 4871 4872 #define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE) 4873 4874 /* symbolic names */ 4875 4876 #define IEEE_SFD 167 4877 4878 #endif /* __ASSEMBLER__ */ 4879 4880 /* SFD_VALUE */ 4881 4882 #define SFD_VALUE0 0 4883 #define SFD_VALUE1 1 4884 #define SFD_VALUE2 2 4885 #define SFD_VALUE3 3 4886 #define SFD_VALUE4 4 4887 #define SFD_VALUE5 5 4888 #define SFD_VALUE6 6 4889 #define SFD_VALUE7 7 4890 4891 /* Transceiver Control Register 2 */ 4892 #define TRX_CTRL_2 _SFR_MEM8(0x14C) 4893 4894 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4895 4896 struct __reg_TRX_CTRL_2 { 4897 unsigned int oqpsk_data_rate : 2; /* Data Rate Selection */ 4898 unsigned int : 5; 4899 unsigned int rx_safe_mode : 1; /* RX Safe Mode */ 4900 }; 4901 4902 #define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2) 4903 4904 /* symbolic names */ 4905 4906 #define RATE_250KB 0 4907 #define RATE_500KB 1 4908 #define RATE_1000KB 2 4909 #define RATE_2000KB 3 4910 4911 #endif /* __ASSEMBLER__ */ 4912 4913 /* TRX_CTRL_2 */ 4914 4915 #define OQPSK_DATA_RATE0 0 4916 #define OQPSK_DATA_RATE1 1 4917 #define RX_SAFE_MODE 7 4918 4919 /* Antenna Diversity Control Register */ 4920 #define ANT_DIV _SFR_MEM8(0x14D) 4921 4922 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4923 4924 struct __reg_ANT_DIV { 4925 unsigned int ant_ctrl : 2; /* Static Antenna Diversity Switch Control */ 4926 unsigned int ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */ 4927 unsigned int ant_div_en : 1; /* Enable Antenna Diversity */ 4928 unsigned int : 3; 4929 unsigned int ant_sel : 1; /* Antenna Diversity Antenna Status */ 4930 }; 4931 4932 #define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV) 4933 4934 /* symbolic names */ 4935 4936 #define ANT_1 1 4937 #define ANT_0 2 4938 #define ANT_RESET 3 4939 #define ANT_DIV_EXT_SW_DIS 0 4940 #define ANT_DIV_EXT_SW_EN 1 4941 #define ANTENNA_0 0 4942 #define ANTENNA_1 1 4943 4944 #endif /* __ASSEMBLER__ */ 4945 4946 /* ANT_DIV */ 4947 4948 #define ANT_CTRL0 0 4949 #define ANT_CTRL1 1 4950 #define ANT_EXT_SW_EN 2 4951 #define ANT_DIV_EN 3 4952 #define ANT_SEL 7 4953 4954 /* Transceiver Interrupt Enable Register */ 4955 #define IRQ_MASK _SFR_MEM8(0x14E) 4956 4957 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4958 4959 struct __reg_IRQ_MASK { 4960 unsigned int pll_lock_en : 1; /* PLL Lock Interrupt Enable */ 4961 unsigned int pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */ 4962 unsigned int rx_start_en : 1; /* RX_START Interrupt Enable */ 4963 unsigned int rx_end_en : 1; /* RX_END Interrupt Enable */ 4964 unsigned int cca_ed_done_en : 1; /* End of ED Measurement Interrupt Enable */ 4965 unsigned int ami_en : 1; /* Address Match Interrupt Enable */ 4966 unsigned int tx_end_en : 1; /* TX_END Interrupt Enable */ 4967 unsigned int awake_en : 1; /* Awake Interrupt Enable */ 4968 }; 4969 4970 #define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK) 4971 4972 #endif /* __ASSEMBLER__ */ 4973 4974 /* IRQ_MASK */ 4975 4976 #define PLL_LOCK_EN 0 4977 #define PLL_UNLOCK_EN 1 4978 #define RX_START_EN 2 4979 #define RX_END_EN 3 4980 #define CCA_ED_DONE_EN 4 4981 #define AMI_EN 5 4982 #define TX_END_EN 6 4983 #define AWAKE_EN 7 4984 4985 /* Transceiver Interrupt Status Register */ 4986 #define IRQ_STATUS _SFR_MEM8(0x14F) 4987 4988 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4989 4990 struct __reg_IRQ_STATUS { 4991 unsigned int pll_lock : 1; /* PLL Lock Interrupt Status */ 4992 unsigned int pll_unlock : 1; /* PLL Unlock Interrupt Status */ 4993 unsigned int rx_start : 1; /* RX_START Interrupt Status */ 4994 unsigned int rx_end : 1; /* RX_END Interrupt Status */ 4995 unsigned int cca_ed_done : 1; /* End of ED Measurement Interrupt Status */ 4996 unsigned int ami : 1; /* Address Match Interrupt Status */ 4997 unsigned int tx_end : 1; /* TX_END Interrupt Status */ 4998 unsigned int awake : 1; /* Awake Interrupt Status */ 4999 }; 5000 5001 #define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS) 5002 5003 #endif /* __ASSEMBLER__ */ 5004 5005 /* IRQ_STATUS */ 5006 5007 #define PLL_LOCK 0 5008 #define PLL_UNLOCK 1 5009 #define RX_START 2 5010 #define RX_END 3 5011 #define CCA_ED_DONE 4 5012 #define AMI 5 5013 #define TX_END 6 5014 #define AWAKE 7 5015 5016 /* Voltage Regulator Control and Status Register */ 5017 #define VREG_CTRL _SFR_MEM8(0x150) 5018 5019 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5020 5021 struct __reg_VREG_CTRL { 5022 unsigned int : 2; 5023 unsigned int dvdd_ok : 1; /* DVDD Supply Voltage Valid */ 5024 unsigned int dvreg_ext : 1; /* Use External DVDD Regulator */ 5025 unsigned int : 2; 5026 unsigned int avdd_ok : 1; /* AVDD Supply Voltage Valid */ 5027 unsigned int avreg_ext : 1; /* Use External AVDD Regulator */ 5028 }; 5029 5030 #define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL) 5031 5032 /* symbolic names */ 5033 5034 #define DVDD_INT 0 5035 #define DVDD_EXT 1 5036 #define AVDD_INT 0 5037 #define AVDD_EXT 1 5038 5039 #endif /* __ASSEMBLER__ */ 5040 5041 /* VREG_CTRL */ 5042 5043 #define DVDD_OK 2 5044 #define DVREG_EXT 3 5045 #define AVDD_OK 6 5046 #define AVREG_EXT 7 5047 5048 /* Battery Monitor Control and Status Register */ 5049 #define BATMON _SFR_MEM8(0x151) 5050 5051 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5052 5053 struct __reg_BATMON { 5054 unsigned int batmon_vth : 4; /* Battery Monitor Threshold Voltage */ 5055 unsigned int batmon_hr : 1; /* Battery Monitor Voltage Range */ 5056 unsigned int batmon_ok : 1; /* Battery Monitor Status */ 5057 unsigned int bat_low_en : 1; /* Battery Monitor Interrupt Enable */ 5058 unsigned int bat_low : 1; /* Battery Monitor Interrupt Status */ 5059 }; 5060 5061 #define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON) 5062 5063 /* symbolic names */ 5064 5065 #define BATMON_HR_DIS 0 5066 #define BATMON_HR_EN 1 5067 5068 #endif /* __ASSEMBLER__ */ 5069 5070 /* BATMON */ 5071 5072 #define BATMON_VTH0 0 5073 #define BATMON_VTH1 1 5074 #define BATMON_VTH2 2 5075 #define BATMON_VTH3 3 5076 #define BATMON_HR 4 5077 #define BATMON_OK 5 5078 #define BAT_LOW_EN 6 5079 #define BAT_LOW 7 5080 5081 /* Crystal Oscillator Control Register */ 5082 #define XOSC_CTRL _SFR_MEM8(0x152) 5083 5084 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5085 5086 struct __reg_XOSC_CTRL { 5087 unsigned int xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */ 5088 unsigned int xtal_mode : 4; /* Crystal Oscillator Operating Mode */ 5089 }; 5090 5091 #define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL) 5092 5093 /* symbolic names */ 5094 5095 #define XTAL_TRIM_MIN 0 5096 #define XTAL_TRIM_MAX 15 5097 5098 #endif /* __ASSEMBLER__ */ 5099 5100 /* XOSC_CTRL */ 5101 5102 #define XTAL_TRIM0 0 5103 #define XTAL_TRIM1 1 5104 #define XTAL_TRIM2 2 5105 #define XTAL_TRIM3 3 5106 #define XTAL_MODE0 4 5107 #define XTAL_MODE1 5 5108 #define XTAL_MODE2 6 5109 #define XTAL_MODE3 7 5110 5111 /* Channel Control Register 0 */ 5112 #define CC_CTRL_0 _SFR_MEM8(0x153) 5113 5114 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5115 5116 struct __reg_CC_CTRL_0 { 5117 unsigned int cc_number : 8; /* Channel Number */ 5118 }; 5119 5120 #define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0) 5121 5122 #endif /* __ASSEMBLER__ */ 5123 5124 /* CC_CTRL_0 */ 5125 5126 #define CC_NUMBER0 0 5127 #define CC_NUMBER1 1 5128 #define CC_NUMBER2 2 5129 #define CC_NUMBER3 3 5130 #define CC_NUMBER4 4 5131 #define CC_NUMBER5 5 5132 #define CC_NUMBER6 6 5133 #define CC_NUMBER7 7 5134 5135 /* Channel Control Register 1 */ 5136 #define CC_CTRL_1 _SFR_MEM8(0x154) 5137 5138 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5139 5140 struct __reg_CC_CTRL_1 { 5141 unsigned int cc_band : 4; /* Channel Band */ 5142 unsigned int : 4; 5143 }; 5144 5145 #define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1) 5146 5147 #endif /* __ASSEMBLER__ */ 5148 5149 /* CC_CTRL_1 */ 5150 5151 #define CC_BAND0 0 5152 #define CC_BAND1 1 5153 #define CC_BAND2 2 5154 #define CC_BAND3 3 5155 5156 /* Transceiver Receiver Sensitivity Control Register */ 5157 #define RX_SYN _SFR_MEM8(0x155) 5158 5159 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5160 5161 struct __reg_RX_SYN { 5162 unsigned int rx_pdt_level : 4; /* Reduce Receiver Sensitivity */ 5163 unsigned int : 2; 5164 unsigned int rx_override : 1; /* Receiver Override Function */ 5165 unsigned int rx_pdt_dis : 1; /* Prevent Frame Reception */ 5166 }; 5167 5168 #define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN) 5169 5170 /* symbolic names */ 5171 5172 #define RX_PDT_LEVEL_MIN 0 5173 #define RX_PDT_LEVEL_MAX 15 5174 5175 #endif /* __ASSEMBLER__ */ 5176 5177 /* RX_SYN */ 5178 5179 #define RX_PDT_LEVEL0 0 5180 #define RX_PDT_LEVEL1 1 5181 #define RX_PDT_LEVEL2 2 5182 #define RX_PDT_LEVEL3 3 5183 #define RX_OVERRIDE 6 5184 #define RX_PDT_DIS 7 5185 5186 /* Transceiver Reduced Power Consumption Control */ 5187 #define TRX_RPC _SFR_MEM8(0x156) 5188 5189 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5190 5191 struct __reg_TRX_RPC { 5192 unsigned int : 1; 5193 unsigned int ipan_rpc_en : 1; /* Smart Receiving Mode IPAN Handling Enable */ 5194 unsigned int res0 : 1; /* Reserved */ 5195 unsigned int pll_rpc_en : 1; /* PLL Smart Receiving Mode Enable */ 5196 unsigned int pdt_rpc_en : 1; /* Smart Receiving Mode Reduced Sensitivity Enable */ 5197 unsigned int rx_rpc_en : 1; /* Receiver Smart Receiving Mode Enable */ 5198 unsigned int rx_rpc_ctrl : 2; /* Smart Receiving Mode Timing */ 5199 }; 5200 5201 #define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC) 5202 5203 #endif /* __ASSEMBLER__ */ 5204 5205 /* TRX_RPC */ 5206 5207 #define IPAN_RPC_EN 1 5208 #define PLL_RPC_EN 3 5209 #define PDT_RPC_EN 4 5210 #define RX_RPC_EN 5 5211 #define RX_RPC_CTRL0 6 5212 #define RX_RPC_CTRL1 7 5213 5214 /* Transceiver Acknowledgment Frame Control Register 1 */ 5215 #define XAH_CTRL_1 _SFR_MEM8(0x157) 5216 5217 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5218 5219 struct __reg_XAH_CTRL_1 { 5220 unsigned int : 1; 5221 unsigned int aack_prom_mode : 1; /* Enable Promiscuous Mode */ 5222 unsigned int aack_ack_time : 1; /* Reduce Acknowledgment Time */ 5223 unsigned int : 1; 5224 unsigned int aack_upld_res_ft : 1; /* Process Reserved Frames */ 5225 unsigned int aack_fltr_res_ft : 1; /* Filter Reserved Frames */ 5226 unsigned int : 2; 5227 }; 5228 5229 #define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1) 5230 5231 /* symbolic names */ 5232 5233 #define AACK_ACK_TIME_12_SYM 0 5234 #define AACK_ACK_TIME_2_SYM 1 5235 5236 #endif /* __ASSEMBLER__ */ 5237 5238 /* XAH_CTRL_1 */ 5239 5240 #define AACK_PROM_MODE 1 5241 #define AACK_ACK_TIME 2 5242 #define AACK_UPLD_RES_FT 4 5243 #define AACK_FLTR_RES_FT 5 5244 5245 /* Transceiver Filter Tuning Control Register */ 5246 #define FTN_CTRL _SFR_MEM8(0x158) 5247 5248 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5249 5250 struct __reg_FTN_CTRL { 5251 unsigned int : 7; 5252 unsigned int ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */ 5253 }; 5254 5255 #define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL) 5256 5257 #endif /* __ASSEMBLER__ */ 5258 5259 /* FTN_CTRL */ 5260 5261 #define FTN_START 7 5262 5263 /* Transceiver Center Frequency Calibration Control Register */ 5264 #define PLL_CF _SFR_MEM8(0x15A) 5265 5266 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5267 5268 struct __reg_PLL_CF { 5269 unsigned int : 7; 5270 unsigned int pll_cf_start : 1; /* Start Center Frequency Calibration */ 5271 }; 5272 5273 #define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF) 5274 5275 #endif /* __ASSEMBLER__ */ 5276 5277 /* PLL_CF */ 5278 5279 #define PLL_CF_START 7 5280 5281 /* Transceiver Delay Cell Calibration Control Register */ 5282 #define PLL_DCU _SFR_MEM8(0x15B) 5283 5284 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5285 5286 struct __reg_PLL_DCU { 5287 unsigned int : 7; 5288 unsigned int pll_dcu_start : 1; /* Start Delay Cell Calibration */ 5289 }; 5290 5291 #define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU) 5292 5293 #endif /* __ASSEMBLER__ */ 5294 5295 /* PLL_DCU */ 5296 5297 #define PLL_DCU_START 7 5298 5299 /* Device Identification Register (Part Number) */ 5300 #define PART_NUM _SFR_MEM8(0x15C) 5301 5302 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5303 5304 struct __reg_PART_NUM { 5305 unsigned int part_num : 8; /* Part Number */ 5306 }; 5307 5308 #define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM) 5309 5310 /* symbolic names */ 5311 5312 #define P_RFR2 148 5313 5314 #endif /* __ASSEMBLER__ */ 5315 5316 /* PART_NUM */ 5317 5318 #define PART_NUM0 0 5319 #define PART_NUM1 1 5320 #define PART_NUM2 2 5321 #define PART_NUM3 3 5322 #define PART_NUM4 4 5323 #define PART_NUM5 5 5324 #define PART_NUM6 6 5325 #define PART_NUM7 7 5326 5327 /* Device Identification Register (Version Number) */ 5328 #define VERSION_NUM _SFR_MEM8(0x15D) 5329 5330 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5331 5332 struct __reg_VERSION_NUM { 5333 unsigned int version_num : 8; /* Version Number */ 5334 }; 5335 5336 #define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM) 5337 5338 /* symbolic names */ 5339 5340 #define REV_A 12 5341 #define REV_B 1 5342 #define REV_C 3 5343 #define REV_D 4 5344 5345 #endif /* __ASSEMBLER__ */ 5346 5347 /* VERSION_NUM */ 5348 5349 #define VERSION_NUM0 0 5350 #define VERSION_NUM1 1 5351 #define VERSION_NUM2 2 5352 #define VERSION_NUM3 3 5353 #define VERSION_NUM4 4 5354 #define VERSION_NUM5 5 5355 #define VERSION_NUM6 6 5356 #define VERSION_NUM7 7 5357 5358 /* Device Identification Register (Manufacture ID Low Byte) */ 5359 #define MAN_ID_0 _SFR_MEM8(0x15E) 5360 5361 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5362 5363 struct __reg_MAN_ID_0 { 5364 unsigned int man_id_00 : 1; /* Manufacturer ID (Low Byte) */ 5365 unsigned int man_id_01 : 1; /* Manufacturer ID (Low Byte) */ 5366 unsigned int man_id_02 : 1; /* Manufacturer ID (Low Byte) */ 5367 unsigned int man_id_03 : 1; /* Manufacturer ID (Low Byte) */ 5368 unsigned int man_id_04 : 1; /* Manufacturer ID (Low Byte) */ 5369 unsigned int man_id_05 : 1; /* Manufacturer ID (Low Byte) */ 5370 unsigned int man_id_06 : 1; /* Manufacturer ID (Low Byte) */ 5371 unsigned int man_id_07 : 1; /* Manufacturer ID (Low Byte) */ 5372 }; 5373 5374 #define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0) 5375 5376 /* symbolic names */ 5377 5378 #define ATMEL_BYTE_0 31 5379 5380 #endif /* __ASSEMBLER__ */ 5381 5382 /* MAN_ID_0 */ 5383 5384 #define MAN_ID_00 0 5385 #define MAN_ID_01 1 5386 #define MAN_ID_02 2 5387 #define MAN_ID_03 3 5388 #define MAN_ID_04 4 5389 #define MAN_ID_05 5 5390 #define MAN_ID_06 6 5391 #define MAN_ID_07 7 5392 5393 /* Device Identification Register (Manufacture ID High Byte) */ 5394 #define MAN_ID_1 _SFR_MEM8(0x15F) 5395 5396 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5397 5398 struct __reg_MAN_ID_1 { 5399 unsigned int man_id_ : 8; /* Manufacturer ID (High Byte) */ 5400 }; 5401 5402 #define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1) 5403 5404 /* symbolic names */ 5405 5406 #define ATMEL_BYTE_1 0 5407 5408 #endif /* __ASSEMBLER__ */ 5409 5410 /* MAN_ID_1 */ 5411 5412 #define MAN_ID_10 0 5413 #define MAN_ID_11 1 5414 #define MAN_ID_12 2 5415 #define MAN_ID_13 3 5416 #define MAN_ID_14 4 5417 #define MAN_ID_15 5 5418 #define MAN_ID_16 6 5419 #define MAN_ID_17 7 5420 5421 /* Transceiver MAC Short Address Register (Low Byte) */ 5422 #define SHORT_ADDR_0 _SFR_MEM8(0x160) 5423 5424 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5425 5426 struct __reg_SHORT_ADDR_0 { 5427 unsigned int short_addr_00 : 1; /* MAC Short Address */ 5428 unsigned int short_addr_01 : 1; /* MAC Short Address */ 5429 unsigned int short_addr_02 : 1; /* MAC Short Address */ 5430 unsigned int short_addr_03 : 1; /* MAC Short Address */ 5431 unsigned int short_addr_04 : 1; /* MAC Short Address */ 5432 unsigned int short_addr_05 : 1; /* MAC Short Address */ 5433 unsigned int short_addr_06 : 1; /* MAC Short Address */ 5434 unsigned int short_addr_07 : 1; /* MAC Short Address */ 5435 }; 5436 5437 #define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0) 5438 5439 #endif /* __ASSEMBLER__ */ 5440 5441 /* SHORT_ADDR_0 */ 5442 5443 #define SHORT_ADDR_00 0 5444 #define SHORT_ADDR_01 1 5445 #define SHORT_ADDR_02 2 5446 #define SHORT_ADDR_03 3 5447 #define SHORT_ADDR_04 4 5448 #define SHORT_ADDR_05 5 5449 #define SHORT_ADDR_06 6 5450 #define SHORT_ADDR_07 7 5451 5452 /* Transceiver MAC Short Address Register (High Byte) */ 5453 #define SHORT_ADDR_1 _SFR_MEM8(0x161) 5454 5455 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5456 5457 struct __reg_SHORT_ADDR_1 { 5458 unsigned int short_addr_ : 8; /* MAC Short Address */ 5459 }; 5460 5461 #define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1) 5462 5463 #endif /* __ASSEMBLER__ */ 5464 5465 /* SHORT_ADDR_1 */ 5466 5467 #define SHORT_ADDR_10 0 5468 #define SHORT_ADDR_11 1 5469 #define SHORT_ADDR_12 2 5470 #define SHORT_ADDR_13 3 5471 #define SHORT_ADDR_14 4 5472 #define SHORT_ADDR_15 5 5473 #define SHORT_ADDR_16 6 5474 #define SHORT_ADDR_17 7 5475 5476 /* Transceiver Personal Area Network ID Register (Low Byte) */ 5477 #define PAN_ID_0 _SFR_MEM8(0x162) 5478 5479 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5480 5481 struct __reg_PAN_ID_0 { 5482 unsigned int pan_id_00 : 1; /* MAC Personal Area Network ID */ 5483 unsigned int pan_id_01 : 1; /* MAC Personal Area Network ID */ 5484 unsigned int pan_id_02 : 1; /* MAC Personal Area Network ID */ 5485 unsigned int pan_id_03 : 1; /* MAC Personal Area Network ID */ 5486 unsigned int pan_id_04 : 1; /* MAC Personal Area Network ID */ 5487 unsigned int pan_id_05 : 1; /* MAC Personal Area Network ID */ 5488 unsigned int pan_id_06 : 1; /* MAC Personal Area Network ID */ 5489 unsigned int pan_id_07 : 1; /* MAC Personal Area Network ID */ 5490 }; 5491 5492 #define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0) 5493 5494 #endif /* __ASSEMBLER__ */ 5495 5496 /* PAN_ID_0 */ 5497 5498 #define PAN_ID_00 0 5499 #define PAN_ID_01 1 5500 #define PAN_ID_02 2 5501 #define PAN_ID_03 3 5502 #define PAN_ID_04 4 5503 #define PAN_ID_05 5 5504 #define PAN_ID_06 6 5505 #define PAN_ID_07 7 5506 5507 /* Transceiver Personal Area Network ID Register (High Byte) */ 5508 #define PAN_ID_1 _SFR_MEM8(0x163) 5509 5510 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5511 5512 struct __reg_PAN_ID_1 { 5513 unsigned int pan_id_ : 8; /* MAC Personal Area Network ID */ 5514 }; 5515 5516 #define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1) 5517 5518 #endif /* __ASSEMBLER__ */ 5519 5520 /* PAN_ID_1 */ 5521 5522 #define PAN_ID_10 0 5523 #define PAN_ID_11 1 5524 #define PAN_ID_12 2 5525 #define PAN_ID_13 3 5526 #define PAN_ID_14 4 5527 #define PAN_ID_15 5 5528 #define PAN_ID_16 6 5529 #define PAN_ID_17 7 5530 5531 /* Transceiver MAC IEEE Address Register 0 */ 5532 #define IEEE_ADDR_0 _SFR_MEM8(0x164) 5533 5534 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5535 5536 struct __reg_IEEE_ADDR_0 { 5537 unsigned int ieee_addr_00 : 1; /* MAC IEEE Address */ 5538 unsigned int ieee_addr_01 : 1; /* MAC IEEE Address */ 5539 unsigned int ieee_addr_02 : 1; /* MAC IEEE Address */ 5540 unsigned int ieee_addr_03 : 1; /* MAC IEEE Address */ 5541 unsigned int ieee_addr_04 : 1; /* MAC IEEE Address */ 5542 unsigned int ieee_addr_05 : 1; /* MAC IEEE Address */ 5543 unsigned int ieee_addr_06 : 1; /* MAC IEEE Address */ 5544 unsigned int ieee_addr_07 : 1; /* MAC IEEE Address */ 5545 }; 5546 5547 #define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0) 5548 5549 #endif /* __ASSEMBLER__ */ 5550 5551 /* IEEE_ADDR_0 */ 5552 5553 #define IEEE_ADDR_00 0 5554 #define IEEE_ADDR_01 1 5555 #define IEEE_ADDR_02 2 5556 #define IEEE_ADDR_03 3 5557 #define IEEE_ADDR_04 4 5558 #define IEEE_ADDR_05 5 5559 #define IEEE_ADDR_06 6 5560 #define IEEE_ADDR_07 7 5561 5562 /* Transceiver MAC IEEE Address Register 1 */ 5563 #define IEEE_ADDR_1 _SFR_MEM8(0x165) 5564 5565 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5566 5567 struct __reg_IEEE_ADDR_1 { 5568 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5569 }; 5570 5571 #define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1) 5572 5573 #endif /* __ASSEMBLER__ */ 5574 5575 /* IEEE_ADDR_1 */ 5576 5577 #define IEEE_ADDR_10 0 5578 #define IEEE_ADDR_11 1 5579 #define IEEE_ADDR_12 2 5580 #define IEEE_ADDR_13 3 5581 #define IEEE_ADDR_14 4 5582 #define IEEE_ADDR_15 5 5583 #define IEEE_ADDR_16 6 5584 #define IEEE_ADDR_17 7 5585 5586 /* Transceiver MAC IEEE Address Register 2 */ 5587 #define IEEE_ADDR_2 _SFR_MEM8(0x166) 5588 5589 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5590 5591 struct __reg_IEEE_ADDR_2 { 5592 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5593 }; 5594 5595 #define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2) 5596 5597 #endif /* __ASSEMBLER__ */ 5598 5599 /* IEEE_ADDR_2 */ 5600 5601 #define IEEE_ADDR_20 0 5602 #define IEEE_ADDR_21 1 5603 #define IEEE_ADDR_22 2 5604 #define IEEE_ADDR_23 3 5605 #define IEEE_ADDR_24 4 5606 #define IEEE_ADDR_25 5 5607 #define IEEE_ADDR_26 6 5608 #define IEEE_ADDR_27 7 5609 5610 /* Transceiver MAC IEEE Address Register 3 */ 5611 #define IEEE_ADDR_3 _SFR_MEM8(0x167) 5612 5613 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5614 5615 struct __reg_IEEE_ADDR_3 { 5616 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5617 }; 5618 5619 #define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3) 5620 5621 #endif /* __ASSEMBLER__ */ 5622 5623 /* IEEE_ADDR_3 */ 5624 5625 #define IEEE_ADDR_30 0 5626 #define IEEE_ADDR_31 1 5627 #define IEEE_ADDR_32 2 5628 #define IEEE_ADDR_33 3 5629 #define IEEE_ADDR_34 4 5630 #define IEEE_ADDR_35 5 5631 #define IEEE_ADDR_36 6 5632 #define IEEE_ADDR_37 7 5633 5634 /* Transceiver MAC IEEE Address Register 4 */ 5635 #define IEEE_ADDR_4 _SFR_MEM8(0x168) 5636 5637 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5638 5639 struct __reg_IEEE_ADDR_4 { 5640 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5641 }; 5642 5643 #define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4) 5644 5645 #endif /* __ASSEMBLER__ */ 5646 5647 /* IEEE_ADDR_4 */ 5648 5649 #define IEEE_ADDR_40 0 5650 #define IEEE_ADDR_41 1 5651 #define IEEE_ADDR_42 2 5652 #define IEEE_ADDR_43 3 5653 #define IEEE_ADDR_44 4 5654 #define IEEE_ADDR_45 5 5655 #define IEEE_ADDR_46 6 5656 #define IEEE_ADDR_47 7 5657 5658 /* Transceiver MAC IEEE Address Register 5 */ 5659 #define IEEE_ADDR_5 _SFR_MEM8(0x169) 5660 5661 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5662 5663 struct __reg_IEEE_ADDR_5 { 5664 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5665 }; 5666 5667 #define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5) 5668 5669 #endif /* __ASSEMBLER__ */ 5670 5671 /* IEEE_ADDR_5 */ 5672 5673 #define IEEE_ADDR_50 0 5674 #define IEEE_ADDR_51 1 5675 #define IEEE_ADDR_52 2 5676 #define IEEE_ADDR_53 3 5677 #define IEEE_ADDR_54 4 5678 #define IEEE_ADDR_55 5 5679 #define IEEE_ADDR_56 6 5680 #define IEEE_ADDR_57 7 5681 5682 /* Transceiver MAC IEEE Address Register 6 */ 5683 #define IEEE_ADDR_6 _SFR_MEM8(0x16A) 5684 5685 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5686 5687 struct __reg_IEEE_ADDR_6 { 5688 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5689 }; 5690 5691 #define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6) 5692 5693 #endif /* __ASSEMBLER__ */ 5694 5695 /* IEEE_ADDR_6 */ 5696 5697 #define IEEE_ADDR_60 0 5698 #define IEEE_ADDR_61 1 5699 #define IEEE_ADDR_62 2 5700 #define IEEE_ADDR_63 3 5701 #define IEEE_ADDR_64 4 5702 #define IEEE_ADDR_65 5 5703 #define IEEE_ADDR_66 6 5704 #define IEEE_ADDR_67 7 5705 5706 /* Transceiver MAC IEEE Address Register 7 */ 5707 #define IEEE_ADDR_7 _SFR_MEM8(0x16B) 5708 5709 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5710 5711 struct __reg_IEEE_ADDR_7 { 5712 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5713 }; 5714 5715 #define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7) 5716 5717 #endif /* __ASSEMBLER__ */ 5718 5719 /* IEEE_ADDR_7 */ 5720 5721 #define IEEE_ADDR_70 0 5722 #define IEEE_ADDR_71 1 5723 #define IEEE_ADDR_72 2 5724 #define IEEE_ADDR_73 3 5725 #define IEEE_ADDR_74 4 5726 #define IEEE_ADDR_75 5 5727 #define IEEE_ADDR_76 6 5728 #define IEEE_ADDR_77 7 5729 5730 /* Transceiver Extended Operating Mode Control Register */ 5731 #define XAH_CTRL_0 _SFR_MEM8(0x16C) 5732 5733 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5734 5735 struct __reg_XAH_CTRL_0 { 5736 unsigned int slotted_operation : 1; /* Set Slotted Acknowledgment */ 5737 unsigned int max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */ 5738 unsigned int max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */ 5739 }; 5740 5741 #define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0) 5742 5743 /* symbolic names */ 5744 5745 #define SLOTTED_OP_DIS 0 5746 #define SLOTTED_OP_EN 1 5747 5748 #endif /* __ASSEMBLER__ */ 5749 5750 /* XAH_CTRL_0 */ 5751 5752 #define SLOTTED_OPERATION 0 5753 #define MAX_CSMA_RETRIES0 1 5754 #define MAX_CSMA_RETRIES1 2 5755 #define MAX_CSMA_RETRIES2 3 5756 #define MAX_FRAME_RETRIES0 4 5757 #define MAX_FRAME_RETRIES1 5 5758 #define MAX_FRAME_RETRIES2 6 5759 #define MAX_FRAME_RETRIES3 7 5760 5761 /* Transceiver CSMA-CA Random Number Generator Seed Register */ 5762 #define CSMA_SEED_0 _SFR_MEM8(0x16D) 5763 5764 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5765 5766 struct __reg_CSMA_SEED_0 { 5767 unsigned int csma_seed_00 : 1; /* Seed Value for CSMA Random Number Generator */ 5768 unsigned int csma_seed_01 : 1; /* Seed Value for CSMA Random Number Generator */ 5769 unsigned int csma_seed_02 : 1; /* Seed Value for CSMA Random Number Generator */ 5770 unsigned int csma_seed_03 : 1; /* Seed Value for CSMA Random Number Generator */ 5771 unsigned int csma_seed_04 : 1; /* Seed Value for CSMA Random Number Generator */ 5772 unsigned int csma_seed_05 : 1; /* Seed Value for CSMA Random Number Generator */ 5773 unsigned int csma_seed_06 : 1; /* Seed Value for CSMA Random Number Generator */ 5774 unsigned int csma_seed_07 : 1; /* Seed Value for CSMA Random Number Generator */ 5775 }; 5776 5777 #define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0) 5778 5779 #endif /* __ASSEMBLER__ */ 5780 5781 /* CSMA_SEED_0 */ 5782 5783 #define CSMA_SEED_00 0 5784 #define CSMA_SEED_01 1 5785 #define CSMA_SEED_02 2 5786 #define CSMA_SEED_03 3 5787 #define CSMA_SEED_04 4 5788 #define CSMA_SEED_05 5 5789 #define CSMA_SEED_06 6 5790 #define CSMA_SEED_07 7 5791 5792 /* Transceiver Acknowledgment Frame Control Register 2 */ 5793 #define CSMA_SEED_1 _SFR_MEM8(0x16E) 5794 5795 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5796 5797 struct __reg_CSMA_SEED_1 { 5798 unsigned int csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */ 5799 unsigned int aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */ 5800 unsigned int aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */ 5801 unsigned int aack_set_pd : 1; /* Set Frame Pending Sub-field */ 5802 unsigned int aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */ 5803 }; 5804 5805 #define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1) 5806 5807 #endif /* __ASSEMBLER__ */ 5808 5809 /* CSMA_SEED_1 */ 5810 5811 #define CSMA_SEED_10 0 5812 #define CSMA_SEED_11 1 5813 #define CSMA_SEED_12 2 5814 #define AACK_I_AM_COORD 3 5815 #define AACK_DIS_ACK 4 5816 #define AACK_SET_PD 5 5817 #define AACK_FVN_MODE0 6 5818 #define AACK_FVN_MODE1 7 5819 5820 /* Transceiver CSMA-CA Back-off Exponent Control Register */ 5821 #define CSMA_BE _SFR_MEM8(0x16F) 5822 5823 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5824 5825 struct __reg_CSMA_BE { 5826 unsigned int min_be : 4; /* Minimum Back-off Exponent */ 5827 unsigned int max_be : 4; /* Maximum Back-off Exponent */ 5828 }; 5829 5830 #define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE) 5831 5832 #endif /* __ASSEMBLER__ */ 5833 5834 /* CSMA_BE */ 5835 5836 #define MIN_BE0 0 5837 #define MIN_BE1 1 5838 #define MIN_BE2 2 5839 #define MIN_BE3 3 5840 #define MAX_BE0 4 5841 #define MAX_BE1 5 5842 #define MAX_BE2 6 5843 #define MAX_BE3 7 5844 5845 /* Transceiver Digital Test Control Register */ 5846 #define TST_CTRL_DIGI _SFR_MEM8(0x176) 5847 5848 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5849 5850 struct __reg_TST_CTRL_DIGI { 5851 unsigned int tst_ctrl_dig : 4; /* Digital Test Controller Register */ 5852 unsigned int : 4; 5853 }; 5854 5855 #define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI) 5856 5857 #endif /* __ASSEMBLER__ */ 5858 5859 /* TST_CTRL_DIGI */ 5860 5861 #define TST_CTRL_DIG0 0 5862 #define TST_CTRL_DIG1 1 5863 #define TST_CTRL_DIG2 2 5864 #define TST_CTRL_DIG3 3 5865 5866 /* Transceiver Received Frame Length Register */ 5867 #define TST_RX_LENGTH _SFR_MEM8(0x17B) 5868 5869 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5870 5871 struct __reg_TST_RX_LENGTH { 5872 unsigned int rx_length : 8; /* Received Frame Length */ 5873 }; 5874 5875 #define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH) 5876 5877 #endif /* __ASSEMBLER__ */ 5878 5879 /* TST_RX_LENGTH */ 5880 5881 #define RX_LENGTH0 0 5882 #define RX_LENGTH1 1 5883 #define RX_LENGTH2 2 5884 #define RX_LENGTH3 3 5885 #define RX_LENGTH4 4 5886 #define RX_LENGTH5 5 5887 #define RX_LENGTH6 6 5888 #define RX_LENGTH7 7 5889 5890 /* Transceiver Automatic Gain Control and Test Register */ 5891 #define TST_AGC _SFR_MEM8(0x17C) 5892 5893 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5894 5895 struct __reg_TST_AGC { 5896 unsigned int gc : 2; /* Receiver Gain Control Word */ 5897 unsigned int agc_hold : 1; /* Select AGC Hold Function */ 5898 unsigned int agc_off : 1; /* Disable AGC Regulation */ 5899 unsigned int agc_rst : 1; /* Reset AGC Gain */ 5900 unsigned int agc_hold_sel : 1; /* Enable AGC Hold Function */ 5901 unsigned int : 2; 5902 }; 5903 5904 #define TST_AGC_struct _SFR_MEM8_STRUCT(0x17c, struct __reg_TST_AGC) 5905 5906 #endif /* __ASSEMBLER__ */ 5907 5908 /* TST_AGC */ 5909 5910 #define GC0 0 5911 #define GC1 1 5912 #define AGC_HOLD 2 5913 #define AGC_OFF 3 5914 #define AGC_RST 4 5915 #define AGC_HOLD_SEL 5 5916 5917 /* Transceiver Sigma-Delta Modulator Control and Test Register */ 5918 #define TST_SDM _SFR_MEM8(0x17D) 5919 5920 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5921 5922 struct __reg_TST_SDM { 5923 unsigned int : 4; 5924 unsigned int tx_rx_sel : 1; /* Select Transmit/Receive Control Signal */ 5925 unsigned int tx_rx : 1; /* Switch between Transmit and Receive */ 5926 unsigned int mod : 1; /* Select Modulation Signal Type */ 5927 unsigned int mod_sel : 1; /* Select Modulation Data Source */ 5928 }; 5929 5930 #define TST_SDM_struct _SFR_MEM8_STRUCT(0x17d, struct __reg_TST_SDM) 5931 5932 #endif /* __ASSEMBLER__ */ 5933 5934 /* TST_SDM */ 5935 5936 #define TX_RX_SEL 4 5937 #define TX_RX 5 5938 #define MOD 6 5939 #define MOD_SEL 7 5940 5941 /* Start of frame buffer */ 5942 #define TRXFBST _SFR_MEM8(0x180) 5943 5944 /* TRXFBST */ 5945 5946 #define TRXFBST0 0 5947 #define TRXFBST1 1 5948 #define TRXFBST2 2 5949 #define TRXFBST3 3 5950 #define TRXFBST4 4 5951 #define TRXFBST5 5 5952 #define TRXFBST6 6 5953 #define TRXFBST7 7 5954 5955 /* End of frame buffer */ 5956 #define TRXFBEND _SFR_MEM8(0x1FF) 5957 5958 /* TRXFBEND */ 5959 5960 #define TRXFBEND0 0 5961 #define TRXFBEND1 1 5962 #define TRXFBEND2 2 5963 #define TRXFBEND3 3 5964 #define TRXFBEND4 4 5965 #define TRXFBEND5 5 5966 #define TRXFBEND6 6 5967 #define TRXFBEND7 7 5968 5969 5970 /* Interrupt vectors */ 5971 /* Vector 0 is the reset vector */ 5972 5973 #define _VECTORS_SIZE 308 5974 5975 /* External Interrupt Request 0 */ 5976 #define INT0_vect _VECTOR(1) 5977 #define INT0_vect_num 1 5978 5979 /* External Interrupt Request 1 */ 5980 #define INT1_vect _VECTOR(2) 5981 #define INT1_vect_num 2 5982 5983 /* External Interrupt Request 2 */ 5984 #define INT2_vect _VECTOR(3) 5985 #define INT2_vect_num 3 5986 5987 /* External Interrupt Request 3 */ 5988 #define INT3_vect _VECTOR(4) 5989 #define INT3_vect_num 4 5990 5991 /* External Interrupt Request 4 */ 5992 #define INT4_vect _VECTOR(5) 5993 #define INT4_vect_num 5 5994 5995 /* External Interrupt Request 5 */ 5996 #define INT5_vect _VECTOR(6) 5997 #define INT5_vect_num 6 5998 5999 /* External Interrupt Request 6 */ 6000 #define INT6_vect _VECTOR(7) 6001 #define INT6_vect_num 7 6002 6003 /* External Interrupt Request 7 */ 6004 #define INT7_vect _VECTOR(8) 6005 #define INT7_vect_num 8 6006 6007 /* Pin Change Interrupt Request 0 */ 6008 #define PCINT0_vect _VECTOR(9) 6009 #define PCINT0_vect_num 9 6010 6011 /* Pin Change Interrupt Request 1 */ 6012 #define PCINT1_vect _VECTOR(10) 6013 #define PCINT1_vect_num 10 6014 6015 /* Pin Change Interrupt Request 2 */ 6016 #define PCINT2_vect _VECTOR(11) 6017 #define PCINT2_vect_num 11 6018 6019 /* Watchdog Time-out Interrupt */ 6020 #define WDT_vect _VECTOR(12) 6021 #define WDT_vect_num 12 6022 6023 /* Timer/Counter2 Compare Match A */ 6024 #define TIMER2_COMPA_vect _VECTOR(13) 6025 #define TIMER2_COMPA_vect_num 13 6026 6027 /* Timer/Counter2 Compare Match B */ 6028 #define TIMER2_COMPB_vect _VECTOR(14) 6029 #define TIMER2_COMPB_vect_num 14 6030 6031 /* Timer/Counter2 Overflow */ 6032 #define TIMER2_OVF_vect _VECTOR(15) 6033 #define TIMER2_OVF_vect_num 15 6034 6035 /* Timer/Counter1 Capture Event */ 6036 #define TIMER1_CAPT_vect _VECTOR(16) 6037 #define TIMER1_CAPT_vect_num 16 6038 6039 /* Timer/Counter1 Compare Match A */ 6040 #define TIMER1_COMPA_vect _VECTOR(17) 6041 #define TIMER1_COMPA_vect_num 17 6042 6043 /* Timer/Counter1 Compare Match B */ 6044 #define TIMER1_COMPB_vect _VECTOR(18) 6045 #define TIMER1_COMPB_vect_num 18 6046 6047 /* Timer/Counter1 Compare Match C */ 6048 #define TIMER1_COMPC_vect _VECTOR(19) 6049 #define TIMER1_COMPC_vect_num 19 6050 6051 /* Timer/Counter1 Overflow */ 6052 #define TIMER1_OVF_vect _VECTOR(20) 6053 #define TIMER1_OVF_vect_num 20 6054 6055 /* Timer/Counter0 Compare Match A */ 6056 #define TIMER0_COMPA_vect _VECTOR(21) 6057 #define TIMER0_COMPA_vect_num 21 6058 6059 /* Timer/Counter0 Compare Match B */ 6060 #define TIMER0_COMPB_vect _VECTOR(22) 6061 #define TIMER0_COMPB_vect_num 22 6062 6063 /* Timer/Counter0 Overflow */ 6064 #define TIMER0_OVF_vect _VECTOR(23) 6065 #define TIMER0_OVF_vect_num 23 6066 6067 /* SPI Serial Transfer Complete */ 6068 #define SPI_STC_vect _VECTOR(24) 6069 #define SPI_STC_vect_num 24 6070 6071 /* USART0, Rx Complete */ 6072 #define USART0_RX_vect _VECTOR(25) 6073 #define USART0_RX_vect_num 25 6074 6075 /* USART0 Data register Empty */ 6076 #define USART0_UDRE_vect _VECTOR(26) 6077 #define USART0_UDRE_vect_num 26 6078 6079 /* USART0, Tx Complete */ 6080 #define USART0_TX_vect _VECTOR(27) 6081 #define USART0_TX_vect_num 27 6082 6083 /* Analog Comparator */ 6084 #define ANALOG_COMP_vect _VECTOR(28) 6085 #define ANALOG_COMP_vect_num 28 6086 6087 /* ADC Conversion Complete */ 6088 #define ADC_vect _VECTOR(29) 6089 #define ADC_vect_num 29 6090 6091 /* EEPROM Ready */ 6092 #define EE_READY_vect _VECTOR(30) 6093 #define EE_READY_vect_num 30 6094 6095 /* Timer/Counter3 Capture Event */ 6096 #define TIMER3_CAPT_vect _VECTOR(31) 6097 #define TIMER3_CAPT_vect_num 31 6098 6099 /* Timer/Counter3 Compare Match A */ 6100 #define TIMER3_COMPA_vect _VECTOR(32) 6101 #define TIMER3_COMPA_vect_num 32 6102 6103 /* Timer/Counter3 Compare Match B */ 6104 #define TIMER3_COMPB_vect _VECTOR(33) 6105 #define TIMER3_COMPB_vect_num 33 6106 6107 /* Timer/Counter3 Compare Match C */ 6108 #define TIMER3_COMPC_vect _VECTOR(34) 6109 #define TIMER3_COMPC_vect_num 34 6110 6111 /* Timer/Counter3 Overflow */ 6112 #define TIMER3_OVF_vect _VECTOR(35) 6113 #define TIMER3_OVF_vect_num 35 6114 6115 /* USART1, Rx Complete */ 6116 #define USART1_RX_vect _VECTOR(36) 6117 #define USART1_RX_vect_num 36 6118 6119 /* USART1 Data register Empty */ 6120 #define USART1_UDRE_vect _VECTOR(37) 6121 #define USART1_UDRE_vect_num 37 6122 6123 /* USART1, Tx Complete */ 6124 #define USART1_TX_vect _VECTOR(38) 6125 #define USART1_TX_vect_num 38 6126 6127 /* 2-wire Serial Interface */ 6128 #define TWI_vect _VECTOR(39) 6129 #define TWI_vect_num 39 6130 6131 /* Store Program Memory Read */ 6132 #define SPM_READY_vect _VECTOR(40) 6133 #define SPM_READY_vect_num 40 6134 6135 /* Timer/Counter4 Capture Event */ 6136 #define TIMER4_CAPT_vect _VECTOR(41) 6137 #define TIMER4_CAPT_vect_num 41 6138 6139 /* Timer/Counter4 Compare Match A */ 6140 #define TIMER4_COMPA_vect _VECTOR(42) 6141 #define TIMER4_COMPA_vect_num 42 6142 6143 /* Timer/Counter4 Compare Match B */ 6144 #define TIMER4_COMPB_vect _VECTOR(43) 6145 #define TIMER4_COMPB_vect_num 43 6146 6147 /* Timer/Counter4 Compare Match C */ 6148 #define TIMER4_COMPC_vect _VECTOR(44) 6149 #define TIMER4_COMPC_vect_num 44 6150 6151 /* Timer/Counter4 Overflow */ 6152 #define TIMER4_OVF_vect _VECTOR(45) 6153 #define TIMER4_OVF_vect_num 45 6154 6155 /* Timer/Counter5 Capture Event */ 6156 #define TIMER5_CAPT_vect _VECTOR(46) 6157 #define TIMER5_CAPT_vect_num 46 6158 6159 /* Timer/Counter5 Compare Match A */ 6160 #define TIMER5_COMPA_vect _VECTOR(47) 6161 #define TIMER5_COMPA_vect_num 47 6162 6163 /* Timer/Counter5 Compare Match B */ 6164 #define TIMER5_COMPB_vect _VECTOR(48) 6165 #define TIMER5_COMPB_vect_num 48 6166 6167 /* Timer/Counter5 Compare Match C */ 6168 #define TIMER5_COMPC_vect _VECTOR(49) 6169 #define TIMER5_COMPC_vect_num 49 6170 6171 /* Timer/Counter5 Overflow */ 6172 #define TIMER5_OVF_vect _VECTOR(50) 6173 #define TIMER5_OVF_vect_num 50 6174 6175 /* Reserved, vector numbers above has to be kept unchanged */ 6176 #define RESERVED_51_vect _VECTOR(51) 6177 #define RESERVED_51_vect_num 51 6178 6179 /* Reserved, vector numbers above has to be kept unchanged */ 6180 #define RESERVED_52_vect _VECTOR(52) 6181 #define RESERVED_52_vect_num 52 6182 6183 /* Reserved, vector numbers above has to be kept unchanged */ 6184 #define RESERVED_53_vect _VECTOR(53) 6185 #define RESERVED_53_vect_num 53 6186 6187 /* Reserved, vector numbers above has to be kept unchanged */ 6188 #define RESERVED_54_vect _VECTOR(54) 6189 #define RESERVED_54_vect_num 54 6190 6191 /* Reserved, vector numbers above has to be kept unchanged */ 6192 #define RESERVED_55_vect _VECTOR(55) 6193 #define RESERVED_55_vect_num 55 6194 6195 /* Reserved, vector numbers above has to be kept unchanged */ 6196 #define RESERVED_56_vect _VECTOR(56) 6197 #define RESERVED_56_vect_num 56 6198 6199 /* TRX24 - PLL lock interrupt */ 6200 #define TRX24_PLL_LOCK_vect _VECTOR(57) 6201 #define TRX24_PLL_LOCK_vect_num 57 6202 6203 /* TRX24 - PLL unlock interrupt */ 6204 #define TRX24_PLL_UNLOCK_vect _VECTOR(58) 6205 #define TRX24_PLL_UNLOCK_vect_num 58 6206 6207 /* TRX24 - Receive start interrupt */ 6208 #define TRX24_RX_START_vect _VECTOR(59) 6209 #define TRX24_RX_START_vect_num 59 6210 6211 /* TRX24 - RX_END interrupt */ 6212 #define TRX24_RX_END_vect _VECTOR(60) 6213 #define TRX24_RX_END_vect_num 60 6214 6215 /* TRX24 - CCA/ED done interrupt */ 6216 #define TRX24_CCA_ED_DONE_vect _VECTOR(61) 6217 #define TRX24_CCA_ED_DONE_vect_num 61 6218 6219 /* TRX24 - XAH - AMI */ 6220 #define TRX24_XAH_AMI_vect _VECTOR(62) 6221 #define TRX24_XAH_AMI_vect_num 62 6222 6223 /* TRX24 - TX_END interrupt */ 6224 #define TRX24_TX_END_vect _VECTOR(63) 6225 #define TRX24_TX_END_vect_num 63 6226 6227 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ 6228 #define TRX24_AWAKE_vect _VECTOR(64) 6229 #define TRX24_AWAKE_vect_num 64 6230 6231 /* Symbol counter - compare match 1 interrupt */ 6232 #define SCNT_CMP1_vect _VECTOR(65) 6233 #define SCNT_CMP1_vect_num 65 6234 6235 /* Symbol counter - compare match 2 interrupt */ 6236 #define SCNT_CMP2_vect _VECTOR(66) 6237 #define SCNT_CMP2_vect_num 66 6238 6239 /* Symbol counter - compare match 3 interrupt */ 6240 #define SCNT_CMP3_vect _VECTOR(67) 6241 #define SCNT_CMP3_vect_num 67 6242 6243 /* Symbol counter - overflow interrupt */ 6244 #define SCNT_OVFL_vect _VECTOR(68) 6245 #define SCNT_OVFL_vect_num 68 6246 6247 /* Symbol counter - backoff interrupt */ 6248 #define SCNT_BACKOFF_vect _VECTOR(69) 6249 #define SCNT_BACKOFF_vect_num 69 6250 6251 /* AES engine ready interrupt */ 6252 #define AES_READY_vect _VECTOR(70) 6253 #define AES_READY_vect_num 70 6254 6255 /* Battery monitor indicates supply voltage below threshold */ 6256 #define BAT_LOW_vect _VECTOR(71) 6257 #define BAT_LOW_vect_num 71 6258 6259 /* TRX24 TX start interrupt */ 6260 #define TRX24_TX_START_vect _VECTOR(72) 6261 #define TRX24_TX_START_vect_num 72 6262 6263 /* Address match interrupt of address filter 0 */ 6264 #define TRX24_AMI0_vect _VECTOR(73) 6265 #define TRX24_AMI0_vect_num 73 6266 6267 /* Address match interrupt of address filter 1 */ 6268 #define TRX24_AMI1_vect _VECTOR(74) 6269 #define TRX24_AMI1_vect_num 74 6270 6271 /* Address match interrupt of address filter 2 */ 6272 #define TRX24_AMI2_vect _VECTOR(75) 6273 #define TRX24_AMI2_vect_num 75 6274 6275 /* Address match interrupt of address filter 3 */ 6276 #define TRX24_AMI3_vect _VECTOR(76) 6277 #define TRX24_AMI3_vect_num 76 6278 6279 6280 /* memory parameters */ 6281 6282 #define SPM_PAGESIZE (256) 6283 #define RAMSTART (0x200) 6284 #define RAMSIZE (0x2000) 6285 #define RAMEND (0x21FF) 6286 #define XRAMSTART (0x0000) 6287 #define XRAMSIZE (0x0000) 6288 #define XRAMEND RAMEND 6289 #define E2END (0x7FF) 6290 #define E2PAGESIZE (0x08) 6291 #define FLASHEND (0xffff) 6292 6293 6294 /* Fuses */ 6295 6296 #define FUSE_MEMORY_SIZE 3 6297 6298 /* LFUSE Byte */ 6299 #define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */ 6300 #define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */ 6301 #define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */ 6302 #define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */ 6303 #define FUSE_SUT0 ~_BV(4) /* Select start-up time */ 6304 #define FUSE_SUT1 ~_BV(5) /* Select start-up time */ 6305 #define FUSE_CKOUT ~_BV(6) /* Clock output */ 6306 #define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ 6307 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) 6308 6309 /* HFUSE Byte */ 6310 #define FUSE_BOOTRST ~_BV(0) /* Select Reset Vector */ 6311 #define FUSE_BOOTSZ0 ~_BV(1) /* Select Boot Size */ 6312 #define FUSE_BOOTSZ1 ~_BV(2) /* Select Boot Size */ 6313 #define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ 6314 #define FUSE_WDTON ~_BV(4) /* Watchdog timer always on */ 6315 #define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ 6316 #define FUSE_JTAGEN ~_BV(6) /* Enable JTAG */ 6317 #define FUSE_OCDEN ~_BV(7) /* Enable OCD */ 6318 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) 6319 6320 /* EFUSE Byte */ 6321 #define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */ 6322 #define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */ 6323 #define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector trigger level */ 6324 #define EFUSE_DEFAULT (0xFF) 6325 6326 6327 6328 /* Lock Bits */ 6329 6330 #define __BOOT_LOCK_BITS_0_EXIST 6331 #define __BOOT_LOCK_BITS_1_EXIST 6332 #define __LOCK_BITS_EXIST 6333 6334 6335 /* Signature */ 6336 6337 #define SIGNATURE_0 0x1E 6338 #define SIGNATURE_1 0xA6 6339 #define SIGNATURE_2 0x02 6340 6341 #define SLEEP_MODE_IDLE (0x00<<1) 6342 #define SLEEP_MODE_ADC (0x01<<1) 6343 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 6344 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 6345 #define SLEEP_MODE_STANDBY (0x06<<1) 6346 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 6347 6348 6349 #endif /* _AVR_IOM64RFR2_H_ */ 6350