1 /***************************************************************************** 2 * 3 * Copyright (C) 2014 Atmel Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * * Neither the name of the copyright holders nor the names of 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 ****************************************************************************/ 33 34 35 /* $Id: iox128b3.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iox128b3.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 #ifndef _AVR_ATXMEGA128B3_H_INCLUDED 48 #define _AVR_ATXMEGA128B3_H_INCLUDED 49 50 /* Ungrouped common registers */ 51 #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 52 #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 53 #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 54 #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 55 56 /* Deprecated */ 57 #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 58 #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 59 #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 60 #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 61 62 #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ 63 #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ 64 #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ 65 #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ 66 #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ 67 #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ 68 #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ 69 #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ 70 #define SREG _SFR_MEM8(0x003F) /* Status Register */ 71 72 /* C Language Only */ 73 #if !defined (__ASSEMBLER__) 74 75 #include <stdint.h> 76 77 typedef volatile uint8_t register8_t; 78 typedef volatile uint16_t register16_t; 79 typedef volatile uint32_t register32_t; 80 81 82 #ifdef _WORDREGISTER 83 #undef _WORDREGISTER 84 #endif 85 #define _WORDREGISTER(regname) \ 86 __extension__ union \ 87 { \ 88 register16_t regname; \ 89 struct \ 90 { \ 91 register8_t regname ## L; \ 92 register8_t regname ## H; \ 93 }; \ 94 } 95 96 #ifdef _DWORDREGISTER 97 #undef _DWORDREGISTER 98 #endif 99 #define _DWORDREGISTER(regname) \ 100 __extension__ union \ 101 { \ 102 register32_t regname; \ 103 struct \ 104 { \ 105 register8_t regname ## 0; \ 106 register8_t regname ## 1; \ 107 register8_t regname ## 2; \ 108 register8_t regname ## 3; \ 109 }; \ 110 } 111 112 113 /* 114 ========================================================================== 115 IO Module Structures 116 ========================================================================== 117 */ 118 119 120 /* 121 -------------------------------------------------------------------------- 122 VPORT - Virtual Ports 123 -------------------------------------------------------------------------- 124 */ 125 126 /* Virtual Port */ 127 typedef struct VPORT_struct 128 { 129 register8_t DIR; /* I/O Port Data Direction */ 130 register8_t OUT; /* I/O Port Output */ 131 register8_t IN; /* I/O Port Input */ 132 register8_t INTFLAGS; /* Interrupt Flag Register */ 133 } VPORT_t; 134 135 136 /* 137 -------------------------------------------------------------------------- 138 XOCD - On-Chip Debug System 139 -------------------------------------------------------------------------- 140 */ 141 142 /* On-Chip Debug System */ 143 typedef struct OCD_struct 144 { 145 register8_t OCDR0; /* OCD Register 0 */ 146 register8_t OCDR1; /* OCD Register 1 */ 147 } OCD_t; 148 149 150 /* 151 -------------------------------------------------------------------------- 152 CPU - CPU 153 -------------------------------------------------------------------------- 154 */ 155 156 /* CCP signatures */ 157 typedef enum CCP_enum 158 { 159 CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ 160 CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ 161 } CCP_t; 162 163 164 /* 165 -------------------------------------------------------------------------- 166 CLK - Clock System 167 -------------------------------------------------------------------------- 168 */ 169 170 /* Clock System */ 171 typedef struct CLK_struct 172 { 173 register8_t CTRL; /* Control Register */ 174 register8_t PSCTRL; /* Prescaler Control Register */ 175 register8_t LOCK; /* Lock register */ 176 register8_t RTCCTRL; /* RTC Control Register */ 177 register8_t USBCTRL; /* USB Control Register */ 178 } CLK_t; 179 180 /* System Clock Selection */ 181 typedef enum CLK_SCLKSEL_enum 182 { 183 CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ 184 CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ 185 CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ 186 CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ 187 CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ 188 } CLK_SCLKSEL_t; 189 190 /* Prescaler A Division Factor */ 191 typedef enum CLK_PSADIV_enum 192 { 193 CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ 194 CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ 195 CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ 196 CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ 197 CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ 198 CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ 199 CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ 200 CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ 201 CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ 202 CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ 203 } CLK_PSADIV_t; 204 205 /* Prescaler B and C Division Factor */ 206 typedef enum CLK_PSBCDIV_enum 207 { 208 CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ 209 CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ 210 CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ 211 CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ 212 } CLK_PSBCDIV_t; 213 214 /* RTC Clock Source */ 215 typedef enum CLK_RTCSRC_enum 216 { 217 CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ 218 CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ 219 CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ 220 CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ 221 CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ 222 CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ 223 } CLK_RTCSRC_t; 224 225 /* USB Prescaler Division Factor */ 226 typedef enum CLK_USBPSDIV_enum 227 { 228 CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ 229 CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ 230 CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ 231 CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ 232 CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ 233 CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ 234 } CLK_USBPSDIV_t; 235 236 /* USB Clock Source */ 237 typedef enum CLK_USBSRC_enum 238 { 239 CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ 240 CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ 241 } CLK_USBSRC_t; 242 243 244 /* 245 -------------------------------------------------------------------------- 246 SLEEP - Sleep Controller 247 -------------------------------------------------------------------------- 248 */ 249 250 /* Sleep Controller */ 251 typedef struct SLEEP_struct 252 { 253 register8_t CTRL; /* Control Register */ 254 } SLEEP_t; 255 256 /* Sleep Mode */ 257 typedef enum SLEEP_SMODE_enum 258 { 259 SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ 260 SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ 261 SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ 262 SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ 263 SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ 264 } SLEEP_SMODE_t; 265 266 267 #define SLEEP_MODE_IDLE (0x00<<1) 268 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 269 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 270 #define SLEEP_MODE_STANDBY (0x06<<1) 271 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 272 273 274 /* 275 -------------------------------------------------------------------------- 276 OSC - Oscillator 277 -------------------------------------------------------------------------- 278 */ 279 280 /* Oscillator */ 281 typedef struct OSC_struct 282 { 283 register8_t CTRL; /* Control Register */ 284 register8_t STATUS; /* Status Register */ 285 register8_t XOSCCTRL; /* External Oscillator Control Register */ 286 register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ 287 register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ 288 register8_t PLLCTRL; /* PLL Control Register */ 289 register8_t DFLLCTRL; /* DFLL Control Register */ 290 } OSC_t; 291 292 /* Oscillator Frequency Range */ 293 typedef enum OSC_FRQRANGE_enum 294 { 295 OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ 296 OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ 297 OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ 298 OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ 299 } OSC_FRQRANGE_t; 300 301 /* External Oscillator Selection and Startup Time */ 302 typedef enum OSC_XOSCSEL_enum 303 { 304 OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ 305 OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ 306 OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ 307 OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ 308 OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ 309 OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ 310 OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ 311 OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ 312 OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ 313 OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ 314 OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ 315 OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ 316 OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ 317 } OSC_XOSCSEL_t; 318 319 /* PLL Clock Source */ 320 typedef enum OSC_PLLSRC_enum 321 { 322 OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ 323 OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ 324 OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ 325 } OSC_PLLSRC_t; 326 327 /* 2 MHz DFLL Calibration Reference */ 328 typedef enum OSC_RC2MCREF_enum 329 { 330 OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ 331 OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ 332 } OSC_RC2MCREF_t; 333 334 /* 32 MHz DFLL Calibration Reference */ 335 typedef enum OSC_RC32MCREF_enum 336 { 337 OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ 338 OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ 339 OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ 340 } OSC_RC32MCREF_t; 341 342 343 /* 344 -------------------------------------------------------------------------- 345 DFLL - DFLL 346 -------------------------------------------------------------------------- 347 */ 348 349 /* DFLL */ 350 typedef struct DFLL_struct 351 { 352 register8_t CTRL; /* Control Register */ 353 register8_t reserved_0x01; 354 register8_t CALA; /* Calibration Register A */ 355 register8_t CALB; /* Calibration Register B */ 356 register8_t COMP0; /* Oscillator Compare Register 0 */ 357 register8_t COMP1; /* Oscillator Compare Register 1 */ 358 register8_t COMP2; /* Oscillator Compare Register 2 */ 359 register8_t reserved_0x07; 360 } DFLL_t; 361 362 363 /* 364 -------------------------------------------------------------------------- 365 PR - Power Reduction 366 -------------------------------------------------------------------------- 367 */ 368 369 /* Power Reduction */ 370 typedef struct PR_struct 371 { 372 register8_t PRGEN; /* General Power Reduction */ 373 register8_t PRPA; /* Power Reduction Port A */ 374 register8_t PRPB; /* Power Reduction Port B */ 375 register8_t PRPC; /* Power Reduction Port C */ 376 register8_t reserved_0x04; 377 register8_t PRPE; /* Power Reduction Port E */ 378 } PR_t; 379 380 381 /* 382 -------------------------------------------------------------------------- 383 RST - Reset 384 -------------------------------------------------------------------------- 385 */ 386 387 /* Reset */ 388 typedef struct RST_struct 389 { 390 register8_t STATUS; /* Status Register */ 391 register8_t CTRL; /* Control Register */ 392 } RST_t; 393 394 395 /* 396 -------------------------------------------------------------------------- 397 WDT - Watch-Dog Timer 398 -------------------------------------------------------------------------- 399 */ 400 401 /* Watch-Dog Timer */ 402 typedef struct WDT_struct 403 { 404 register8_t CTRL; /* Control */ 405 register8_t WINCTRL; /* Windowed Mode Control */ 406 register8_t STATUS; /* Status */ 407 } WDT_t; 408 409 /* Period setting */ 410 typedef enum WDT_PER_enum 411 { 412 WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 413 WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 414 WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 415 WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 416 WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ 417 WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ 418 WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ 419 WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 420 WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 421 WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 422 WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 423 } WDT_PER_t; 424 425 /* Closed window period */ 426 typedef enum WDT_WPER_enum 427 { 428 WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 429 WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 430 WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 431 WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 432 WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ 433 WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ 434 WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ 435 WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 436 WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 437 WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 438 WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 439 } WDT_WPER_t; 440 441 442 /* 443 -------------------------------------------------------------------------- 444 MCU - MCU Control 445 -------------------------------------------------------------------------- 446 */ 447 448 /* MCU Control */ 449 typedef struct MCU_struct 450 { 451 register8_t DEVID0; /* Device ID byte 0 */ 452 register8_t DEVID1; /* Device ID byte 1 */ 453 register8_t DEVID2; /* Device ID byte 2 */ 454 register8_t REVID; /* Revision ID */ 455 register8_t JTAGUID; /* JTAG User ID */ 456 register8_t reserved_0x05; 457 register8_t MCUCR; /* MCU Control */ 458 register8_t ANAINIT; /* Analog Startup Delay */ 459 register8_t EVSYSLOCK; /* Event System Lock */ 460 register8_t AWEXLOCK; /* AWEX Lock */ 461 register8_t reserved_0x0A; 462 register8_t reserved_0x0B; 463 } MCU_t; 464 465 466 /* 467 -------------------------------------------------------------------------- 468 PMIC - Programmable Multi-level Interrupt Controller 469 -------------------------------------------------------------------------- 470 */ 471 472 /* Programmable Multi-level Interrupt Controller */ 473 typedef struct PMIC_struct 474 { 475 register8_t STATUS; /* Status Register */ 476 register8_t INTPRI; /* Interrupt Priority */ 477 register8_t CTRL; /* Control Register */ 478 register8_t reserved_0x03; 479 register8_t reserved_0x04; 480 register8_t reserved_0x05; 481 register8_t reserved_0x06; 482 register8_t reserved_0x07; 483 register8_t reserved_0x08; 484 register8_t reserved_0x09; 485 register8_t reserved_0x0A; 486 register8_t reserved_0x0B; 487 register8_t reserved_0x0C; 488 register8_t reserved_0x0D; 489 register8_t reserved_0x0E; 490 register8_t reserved_0x0F; 491 } PMIC_t; 492 493 494 /* 495 -------------------------------------------------------------------------- 496 PORTCFG - Port Configuration 497 -------------------------------------------------------------------------- 498 */ 499 500 /* I/O port Configuration */ 501 typedef struct PORTCFG_struct 502 { 503 register8_t MPCMASK; /* Multi-pin Configuration Mask */ 504 register8_t reserved_0x01; 505 register8_t VPCTRLA; /* Virtual Port Control Register A */ 506 register8_t VPCTRLB; /* Virtual Port Control Register B */ 507 register8_t CLKEVOUT; /* Clock and Event Out Register */ 508 register8_t reserved_0x05; 509 register8_t EVOUTSEL; /* Event Output Select */ 510 } PORTCFG_t; 511 512 /* Virtual Port Mapping */ 513 typedef enum PORTCFG_VP02MAP_enum 514 { 515 PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 516 PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 517 PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 518 PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 519 PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 520 PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 521 PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 522 PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 523 } PORTCFG_VP02MAP_t; 524 525 /* Virtual Port Mapping */ 526 typedef enum PORTCFG_VP13MAP_enum 527 { 528 PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 529 PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 530 PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 531 PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 532 PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 533 PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 534 PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 535 PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 536 } PORTCFG_VP13MAP_t; 537 538 /* System Clock Output Port */ 539 typedef enum PORTCFG_CLKOUT_enum 540 { 541 PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ 542 PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ 543 PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ 544 } PORTCFG_CLKOUT_t; 545 546 /* Peripheral Clock Output Select */ 547 typedef enum PORTCFG_CLKOUTSEL_enum 548 { 549 PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ 550 PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ 551 PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ 552 } PORTCFG_CLKOUTSEL_t; 553 554 /* Event Output Port */ 555 typedef enum PORTCFG_EVOUT_enum 556 { 557 PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ 558 PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ 559 PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ 560 } PORTCFG_EVOUT_t; 561 562 /* Clock and Event Output Port */ 563 typedef enum PORTCFG_CLKEVPIN_enum 564 { 565 PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ 566 PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ 567 } PORTCFG_CLKEVPIN_t; 568 569 /* Event Output Select */ 570 typedef enum PORTCFG_EVOUTSEL_enum 571 { 572 PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ 573 PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ 574 PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ 575 PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ 576 } PORTCFG_EVOUTSEL_t; 577 578 579 /* 580 -------------------------------------------------------------------------- 581 AES - AES Module 582 -------------------------------------------------------------------------- 583 */ 584 585 /* AES Module */ 586 typedef struct AES_struct 587 { 588 register8_t CTRL; /* AES Control Register */ 589 register8_t STATUS; /* AES Status Register */ 590 register8_t STATE; /* AES State Register */ 591 register8_t KEY; /* AES Key Register */ 592 register8_t INTCTRL; /* AES Interrupt Control Register */ 593 } AES_t; 594 595 /* Interrupt level */ 596 typedef enum AES_INTLVL_enum 597 { 598 AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 599 AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 600 AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 601 AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ 602 } AES_INTLVL_t; 603 604 605 /* 606 -------------------------------------------------------------------------- 607 CRC - Cyclic Redundancy Checker 608 -------------------------------------------------------------------------- 609 */ 610 611 /* Cyclic Redundancy Checker */ 612 typedef struct CRC_struct 613 { 614 register8_t CTRL; /* Control Register */ 615 register8_t STATUS; /* Status Register */ 616 register8_t reserved_0x02; 617 register8_t DATAIN; /* Data Input */ 618 register8_t CHECKSUM0; /* Checksum byte 0 */ 619 register8_t CHECKSUM1; /* Checksum byte 1 */ 620 register8_t CHECKSUM2; /* Checksum byte 2 */ 621 register8_t CHECKSUM3; /* Checksum byte 3 */ 622 } CRC_t; 623 624 /* Reset */ 625 typedef enum CRC_RESET_enum 626 { 627 CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ 628 CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ 629 CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ 630 } CRC_RESET_t; 631 632 /* Input Source */ 633 typedef enum CRC_SOURCE_enum 634 { 635 CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ 636 CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ 637 CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ 638 CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ 639 CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ 640 } CRC_SOURCE_t; 641 642 643 /* 644 -------------------------------------------------------------------------- 645 DMA - DMA Controller 646 -------------------------------------------------------------------------- 647 */ 648 649 /* DMA Channel */ 650 typedef struct DMA_CH_struct 651 { 652 register8_t CTRLA; /* Channel Control */ 653 register8_t CTRLB; /* Channel Control */ 654 register8_t ADDRCTRL; /* Address Control */ 655 register8_t TRIGSRC; /* Channel Trigger Source */ 656 _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ 657 register8_t REPCNT; /* Channel Repeat Count */ 658 register8_t reserved_0x07; 659 register8_t SRCADDR0; /* Channel Source Address 0 */ 660 register8_t SRCADDR1; /* Channel Source Address 1 */ 661 register8_t reserved_0x0A; 662 register8_t reserved_0x0B; 663 register8_t DESTADDR0; /* Channel Destination Address 0 */ 664 register8_t DESTADDR1; /* Channel Destination Address 1 */ 665 register8_t reserved_0x0E; 666 register8_t reserved_0x0F; 667 } DMA_CH_t; 668 669 670 /* DMA Controller */ 671 typedef struct DMA_struct 672 { 673 register8_t CTRL; /* Control */ 674 register8_t reserved_0x01; 675 register8_t reserved_0x02; 676 register8_t INTFLAGS; /* Transfer Interrupt Status */ 677 register8_t STATUS; /* Status */ 678 register8_t reserved_0x05; 679 _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ 680 register8_t reserved_0x08; 681 register8_t reserved_0x09; 682 register8_t reserved_0x0A; 683 register8_t reserved_0x0B; 684 register8_t reserved_0x0C; 685 register8_t reserved_0x0D; 686 register8_t reserved_0x0E; 687 register8_t reserved_0x0F; 688 DMA_CH_t CH0; /* DMA Channel 0 */ 689 DMA_CH_t CH1; /* DMA Channel 1 */ 690 } DMA_t; 691 692 /* Burst mode */ 693 typedef enum DMA_CH_BURSTLEN_enum 694 { 695 DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ 696 DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ 697 DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ 698 DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ 699 } DMA_CH_BURSTLEN_t; 700 701 /* Source address reload mode */ 702 typedef enum DMA_CH_SRCRELOAD_enum 703 { 704 DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ 705 DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ 706 DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ 707 DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ 708 } DMA_CH_SRCRELOAD_t; 709 710 /* Source addressing mode */ 711 typedef enum DMA_CH_SRCDIR_enum 712 { 713 DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ 714 DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ 715 DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ 716 } DMA_CH_SRCDIR_t; 717 718 /* Destination adress reload mode */ 719 typedef enum DMA_CH_DESTRELOAD_enum 720 { 721 DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ 722 DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ 723 DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ 724 DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ 725 } DMA_CH_DESTRELOAD_t; 726 727 /* Destination adressing mode */ 728 typedef enum DMA_CH_DESTDIR_enum 729 { 730 DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ 731 DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ 732 DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ 733 } DMA_CH_DESTDIR_t; 734 735 /* Transfer trigger source */ 736 typedef enum DMA_CH_TRIGSRC_enum 737 { 738 DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ 739 DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ 740 DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ 741 DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ 742 DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ 743 DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ 744 DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ 745 DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ 746 DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ 747 DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ 748 DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ 749 DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ 750 DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ 751 DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ 752 DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ 753 DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ 754 DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ 755 DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ 756 DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ 757 DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ 758 DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ 759 DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ 760 DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ 761 DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ 762 DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ 763 DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ 764 DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ 765 } DMA_CH_TRIGSRC_t; 766 767 /* Double buffering mode */ 768 typedef enum DMA_DBUFMODE_enum 769 { 770 DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ 771 DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ 772 } DMA_DBUFMODE_t; 773 774 /* Priority mode */ 775 typedef enum DMA_PRIMODE_enum 776 { 777 DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ 778 DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ 779 } DMA_PRIMODE_t; 780 781 /* Interrupt level */ 782 typedef enum DMA_CH_ERRINTLVL_enum 783 { 784 DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 785 DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ 786 DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ 787 DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ 788 } DMA_CH_ERRINTLVL_t; 789 790 /* Interrupt level */ 791 typedef enum DMA_CH_TRNINTLVL_enum 792 { 793 DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 794 DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ 795 DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ 796 DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ 797 } DMA_CH_TRNINTLVL_t; 798 799 800 /* 801 -------------------------------------------------------------------------- 802 EVSYS - Event System 803 -------------------------------------------------------------------------- 804 */ 805 806 /* Event System */ 807 typedef struct EVSYS_struct 808 { 809 register8_t CH0MUX; /* Event Channel 0 Multiplexer */ 810 register8_t CH1MUX; /* Event Channel 1 Multiplexer */ 811 register8_t CH2MUX; /* Event Channel 2 Multiplexer */ 812 register8_t CH3MUX; /* Event Channel 3 Multiplexer */ 813 register8_t reserved_0x04; 814 register8_t reserved_0x05; 815 register8_t reserved_0x06; 816 register8_t reserved_0x07; 817 register8_t CH0CTRL; /* Channel 0 Control Register */ 818 register8_t CH1CTRL; /* Channel 1 Control Register */ 819 register8_t CH2CTRL; /* Channel 2 Control Register */ 820 register8_t CH3CTRL; /* Channel 3 Control Register */ 821 register8_t reserved_0x0C; 822 register8_t reserved_0x0D; 823 register8_t reserved_0x0E; 824 register8_t reserved_0x0F; 825 register8_t STROBE; /* Event Strobe */ 826 register8_t DATA; /* Event Data */ 827 } EVSYS_t; 828 829 /* Quadrature Decoder Index Recognition Mode */ 830 typedef enum EVSYS_QDIRM_enum 831 { 832 EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ 833 EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ 834 EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ 835 EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ 836 } EVSYS_QDIRM_t; 837 838 /* Digital filter coefficient */ 839 typedef enum EVSYS_DIGFILT_enum 840 { 841 EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ 842 EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ 843 EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ 844 EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ 845 EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ 846 EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ 847 EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ 848 EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ 849 } EVSYS_DIGFILT_t; 850 851 /* Event Channel multiplexer input selection */ 852 typedef enum EVSYS_CHMUX_enum 853 { 854 EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ 855 EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ 856 EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ 857 EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ 858 EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ 859 EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ 860 EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ 861 EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ 862 EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ 863 EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ 864 EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ 865 EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ 866 EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ 867 EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ 868 EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ 869 EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ 870 EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ 871 EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ 872 EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ 873 EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ 874 EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ 875 EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ 876 EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ 877 EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ 878 EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ 879 EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ 880 EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ 881 EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ 882 EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ 883 EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ 884 EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ 885 EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ 886 EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ 887 EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ 888 EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ 889 EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ 890 EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ 891 EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ 892 EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ 893 EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ 894 EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ 895 EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ 896 EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ 897 EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ 898 EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ 899 EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ 900 EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ 901 EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ 902 EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ 903 EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ 904 EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ 905 EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ 906 EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ 907 EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ 908 EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ 909 EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ 910 EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ 911 EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ 912 EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ 913 EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ 914 EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ 915 EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ 916 EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ 917 EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ 918 EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ 919 EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ 920 EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ 921 EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ 922 EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ 923 EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ 924 EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ 925 EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ 926 EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ 927 EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ 928 EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ 929 EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ 930 EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ 931 EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ 932 EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ 933 } EVSYS_CHMUX_t; 934 935 936 /* 937 -------------------------------------------------------------------------- 938 NVM - Non Volatile Memory Controller 939 -------------------------------------------------------------------------- 940 */ 941 942 /* Non-volatile Memory Controller */ 943 typedef struct NVM_struct 944 { 945 register8_t ADDR0; /* Address Register 0 */ 946 register8_t ADDR1; /* Address Register 1 */ 947 register8_t ADDR2; /* Address Register 2 */ 948 register8_t reserved_0x03; 949 register8_t DATA0; /* Data Register 0 */ 950 register8_t DATA1; /* Data Register 1 */ 951 register8_t DATA2; /* Data Register 2 */ 952 register8_t reserved_0x07; 953 register8_t reserved_0x08; 954 register8_t reserved_0x09; 955 register8_t CMD; /* Command */ 956 register8_t CTRLA; /* Control Register A */ 957 register8_t CTRLB; /* Control Register B */ 958 register8_t INTCTRL; /* Interrupt Control */ 959 register8_t reserved_0x0E; 960 register8_t STATUS; /* Status */ 961 register8_t LOCKBITS; /* Lock Bits */ 962 } NVM_t; 963 964 /* NVM Command */ 965 typedef enum NVM_CMD_enum 966 { 967 NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ 968 NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ 969 NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ 970 NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ 971 NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ 972 NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ 973 NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ 974 NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ 975 NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ 976 NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ 977 NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ 978 NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ 979 NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ 980 NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ 981 NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ 982 NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ 983 NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ 984 NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ 985 NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ 986 NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ 987 NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ 988 NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ 989 NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ 990 NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ 991 NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ 992 NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ 993 NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ 994 NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ 995 NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ 996 NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ 997 NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ 998 NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ 999 NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ 1000 NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ 1001 } NVM_CMD_t; 1002 1003 /* SPM ready interrupt level */ 1004 typedef enum NVM_SPMLVL_enum 1005 { 1006 NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 1007 NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ 1008 NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ 1009 NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ 1010 } NVM_SPMLVL_t; 1011 1012 /* EEPROM ready interrupt level */ 1013 typedef enum NVM_EELVL_enum 1014 { 1015 NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1016 NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ 1017 NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ 1018 NVM_EELVL_HI_gc = (0x03<<0), /* High level */ 1019 } NVM_EELVL_t; 1020 1021 /* Boot lock bits - boot setcion */ 1022 typedef enum NVM_BLBB_enum 1023 { 1024 NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 1025 NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 1026 NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 1027 NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 1028 } NVM_BLBB_t; 1029 1030 /* Boot lock bits - application section */ 1031 typedef enum NVM_BLBA_enum 1032 { 1033 NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 1034 NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 1035 NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 1036 NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 1037 } NVM_BLBA_t; 1038 1039 /* Boot lock bits - application table section */ 1040 typedef enum NVM_BLBAT_enum 1041 { 1042 NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 1043 NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 1044 NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 1045 NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 1046 } NVM_BLBAT_t; 1047 1048 /* Lock bits */ 1049 typedef enum NVM_LB_enum 1050 { 1051 NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 1052 NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 1053 NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 1054 } NVM_LB_t; 1055 1056 1057 /* 1058 -------------------------------------------------------------------------- 1059 ADC - Analog/Digital Converter 1060 -------------------------------------------------------------------------- 1061 */ 1062 1063 /* ADC Channel */ 1064 typedef struct ADC_CH_struct 1065 { 1066 register8_t CTRL; /* Control Register */ 1067 register8_t MUXCTRL; /* MUX Control */ 1068 register8_t INTCTRL; /* Channel Interrupt Control Register */ 1069 register8_t INTFLAGS; /* Interrupt Flags */ 1070 _WORDREGISTER(RES); /* Channel Result */ 1071 register8_t SCAN; /* Input Channel Scan */ 1072 register8_t reserved_0x07; 1073 } ADC_CH_t; 1074 1075 1076 /* Analog-to-Digital Converter */ 1077 typedef struct ADC_struct 1078 { 1079 register8_t CTRLA; /* Control Register A */ 1080 register8_t CTRLB; /* Control Register B */ 1081 register8_t REFCTRL; /* Reference Control */ 1082 register8_t EVCTRL; /* Event Control */ 1083 register8_t PRESCALER; /* Clock Prescaler */ 1084 register8_t reserved_0x05; 1085 register8_t INTFLAGS; /* Interrupt Flags */ 1086 register8_t TEMP; /* Temporary Register */ 1087 register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ 1088 register8_t reserved_0x09; 1089 register8_t reserved_0x0A; 1090 register8_t reserved_0x0B; 1091 _WORDREGISTER(CAL); /* Calibration Value */ 1092 register8_t reserved_0x0E; 1093 register8_t reserved_0x0F; 1094 _WORDREGISTER(CH0RES); /* Channel 0 Result */ 1095 register8_t reserved_0x12; 1096 register8_t reserved_0x13; 1097 register8_t reserved_0x14; 1098 register8_t reserved_0x15; 1099 register8_t reserved_0x16; 1100 register8_t reserved_0x17; 1101 _WORDREGISTER(CMP); /* Compare Value */ 1102 register8_t reserved_0x1A; 1103 register8_t reserved_0x1B; 1104 register8_t reserved_0x1C; 1105 register8_t reserved_0x1D; 1106 register8_t reserved_0x1E; 1107 register8_t reserved_0x1F; 1108 ADC_CH_t CH0; /* ADC Channel 0 */ 1109 } ADC_t; 1110 1111 /* Current Limitation */ 1112 typedef enum ADC_CURRLIMIT_enum 1113 { 1114 ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ 1115 ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ 1116 ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ 1117 ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ 1118 } ADC_CURRLIMIT_t; 1119 1120 /* Positive input multiplexer selection */ 1121 typedef enum ADC_CH_MUXPOS_enum 1122 { 1123 ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ 1124 ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ 1125 ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ 1126 ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ 1127 ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ 1128 ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ 1129 ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ 1130 ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ 1131 ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ 1132 ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ 1133 ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ 1134 ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ 1135 ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ 1136 ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ 1137 ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ 1138 ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ 1139 } ADC_CH_MUXPOS_t; 1140 1141 /* Internal input multiplexer selections */ 1142 typedef enum ADC_CH_MUXINT_enum 1143 { 1144 ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ 1145 ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ 1146 ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ 1147 } ADC_CH_MUXINT_t; 1148 1149 /* Negative input multiplexer selection */ 1150 typedef enum ADC_CH_MUXNEG_enum 1151 { 1152 ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ 1153 ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ 1154 ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ 1155 ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ 1156 ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ 1157 ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ 1158 ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ 1159 ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ 1160 } ADC_CH_MUXNEG_t; 1161 1162 /* Input mode */ 1163 typedef enum ADC_CH_INPUTMODE_enum 1164 { 1165 ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ 1166 ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ 1167 ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ 1168 ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ 1169 } ADC_CH_INPUTMODE_t; 1170 1171 /* Gain factor */ 1172 typedef enum ADC_CH_GAIN_enum 1173 { 1174 ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ 1175 ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ 1176 ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ 1177 ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ 1178 ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ 1179 ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ 1180 ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ 1181 ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ 1182 } ADC_CH_GAIN_t; 1183 1184 /* Conversion result resolution */ 1185 typedef enum ADC_RESOLUTION_enum 1186 { 1187 ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ 1188 ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ 1189 ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ 1190 } ADC_RESOLUTION_t; 1191 1192 /* Voltage reference selection */ 1193 typedef enum ADC_REFSEL_enum 1194 { 1195 ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ 1196 ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ 1197 ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ 1198 ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ 1199 ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ 1200 } ADC_REFSEL_t; 1201 1202 /* Event channel input selection */ 1203 typedef enum ADC_EVSEL_enum 1204 { 1205 ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ 1206 ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ 1207 ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ 1208 ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ 1209 } ADC_EVSEL_t; 1210 1211 /* Event action selection */ 1212 typedef enum ADC_EVACT_enum 1213 { 1214 ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ 1215 ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ 1216 ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ 1217 } ADC_EVACT_t; 1218 1219 /* Interupt mode */ 1220 typedef enum ADC_CH_INTMODE_enum 1221 { 1222 ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ 1223 ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ 1224 ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ 1225 } ADC_CH_INTMODE_t; 1226 1227 /* Interrupt level */ 1228 typedef enum ADC_CH_INTLVL_enum 1229 { 1230 ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1231 ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1232 ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1233 ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ 1234 } ADC_CH_INTLVL_t; 1235 1236 /* Clock prescaler */ 1237 typedef enum ADC_PRESCALER_enum 1238 { 1239 ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ 1240 ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ 1241 ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ 1242 ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ 1243 ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ 1244 ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ 1245 ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ 1246 ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ 1247 } ADC_PRESCALER_t; 1248 1249 1250 /* 1251 -------------------------------------------------------------------------- 1252 AC - Analog Comparator 1253 -------------------------------------------------------------------------- 1254 */ 1255 1256 /* Analog Comparator */ 1257 typedef struct AC_struct 1258 { 1259 register8_t AC0CTRL; /* Analog Comparator 0 Control */ 1260 register8_t AC1CTRL; /* Analog Comparator 1 Control */ 1261 register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ 1262 register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ 1263 register8_t CTRLA; /* Control Register A */ 1264 register8_t CTRLB; /* Control Register B */ 1265 register8_t WINCTRL; /* Window Mode Control */ 1266 register8_t STATUS; /* Status */ 1267 register8_t CURRCTRL; /* Current Source Control Register */ 1268 register8_t CURRCALIB; /* Current Source Calibration Register */ 1269 } AC_t; 1270 1271 /* Interrupt mode */ 1272 typedef enum AC_INTMODE_enum 1273 { 1274 AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ 1275 AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ 1276 AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ 1277 } AC_INTMODE_t; 1278 1279 /* Interrupt level */ 1280 typedef enum AC_INTLVL_enum 1281 { 1282 AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ 1283 AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ 1284 AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ 1285 AC_INTLVL_HI_gc = (0x03<<4), /* High level */ 1286 } AC_INTLVL_t; 1287 1288 /* Hysteresis mode selection */ 1289 typedef enum AC_HYSMODE_enum 1290 { 1291 AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ 1292 AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ 1293 AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ 1294 } AC_HYSMODE_t; 1295 1296 /* Positive input multiplexer selection */ 1297 typedef enum AC_MUXPOS_enum 1298 { 1299 AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ 1300 AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ 1301 AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ 1302 AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ 1303 AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ 1304 AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ 1305 AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ 1306 } AC_MUXPOS_t; 1307 1308 /* Negative input multiplexer selection */ 1309 typedef enum AC_MUXNEG_enum 1310 { 1311 AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ 1312 AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ 1313 AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ 1314 AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ 1315 AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ 1316 AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ 1317 AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ 1318 } AC_MUXNEG_t; 1319 1320 /* Windows interrupt mode */ 1321 typedef enum AC_WINTMODE_enum 1322 { 1323 AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ 1324 AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ 1325 AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ 1326 AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ 1327 } AC_WINTMODE_t; 1328 1329 /* Window interrupt level */ 1330 typedef enum AC_WINTLVL_enum 1331 { 1332 AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1333 AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ 1334 AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ 1335 AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ 1336 } AC_WINTLVL_t; 1337 1338 /* Window mode state */ 1339 typedef enum AC_WSTATE_enum 1340 { 1341 AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ 1342 AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ 1343 AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ 1344 } AC_WSTATE_t; 1345 1346 1347 /* 1348 -------------------------------------------------------------------------- 1349 RTC - Real-Time Counter 1350 -------------------------------------------------------------------------- 1351 */ 1352 1353 /* Real-Time Counter */ 1354 typedef struct RTC_struct 1355 { 1356 register8_t CTRL; /* Control Register */ 1357 register8_t STATUS; /* Status Register */ 1358 register8_t INTCTRL; /* Interrupt Control Register */ 1359 register8_t INTFLAGS; /* Interrupt Flags */ 1360 register8_t TEMP; /* Temporary register */ 1361 register8_t reserved_0x05; 1362 register8_t reserved_0x06; 1363 register8_t reserved_0x07; 1364 _WORDREGISTER(CNT); /* Count Register */ 1365 _WORDREGISTER(PER); /* Period Register */ 1366 _WORDREGISTER(COMP); /* Compare Register */ 1367 } RTC_t; 1368 1369 /* Prescaler Factor */ 1370 typedef enum RTC_PRESCALER_enum 1371 { 1372 RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ 1373 RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ 1374 RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ 1375 RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ 1376 RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ 1377 RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ 1378 RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ 1379 RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ 1380 } RTC_PRESCALER_t; 1381 1382 /* Compare Interrupt level */ 1383 typedef enum RTC_COMPINTLVL_enum 1384 { 1385 RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1386 RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1387 RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1388 RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ 1389 } RTC_COMPINTLVL_t; 1390 1391 /* Overflow Interrupt level */ 1392 typedef enum RTC_OVFINTLVL_enum 1393 { 1394 RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1395 RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1396 RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1397 RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1398 } RTC_OVFINTLVL_t; 1399 1400 1401 /* 1402 -------------------------------------------------------------------------- 1403 TWI - Two-Wire Interface 1404 -------------------------------------------------------------------------- 1405 */ 1406 1407 /* */ 1408 typedef struct TWI_MASTER_struct 1409 { 1410 register8_t CTRLA; /* Control Register A */ 1411 register8_t CTRLB; /* Control Register B */ 1412 register8_t CTRLC; /* Control Register C */ 1413 register8_t STATUS; /* Status Register */ 1414 register8_t BAUD; /* Baurd Rate Control Register */ 1415 register8_t ADDR; /* Address Register */ 1416 register8_t DATA; /* Data Register */ 1417 } TWI_MASTER_t; 1418 1419 1420 /* */ 1421 typedef struct TWI_SLAVE_struct 1422 { 1423 register8_t CTRLA; /* Control Register A */ 1424 register8_t CTRLB; /* Control Register B */ 1425 register8_t STATUS; /* Status Register */ 1426 register8_t ADDR; /* Address Register */ 1427 register8_t DATA; /* Data Register */ 1428 register8_t ADDRMASK; /* Address Mask Register */ 1429 } TWI_SLAVE_t; 1430 1431 1432 /* Two-Wire Interface */ 1433 typedef struct TWI_struct 1434 { 1435 register8_t CTRL; /* TWI Common Control Register */ 1436 TWI_MASTER_t MASTER; /* TWI master module */ 1437 TWI_SLAVE_t SLAVE; /* TWI slave module */ 1438 } TWI_t; 1439 1440 /* SDA Hold Time */ 1441 typedef enum TWI_SDAHOLD_enum 1442 { 1443 TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ 1444 TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ 1445 TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ 1446 TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ 1447 } TWI_SDAHOLD_t; 1448 1449 /* Master Interrupt Level */ 1450 typedef enum TWI_MASTER_INTLVL_enum 1451 { 1452 TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1453 TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1454 TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1455 TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1456 } TWI_MASTER_INTLVL_t; 1457 1458 /* Inactive Timeout */ 1459 typedef enum TWI_MASTER_TIMEOUT_enum 1460 { 1461 TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ 1462 TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ 1463 TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ 1464 TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ 1465 } TWI_MASTER_TIMEOUT_t; 1466 1467 /* Master Command */ 1468 typedef enum TWI_MASTER_CMD_enum 1469 { 1470 TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1471 TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ 1472 TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ 1473 TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ 1474 } TWI_MASTER_CMD_t; 1475 1476 /* Master Bus State */ 1477 typedef enum TWI_MASTER_BUSSTATE_enum 1478 { 1479 TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ 1480 TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ 1481 TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ 1482 TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ 1483 } TWI_MASTER_BUSSTATE_t; 1484 1485 /* Slave Interrupt Level */ 1486 typedef enum TWI_SLAVE_INTLVL_enum 1487 { 1488 TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1489 TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1490 TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1491 TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1492 } TWI_SLAVE_INTLVL_t; 1493 1494 /* Slave Command */ 1495 typedef enum TWI_SLAVE_CMD_enum 1496 { 1497 TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1498 TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ 1499 TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ 1500 } TWI_SLAVE_CMD_t; 1501 1502 1503 /* 1504 -------------------------------------------------------------------------- 1505 USB - USB 1506 -------------------------------------------------------------------------- 1507 */ 1508 1509 /* USB Endpoint */ 1510 typedef struct USB_EP_struct 1511 { 1512 register8_t STATUS; /* Endpoint Status */ 1513 register8_t CTRL; /* Endpoint Control */ 1514 _WORDREGISTER(CNT); /* USB Endpoint Counter */ 1515 _WORDREGISTER(DATAPTR); /* Data Pointer */ 1516 _WORDREGISTER(AUXDATA); /* Auxiliary Data */ 1517 } USB_EP_t; 1518 1519 1520 /* Universal Serial Bus */ 1521 typedef struct USB_struct 1522 { 1523 register8_t CTRLA; /* Control Register A */ 1524 register8_t CTRLB; /* Control Register B */ 1525 register8_t STATUS; /* Status Register */ 1526 register8_t ADDR; /* Address Register */ 1527 register8_t FIFOWP; /* FIFO Write Pointer Register */ 1528 register8_t FIFORP; /* FIFO Read Pointer Register */ 1529 _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ 1530 register8_t INTCTRLA; /* Interrupt Control Register A */ 1531 register8_t INTCTRLB; /* Interrupt Control Register B */ 1532 register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ 1533 register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ 1534 register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ 1535 register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ 1536 register8_t reserved_0x0E; 1537 register8_t reserved_0x0F; 1538 register8_t reserved_0x10; 1539 register8_t reserved_0x11; 1540 register8_t reserved_0x12; 1541 register8_t reserved_0x13; 1542 register8_t reserved_0x14; 1543 register8_t reserved_0x15; 1544 register8_t reserved_0x16; 1545 register8_t reserved_0x17; 1546 register8_t reserved_0x18; 1547 register8_t reserved_0x19; 1548 register8_t reserved_0x1A; 1549 register8_t reserved_0x1B; 1550 register8_t reserved_0x1C; 1551 register8_t reserved_0x1D; 1552 register8_t reserved_0x1E; 1553 register8_t reserved_0x1F; 1554 register8_t reserved_0x20; 1555 register8_t reserved_0x21; 1556 register8_t reserved_0x22; 1557 register8_t reserved_0x23; 1558 register8_t reserved_0x24; 1559 register8_t reserved_0x25; 1560 register8_t reserved_0x26; 1561 register8_t reserved_0x27; 1562 register8_t reserved_0x28; 1563 register8_t reserved_0x29; 1564 register8_t reserved_0x2A; 1565 register8_t reserved_0x2B; 1566 register8_t reserved_0x2C; 1567 register8_t reserved_0x2D; 1568 register8_t reserved_0x2E; 1569 register8_t reserved_0x2F; 1570 register8_t reserved_0x30; 1571 register8_t reserved_0x31; 1572 register8_t reserved_0x32; 1573 register8_t reserved_0x33; 1574 register8_t reserved_0x34; 1575 register8_t reserved_0x35; 1576 register8_t reserved_0x36; 1577 register8_t reserved_0x37; 1578 register8_t reserved_0x38; 1579 register8_t reserved_0x39; 1580 register8_t CAL0; /* Calibration Byte 0 */ 1581 register8_t CAL1; /* Calibration Byte 1 */ 1582 } USB_t; 1583 1584 1585 /* USB Endpoint Table */ 1586 typedef struct USB_EP_TABLE_struct 1587 { 1588 USB_EP_t EP0OUT; /* Endpoint 0 */ 1589 USB_EP_t EP0IN; /* Endpoint 0 */ 1590 USB_EP_t EP1OUT; /* Endpoint 1 */ 1591 USB_EP_t EP1IN; /* Endpoint 1 */ 1592 USB_EP_t EP2OUT; /* Endpoint 2 */ 1593 USB_EP_t EP2IN; /* Endpoint 2 */ 1594 USB_EP_t EP3OUT; /* Endpoint 3 */ 1595 USB_EP_t EP3IN; /* Endpoint 3 */ 1596 USB_EP_t EP4OUT; /* Endpoint 4 */ 1597 USB_EP_t EP4IN; /* Endpoint 4 */ 1598 USB_EP_t EP5OUT; /* Endpoint 5 */ 1599 USB_EP_t EP5IN; /* Endpoint 5 */ 1600 USB_EP_t EP6OUT; /* Endpoint 6 */ 1601 USB_EP_t EP6IN; /* Endpoint 6 */ 1602 USB_EP_t EP7OUT; /* Endpoint 7 */ 1603 USB_EP_t EP7IN; /* Endpoint 7 */ 1604 USB_EP_t EP8OUT; /* Endpoint 8 */ 1605 USB_EP_t EP8IN; /* Endpoint 8 */ 1606 USB_EP_t EP9OUT; /* Endpoint 9 */ 1607 USB_EP_t EP9IN; /* Endpoint 9 */ 1608 USB_EP_t EP10OUT; /* Endpoint 10 */ 1609 USB_EP_t EP10IN; /* Endpoint 10 */ 1610 USB_EP_t EP11OUT; /* Endpoint 11 */ 1611 USB_EP_t EP11IN; /* Endpoint 11 */ 1612 USB_EP_t EP12OUT; /* Endpoint 12 */ 1613 USB_EP_t EP12IN; /* Endpoint 12 */ 1614 USB_EP_t EP13OUT; /* Endpoint 13 */ 1615 USB_EP_t EP13IN; /* Endpoint 13 */ 1616 USB_EP_t EP14OUT; /* Endpoint 14 */ 1617 USB_EP_t EP14IN; /* Endpoint 14 */ 1618 USB_EP_t EP15OUT; /* Endpoint 15 */ 1619 USB_EP_t EP15IN; /* Endpoint 15 */ 1620 register8_t reserved_0x100; 1621 register8_t reserved_0x101; 1622 register8_t reserved_0x102; 1623 register8_t reserved_0x103; 1624 register8_t reserved_0x104; 1625 register8_t reserved_0x105; 1626 register8_t reserved_0x106; 1627 register8_t reserved_0x107; 1628 register8_t reserved_0x108; 1629 register8_t reserved_0x109; 1630 register8_t reserved_0x10A; 1631 register8_t reserved_0x10B; 1632 register8_t reserved_0x10C; 1633 register8_t reserved_0x10D; 1634 register8_t reserved_0x10E; 1635 register8_t reserved_0x10F; 1636 register8_t FRAMENUML; /* Frame Number Low Byte */ 1637 register8_t FRAMENUMH; /* Frame Number High Byte */ 1638 } USB_EP_TABLE_t; 1639 1640 /* Interrupt level */ 1641 typedef enum USB_INTLVL_enum 1642 { 1643 USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1644 USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1645 USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1646 USB_INTLVL_HI_gc = (0x03<<0), /* High level */ 1647 } USB_INTLVL_t; 1648 1649 /* USB Endpoint Type */ 1650 typedef enum USB_EP_TYPE_enum 1651 { 1652 USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ 1653 USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ 1654 USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ 1655 USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ 1656 } USB_EP_TYPE_t; 1657 1658 /* USB Endpoint Buffersize */ 1659 typedef enum USB_EP_BUFSIZE_enum 1660 { 1661 USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ 1662 USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ 1663 USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ 1664 USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ 1665 USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ 1666 USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ 1667 USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ 1668 USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ 1669 } USB_EP_BUFSIZE_t; 1670 1671 1672 /* 1673 -------------------------------------------------------------------------- 1674 PORT - I/O Port Configuration 1675 -------------------------------------------------------------------------- 1676 */ 1677 1678 /* I/O Ports */ 1679 typedef struct PORT_struct 1680 { 1681 register8_t DIR; /* I/O Port Data Direction */ 1682 register8_t DIRSET; /* I/O Port Data Direction Set */ 1683 register8_t DIRCLR; /* I/O Port Data Direction Clear */ 1684 register8_t DIRTGL; /* I/O Port Data Direction Toggle */ 1685 register8_t OUT; /* I/O Port Output */ 1686 register8_t OUTSET; /* I/O Port Output Set */ 1687 register8_t OUTCLR; /* I/O Port Output Clear */ 1688 register8_t OUTTGL; /* I/O Port Output Toggle */ 1689 register8_t IN; /* I/O port Input */ 1690 register8_t INTCTRL; /* Interrupt Control Register */ 1691 register8_t INT0MASK; /* Port Interrupt 0 Mask */ 1692 register8_t INT1MASK; /* Port Interrupt 1 Mask */ 1693 register8_t INTFLAGS; /* Interrupt Flag Register */ 1694 register8_t reserved_0x0D; 1695 register8_t REMAP; /* I/O Port Pin Remap Register */ 1696 register8_t reserved_0x0F; 1697 register8_t PIN0CTRL; /* Pin 0 Control Register */ 1698 register8_t PIN1CTRL; /* Pin 1 Control Register */ 1699 register8_t PIN2CTRL; /* Pin 2 Control Register */ 1700 register8_t PIN3CTRL; /* Pin 3 Control Register */ 1701 register8_t PIN4CTRL; /* Pin 4 Control Register */ 1702 register8_t PIN5CTRL; /* Pin 5 Control Register */ 1703 register8_t PIN6CTRL; /* Pin 6 Control Register */ 1704 register8_t PIN7CTRL; /* Pin 7 Control Register */ 1705 } PORT_t; 1706 1707 /* Port Interrupt 0 Level */ 1708 typedef enum PORT_INT0LVL_enum 1709 { 1710 PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1711 PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ 1712 PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ 1713 PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ 1714 } PORT_INT0LVL_t; 1715 1716 /* Port Interrupt 1 Level */ 1717 typedef enum PORT_INT1LVL_enum 1718 { 1719 PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1720 PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ 1721 PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ 1722 PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ 1723 } PORT_INT1LVL_t; 1724 1725 /* Output/Pull Configuration */ 1726 typedef enum PORT_OPC_enum 1727 { 1728 PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ 1729 PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ 1730 PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ 1731 PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ 1732 PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ 1733 PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ 1734 PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ 1735 PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ 1736 } PORT_OPC_t; 1737 1738 /* Input/Sense Configuration */ 1739 typedef enum PORT_ISC_enum 1740 { 1741 PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ 1742 PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ 1743 PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ 1744 PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ 1745 PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ 1746 } PORT_ISC_t; 1747 1748 1749 /* 1750 -------------------------------------------------------------------------- 1751 TC - 16-bit Timer/Counter With PWM 1752 -------------------------------------------------------------------------- 1753 */ 1754 1755 /* 16-bit Timer/Counter 0 */ 1756 typedef struct TC0_struct 1757 { 1758 register8_t CTRLA; /* Control Register A */ 1759 register8_t CTRLB; /* Control Register B */ 1760 register8_t CTRLC; /* Control register C */ 1761 register8_t CTRLD; /* Control Register D */ 1762 register8_t CTRLE; /* Control Register E */ 1763 register8_t reserved_0x05; 1764 register8_t INTCTRLA; /* Interrupt Control Register A */ 1765 register8_t INTCTRLB; /* Interrupt Control Register B */ 1766 register8_t CTRLFCLR; /* Control Register F Clear */ 1767 register8_t CTRLFSET; /* Control Register F Set */ 1768 register8_t CTRLGCLR; /* Control Register G Clear */ 1769 register8_t CTRLGSET; /* Control Register G Set */ 1770 register8_t INTFLAGS; /* Interrupt Flag Register */ 1771 register8_t reserved_0x0D; 1772 register8_t reserved_0x0E; 1773 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1774 register8_t reserved_0x10; 1775 register8_t reserved_0x11; 1776 register8_t reserved_0x12; 1777 register8_t reserved_0x13; 1778 register8_t reserved_0x14; 1779 register8_t reserved_0x15; 1780 register8_t reserved_0x16; 1781 register8_t reserved_0x17; 1782 register8_t reserved_0x18; 1783 register8_t reserved_0x19; 1784 register8_t reserved_0x1A; 1785 register8_t reserved_0x1B; 1786 register8_t reserved_0x1C; 1787 register8_t reserved_0x1D; 1788 register8_t reserved_0x1E; 1789 register8_t reserved_0x1F; 1790 _WORDREGISTER(CNT); /* Count */ 1791 register8_t reserved_0x22; 1792 register8_t reserved_0x23; 1793 register8_t reserved_0x24; 1794 register8_t reserved_0x25; 1795 _WORDREGISTER(PER); /* Period */ 1796 _WORDREGISTER(CCA); /* Compare or Capture A */ 1797 _WORDREGISTER(CCB); /* Compare or Capture B */ 1798 _WORDREGISTER(CCC); /* Compare or Capture C */ 1799 _WORDREGISTER(CCD); /* Compare or Capture D */ 1800 register8_t reserved_0x30; 1801 register8_t reserved_0x31; 1802 register8_t reserved_0x32; 1803 register8_t reserved_0x33; 1804 register8_t reserved_0x34; 1805 register8_t reserved_0x35; 1806 _WORDREGISTER(PERBUF); /* Period Buffer */ 1807 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1808 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1809 _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ 1810 _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ 1811 } TC0_t; 1812 1813 1814 /* 16-bit Timer/Counter 1 */ 1815 typedef struct TC1_struct 1816 { 1817 register8_t CTRLA; /* Control Register A */ 1818 register8_t CTRLB; /* Control Register B */ 1819 register8_t CTRLC; /* Control register C */ 1820 register8_t CTRLD; /* Control Register D */ 1821 register8_t CTRLE; /* Control Register E */ 1822 register8_t reserved_0x05; 1823 register8_t INTCTRLA; /* Interrupt Control Register A */ 1824 register8_t INTCTRLB; /* Interrupt Control Register B */ 1825 register8_t CTRLFCLR; /* Control Register F Clear */ 1826 register8_t CTRLFSET; /* Control Register F Set */ 1827 register8_t CTRLGCLR; /* Control Register G Clear */ 1828 register8_t CTRLGSET; /* Control Register G Set */ 1829 register8_t INTFLAGS; /* Interrupt Flag Register */ 1830 register8_t reserved_0x0D; 1831 register8_t reserved_0x0E; 1832 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1833 register8_t reserved_0x10; 1834 register8_t reserved_0x11; 1835 register8_t reserved_0x12; 1836 register8_t reserved_0x13; 1837 register8_t reserved_0x14; 1838 register8_t reserved_0x15; 1839 register8_t reserved_0x16; 1840 register8_t reserved_0x17; 1841 register8_t reserved_0x18; 1842 register8_t reserved_0x19; 1843 register8_t reserved_0x1A; 1844 register8_t reserved_0x1B; 1845 register8_t reserved_0x1C; 1846 register8_t reserved_0x1D; 1847 register8_t reserved_0x1E; 1848 register8_t reserved_0x1F; 1849 _WORDREGISTER(CNT); /* Count */ 1850 register8_t reserved_0x22; 1851 register8_t reserved_0x23; 1852 register8_t reserved_0x24; 1853 register8_t reserved_0x25; 1854 _WORDREGISTER(PER); /* Period */ 1855 _WORDREGISTER(CCA); /* Compare or Capture A */ 1856 _WORDREGISTER(CCB); /* Compare or Capture B */ 1857 register8_t reserved_0x2C; 1858 register8_t reserved_0x2D; 1859 register8_t reserved_0x2E; 1860 register8_t reserved_0x2F; 1861 register8_t reserved_0x30; 1862 register8_t reserved_0x31; 1863 register8_t reserved_0x32; 1864 register8_t reserved_0x33; 1865 register8_t reserved_0x34; 1866 register8_t reserved_0x35; 1867 _WORDREGISTER(PERBUF); /* Period Buffer */ 1868 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1869 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1870 } TC1_t; 1871 1872 /* Clock Selection */ 1873 typedef enum TC_CLKSEL_enum 1874 { 1875 TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 1876 TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 1877 TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 1878 TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 1879 TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 1880 TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 1881 TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 1882 TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 1883 TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 1884 TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 1885 TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 1886 TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 1887 } TC_CLKSEL_t; 1888 1889 /* Waveform Generation Mode */ 1890 typedef enum TC_WGMODE_enum 1891 { 1892 TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ 1893 TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ 1894 TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ 1895 TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ 1896 TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 1897 TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 1898 TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ 1899 TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ 1900 TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 1901 TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 1902 } TC_WGMODE_t; 1903 1904 /* Byte Mode */ 1905 typedef enum TC_BYTEM_enum 1906 { 1907 TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ 1908 TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ 1909 TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ 1910 } TC_BYTEM_t; 1911 1912 /* Event Action */ 1913 typedef enum TC_EVACT_enum 1914 { 1915 TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ 1916 TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ 1917 TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ 1918 TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ 1919 TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ 1920 TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ 1921 TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ 1922 } TC_EVACT_t; 1923 1924 /* Event Selection */ 1925 typedef enum TC_EVSEL_enum 1926 { 1927 TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 1928 TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ 1929 TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ 1930 TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ 1931 TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ 1932 } TC_EVSEL_t; 1933 1934 /* Error Interrupt Level */ 1935 typedef enum TC_ERRINTLVL_enum 1936 { 1937 TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1938 TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1939 TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1940 TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ 1941 } TC_ERRINTLVL_t; 1942 1943 /* Overflow Interrupt Level */ 1944 typedef enum TC_OVFINTLVL_enum 1945 { 1946 TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1947 TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1948 TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1949 TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1950 } TC_OVFINTLVL_t; 1951 1952 /* Compare or Capture D Interrupt Level */ 1953 typedef enum TC_CCDINTLVL_enum 1954 { 1955 TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1956 TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 1957 TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1958 TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ 1959 } TC_CCDINTLVL_t; 1960 1961 /* Compare or Capture C Interrupt Level */ 1962 typedef enum TC_CCCINTLVL_enum 1963 { 1964 TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 1965 TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 1966 TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 1967 TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ 1968 } TC_CCCINTLVL_t; 1969 1970 /* Compare or Capture B Interrupt Level */ 1971 typedef enum TC_CCBINTLVL_enum 1972 { 1973 TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1974 TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1975 TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1976 TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ 1977 } TC_CCBINTLVL_t; 1978 1979 /* Compare or Capture A Interrupt Level */ 1980 typedef enum TC_CCAINTLVL_enum 1981 { 1982 TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1983 TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1984 TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1985 TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ 1986 } TC_CCAINTLVL_t; 1987 1988 /* Timer/Counter Command */ 1989 typedef enum TC_CMD_enum 1990 { 1991 TC_CMD_NONE_gc = (0x00<<2), /* No Command */ 1992 TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ 1993 TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 1994 TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 1995 } TC_CMD_t; 1996 1997 1998 /* 1999 -------------------------------------------------------------------------- 2000 AWEX - Timer/Counter Advanced Waveform Extension 2001 -------------------------------------------------------------------------- 2002 */ 2003 2004 /* Advanced Waveform Extension */ 2005 typedef struct AWEX_struct 2006 { 2007 register8_t CTRL; /* Control Register */ 2008 register8_t reserved_0x01; 2009 register8_t FDEMASK; /* Fault Detection Event Mask */ 2010 register8_t FDCTRL; /* Fault Detection Control Register */ 2011 register8_t STATUS; /* Status Register */ 2012 register8_t STATUSSET; /* Status Set Register */ 2013 register8_t DTBOTH; /* Dead Time Both Sides */ 2014 register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ 2015 register8_t DTLS; /* Dead Time Low Side */ 2016 register8_t DTHS; /* Dead Time High Side */ 2017 register8_t DTLSBUF; /* Dead Time Low Side Buffer */ 2018 register8_t DTHSBUF; /* Dead Time High Side Buffer */ 2019 register8_t OUTOVEN; /* Output Override Enable */ 2020 } AWEX_t; 2021 2022 /* Fault Detect Action */ 2023 typedef enum AWEX_FDACT_enum 2024 { 2025 AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ 2026 AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ 2027 AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ 2028 } AWEX_FDACT_t; 2029 2030 2031 /* 2032 -------------------------------------------------------------------------- 2033 HIRES - Timer/Counter High-Resolution Extension 2034 -------------------------------------------------------------------------- 2035 */ 2036 2037 /* High-Resolution Extension */ 2038 typedef struct HIRES_struct 2039 { 2040 register8_t CTRLA; /* Control Register */ 2041 } HIRES_t; 2042 2043 /* High Resolution Enable */ 2044 typedef enum HIRES_HREN_enum 2045 { 2046 HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ 2047 HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ 2048 HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ 2049 HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ 2050 } HIRES_HREN_t; 2051 2052 2053 /* 2054 -------------------------------------------------------------------------- 2055 USART - Universal Asynchronous Receiver-Transmitter 2056 -------------------------------------------------------------------------- 2057 */ 2058 2059 /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2060 typedef struct USART_struct 2061 { 2062 register8_t DATA; /* Data Register */ 2063 register8_t STATUS; /* Status Register */ 2064 register8_t reserved_0x02; 2065 register8_t CTRLA; /* Control Register A */ 2066 register8_t CTRLB; /* Control Register B */ 2067 register8_t CTRLC; /* Control Register C */ 2068 register8_t BAUDCTRLA; /* Baud Rate Control Register A */ 2069 register8_t BAUDCTRLB; /* Baud Rate Control Register B */ 2070 } USART_t; 2071 2072 /* Receive Complete Interrupt level */ 2073 typedef enum USART_RXCINTLVL_enum 2074 { 2075 USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2076 USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2077 USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2078 USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2079 } USART_RXCINTLVL_t; 2080 2081 /* Transmit Complete Interrupt level */ 2082 typedef enum USART_TXCINTLVL_enum 2083 { 2084 USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2085 USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2086 USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2087 USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ 2088 } USART_TXCINTLVL_t; 2089 2090 /* Data Register Empty Interrupt level */ 2091 typedef enum USART_DREINTLVL_enum 2092 { 2093 USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2094 USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2095 USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2096 USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ 2097 } USART_DREINTLVL_t; 2098 2099 /* Character Size */ 2100 typedef enum USART_CHSIZE_enum 2101 { 2102 USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ 2103 USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ 2104 USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ 2105 USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ 2106 USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ 2107 } USART_CHSIZE_t; 2108 2109 /* Communication Mode */ 2110 typedef enum USART_CMODE_enum 2111 { 2112 USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ 2113 USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ 2114 USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ 2115 USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ 2116 } USART_CMODE_t; 2117 2118 /* Parity Mode */ 2119 typedef enum USART_PMODE_enum 2120 { 2121 USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ 2122 USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ 2123 USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ 2124 } USART_PMODE_t; 2125 2126 2127 /* 2128 -------------------------------------------------------------------------- 2129 SPI - Serial Peripheral Interface 2130 -------------------------------------------------------------------------- 2131 */ 2132 2133 /* Serial Peripheral Interface */ 2134 typedef struct SPI_struct 2135 { 2136 register8_t CTRL; /* Control Register */ 2137 register8_t INTCTRL; /* Interrupt Control Register */ 2138 register8_t STATUS; /* Status Register */ 2139 register8_t DATA; /* Data Register */ 2140 } SPI_t; 2141 2142 /* SPI Mode */ 2143 typedef enum SPI_MODE_enum 2144 { 2145 SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ 2146 SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ 2147 SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ 2148 SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ 2149 } SPI_MODE_t; 2150 2151 /* Prescaler setting */ 2152 typedef enum SPI_PRESCALER_enum 2153 { 2154 SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ 2155 SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ 2156 SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ 2157 SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ 2158 } SPI_PRESCALER_t; 2159 2160 /* Interrupt level */ 2161 typedef enum SPI_INTLVL_enum 2162 { 2163 SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2164 SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 2165 SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2166 SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ 2167 } SPI_INTLVL_t; 2168 2169 2170 /* 2171 -------------------------------------------------------------------------- 2172 IRCOM - IR Communication Module 2173 -------------------------------------------------------------------------- 2174 */ 2175 2176 /* IR Communication Module */ 2177 typedef struct IRCOM_struct 2178 { 2179 register8_t CTRL; /* Control Register */ 2180 register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ 2181 register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ 2182 } IRCOM_t; 2183 2184 /* Event channel selection */ 2185 typedef enum IRDA_EVSEL_enum 2186 { 2187 IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 2188 IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ 2189 IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ 2190 IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ 2191 IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ 2192 } IRDA_EVSEL_t; 2193 2194 2195 /* 2196 -------------------------------------------------------------------------- 2197 LCD - LCD Controller 2198 -------------------------------------------------------------------------- 2199 */ 2200 2201 /* LCD Controller */ 2202 typedef struct LCD_struct 2203 { 2204 register8_t CTRLA; /* Control Register A */ 2205 register8_t CTRLB; /* Control Register B */ 2206 register8_t CTRLC; /* Control Register C */ 2207 register8_t INTCTRL; /* Interrupt Enable Register */ 2208 register8_t INTFLAG; /* Interrupt Flag Register */ 2209 register8_t CTRLD; /* Control Register D */ 2210 register8_t CTRLE; /* Control Register E */ 2211 register8_t CTRLF; /* Control Register F */ 2212 register8_t CTRLG; /* Control Register G */ 2213 register8_t CTRLH; /* Control Register H */ 2214 register8_t reserved_0x0A; 2215 register8_t reserved_0x0B; 2216 register8_t reserved_0x0C; 2217 register8_t reserved_0x0D; 2218 register8_t reserved_0x0E; 2219 register8_t reserved_0x0F; 2220 register8_t DATA0; /* LCD Data Register 0 */ 2221 register8_t DATA1; /* LCD Data Register 1 */ 2222 register8_t DATA2; /* LCD Data Register 2 */ 2223 register8_t DATA3; /* LCD Data Register 3 */ 2224 register8_t DATA4; /* LCD Data Register 4 */ 2225 register8_t DATA5; /* LCD Data Register 5 */ 2226 register8_t DATA6; /* LCD Data Register 6 */ 2227 register8_t DATA7; /* LCD Data Register 7 */ 2228 register8_t DATA8; /* LCD Data Register 8 */ 2229 register8_t DATA9; /* LCD Data Register 9 */ 2230 register8_t DATA10; /* LCD Data Register 10 */ 2231 register8_t DATA11; /* LCD Data Register 11 */ 2232 register8_t DATA12; /* LCD Data Register 12 */ 2233 register8_t DATA13; /* LCD Data Register 13 */ 2234 register8_t DATA14; /* LCD Data Register 14 */ 2235 register8_t DATA15; /* LCD Data Register 15 */ 2236 register8_t DATA16; /* LCD Data Register 16 */ 2237 register8_t DATA17; /* LCD Data Register 17 */ 2238 register8_t DATA18; /* LCD Data Register 18 */ 2239 register8_t DATA19; /* LCD Data Register 19 */ 2240 } LCD_t; 2241 2242 /* LCD Blink Rate */ 2243 typedef enum LCD_BLINKRATE_enum 2244 { 2245 LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ 2246 LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ 2247 LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ 2248 LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ 2249 } LCD_BLINKRATE_t; 2250 2251 /* LCD Clock Divide */ 2252 typedef enum LCD_CLKDIV_enum 2253 { 2254 LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ 2255 LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ 2256 LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ 2257 LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ 2258 LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ 2259 LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ 2260 LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ 2261 LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ 2262 } LCD_CLKDIV_t; 2263 2264 /* Duty Select */ 2265 typedef enum LCD_DUTY_enum 2266 { 2267 LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ 2268 LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ 2269 LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ 2270 LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ 2271 } LCD_DUTY_t; 2272 2273 /* LCD Prescaler Select */ 2274 typedef enum LCD_PRESC_enum 2275 { 2276 LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ 2277 LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ 2278 } LCD_PRESC_t; 2279 2280 /* Type of Digit */ 2281 typedef enum LCD_TDG_enum 2282 { 2283 LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ 2284 LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ 2285 LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ 2286 LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ 2287 } LCD_TDG_t; 2288 2289 2290 /* 2291 -------------------------------------------------------------------------- 2292 FUSE - Fuses and Lockbits 2293 -------------------------------------------------------------------------- 2294 */ 2295 2296 /* Fuses */ 2297 typedef struct NVM_FUSES_struct 2298 { 2299 register8_t FUSEBYTE0; /* JTAG User ID */ 2300 register8_t FUSEBYTE1; /* Watchdog Configuration */ 2301 register8_t FUSEBYTE2; /* Reset Configuration */ 2302 register8_t reserved_0x03; 2303 register8_t FUSEBYTE4; /* Start-up Configuration */ 2304 register8_t FUSEBYTE5; /* EESAVE and BOD Level */ 2305 } NVM_FUSES_t; 2306 2307 /* Boot Loader Section Reset Vector */ 2308 typedef enum BOOTRST_enum 2309 { 2310 BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ 2311 BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ 2312 } BOOTRST_t; 2313 2314 /* Timer Oscillator pin location */ 2315 typedef enum TOSCSEL_enum 2316 { 2317 TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ 2318 TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ 2319 } TOSCSEL_t; 2320 2321 /* BOD operation */ 2322 typedef enum BOD_enum 2323 { 2324 BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ 2325 BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ 2326 BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ 2327 } BOD_t; 2328 2329 /* BOD operation */ 2330 typedef enum BODACT_enum 2331 { 2332 BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ 2333 BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ 2334 BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ 2335 } BODACT_t; 2336 2337 /* Watchdog (Window) Timeout Period */ 2338 typedef enum WD_enum 2339 { 2340 WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ 2341 WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ 2342 WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ 2343 WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ 2344 WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ 2345 WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ 2346 WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ 2347 WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ 2348 WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ 2349 WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ 2350 WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ 2351 } WD_t; 2352 2353 /* Watchdog (Window) Timeout Period */ 2354 typedef enum WDP_enum 2355 { 2356 WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ 2357 WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ 2358 WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ 2359 WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ 2360 WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ 2361 WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ 2362 WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ 2363 WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ 2364 WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ 2365 WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ 2366 WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ 2367 } WDP_t; 2368 2369 /* Start-up Time */ 2370 typedef enum SUT_enum 2371 { 2372 SUT_0MS_gc = (0x03<<2), /* 0 ms */ 2373 SUT_4MS_gc = (0x01<<2), /* 4 ms */ 2374 SUT_64MS_gc = (0x00<<2), /* 64 ms */ 2375 } SUT_t; 2376 2377 /* Brown Out Detection Voltage Level */ 2378 typedef enum BODLVL_enum 2379 { 2380 BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ 2381 BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ 2382 BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ 2383 BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ 2384 BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ 2385 BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ 2386 BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ 2387 BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ 2388 } BODLVL_t; 2389 2390 2391 /* 2392 -------------------------------------------------------------------------- 2393 LOCKBIT - Fuses and Lockbits 2394 -------------------------------------------------------------------------- 2395 */ 2396 2397 /* Lock Bits */ 2398 typedef struct NVM_LOCKBITS_struct 2399 { 2400 register8_t LOCKBITS; /* Lock Bits */ 2401 } NVM_LOCKBITS_t; 2402 2403 /* Boot lock bits - boot setcion */ 2404 typedef enum FUSE_BLBB_enum 2405 { 2406 FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 2407 FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 2408 FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 2409 FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 2410 } FUSE_BLBB_t; 2411 2412 /* Boot lock bits - application section */ 2413 typedef enum FUSE_BLBA_enum 2414 { 2415 FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 2416 FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 2417 FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 2418 FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 2419 } FUSE_BLBA_t; 2420 2421 /* Boot lock bits - application table section */ 2422 typedef enum FUSE_BLBAT_enum 2423 { 2424 FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 2425 FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 2426 FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 2427 FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 2428 } FUSE_BLBAT_t; 2429 2430 /* Lock bits */ 2431 typedef enum FUSE_LB_enum 2432 { 2433 FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 2434 FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 2435 FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 2436 } FUSE_LB_t; 2437 2438 2439 /* 2440 -------------------------------------------------------------------------- 2441 SIGROW - Signature Row 2442 -------------------------------------------------------------------------- 2443 */ 2444 2445 /* Production Signatures */ 2446 typedef struct NVM_PROD_SIGNATURES_struct 2447 { 2448 register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ 2449 register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ 2450 register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ 2451 register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ 2452 register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ 2453 register8_t reserved_0x05; 2454 register8_t reserved_0x06; 2455 register8_t reserved_0x07; 2456 register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ 2457 register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ 2458 register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ 2459 register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ 2460 register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ 2461 register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ 2462 register8_t reserved_0x0E; 2463 register8_t reserved_0x0F; 2464 register8_t WAFNUM; /* Wafer Number */ 2465 register8_t reserved_0x11; 2466 register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ 2467 register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ 2468 register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ 2469 register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ 2470 register8_t reserved_0x16; 2471 register8_t reserved_0x17; 2472 register8_t reserved_0x18; 2473 register8_t reserved_0x19; 2474 register8_t USBCAL0; /* USB Calibration Byte 0 */ 2475 register8_t USBCAL1; /* USB Calibration Byte 1 */ 2476 register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ 2477 register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ 2478 register8_t reserved_0x1E; 2479 register8_t reserved_0x1F; 2480 register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ 2481 register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ 2482 register8_t reserved_0x22; 2483 register8_t reserved_0x23; 2484 register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ 2485 register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ 2486 register8_t reserved_0x26; 2487 register8_t reserved_0x27; 2488 register8_t reserved_0x28; 2489 register8_t reserved_0x29; 2490 register8_t reserved_0x2A; 2491 register8_t reserved_0x2B; 2492 register8_t reserved_0x2C; 2493 register8_t reserved_0x2D; 2494 register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ 2495 register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ 2496 register8_t reserved_0x30; 2497 register8_t reserved_0x31; 2498 register8_t reserved_0x32; 2499 register8_t reserved_0x33; 2500 register8_t reserved_0x34; 2501 register8_t reserved_0x35; 2502 register8_t reserved_0x36; 2503 register8_t reserved_0x37; 2504 register8_t reserved_0x38; 2505 register8_t reserved_0x39; 2506 register8_t reserved_0x3A; 2507 register8_t reserved_0x3B; 2508 register8_t reserved_0x3C; 2509 register8_t reserved_0x3D; 2510 register8_t reserved_0x3E; 2511 register8_t reserved_0x3F; 2512 register8_t reserved_0x40; 2513 register8_t reserved_0x41; 2514 register8_t reserved_0x42; 2515 register8_t reserved_0x43; 2516 register8_t reserved_0x44; 2517 register8_t reserved_0x45; 2518 register8_t reserved_0x46; 2519 register8_t reserved_0x47; 2520 } NVM_PROD_SIGNATURES_t; 2521 2522 /* 2523 ========================================================================== 2524 IO Module Instances. Mapped to memory. 2525 ========================================================================== 2526 */ 2527 2528 #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ 2529 #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ 2530 #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ 2531 #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ 2532 #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ 2533 #define CLK (*(CLK_t *) 0x0040) /* Clock System */ 2534 #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ 2535 #define OSC (*(OSC_t *) 0x0050) /* Oscillator */ 2536 #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ 2537 #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ 2538 #define PR (*(PR_t *) 0x0070) /* Power Reduction */ 2539 #define RST (*(RST_t *) 0x0078) /* Reset */ 2540 #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ 2541 #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ 2542 #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ 2543 #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ 2544 #define AES (*(AES_t *) 0x00C0) /* AES Module */ 2545 #define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ 2546 #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ 2547 #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ 2548 #define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ 2549 #define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ 2550 #define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ 2551 #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ 2552 #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ 2553 #define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ 2554 #define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ 2555 #define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ 2556 #define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ 2557 #define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ 2558 #define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ 2559 #define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ 2560 #define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ 2561 #define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ 2562 #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ 2563 #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ 2564 #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2565 #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ 2566 #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ 2567 #define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ 2568 2569 2570 #endif /* !defined (__ASSEMBLER__) */ 2571 2572 2573 /* ========== Flattened fully qualified IO register names ========== */ 2574 2575 /* GPIO - General Purpose IO Registers */ 2576 #define GPIO_GPIOR0 _SFR_MEM8(0x0000) 2577 #define GPIO_GPIOR1 _SFR_MEM8(0x0001) 2578 #define GPIO_GPIOR2 _SFR_MEM8(0x0002) 2579 #define GPIO_GPIOR3 _SFR_MEM8(0x0003) 2580 2581 /* Deprecated */ 2582 #define GPIO_GPIO0 _SFR_MEM8(0x0000) 2583 #define GPIO_GPIO1 _SFR_MEM8(0x0001) 2584 #define GPIO_GPIO2 _SFR_MEM8(0x0002) 2585 #define GPIO_GPIO3 _SFR_MEM8(0x0003) 2586 2587 /* NVM_FUSES - Fuses */ 2588 #define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) 2589 #define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) 2590 #define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) 2591 #define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) 2592 #define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) 2593 2594 /* NVM_LOCKBITS - Lock Bits */ 2595 #define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) 2596 2597 /* NVM_PROD_SIGNATURES - Production Signatures */ 2598 #define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) 2599 #define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) 2600 #define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) 2601 #define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) 2602 #define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) 2603 #define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) 2604 #define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) 2605 #define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) 2606 #define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) 2607 #define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) 2608 #define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) 2609 #define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) 2610 #define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) 2611 #define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) 2612 #define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) 2613 #define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) 2614 #define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) 2615 #define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) 2616 #define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) 2617 #define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) 2618 #define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) 2619 #define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) 2620 #define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) 2621 #define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) 2622 #define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) 2623 #define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) 2624 2625 /* VPORT - Virtual Port */ 2626 #define VPORT0_DIR _SFR_MEM8(0x0010) 2627 #define VPORT0_OUT _SFR_MEM8(0x0011) 2628 #define VPORT0_IN _SFR_MEM8(0x0012) 2629 #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) 2630 2631 /* VPORT - Virtual Port */ 2632 #define VPORT1_DIR _SFR_MEM8(0x0014) 2633 #define VPORT1_OUT _SFR_MEM8(0x0015) 2634 #define VPORT1_IN _SFR_MEM8(0x0016) 2635 #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) 2636 2637 /* VPORT - Virtual Port */ 2638 #define VPORT2_DIR _SFR_MEM8(0x0018) 2639 #define VPORT2_OUT _SFR_MEM8(0x0019) 2640 #define VPORT2_IN _SFR_MEM8(0x001A) 2641 #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) 2642 2643 /* VPORT - Virtual Port */ 2644 #define VPORT3_DIR _SFR_MEM8(0x001C) 2645 #define VPORT3_OUT _SFR_MEM8(0x001D) 2646 #define VPORT3_IN _SFR_MEM8(0x001E) 2647 #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) 2648 2649 /* OCD - On-Chip Debug System */ 2650 #define OCD_OCDR0 _SFR_MEM8(0x002E) 2651 #define OCD_OCDR1 _SFR_MEM8(0x002F) 2652 2653 /* CPU - CPU registers */ 2654 #define CPU_CCP _SFR_MEM8(0x0034) 2655 #define CPU_RAMPD _SFR_MEM8(0x0038) 2656 #define CPU_RAMPX _SFR_MEM8(0x0039) 2657 #define CPU_RAMPY _SFR_MEM8(0x003A) 2658 #define CPU_RAMPZ _SFR_MEM8(0x003B) 2659 #define CPU_EIND _SFR_MEM8(0x003C) 2660 #define CPU_SPL _SFR_MEM8(0x003D) 2661 #define CPU_SPH _SFR_MEM8(0x003E) 2662 #define CPU_SREG _SFR_MEM8(0x003F) 2663 2664 /* CLK - Clock System */ 2665 #define CLK_CTRL _SFR_MEM8(0x0040) 2666 #define CLK_PSCTRL _SFR_MEM8(0x0041) 2667 #define CLK_LOCK _SFR_MEM8(0x0042) 2668 #define CLK_RTCCTRL _SFR_MEM8(0x0043) 2669 #define CLK_USBCTRL _SFR_MEM8(0x0044) 2670 2671 /* SLEEP - Sleep Controller */ 2672 #define SLEEP_CTRL _SFR_MEM8(0x0048) 2673 2674 /* OSC - Oscillator */ 2675 #define OSC_CTRL _SFR_MEM8(0x0050) 2676 #define OSC_STATUS _SFR_MEM8(0x0051) 2677 #define OSC_XOSCCTRL _SFR_MEM8(0x0052) 2678 #define OSC_XOSCFAIL _SFR_MEM8(0x0053) 2679 #define OSC_RC32KCAL _SFR_MEM8(0x0054) 2680 #define OSC_PLLCTRL _SFR_MEM8(0x0055) 2681 #define OSC_DFLLCTRL _SFR_MEM8(0x0056) 2682 2683 /* DFLL - DFLL */ 2684 #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) 2685 #define DFLLRC32M_CALA _SFR_MEM8(0x0062) 2686 #define DFLLRC32M_CALB _SFR_MEM8(0x0063) 2687 #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) 2688 #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) 2689 #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) 2690 2691 /* DFLL - DFLL */ 2692 #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) 2693 #define DFLLRC2M_CALA _SFR_MEM8(0x006A) 2694 #define DFLLRC2M_CALB _SFR_MEM8(0x006B) 2695 #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) 2696 #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) 2697 #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) 2698 2699 /* PR - Power Reduction */ 2700 #define PR_PRGEN _SFR_MEM8(0x0070) 2701 #define PR_PRPA _SFR_MEM8(0x0071) 2702 #define PR_PRPB _SFR_MEM8(0x0072) 2703 #define PR_PRPC _SFR_MEM8(0x0073) 2704 #define PR_PRPE _SFR_MEM8(0x0075) 2705 2706 /* RST - Reset */ 2707 #define RST_STATUS _SFR_MEM8(0x0078) 2708 #define RST_CTRL _SFR_MEM8(0x0079) 2709 2710 /* WDT - Watch-Dog Timer */ 2711 #define WDT_CTRL _SFR_MEM8(0x0080) 2712 #define WDT_WINCTRL _SFR_MEM8(0x0081) 2713 #define WDT_STATUS _SFR_MEM8(0x0082) 2714 2715 /* MCU - MCU Control */ 2716 #define MCU_DEVID0 _SFR_MEM8(0x0090) 2717 #define MCU_DEVID1 _SFR_MEM8(0x0091) 2718 #define MCU_DEVID2 _SFR_MEM8(0x0092) 2719 #define MCU_REVID _SFR_MEM8(0x0093) 2720 #define MCU_JTAGUID _SFR_MEM8(0x0094) 2721 #define MCU_MCUCR _SFR_MEM8(0x0096) 2722 #define MCU_ANAINIT _SFR_MEM8(0x0097) 2723 #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) 2724 #define MCU_AWEXLOCK _SFR_MEM8(0x0099) 2725 2726 /* PMIC - Programmable Multi-level Interrupt Controller */ 2727 #define PMIC_STATUS _SFR_MEM8(0x00A0) 2728 #define PMIC_INTPRI _SFR_MEM8(0x00A1) 2729 #define PMIC_CTRL _SFR_MEM8(0x00A2) 2730 2731 /* PORTCFG - I/O port Configuration */ 2732 #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) 2733 #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) 2734 #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) 2735 #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) 2736 #define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) 2737 2738 /* AES - AES Module */ 2739 #define AES_CTRL _SFR_MEM8(0x00C0) 2740 #define AES_STATUS _SFR_MEM8(0x00C1) 2741 #define AES_STATE _SFR_MEM8(0x00C2) 2742 #define AES_KEY _SFR_MEM8(0x00C3) 2743 #define AES_INTCTRL _SFR_MEM8(0x00C4) 2744 2745 /* CRC - Cyclic Redundancy Checker */ 2746 #define CRC_CTRL _SFR_MEM8(0x00D0) 2747 #define CRC_STATUS _SFR_MEM8(0x00D1) 2748 #define CRC_DATAIN _SFR_MEM8(0x00D3) 2749 #define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) 2750 #define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) 2751 #define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) 2752 #define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) 2753 2754 /* DMA - DMA Controller */ 2755 #define DMA_CTRL _SFR_MEM8(0x0100) 2756 #define DMA_INTFLAGS _SFR_MEM8(0x0103) 2757 #define DMA_STATUS _SFR_MEM8(0x0104) 2758 #define DMA_TEMP _SFR_MEM16(0x0106) 2759 #define DMA_CH0_CTRLA _SFR_MEM8(0x0110) 2760 #define DMA_CH0_CTRLB _SFR_MEM8(0x0111) 2761 #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) 2762 #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) 2763 #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) 2764 #define DMA_CH0_REPCNT _SFR_MEM8(0x0116) 2765 #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) 2766 #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) 2767 #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) 2768 #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) 2769 #define DMA_CH1_CTRLA _SFR_MEM8(0x0120) 2770 #define DMA_CH1_CTRLB _SFR_MEM8(0x0121) 2771 #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) 2772 #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) 2773 #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) 2774 #define DMA_CH1_REPCNT _SFR_MEM8(0x0126) 2775 #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) 2776 #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) 2777 #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) 2778 #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) 2779 2780 /* EVSYS - Event System */ 2781 #define EVSYS_CH0MUX _SFR_MEM8(0x0180) 2782 #define EVSYS_CH1MUX _SFR_MEM8(0x0181) 2783 #define EVSYS_CH2MUX _SFR_MEM8(0x0182) 2784 #define EVSYS_CH3MUX _SFR_MEM8(0x0183) 2785 #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) 2786 #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) 2787 #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) 2788 #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) 2789 #define EVSYS_STROBE _SFR_MEM8(0x0190) 2790 #define EVSYS_DATA _SFR_MEM8(0x0191) 2791 2792 /* NVM - Non-volatile Memory Controller */ 2793 #define NVM_ADDR0 _SFR_MEM8(0x01C0) 2794 #define NVM_ADDR1 _SFR_MEM8(0x01C1) 2795 #define NVM_ADDR2 _SFR_MEM8(0x01C2) 2796 #define NVM_DATA0 _SFR_MEM8(0x01C4) 2797 #define NVM_DATA1 _SFR_MEM8(0x01C5) 2798 #define NVM_DATA2 _SFR_MEM8(0x01C6) 2799 #define NVM_CMD _SFR_MEM8(0x01CA) 2800 #define NVM_CTRLA _SFR_MEM8(0x01CB) 2801 #define NVM_CTRLB _SFR_MEM8(0x01CC) 2802 #define NVM_INTCTRL _SFR_MEM8(0x01CD) 2803 #define NVM_STATUS _SFR_MEM8(0x01CF) 2804 #define NVM_LOCKBITS _SFR_MEM8(0x01D0) 2805 2806 /* ADC - Analog-to-Digital Converter */ 2807 #define ADCB_CTRLA _SFR_MEM8(0x0240) 2808 #define ADCB_CTRLB _SFR_MEM8(0x0241) 2809 #define ADCB_REFCTRL _SFR_MEM8(0x0242) 2810 #define ADCB_EVCTRL _SFR_MEM8(0x0243) 2811 #define ADCB_PRESCALER _SFR_MEM8(0x0244) 2812 #define ADCB_INTFLAGS _SFR_MEM8(0x0246) 2813 #define ADCB_TEMP _SFR_MEM8(0x0247) 2814 #define ADCB_SAMPCTRL _SFR_MEM8(0x0248) 2815 #define ADCB_CAL _SFR_MEM16(0x024C) 2816 #define ADCB_CH0RES _SFR_MEM16(0x0250) 2817 #define ADCB_CMP _SFR_MEM16(0x0258) 2818 #define ADCB_CH0_CTRL _SFR_MEM8(0x0260) 2819 #define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) 2820 #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) 2821 #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) 2822 #define ADCB_CH0_RES _SFR_MEM16(0x0264) 2823 #define ADCB_CH0_SCAN _SFR_MEM8(0x0266) 2824 2825 /* AC - Analog Comparator */ 2826 #define ACB_AC0CTRL _SFR_MEM8(0x0390) 2827 #define ACB_AC1CTRL _SFR_MEM8(0x0391) 2828 #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) 2829 #define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) 2830 #define ACB_CTRLA _SFR_MEM8(0x0394) 2831 #define ACB_CTRLB _SFR_MEM8(0x0395) 2832 #define ACB_WINCTRL _SFR_MEM8(0x0396) 2833 #define ACB_STATUS _SFR_MEM8(0x0397) 2834 #define ACB_CURRCTRL _SFR_MEM8(0x0398) 2835 #define ACB_CURRCALIB _SFR_MEM8(0x0399) 2836 2837 /* RTC - Real-Time Counter */ 2838 #define RTC_CTRL _SFR_MEM8(0x0400) 2839 #define RTC_STATUS _SFR_MEM8(0x0401) 2840 #define RTC_INTCTRL _SFR_MEM8(0x0402) 2841 #define RTC_INTFLAGS _SFR_MEM8(0x0403) 2842 #define RTC_TEMP _SFR_MEM8(0x0404) 2843 #define RTC_CNT _SFR_MEM16(0x0408) 2844 #define RTC_PER _SFR_MEM16(0x040A) 2845 #define RTC_COMP _SFR_MEM16(0x040C) 2846 2847 /* TWI - Two-Wire Interface */ 2848 #define TWIC_CTRL _SFR_MEM8(0x0480) 2849 #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) 2850 #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) 2851 #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) 2852 #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) 2853 #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) 2854 #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) 2855 #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) 2856 #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) 2857 #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) 2858 #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) 2859 #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) 2860 #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) 2861 #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) 2862 2863 /* USB - Universal Serial Bus */ 2864 #define USB_CTRLA _SFR_MEM8(0x04C0) 2865 #define USB_CTRLB _SFR_MEM8(0x04C1) 2866 #define USB_STATUS _SFR_MEM8(0x04C2) 2867 #define USB_ADDR _SFR_MEM8(0x04C3) 2868 #define USB_FIFOWP _SFR_MEM8(0x04C4) 2869 #define USB_FIFORP _SFR_MEM8(0x04C5) 2870 #define USB_EPPTR _SFR_MEM16(0x04C6) 2871 #define USB_INTCTRLA _SFR_MEM8(0x04C8) 2872 #define USB_INTCTRLB _SFR_MEM8(0x04C9) 2873 #define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) 2874 #define USB_INTFLAGSASET _SFR_MEM8(0x04CB) 2875 #define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) 2876 #define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) 2877 #define USB_CAL0 _SFR_MEM8(0x04FA) 2878 #define USB_CAL1 _SFR_MEM8(0x04FB) 2879 2880 /* PORT - I/O Ports */ 2881 #define PORTB_DIR _SFR_MEM8(0x0620) 2882 #define PORTB_DIRSET _SFR_MEM8(0x0621) 2883 #define PORTB_DIRCLR _SFR_MEM8(0x0622) 2884 #define PORTB_DIRTGL _SFR_MEM8(0x0623) 2885 #define PORTB_OUT _SFR_MEM8(0x0624) 2886 #define PORTB_OUTSET _SFR_MEM8(0x0625) 2887 #define PORTB_OUTCLR _SFR_MEM8(0x0626) 2888 #define PORTB_OUTTGL _SFR_MEM8(0x0627) 2889 #define PORTB_IN _SFR_MEM8(0x0628) 2890 #define PORTB_INTCTRL _SFR_MEM8(0x0629) 2891 #define PORTB_INT0MASK _SFR_MEM8(0x062A) 2892 #define PORTB_INT1MASK _SFR_MEM8(0x062B) 2893 #define PORTB_INTFLAGS _SFR_MEM8(0x062C) 2894 #define PORTB_REMAP _SFR_MEM8(0x062E) 2895 #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) 2896 #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) 2897 #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) 2898 #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) 2899 #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) 2900 #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) 2901 #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) 2902 #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) 2903 2904 /* PORT - I/O Ports */ 2905 #define PORTC_DIR _SFR_MEM8(0x0640) 2906 #define PORTC_DIRSET _SFR_MEM8(0x0641) 2907 #define PORTC_DIRCLR _SFR_MEM8(0x0642) 2908 #define PORTC_DIRTGL _SFR_MEM8(0x0643) 2909 #define PORTC_OUT _SFR_MEM8(0x0644) 2910 #define PORTC_OUTSET _SFR_MEM8(0x0645) 2911 #define PORTC_OUTCLR _SFR_MEM8(0x0646) 2912 #define PORTC_OUTTGL _SFR_MEM8(0x0647) 2913 #define PORTC_IN _SFR_MEM8(0x0648) 2914 #define PORTC_INTCTRL _SFR_MEM8(0x0649) 2915 #define PORTC_INT0MASK _SFR_MEM8(0x064A) 2916 #define PORTC_INT1MASK _SFR_MEM8(0x064B) 2917 #define PORTC_INTFLAGS _SFR_MEM8(0x064C) 2918 #define PORTC_REMAP _SFR_MEM8(0x064E) 2919 #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) 2920 #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) 2921 #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) 2922 #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) 2923 #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) 2924 #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) 2925 #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) 2926 #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) 2927 2928 /* PORT - I/O Ports */ 2929 #define PORTD_DIR _SFR_MEM8(0x0660) 2930 #define PORTD_DIRSET _SFR_MEM8(0x0661) 2931 #define PORTD_DIRCLR _SFR_MEM8(0x0662) 2932 #define PORTD_DIRTGL _SFR_MEM8(0x0663) 2933 #define PORTD_OUT _SFR_MEM8(0x0664) 2934 #define PORTD_OUTSET _SFR_MEM8(0x0665) 2935 #define PORTD_OUTCLR _SFR_MEM8(0x0666) 2936 #define PORTD_OUTTGL _SFR_MEM8(0x0667) 2937 #define PORTD_IN _SFR_MEM8(0x0668) 2938 #define PORTD_INTCTRL _SFR_MEM8(0x0669) 2939 #define PORTD_INT0MASK _SFR_MEM8(0x066A) 2940 #define PORTD_INT1MASK _SFR_MEM8(0x066B) 2941 #define PORTD_INTFLAGS _SFR_MEM8(0x066C) 2942 #define PORTD_REMAP _SFR_MEM8(0x066E) 2943 #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) 2944 #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) 2945 #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) 2946 #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) 2947 #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) 2948 #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) 2949 #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) 2950 #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) 2951 2952 /* PORT - I/O Ports */ 2953 #define PORTG_DIR _SFR_MEM8(0x06C0) 2954 #define PORTG_DIRSET _SFR_MEM8(0x06C1) 2955 #define PORTG_DIRCLR _SFR_MEM8(0x06C2) 2956 #define PORTG_DIRTGL _SFR_MEM8(0x06C3) 2957 #define PORTG_OUT _SFR_MEM8(0x06C4) 2958 #define PORTG_OUTSET _SFR_MEM8(0x06C5) 2959 #define PORTG_OUTCLR _SFR_MEM8(0x06C6) 2960 #define PORTG_OUTTGL _SFR_MEM8(0x06C7) 2961 #define PORTG_IN _SFR_MEM8(0x06C8) 2962 #define PORTG_INTCTRL _SFR_MEM8(0x06C9) 2963 #define PORTG_INT0MASK _SFR_MEM8(0x06CA) 2964 #define PORTG_INT1MASK _SFR_MEM8(0x06CB) 2965 #define PORTG_INTFLAGS _SFR_MEM8(0x06CC) 2966 #define PORTG_REMAP _SFR_MEM8(0x06CE) 2967 #define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) 2968 #define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) 2969 #define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) 2970 #define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) 2971 #define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) 2972 #define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) 2973 #define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) 2974 #define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) 2975 2976 /* PORT - I/O Ports */ 2977 #define PORTM_DIR _SFR_MEM8(0x0760) 2978 #define PORTM_DIRSET _SFR_MEM8(0x0761) 2979 #define PORTM_DIRCLR _SFR_MEM8(0x0762) 2980 #define PORTM_DIRTGL _SFR_MEM8(0x0763) 2981 #define PORTM_OUT _SFR_MEM8(0x0764) 2982 #define PORTM_OUTSET _SFR_MEM8(0x0765) 2983 #define PORTM_OUTCLR _SFR_MEM8(0x0766) 2984 #define PORTM_OUTTGL _SFR_MEM8(0x0767) 2985 #define PORTM_IN _SFR_MEM8(0x0768) 2986 #define PORTM_INTCTRL _SFR_MEM8(0x0769) 2987 #define PORTM_INT0MASK _SFR_MEM8(0x076A) 2988 #define PORTM_INT1MASK _SFR_MEM8(0x076B) 2989 #define PORTM_INTFLAGS _SFR_MEM8(0x076C) 2990 #define PORTM_REMAP _SFR_MEM8(0x076E) 2991 #define PORTM_PIN0CTRL _SFR_MEM8(0x0770) 2992 #define PORTM_PIN1CTRL _SFR_MEM8(0x0771) 2993 #define PORTM_PIN2CTRL _SFR_MEM8(0x0772) 2994 #define PORTM_PIN3CTRL _SFR_MEM8(0x0773) 2995 #define PORTM_PIN4CTRL _SFR_MEM8(0x0774) 2996 #define PORTM_PIN5CTRL _SFR_MEM8(0x0775) 2997 #define PORTM_PIN6CTRL _SFR_MEM8(0x0776) 2998 #define PORTM_PIN7CTRL _SFR_MEM8(0x0777) 2999 3000 /* PORT - I/O Ports */ 3001 #define PORTR_DIR _SFR_MEM8(0x07E0) 3002 #define PORTR_DIRSET _SFR_MEM8(0x07E1) 3003 #define PORTR_DIRCLR _SFR_MEM8(0x07E2) 3004 #define PORTR_DIRTGL _SFR_MEM8(0x07E3) 3005 #define PORTR_OUT _SFR_MEM8(0x07E4) 3006 #define PORTR_OUTSET _SFR_MEM8(0x07E5) 3007 #define PORTR_OUTCLR _SFR_MEM8(0x07E6) 3008 #define PORTR_OUTTGL _SFR_MEM8(0x07E7) 3009 #define PORTR_IN _SFR_MEM8(0x07E8) 3010 #define PORTR_INTCTRL _SFR_MEM8(0x07E9) 3011 #define PORTR_INT0MASK _SFR_MEM8(0x07EA) 3012 #define PORTR_INT1MASK _SFR_MEM8(0x07EB) 3013 #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) 3014 #define PORTR_REMAP _SFR_MEM8(0x07EE) 3015 #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) 3016 #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) 3017 #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) 3018 #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) 3019 #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) 3020 #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) 3021 #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) 3022 #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) 3023 3024 /* TC0 - 16-bit Timer/Counter 0 */ 3025 #define TCC0_CTRLA _SFR_MEM8(0x0800) 3026 #define TCC0_CTRLB _SFR_MEM8(0x0801) 3027 #define TCC0_CTRLC _SFR_MEM8(0x0802) 3028 #define TCC0_CTRLD _SFR_MEM8(0x0803) 3029 #define TCC0_CTRLE _SFR_MEM8(0x0804) 3030 #define TCC0_INTCTRLA _SFR_MEM8(0x0806) 3031 #define TCC0_INTCTRLB _SFR_MEM8(0x0807) 3032 #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) 3033 #define TCC0_CTRLFSET _SFR_MEM8(0x0809) 3034 #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) 3035 #define TCC0_CTRLGSET _SFR_MEM8(0x080B) 3036 #define TCC0_INTFLAGS _SFR_MEM8(0x080C) 3037 #define TCC0_TEMP _SFR_MEM8(0x080F) 3038 #define TCC0_CNT _SFR_MEM16(0x0820) 3039 #define TCC0_PER _SFR_MEM16(0x0826) 3040 #define TCC0_CCA _SFR_MEM16(0x0828) 3041 #define TCC0_CCB _SFR_MEM16(0x082A) 3042 #define TCC0_CCC _SFR_MEM16(0x082C) 3043 #define TCC0_CCD _SFR_MEM16(0x082E) 3044 #define TCC0_PERBUF _SFR_MEM16(0x0836) 3045 #define TCC0_CCABUF _SFR_MEM16(0x0838) 3046 #define TCC0_CCBBUF _SFR_MEM16(0x083A) 3047 #define TCC0_CCCBUF _SFR_MEM16(0x083C) 3048 #define TCC0_CCDBUF _SFR_MEM16(0x083E) 3049 3050 /* TC1 - 16-bit Timer/Counter 1 */ 3051 #define TCC1_CTRLA _SFR_MEM8(0x0840) 3052 #define TCC1_CTRLB _SFR_MEM8(0x0841) 3053 #define TCC1_CTRLC _SFR_MEM8(0x0842) 3054 #define TCC1_CTRLD _SFR_MEM8(0x0843) 3055 #define TCC1_CTRLE _SFR_MEM8(0x0844) 3056 #define TCC1_INTCTRLA _SFR_MEM8(0x0846) 3057 #define TCC1_INTCTRLB _SFR_MEM8(0x0847) 3058 #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) 3059 #define TCC1_CTRLFSET _SFR_MEM8(0x0849) 3060 #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) 3061 #define TCC1_CTRLGSET _SFR_MEM8(0x084B) 3062 #define TCC1_INTFLAGS _SFR_MEM8(0x084C) 3063 #define TCC1_TEMP _SFR_MEM8(0x084F) 3064 #define TCC1_CNT _SFR_MEM16(0x0860) 3065 #define TCC1_PER _SFR_MEM16(0x0866) 3066 #define TCC1_CCA _SFR_MEM16(0x0868) 3067 #define TCC1_CCB _SFR_MEM16(0x086A) 3068 #define TCC1_PERBUF _SFR_MEM16(0x0876) 3069 #define TCC1_CCABUF _SFR_MEM16(0x0878) 3070 #define TCC1_CCBBUF _SFR_MEM16(0x087A) 3071 3072 /* AWEX - Advanced Waveform Extension */ 3073 #define AWEXC_CTRL _SFR_MEM8(0x0880) 3074 #define AWEXC_FDEMASK _SFR_MEM8(0x0882) 3075 #define AWEXC_FDCTRL _SFR_MEM8(0x0883) 3076 #define AWEXC_STATUS _SFR_MEM8(0x0884) 3077 #define AWEXC_STATUSSET _SFR_MEM8(0x0885) 3078 #define AWEXC_DTBOTH _SFR_MEM8(0x0886) 3079 #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) 3080 #define AWEXC_DTLS _SFR_MEM8(0x0888) 3081 #define AWEXC_DTHS _SFR_MEM8(0x0889) 3082 #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) 3083 #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) 3084 #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) 3085 3086 /* HIRES - High-Resolution Extension */ 3087 #define HIRESC_CTRLA _SFR_MEM8(0x0890) 3088 3089 /* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ 3090 #define USARTC0_DATA _SFR_MEM8(0x08A0) 3091 #define USARTC0_STATUS _SFR_MEM8(0x08A1) 3092 #define USARTC0_CTRLA _SFR_MEM8(0x08A3) 3093 #define USARTC0_CTRLB _SFR_MEM8(0x08A4) 3094 #define USARTC0_CTRLC _SFR_MEM8(0x08A5) 3095 #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) 3096 #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) 3097 3098 /* SPI - Serial Peripheral Interface */ 3099 #define SPIC_CTRL _SFR_MEM8(0x08C0) 3100 #define SPIC_INTCTRL _SFR_MEM8(0x08C1) 3101 #define SPIC_STATUS _SFR_MEM8(0x08C2) 3102 #define SPIC_DATA _SFR_MEM8(0x08C3) 3103 3104 /* IRCOM - IR Communication Module */ 3105 #define IRCOM_CTRL _SFR_MEM8(0x08F8) 3106 #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) 3107 #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) 3108 3109 /* LCD - LCD Controller */ 3110 #define LCD_CTRLA _SFR_MEM8(0x0D00) 3111 #define LCD_CTRLB _SFR_MEM8(0x0D01) 3112 #define LCD_CTRLC _SFR_MEM8(0x0D02) 3113 #define LCD_INTCTRL _SFR_MEM8(0x0D03) 3114 #define LCD_INTFLAG _SFR_MEM8(0x0D04) 3115 #define LCD_CTRLD _SFR_MEM8(0x0D05) 3116 #define LCD_CTRLE _SFR_MEM8(0x0D06) 3117 #define LCD_CTRLF _SFR_MEM8(0x0D07) 3118 #define LCD_CTRLG _SFR_MEM8(0x0D08) 3119 #define LCD_CTRLH _SFR_MEM8(0x0D09) 3120 #define LCD_DATA0 _SFR_MEM8(0x0D10) 3121 #define LCD_DATA1 _SFR_MEM8(0x0D11) 3122 #define LCD_DATA2 _SFR_MEM8(0x0D12) 3123 #define LCD_DATA3 _SFR_MEM8(0x0D13) 3124 #define LCD_DATA4 _SFR_MEM8(0x0D14) 3125 #define LCD_DATA5 _SFR_MEM8(0x0D15) 3126 #define LCD_DATA6 _SFR_MEM8(0x0D16) 3127 #define LCD_DATA7 _SFR_MEM8(0x0D17) 3128 #define LCD_DATA8 _SFR_MEM8(0x0D18) 3129 #define LCD_DATA9 _SFR_MEM8(0x0D19) 3130 #define LCD_DATA10 _SFR_MEM8(0x0D1A) 3131 #define LCD_DATA11 _SFR_MEM8(0x0D1B) 3132 #define LCD_DATA12 _SFR_MEM8(0x0D1C) 3133 #define LCD_DATA13 _SFR_MEM8(0x0D1D) 3134 #define LCD_DATA14 _SFR_MEM8(0x0D1E) 3135 #define LCD_DATA15 _SFR_MEM8(0x0D1F) 3136 #define LCD_DATA16 _SFR_MEM8(0x0D20) 3137 #define LCD_DATA17 _SFR_MEM8(0x0D21) 3138 #define LCD_DATA18 _SFR_MEM8(0x0D22) 3139 #define LCD_DATA19 _SFR_MEM8(0x0D23) 3140 3141 3142 3143 /*================== Bitfield Definitions ================== */ 3144 3145 /* VPORT - Virtual Ports */ 3146 /* VPORT.INTFLAGS bit masks and bit positions */ 3147 #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 3148 #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 3149 3150 #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 3151 #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 3152 3153 /* XOCD - On-Chip Debug System */ 3154 /* OCD.OCDR0 bit masks and bit positions */ 3155 #define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ 3156 #define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ 3157 #define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ 3158 #define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ 3159 #define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ 3160 #define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ 3161 #define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ 3162 #define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ 3163 #define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ 3164 #define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ 3165 #define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ 3166 #define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ 3167 #define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ 3168 #define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ 3169 #define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ 3170 #define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ 3171 #define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ 3172 #define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ 3173 3174 /* OCD.OCDR1 bit masks and bit positions */ 3175 /* OCD_OCDRD Predefined. */ 3176 /* OCD_OCDRD Predefined. */ 3177 3178 /* CPU - CPU */ 3179 /* CPU.CCP bit masks and bit positions */ 3180 #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ 3181 #define CPU_CCP_gp 0 /* CCP signature group position. */ 3182 #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ 3183 #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ 3184 #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ 3185 #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ 3186 #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ 3187 #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ 3188 #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ 3189 #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ 3190 #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ 3191 #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ 3192 #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ 3193 #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ 3194 #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ 3195 #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ 3196 #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ 3197 #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ 3198 3199 /* CPU.SREG bit masks and bit positions */ 3200 #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ 3201 #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ 3202 3203 #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ 3204 #define CPU_T_bp 6 /* Transfer Bit bit position. */ 3205 3206 #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ 3207 #define CPU_H_bp 5 /* Half Carry Flag bit position. */ 3208 3209 #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ 3210 #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ 3211 3212 #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ 3213 #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ 3214 3215 #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ 3216 #define CPU_N_bp 2 /* Negative Flag bit position. */ 3217 3218 #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ 3219 #define CPU_Z_bp 1 /* Zero Flag bit position. */ 3220 3221 #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ 3222 #define CPU_C_bp 0 /* Carry Flag bit position. */ 3223 3224 /* CLK - Clock System */ 3225 /* CLK.CTRL bit masks and bit positions */ 3226 #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ 3227 #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ 3228 #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ 3229 #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ 3230 #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ 3231 #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ 3232 #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ 3233 #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ 3234 3235 /* CLK.PSCTRL bit masks and bit positions */ 3236 #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ 3237 #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ 3238 #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ 3239 #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ 3240 #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ 3241 #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ 3242 #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ 3243 #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ 3244 #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ 3245 #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ 3246 #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ 3247 #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ 3248 3249 #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ 3250 #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ 3251 #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ 3252 #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ 3253 #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ 3254 #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ 3255 3256 /* CLK.LOCK bit masks and bit positions */ 3257 #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ 3258 #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ 3259 3260 /* CLK.RTCCTRL bit masks and bit positions */ 3261 #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ 3262 #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ 3263 #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 3264 #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ 3265 #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 3266 #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ 3267 #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ 3268 #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ 3269 3270 #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ 3271 #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ 3272 3273 /* CLK.USBCTRL bit masks and bit positions */ 3274 #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ 3275 #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ 3276 #define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ 3277 #define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ 3278 #define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ 3279 #define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ 3280 #define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ 3281 #define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ 3282 3283 #define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ 3284 #define CLK_USBSRC_gp 1 /* Clock Source group position. */ 3285 #define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 3286 #define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ 3287 #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 3288 #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ 3289 3290 #define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ 3291 #define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ 3292 3293 /* SLEEP - Sleep Controller */ 3294 /* SLEEP.CTRL bit masks and bit positions */ 3295 #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ 3296 #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ 3297 #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ 3298 #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ 3299 #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ 3300 #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ 3301 #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ 3302 #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ 3303 3304 #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ 3305 #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ 3306 3307 /* OSC - Oscillator */ 3308 /* OSC.CTRL bit masks and bit positions */ 3309 #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ 3310 #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ 3311 3312 #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ 3313 #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ 3314 3315 #define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ 3316 #define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ 3317 3318 #define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ 3319 #define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ 3320 3321 #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ 3322 #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ 3323 3324 /* OSC.STATUS bit masks and bit positions */ 3325 #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ 3326 #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ 3327 3328 #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ 3329 #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ 3330 3331 #define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ 3332 #define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ 3333 3334 #define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ 3335 #define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ 3336 3337 #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ 3338 #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ 3339 3340 /* OSC.XOSCCTRL bit masks and bit positions */ 3341 #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ 3342 #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ 3343 #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ 3344 #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ 3345 #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ 3346 #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ 3347 3348 #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ 3349 #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ 3350 3351 #define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ 3352 #define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ 3353 3354 #define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ 3355 #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ 3356 #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ 3357 #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ 3358 #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ 3359 #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ 3360 #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ 3361 #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ 3362 #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ 3363 #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ 3364 #define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ 3365 #define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ 3366 3367 /* OSC.XOSCFAIL bit masks and bit positions */ 3368 #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ 3369 #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ 3370 3371 #define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ 3372 #define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ 3373 3374 #define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ 3375 #define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ 3376 3377 #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ 3378 #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ 3379 3380 /* OSC.PLLCTRL bit masks and bit positions */ 3381 #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ 3382 #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ 3383 #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ 3384 #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ 3385 #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ 3386 #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ 3387 3388 #define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ 3389 #define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ 3390 3391 #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ 3392 #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ 3393 #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ 3394 #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ 3395 #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ 3396 #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ 3397 #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ 3398 #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ 3399 #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ 3400 #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ 3401 #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ 3402 #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ 3403 3404 /* OSC.DFLLCTRL bit masks and bit positions */ 3405 #define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ 3406 #define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ 3407 #define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ 3408 #define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ 3409 #define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ 3410 #define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ 3411 3412 #define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ 3413 #define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ 3414 3415 /* DFLL - DFLL */ 3416 /* DFLL.CTRL bit masks and bit positions */ 3417 #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ 3418 #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ 3419 3420 /* DFLL.CALA bit masks and bit positions */ 3421 #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ 3422 #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ 3423 #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ 3424 #define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ 3425 #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ 3426 #define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ 3427 #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ 3428 #define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ 3429 #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ 3430 #define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ 3431 #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ 3432 #define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ 3433 #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ 3434 #define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ 3435 #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ 3436 #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ 3437 3438 /* DFLL.CALB bit masks and bit positions */ 3439 #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ 3440 #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ 3441 #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ 3442 #define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ 3443 #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ 3444 #define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ 3445 #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ 3446 #define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ 3447 #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ 3448 #define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ 3449 #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ 3450 #define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ 3451 #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ 3452 #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ 3453 3454 /* PR - Power Reduction */ 3455 /* PR.PRGEN bit masks and bit positions */ 3456 #define PR_LCD_bm 0x80 /* LCD Module bit mask. */ 3457 #define PR_LCD_bp 7 /* LCD Module bit position. */ 3458 3459 #define PR_USB_bm 0x40 /* USB bit mask. */ 3460 #define PR_USB_bp 6 /* USB bit position. */ 3461 3462 #define PR_AES_bm 0x10 /* AES bit mask. */ 3463 #define PR_AES_bp 4 /* AES bit position. */ 3464 3465 #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ 3466 #define PR_RTC_bp 2 /* Real-time Counter bit position. */ 3467 3468 #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ 3469 #define PR_EVSYS_bp 1 /* Event System bit position. */ 3470 3471 #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ 3472 #define PR_DMA_bp 0 /* DMA-Controller bit position. */ 3473 3474 /* PR.PRPA bit masks and bit positions */ 3475 #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ 3476 #define PR_ADC_bp 1 /* Port A ADC bit position. */ 3477 3478 #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ 3479 #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ 3480 3481 /* PR.PRPB bit masks and bit positions */ 3482 /* PR_ADC Predefined. */ 3483 /* PR_ADC Predefined. */ 3484 3485 /* PR_AC Predefined. */ 3486 /* PR_AC Predefined. */ 3487 3488 /* PR.PRPC bit masks and bit positions */ 3489 #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ 3490 #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ 3491 3492 #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ 3493 #define PR_USART0_bp 4 /* Port C USART0 bit position. */ 3494 3495 #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ 3496 #define PR_SPI_bp 3 /* Port C SPI bit position. */ 3497 3498 #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ 3499 #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ 3500 3501 #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ 3502 #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ 3503 3504 #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ 3505 #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ 3506 3507 /* PR.PRPE bit masks and bit positions */ 3508 /* PR_USART0 Predefined. */ 3509 /* PR_USART0 Predefined. */ 3510 3511 /* PR_TC0 Predefined. */ 3512 /* PR_TC0 Predefined. */ 3513 3514 /* RST - Reset */ 3515 /* RST.STATUS bit masks and bit positions */ 3516 #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ 3517 #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ 3518 3519 #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ 3520 #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ 3521 3522 #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ 3523 #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ 3524 3525 #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ 3526 #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ 3527 3528 #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ 3529 #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ 3530 3531 #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ 3532 #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ 3533 3534 #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ 3535 #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ 3536 3537 /* RST.CTRL bit masks and bit positions */ 3538 #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ 3539 #define RST_SWRST_bp 0 /* Software Reset bit position. */ 3540 3541 /* WDT - Watch-Dog Timer */ 3542 /* WDT.CTRL bit masks and bit positions */ 3543 #define WDT_PER_gm 0x3C /* Period group mask. */ 3544 #define WDT_PER_gp 2 /* Period group position. */ 3545 #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ 3546 #define WDT_PER0_bp 2 /* Period bit 0 position. */ 3547 #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ 3548 #define WDT_PER1_bp 3 /* Period bit 1 position. */ 3549 #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ 3550 #define WDT_PER2_bp 4 /* Period bit 2 position. */ 3551 #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ 3552 #define WDT_PER3_bp 5 /* Period bit 3 position. */ 3553 3554 #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ 3555 #define WDT_ENABLE_bp 1 /* Enable bit position. */ 3556 3557 #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ 3558 #define WDT_CEN_bp 0 /* Change Enable bit position. */ 3559 3560 /* WDT.WINCTRL bit masks and bit positions */ 3561 #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ 3562 #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ 3563 #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ 3564 #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ 3565 #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ 3566 #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ 3567 #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ 3568 #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ 3569 #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ 3570 #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ 3571 3572 #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ 3573 #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ 3574 3575 #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ 3576 #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ 3577 3578 /* WDT.STATUS bit masks and bit positions */ 3579 #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ 3580 #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ 3581 3582 /* MCU - MCU Control */ 3583 /* MCU.MCUCR bit masks and bit positions */ 3584 #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ 3585 #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ 3586 3587 /* MCU.ANAINIT bit masks and bit positions */ 3588 #define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ 3589 #define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ 3590 #define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ 3591 #define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ 3592 #define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ 3593 #define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ 3594 3595 #define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ 3596 #define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ 3597 #define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ 3598 #define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ 3599 #define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ 3600 #define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ 3601 3602 /* MCU.EVSYSLOCK bit masks and bit positions */ 3603 #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ 3604 #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ 3605 3606 #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ 3607 #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ 3608 3609 /* MCU.AWEXLOCK bit masks and bit positions */ 3610 #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ 3611 #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ 3612 3613 /* PMIC - Programmable Multi-level Interrupt Controller */ 3614 /* PMIC.STATUS bit masks and bit positions */ 3615 #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ 3616 #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ 3617 3618 #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ 3619 #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ 3620 3621 #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ 3622 #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ 3623 3624 #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ 3625 #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ 3626 3627 /* PMIC.INTPRI bit masks and bit positions */ 3628 #define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ 3629 #define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ 3630 #define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ 3631 #define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ 3632 #define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ 3633 #define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ 3634 #define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ 3635 #define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ 3636 #define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ 3637 #define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ 3638 #define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ 3639 #define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ 3640 #define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ 3641 #define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ 3642 #define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ 3643 #define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ 3644 #define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ 3645 #define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ 3646 3647 /* PMIC.CTRL bit masks and bit positions */ 3648 #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ 3649 #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ 3650 3651 #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ 3652 #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ 3653 3654 #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ 3655 #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ 3656 3657 #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ 3658 #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ 3659 3660 #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ 3661 #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ 3662 3663 /* PORTCFG - Port Configuration */ 3664 /* PORTCFG.VPCTRLA bit masks and bit positions */ 3665 #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ 3666 #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ 3667 #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ 3668 #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ 3669 #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ 3670 #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ 3671 #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ 3672 #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ 3673 #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ 3674 #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ 3675 3676 #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ 3677 #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ 3678 #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ 3679 #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ 3680 #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ 3681 #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ 3682 #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ 3683 #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ 3684 #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ 3685 #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ 3686 3687 /* PORTCFG.VPCTRLB bit masks and bit positions */ 3688 #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ 3689 #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ 3690 #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ 3691 #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ 3692 #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ 3693 #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ 3694 #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ 3695 #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ 3696 #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ 3697 #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ 3698 3699 #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ 3700 #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ 3701 #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ 3702 #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ 3703 #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ 3704 #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ 3705 #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ 3706 #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ 3707 #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ 3708 #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ 3709 3710 /* PORTCFG.CLKEVOUT bit masks and bit positions */ 3711 #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ 3712 #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ 3713 #define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ 3714 #define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ 3715 #define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ 3716 #define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ 3717 3718 #define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ 3719 #define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ 3720 #define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ 3721 #define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ 3722 #define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ 3723 #define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ 3724 3725 #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ 3726 #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ 3727 #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ 3728 #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ 3729 #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ 3730 #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ 3731 3732 #define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ 3733 #define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ 3734 3735 #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ 3736 #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ 3737 3738 /* PORTCFG.EVOUTSEL bit masks and bit positions */ 3739 #define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ 3740 #define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ 3741 3742 /* AES - AES Module */ 3743 /* AES.CTRL bit masks and bit positions */ 3744 #define AES_START_bm 0x80 /* Start/Run bit mask. */ 3745 #define AES_START_bp 7 /* Start/Run bit position. */ 3746 3747 #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ 3748 #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ 3749 3750 #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ 3751 #define AES_RESET_bp 5 /* AES Software Reset bit position. */ 3752 3753 #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ 3754 #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ 3755 3756 #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ 3757 #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ 3758 3759 /* AES.STATUS bit masks and bit positions */ 3760 #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ 3761 #define AES_ERROR_bp 7 /* AES Error bit position. */ 3762 3763 #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ 3764 #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ 3765 3766 /* AES.INTCTRL bit masks and bit positions */ 3767 #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ 3768 #define AES_INTLVL_gp 0 /* Interrupt level group position. */ 3769 #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 3770 #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 3771 #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 3772 #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 3773 3774 /* CRC - Cyclic Redundancy Checker */ 3775 /* CRC.CTRL bit masks and bit positions */ 3776 #define CRC_RESET_gm 0xC0 /* Reset group mask. */ 3777 #define CRC_RESET_gp 6 /* Reset group position. */ 3778 #define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ 3779 #define CRC_RESET0_bp 6 /* Reset bit 0 position. */ 3780 #define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ 3781 #define CRC_RESET1_bp 7 /* Reset bit 1 position. */ 3782 3783 #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ 3784 #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ 3785 3786 #define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ 3787 #define CRC_SOURCE_gp 0 /* Input Source group position. */ 3788 #define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ 3789 #define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ 3790 #define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ 3791 #define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ 3792 #define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ 3793 #define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ 3794 #define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ 3795 #define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ 3796 3797 /* CRC.STATUS bit masks and bit positions */ 3798 #define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ 3799 #define CRC_ZERO_bp 1 /* Zero detection bit position. */ 3800 3801 #define CRC_BUSY_bm 0x01 /* Busy bit mask. */ 3802 #define CRC_BUSY_bp 0 /* Busy bit position. */ 3803 3804 /* DMA - DMA Controller */ 3805 /* DMA_CH.CTRLA bit masks and bit positions */ 3806 #define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ 3807 #define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ 3808 3809 #define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ 3810 #define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ 3811 3812 #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ 3813 #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ 3814 3815 #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ 3816 #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ 3817 3818 #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ 3819 #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ 3820 3821 #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ 3822 #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ 3823 #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ 3824 #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ 3825 #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ 3826 #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ 3827 3828 /* DMA_CH.CTRLB bit masks and bit positions */ 3829 #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ 3830 #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ 3831 3832 #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ 3833 #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ 3834 3835 #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ 3836 #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ 3837 3838 #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ 3839 #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ 3840 3841 #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ 3842 #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ 3843 #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ 3844 #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ 3845 #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ 3846 #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ 3847 3848 #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ 3849 #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ 3850 #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ 3851 #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ 3852 #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ 3853 #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ 3854 3855 /* DMA_CH.ADDRCTRL bit masks and bit positions */ 3856 #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ 3857 #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ 3858 #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ 3859 #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ 3860 #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ 3861 #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ 3862 3863 #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ 3864 #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ 3865 #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ 3866 #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ 3867 #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ 3868 #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ 3869 3870 #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ 3871 #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ 3872 #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ 3873 #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ 3874 #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ 3875 #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ 3876 3877 #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ 3878 #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ 3879 #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ 3880 #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ 3881 #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ 3882 #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ 3883 3884 /* DMA_CH.TRIGSRC bit masks and bit positions */ 3885 #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ 3886 #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ 3887 #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ 3888 #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ 3889 #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ 3890 #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ 3891 #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ 3892 #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ 3893 #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ 3894 #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ 3895 #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ 3896 #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ 3897 #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ 3898 #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ 3899 #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ 3900 #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ 3901 #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ 3902 #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ 3903 3904 /* DMA.CTRL bit masks and bit positions */ 3905 #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ 3906 #define DMA_ENABLE_bp 7 /* Enable bit position. */ 3907 3908 #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ 3909 #define DMA_RESET_bp 6 /* Software Reset bit position. */ 3910 3911 #define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ 3912 #define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ 3913 3914 #define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ 3915 #define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ 3916 3917 /* DMA.INTFLAGS bit masks and bit positions */ 3918 #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ 3919 #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ 3920 3921 #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ 3922 #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ 3923 3924 #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ 3925 #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ 3926 3927 #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ 3928 #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ 3929 3930 /* DMA.STATUS bit masks and bit positions */ 3931 #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ 3932 #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ 3933 3934 #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ 3935 #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ 3936 3937 #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ 3938 #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ 3939 3940 #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ 3941 #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ 3942 3943 /* EVSYS - Event System */ 3944 /* EVSYS.CH0MUX bit masks and bit positions */ 3945 #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ 3946 #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ 3947 #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ 3948 #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ 3949 #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ 3950 #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ 3951 #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ 3952 #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ 3953 #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ 3954 #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ 3955 #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ 3956 #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ 3957 #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ 3958 #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ 3959 #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ 3960 #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ 3961 #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ 3962 #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ 3963 3964 /* EVSYS.CH1MUX bit masks and bit positions */ 3965 /* EVSYS_CHMUX Predefined. */ 3966 /* EVSYS_CHMUX Predefined. */ 3967 3968 /* EVSYS.CH2MUX bit masks and bit positions */ 3969 /* EVSYS_CHMUX Predefined. */ 3970 /* EVSYS_CHMUX Predefined. */ 3971 3972 /* EVSYS.CH3MUX bit masks and bit positions */ 3973 /* EVSYS_CHMUX Predefined. */ 3974 /* EVSYS_CHMUX Predefined. */ 3975 3976 /* EVSYS.CH0CTRL bit masks and bit positions */ 3977 #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ 3978 #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ 3979 #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ 3980 #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ 3981 #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ 3982 #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ 3983 3984 #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ 3985 #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ 3986 3987 #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ 3988 #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ 3989 3990 #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ 3991 #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ 3992 #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ 3993 #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ 3994 #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ 3995 #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ 3996 #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ 3997 #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ 3998 3999 /* EVSYS.CH1CTRL bit masks and bit positions */ 4000 /* EVSYS_DIGFILT Predefined. */ 4001 /* EVSYS_DIGFILT Predefined. */ 4002 4003 /* EVSYS.CH2CTRL bit masks and bit positions */ 4004 /* EVSYS_DIGFILT Predefined. */ 4005 /* EVSYS_DIGFILT Predefined. */ 4006 4007 /* EVSYS.CH3CTRL bit masks and bit positions */ 4008 /* EVSYS_DIGFILT Predefined. */ 4009 /* EVSYS_DIGFILT Predefined. */ 4010 4011 /* NVM - Non Volatile Memory Controller */ 4012 /* NVM.CMD bit masks and bit positions */ 4013 #define NVM_CMD_gm 0x7F /* Command group mask. */ 4014 #define NVM_CMD_gp 0 /* Command group position. */ 4015 #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4016 #define NVM_CMD0_bp 0 /* Command bit 0 position. */ 4017 #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4018 #define NVM_CMD1_bp 1 /* Command bit 1 position. */ 4019 #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ 4020 #define NVM_CMD2_bp 2 /* Command bit 2 position. */ 4021 #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ 4022 #define NVM_CMD3_bp 3 /* Command bit 3 position. */ 4023 #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ 4024 #define NVM_CMD4_bp 4 /* Command bit 4 position. */ 4025 #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ 4026 #define NVM_CMD5_bp 5 /* Command bit 5 position. */ 4027 #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ 4028 #define NVM_CMD6_bp 6 /* Command bit 6 position. */ 4029 4030 /* NVM.CTRLA bit masks and bit positions */ 4031 #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ 4032 #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ 4033 4034 /* NVM.CTRLB bit masks and bit positions */ 4035 #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ 4036 #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ 4037 4038 #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ 4039 #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ 4040 4041 #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ 4042 #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ 4043 4044 #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ 4045 #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ 4046 4047 /* NVM.INTCTRL bit masks and bit positions */ 4048 #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ 4049 #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ 4050 #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ 4051 #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ 4052 #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ 4053 #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ 4054 4055 #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ 4056 #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ 4057 #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ 4058 #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ 4059 #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ 4060 #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ 4061 4062 /* NVM.STATUS bit masks and bit positions */ 4063 #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ 4064 #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ 4065 4066 #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ 4067 #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ 4068 4069 #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ 4070 #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ 4071 4072 #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ 4073 #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ 4074 4075 /* NVM.LOCKBITS bit masks and bit positions */ 4076 #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 4077 #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 4078 #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 4079 #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 4080 #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 4081 #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 4082 4083 #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 4084 #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 4085 #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 4086 #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 4087 #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 4088 #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 4089 4090 #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 4091 #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 4092 #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 4093 #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 4094 #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 4095 #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 4096 4097 #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ 4098 #define NVM_LB_gp 0 /* Lock Bits group position. */ 4099 #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 4100 #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ 4101 #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 4102 #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ 4103 4104 /* ADC - Analog/Digital Converter */ 4105 /* ADC_CH.CTRL bit masks and bit positions */ 4106 #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ 4107 #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ 4108 4109 #define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ 4110 #define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ 4111 #define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ 4112 #define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ 4113 #define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ 4114 #define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ 4115 #define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ 4116 #define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ 4117 4118 #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ 4119 #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ 4120 #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ 4121 #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ 4122 #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ 4123 #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ 4124 4125 /* ADC_CH.MUXCTRL bit masks and bit positions */ 4126 #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ 4127 #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ 4128 #define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ 4129 #define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ 4130 #define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ 4131 #define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ 4132 #define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ 4133 #define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ 4134 #define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ 4135 #define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ 4136 4137 #define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ 4138 #define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ 4139 #define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ 4140 #define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ 4141 #define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ 4142 #define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ 4143 #define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ 4144 #define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ 4145 #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ 4146 #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ 4147 4148 #define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ 4149 #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ 4150 #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ 4151 #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ 4152 #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ 4153 #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ 4154 4155 /* ADC_CH.INTCTRL bit masks and bit positions */ 4156 #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ 4157 #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ 4158 #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ 4159 #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ 4160 #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ 4161 #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ 4162 4163 #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 4164 #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ 4165 #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 4166 #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 4167 #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 4168 #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 4169 4170 /* ADC_CH.INTFLAGS bit masks and bit positions */ 4171 #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ 4172 #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ 4173 4174 /* ADC_CH.SCAN bit masks and bit positions */ 4175 #define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ 4176 #define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ 4177 #define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ 4178 #define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ 4179 #define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ 4180 #define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ 4181 #define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ 4182 #define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ 4183 #define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ 4184 #define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ 4185 4186 #define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ 4187 #define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ 4188 #define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ 4189 #define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ 4190 #define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ 4191 #define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ 4192 #define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ 4193 #define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ 4194 #define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ 4195 #define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ 4196 4197 /* ADC.CTRLA bit masks and bit positions */ 4198 #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ 4199 #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ 4200 4201 #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ 4202 #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ 4203 4204 #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ 4205 #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ 4206 4207 /* ADC.CTRLB bit masks and bit positions */ 4208 #define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ 4209 #define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ 4210 #define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ 4211 #define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ 4212 #define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ 4213 #define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ 4214 4215 #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ 4216 #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ 4217 4218 #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ 4219 #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ 4220 4221 #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ 4222 #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ 4223 #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ 4224 #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ 4225 #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ 4226 #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ 4227 4228 /* ADC.REFCTRL bit masks and bit positions */ 4229 #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ 4230 #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ 4231 #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ 4232 #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ 4233 #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ 4234 #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ 4235 #define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ 4236 #define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ 4237 4238 #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ 4239 #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ 4240 4241 #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ 4242 #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ 4243 4244 /* ADC.EVCTRL bit masks and bit positions */ 4245 #define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ 4246 #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ 4247 #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ 4248 #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ 4249 #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ 4250 #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ 4251 4252 #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ 4253 #define ADC_EVACT_gp 0 /* Event Action Select group position. */ 4254 #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ 4255 #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ 4256 #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ 4257 #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ 4258 #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ 4259 #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ 4260 4261 /* ADC.PRESCALER bit masks and bit positions */ 4262 #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ 4263 #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ 4264 #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ 4265 #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ 4266 #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ 4267 #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ 4268 #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ 4269 #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ 4270 4271 /* ADC.INTFLAGS bit masks and bit positions */ 4272 #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ 4273 #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ 4274 4275 /* ADC.SAMPCTRL bit masks and bit positions */ 4276 #define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ 4277 #define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ 4278 #define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ 4279 #define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ 4280 #define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ 4281 #define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ 4282 #define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ 4283 #define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ 4284 #define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ 4285 #define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ 4286 #define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ 4287 #define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ 4288 #define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ 4289 #define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ 4290 4291 /* AC - Analog Comparator */ 4292 /* AC.AC0CTRL bit masks and bit positions */ 4293 #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ 4294 #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ 4295 #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ 4296 #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ 4297 #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ 4298 #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ 4299 4300 #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ 4301 #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ 4302 #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ 4303 #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ 4304 #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ 4305 #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ 4306 4307 #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ 4308 #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ 4309 #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ 4310 #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ 4311 #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ 4312 #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ 4313 4314 #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ 4315 #define AC_ENABLE_bp 0 /* Enable bit position. */ 4316 4317 /* AC.AC1CTRL bit masks and bit positions */ 4318 /* AC_INTMODE Predefined. */ 4319 /* AC_INTMODE Predefined. */ 4320 4321 /* AC_INTLVL Predefined. */ 4322 /* AC_INTLVL Predefined. */ 4323 4324 /* AC_HYSMODE Predefined. */ 4325 /* AC_HYSMODE Predefined. */ 4326 4327 /* AC_ENABLE Predefined. */ 4328 /* AC_ENABLE Predefined. */ 4329 4330 /* AC.AC0MUXCTRL bit masks and bit positions */ 4331 #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ 4332 #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ 4333 #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ 4334 #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ 4335 #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ 4336 #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ 4337 #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ 4338 #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ 4339 4340 #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ 4341 #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ 4342 #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ 4343 #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ 4344 #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ 4345 #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ 4346 #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ 4347 #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ 4348 4349 /* AC.AC1MUXCTRL bit masks and bit positions */ 4350 /* AC_MUXPOS Predefined. */ 4351 /* AC_MUXPOS Predefined. */ 4352 4353 /* AC_MUXNEG Predefined. */ 4354 /* AC_MUXNEG Predefined. */ 4355 4356 /* AC.CTRLA bit masks and bit positions */ 4357 #define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ 4358 #define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ 4359 4360 #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ 4361 #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ 4362 4363 /* AC.CTRLB bit masks and bit positions */ 4364 #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ 4365 #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ 4366 #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ 4367 #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ 4368 #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ 4369 #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ 4370 #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ 4371 #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ 4372 #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ 4373 #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ 4374 #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ 4375 #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ 4376 #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ 4377 #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ 4378 4379 /* AC.WINCTRL bit masks and bit positions */ 4380 #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ 4381 #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ 4382 4383 #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ 4384 #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ 4385 #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ 4386 #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ 4387 #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ 4388 #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ 4389 4390 #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ 4391 #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ 4392 #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ 4393 #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ 4394 #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ 4395 #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ 4396 4397 /* AC.STATUS bit masks and bit positions */ 4398 #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ 4399 #define AC_WSTATE_gp 6 /* Window Mode State group position. */ 4400 #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ 4401 #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ 4402 #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ 4403 #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ 4404 4405 #define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ 4406 #define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ 4407 4408 #define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ 4409 #define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ 4410 4411 #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ 4412 #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ 4413 4414 #define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ 4415 #define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ 4416 4417 #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ 4418 #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ 4419 4420 /* AC.CURRCTRL bit masks and bit positions */ 4421 #define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ 4422 #define AC_CURREN_bp 7 /* Current Source Enable bit position. */ 4423 4424 #define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ 4425 #define AC_CURRMODE_bp 6 /* Current Mode bit position. */ 4426 4427 #define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ 4428 #define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ 4429 4430 #define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ 4431 #define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ 4432 4433 /* AC.CURRCALIB bit masks and bit positions */ 4434 #define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ 4435 #define AC_CALIB_gp 0 /* Current Source Calibration group position. */ 4436 #define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ 4437 #define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ 4438 #define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ 4439 #define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ 4440 #define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ 4441 #define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ 4442 #define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ 4443 #define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ 4444 4445 /* RTC - Real-Time Counter */ 4446 /* RTC.CTRL bit masks and bit positions */ 4447 #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ 4448 #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ 4449 #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ 4450 #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ 4451 #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ 4452 #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ 4453 #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ 4454 #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ 4455 4456 /* RTC.STATUS bit masks and bit positions */ 4457 #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ 4458 #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ 4459 4460 /* RTC.INTCTRL bit masks and bit positions */ 4461 #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ 4462 #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ 4463 #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ 4464 #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ 4465 #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ 4466 #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ 4467 4468 #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ 4469 #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ 4470 #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ 4471 #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ 4472 #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ 4473 #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ 4474 4475 /* RTC.INTFLAGS bit masks and bit positions */ 4476 #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ 4477 #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ 4478 4479 #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4480 #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 4481 4482 /* TWI - Two-Wire Interface */ 4483 /* TWI_MASTER.CTRLA bit masks and bit positions */ 4484 #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4485 #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ 4486 #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4487 #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4488 #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4489 #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4490 4491 #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ 4492 #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ 4493 4494 #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ 4495 #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ 4496 4497 #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ 4498 #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ 4499 4500 /* TWI_MASTER.CTRLB bit masks and bit positions */ 4501 #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ 4502 #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ 4503 #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ 4504 #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ 4505 #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ 4506 #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ 4507 4508 #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ 4509 #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ 4510 4511 #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4512 #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4513 4514 /* TWI_MASTER.CTRLC bit masks and bit positions */ 4515 #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4516 #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4517 4518 #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ 4519 #define TWI_MASTER_CMD_gp 0 /* Command group position. */ 4520 #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4521 #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ 4522 #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4523 #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ 4524 4525 /* TWI_MASTER.STATUS bit masks and bit positions */ 4526 #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ 4527 #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ 4528 4529 #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ 4530 #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ 4531 4532 #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4533 #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4534 4535 #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4536 #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ 4537 4538 #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ 4539 #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ 4540 4541 #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4542 #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ 4543 4544 #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ 4545 #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ 4546 #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ 4547 #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ 4548 #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ 4549 #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ 4550 4551 /* TWI_SLAVE.CTRLA bit masks and bit positions */ 4552 #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4553 #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ 4554 #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4555 #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4556 #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4557 #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4558 4559 #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ 4560 #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ 4561 4562 #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ 4563 #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ 4564 4565 #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ 4566 #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ 4567 4568 #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ 4569 #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ 4570 4571 #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ 4572 #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ 4573 4574 #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4575 #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4576 4577 /* TWI_SLAVE.CTRLB bit masks and bit positions */ 4578 #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4579 #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4580 4581 #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ 4582 #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ 4583 #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4584 #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ 4585 #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4586 #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ 4587 4588 /* TWI_SLAVE.STATUS bit masks and bit positions */ 4589 #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ 4590 #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ 4591 4592 #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ 4593 #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ 4594 4595 #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4596 #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4597 4598 #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4599 #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ 4600 4601 #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ 4602 #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ 4603 4604 #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4605 #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ 4606 4607 #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ 4608 #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ 4609 4610 #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ 4611 #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ 4612 4613 /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ 4614 #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ 4615 #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ 4616 #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ 4617 #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ 4618 #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ 4619 #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ 4620 #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ 4621 #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ 4622 #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ 4623 #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ 4624 #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ 4625 #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ 4626 #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ 4627 #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ 4628 #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ 4629 #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ 4630 4631 #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ 4632 #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ 4633 4634 /* TWI.CTRL bit masks and bit positions */ 4635 #define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ 4636 #define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ 4637 #define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ 4638 #define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ 4639 #define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ 4640 #define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ 4641 4642 #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ 4643 #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ 4644 4645 /* USB - USB */ 4646 /* USB_EP.STATUS bit masks and bit positions */ 4647 #define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ 4648 #define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ 4649 4650 #define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ 4651 #define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ 4652 4653 #define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ 4654 #define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ 4655 4656 #define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ 4657 #define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ 4658 4659 #define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ 4660 #define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ 4661 4662 #define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ 4663 #define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ 4664 4665 #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ 4666 #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ 4667 4668 #define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ 4669 #define USB_EP_BANK_bp 3 /* Bank Select bit position. */ 4670 4671 #define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ 4672 #define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ 4673 4674 #define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ 4675 #define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ 4676 4677 #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ 4678 #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ 4679 4680 /* USB_EP.CTRL bit masks and bit positions */ 4681 #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ 4682 #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ 4683 #define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ 4684 #define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ 4685 #define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ 4686 #define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ 4687 4688 #define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ 4689 #define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ 4690 4691 #define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ 4692 #define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ 4693 4694 #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ 4695 #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ 4696 4697 #define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ 4698 #define USB_EP_STALL_bp 2 /* Data Stall bit position. */ 4699 4700 #define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ 4701 #define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ 4702 #define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ 4703 #define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ 4704 #define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ 4705 #define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ 4706 #define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ 4707 #define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ 4708 4709 /* USB_EP.CNT bit masks and bit positions */ 4710 #define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ 4711 #define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ 4712 4713 /* USB.CTRLA bit masks and bit positions */ 4714 #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ 4715 #define USB_ENABLE_bp 7 /* USB Enable bit position. */ 4716 4717 #define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ 4718 #define USB_SPEED_bp 6 /* Speed Select bit position. */ 4719 4720 #define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ 4721 #define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ 4722 4723 #define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ 4724 #define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ 4725 4726 #define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ 4727 #define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ 4728 #define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ 4729 #define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ 4730 #define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ 4731 #define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ 4732 #define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ 4733 #define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ 4734 #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ 4735 #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ 4736 4737 /* USB.CTRLB bit masks and bit positions */ 4738 #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ 4739 #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ 4740 4741 #define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ 4742 #define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ 4743 4744 #define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ 4745 #define USB_GNACK_bp 1 /* Global NACK bit position. */ 4746 4747 #define USB_ATTACH_bm 0x01 /* Attach bit mask. */ 4748 #define USB_ATTACH_bp 0 /* Attach bit position. */ 4749 4750 /* USB.STATUS bit masks and bit positions */ 4751 #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ 4752 #define USB_URESUME_bp 3 /* Upstream Resume bit position. */ 4753 4754 #define USB_RESUME_bm 0x04 /* Resume bit mask. */ 4755 #define USB_RESUME_bp 2 /* Resume bit position. */ 4756 4757 #define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ 4758 #define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ 4759 4760 #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ 4761 #define USB_BUSRST_bp 0 /* Bus Reset bit position. */ 4762 4763 /* USB.ADDR bit masks and bit positions */ 4764 #define USB_ADDR_gm 0x7F /* Device Address group mask. */ 4765 #define USB_ADDR_gp 0 /* Device Address group position. */ 4766 #define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ 4767 #define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ 4768 #define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ 4769 #define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ 4770 #define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ 4771 #define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ 4772 #define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ 4773 #define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ 4774 #define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ 4775 #define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ 4776 #define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ 4777 #define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ 4778 #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ 4779 #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ 4780 4781 /* USB.FIFOWP bit masks and bit positions */ 4782 #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ 4783 #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ 4784 #define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ 4785 #define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ 4786 #define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ 4787 #define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ 4788 #define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ 4789 #define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ 4790 #define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ 4791 #define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ 4792 #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ 4793 #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ 4794 4795 /* USB.FIFORP bit masks and bit positions */ 4796 #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ 4797 #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ 4798 #define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ 4799 #define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ 4800 #define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ 4801 #define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ 4802 #define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ 4803 #define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ 4804 #define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ 4805 #define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ 4806 #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ 4807 #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ 4808 4809 /* USB.INTCTRLA bit masks and bit positions */ 4810 #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ 4811 #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ 4812 4813 #define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ 4814 #define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ 4815 4816 #define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ 4817 #define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ 4818 4819 #define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ 4820 #define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ 4821 4822 #define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 4823 #define USB_INTLVL_gp 0 /* Interrupt Level group position. */ 4824 #define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 4825 #define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 4826 #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 4827 #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 4828 4829 /* USB.INTCTRLB bit masks and bit positions */ 4830 #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ 4831 #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ 4832 4833 #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ 4834 #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ 4835 4836 /* USB.INTFLAGSACLR bit masks and bit positions */ 4837 #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ 4838 #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ 4839 4840 #define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ 4841 #define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ 4842 4843 #define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ 4844 #define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ 4845 4846 #define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ 4847 #define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ 4848 4849 #define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ 4850 #define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ 4851 4852 #define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ 4853 #define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ 4854 4855 #define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ 4856 #define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ 4857 4858 #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ 4859 #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ 4860 4861 /* USB.INTFLAGSASET bit masks and bit positions */ 4862 /* USB_SOFIF Predefined. */ 4863 /* USB_SOFIF Predefined. */ 4864 4865 /* USB_SUSPENDIF Predefined. */ 4866 /* USB_SUSPENDIF Predefined. */ 4867 4868 /* USB_RESUMEIF Predefined. */ 4869 /* USB_RESUMEIF Predefined. */ 4870 4871 /* USB_RSTIF Predefined. */ 4872 /* USB_RSTIF Predefined. */ 4873 4874 /* USB_CRCIF Predefined. */ 4875 /* USB_CRCIF Predefined. */ 4876 4877 /* USB_UNFIF Predefined. */ 4878 /* USB_UNFIF Predefined. */ 4879 4880 /* USB_OVFIF Predefined. */ 4881 /* USB_OVFIF Predefined. */ 4882 4883 /* USB_STALLIF Predefined. */ 4884 /* USB_STALLIF Predefined. */ 4885 4886 /* USB.INTFLAGSBCLR bit masks and bit positions */ 4887 #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ 4888 #define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ 4889 4890 #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ 4891 #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ 4892 4893 /* USB.INTFLAGSBSET bit masks and bit positions */ 4894 /* USB_TRNIF Predefined. */ 4895 /* USB_TRNIF Predefined. */ 4896 4897 /* USB_SETUPIF Predefined. */ 4898 /* USB_SETUPIF Predefined. */ 4899 4900 /* PORT - I/O Port Configuration */ 4901 /* PORT.INTCTRL bit masks and bit positions */ 4902 #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ 4903 #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ 4904 #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ 4905 #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ 4906 #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ 4907 #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ 4908 4909 #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ 4910 #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ 4911 #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ 4912 #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ 4913 #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ 4914 #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ 4915 4916 /* PORT.INTFLAGS bit masks and bit positions */ 4917 #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 4918 #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 4919 4920 #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 4921 #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 4922 4923 /* PORT.REMAP bit masks and bit positions */ 4924 #define PORT_SPI_bm 0x20 /* SPI bit mask. */ 4925 #define PORT_SPI_bp 5 /* SPI bit position. */ 4926 4927 #define PORT_USART0_bm 0x10 /* USART0 bit mask. */ 4928 #define PORT_USART0_bp 4 /* USART0 bit position. */ 4929 4930 #define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ 4931 #define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ 4932 4933 #define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ 4934 #define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ 4935 4936 #define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ 4937 #define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ 4938 4939 #define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ 4940 #define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ 4941 4942 /* PORT.PIN0CTRL bit masks and bit positions */ 4943 #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ 4944 #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ 4945 4946 #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ 4947 #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ 4948 4949 #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ 4950 #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ 4951 #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ 4952 #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ 4953 #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ 4954 #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ 4955 #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ 4956 #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ 4957 4958 #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ 4959 #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ 4960 #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ 4961 #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ 4962 #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ 4963 #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ 4964 #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ 4965 #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ 4966 4967 /* PORT.PIN1CTRL bit masks and bit positions */ 4968 /* PORT_SRLEN Predefined. */ 4969 /* PORT_SRLEN Predefined. */ 4970 4971 /* PORT_INVEN Predefined. */ 4972 /* PORT_INVEN Predefined. */ 4973 4974 /* PORT_OPC Predefined. */ 4975 /* PORT_OPC Predefined. */ 4976 4977 /* PORT_ISC Predefined. */ 4978 /* PORT_ISC Predefined. */ 4979 4980 /* PORT.PIN2CTRL bit masks and bit positions */ 4981 /* PORT_SRLEN Predefined. */ 4982 /* PORT_SRLEN Predefined. */ 4983 4984 /* PORT_INVEN Predefined. */ 4985 /* PORT_INVEN Predefined. */ 4986 4987 /* PORT_OPC Predefined. */ 4988 /* PORT_OPC Predefined. */ 4989 4990 /* PORT_ISC Predefined. */ 4991 /* PORT_ISC Predefined. */ 4992 4993 /* PORT.PIN3CTRL bit masks and bit positions */ 4994 /* PORT_SRLEN Predefined. */ 4995 /* PORT_SRLEN Predefined. */ 4996 4997 /* PORT_INVEN Predefined. */ 4998 /* PORT_INVEN Predefined. */ 4999 5000 /* PORT_OPC Predefined. */ 5001 /* PORT_OPC Predefined. */ 5002 5003 /* PORT_ISC Predefined. */ 5004 /* PORT_ISC Predefined. */ 5005 5006 /* PORT.PIN4CTRL bit masks and bit positions */ 5007 /* PORT_SRLEN Predefined. */ 5008 /* PORT_SRLEN Predefined. */ 5009 5010 /* PORT_INVEN Predefined. */ 5011 /* PORT_INVEN Predefined. */ 5012 5013 /* PORT_OPC Predefined. */ 5014 /* PORT_OPC Predefined. */ 5015 5016 /* PORT_ISC Predefined. */ 5017 /* PORT_ISC Predefined. */ 5018 5019 /* PORT.PIN5CTRL bit masks and bit positions */ 5020 /* PORT_SRLEN Predefined. */ 5021 /* PORT_SRLEN Predefined. */ 5022 5023 /* PORT_INVEN Predefined. */ 5024 /* PORT_INVEN Predefined. */ 5025 5026 /* PORT_OPC Predefined. */ 5027 /* PORT_OPC Predefined. */ 5028 5029 /* PORT_ISC Predefined. */ 5030 /* PORT_ISC Predefined. */ 5031 5032 /* PORT.PIN6CTRL bit masks and bit positions */ 5033 /* PORT_SRLEN Predefined. */ 5034 /* PORT_SRLEN Predefined. */ 5035 5036 /* PORT_INVEN Predefined. */ 5037 /* PORT_INVEN Predefined. */ 5038 5039 /* PORT_OPC Predefined. */ 5040 /* PORT_OPC Predefined. */ 5041 5042 /* PORT_ISC Predefined. */ 5043 /* PORT_ISC Predefined. */ 5044 5045 /* PORT.PIN7CTRL bit masks and bit positions */ 5046 /* PORT_SRLEN Predefined. */ 5047 /* PORT_SRLEN Predefined. */ 5048 5049 /* PORT_INVEN Predefined. */ 5050 /* PORT_INVEN Predefined. */ 5051 5052 /* PORT_OPC Predefined. */ 5053 /* PORT_OPC Predefined. */ 5054 5055 /* PORT_ISC Predefined. */ 5056 /* PORT_ISC Predefined. */ 5057 5058 /* TC - 16-bit Timer/Counter With PWM */ 5059 /* TC0.CTRLA bit masks and bit positions */ 5060 #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 5061 #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ 5062 #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 5063 #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 5064 #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 5065 #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 5066 #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 5067 #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 5068 #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 5069 #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 5070 5071 /* TC0.CTRLB bit masks and bit positions */ 5072 #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ 5073 #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ 5074 5075 #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ 5076 #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ 5077 5078 #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 5079 #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 5080 5081 #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 5082 #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 5083 5084 #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 5085 #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ 5086 #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 5087 #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 5088 #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 5089 #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 5090 #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 5091 #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 5092 5093 /* TC0.CTRLC bit masks and bit positions */ 5094 #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ 5095 #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ 5096 5097 #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ 5098 #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ 5099 5100 #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 5101 #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ 5102 5103 #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 5104 #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ 5105 5106 /* TC0.CTRLD bit masks and bit positions */ 5107 #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ 5108 #define TC0_EVACT_gp 5 /* Event Action group position. */ 5109 #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 5110 #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ 5111 #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 5112 #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ 5113 #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 5114 #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ 5115 5116 #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ 5117 #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ 5118 5119 #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ 5120 #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ 5121 #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 5122 #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 5123 #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 5124 #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 5125 #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 5126 #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 5127 #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 5128 #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 5129 5130 /* TC0.CTRLE bit masks and bit positions */ 5131 #define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ 5132 #define TC0_BYTEM_gp 0 /* Byte Mode group position. */ 5133 #define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ 5134 #define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ 5135 #define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ 5136 #define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ 5137 5138 /* TC0.INTCTRLA bit masks and bit positions */ 5139 #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 5140 #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 5141 #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 5142 #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 5143 #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 5144 #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 5145 5146 #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 5147 #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 5148 #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 5149 #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 5150 #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 5151 #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 5152 5153 /* TC0.INTCTRLB bit masks and bit positions */ 5154 #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ 5155 #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ 5156 #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ 5157 #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ 5158 #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ 5159 #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ 5160 5161 #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ 5162 #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ 5163 #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ 5164 #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ 5165 #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ 5166 #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ 5167 5168 #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 5169 #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 5170 #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 5171 #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 5172 #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 5173 #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 5174 5175 #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 5176 #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 5177 #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 5178 #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 5179 #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 5180 #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 5181 5182 /* TC0.CTRLFCLR bit masks and bit positions */ 5183 #define TC0_CMD_gm 0x0C /* Command group mask. */ 5184 #define TC0_CMD_gp 2 /* Command group position. */ 5185 #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5186 #define TC0_CMD0_bp 2 /* Command bit 0 position. */ 5187 #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5188 #define TC0_CMD1_bp 3 /* Command bit 1 position. */ 5189 5190 #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ 5191 #define TC0_LUPD_bp 1 /* Lock Update bit position. */ 5192 5193 #define TC0_DIR_bm 0x01 /* Direction bit mask. */ 5194 #define TC0_DIR_bp 0 /* Direction bit position. */ 5195 5196 /* TC0.CTRLFSET bit masks and bit positions */ 5197 /* TC0_CMD Predefined. */ 5198 /* TC0_CMD Predefined. */ 5199 5200 /* TC0_LUPD Predefined. */ 5201 /* TC0_LUPD Predefined. */ 5202 5203 /* TC0_DIR Predefined. */ 5204 /* TC0_DIR Predefined. */ 5205 5206 /* TC0.CTRLGCLR bit masks and bit positions */ 5207 #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ 5208 #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ 5209 5210 #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ 5211 #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ 5212 5213 #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5214 #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5215 5216 #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5217 #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5218 5219 #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5220 #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5221 5222 /* TC0.CTRLGSET bit masks and bit positions */ 5223 /* TC0_CCDBV Predefined. */ 5224 /* TC0_CCDBV Predefined. */ 5225 5226 /* TC0_CCCBV Predefined. */ 5227 /* TC0_CCCBV Predefined. */ 5228 5229 /* TC0_CCBBV Predefined. */ 5230 /* TC0_CCBBV Predefined. */ 5231 5232 /* TC0_CCABV Predefined. */ 5233 /* TC0_CCABV Predefined. */ 5234 5235 /* TC0_PERBV Predefined. */ 5236 /* TC0_PERBV Predefined. */ 5237 5238 /* TC0.INTFLAGS bit masks and bit positions */ 5239 #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ 5240 #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ 5241 5242 #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ 5243 #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ 5244 5245 #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5246 #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5247 5248 #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5249 #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5250 5251 #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5252 #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5253 5254 #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5255 #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5256 5257 /* TC1.CTRLA bit masks and bit positions */ 5258 #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 5259 #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ 5260 #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 5261 #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 5262 #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 5263 #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 5264 #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 5265 #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 5266 #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 5267 #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 5268 5269 /* TC1.CTRLB bit masks and bit positions */ 5270 #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 5271 #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 5272 5273 #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 5274 #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 5275 5276 #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 5277 #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ 5278 #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 5279 #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 5280 #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 5281 #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 5282 #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 5283 #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 5284 5285 /* TC1.CTRLC bit masks and bit positions */ 5286 #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 5287 #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ 5288 5289 #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 5290 #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ 5291 5292 /* TC1.CTRLD bit masks and bit positions */ 5293 #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ 5294 #define TC1_EVACT_gp 5 /* Event Action group position. */ 5295 #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 5296 #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ 5297 #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 5298 #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ 5299 #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 5300 #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ 5301 5302 #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ 5303 #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ 5304 5305 #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ 5306 #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ 5307 #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 5308 #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 5309 #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 5310 #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 5311 #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 5312 #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 5313 #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 5314 #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 5315 5316 /* TC1.CTRLE bit masks and bit positions */ 5317 #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 5318 #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ 5319 5320 /* TC1.INTCTRLA bit masks and bit positions */ 5321 #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 5322 #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 5323 #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 5324 #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 5325 #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 5326 #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 5327 5328 #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 5329 #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 5330 #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 5331 #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 5332 #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 5333 #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 5334 5335 /* TC1.INTCTRLB bit masks and bit positions */ 5336 #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 5337 #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 5338 #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 5339 #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 5340 #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 5341 #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 5342 5343 #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 5344 #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 5345 #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 5346 #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 5347 #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 5348 #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 5349 5350 /* TC1.CTRLFCLR bit masks and bit positions */ 5351 #define TC1_CMD_gm 0x0C /* Command group mask. */ 5352 #define TC1_CMD_gp 2 /* Command group position. */ 5353 #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5354 #define TC1_CMD0_bp 2 /* Command bit 0 position. */ 5355 #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5356 #define TC1_CMD1_bp 3 /* Command bit 1 position. */ 5357 5358 #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ 5359 #define TC1_LUPD_bp 1 /* Lock Update bit position. */ 5360 5361 #define TC1_DIR_bm 0x01 /* Direction bit mask. */ 5362 #define TC1_DIR_bp 0 /* Direction bit position. */ 5363 5364 /* TC1.CTRLFSET bit masks and bit positions */ 5365 /* TC1_CMD Predefined. */ 5366 /* TC1_CMD Predefined. */ 5367 5368 /* TC1_LUPD Predefined. */ 5369 /* TC1_LUPD Predefined. */ 5370 5371 /* TC1_DIR Predefined. */ 5372 /* TC1_DIR Predefined. */ 5373 5374 /* TC1.CTRLGCLR bit masks and bit positions */ 5375 #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5376 #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5377 5378 #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5379 #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5380 5381 #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5382 #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5383 5384 /* TC1.CTRLGSET bit masks and bit positions */ 5385 /* TC1_CCBBV Predefined. */ 5386 /* TC1_CCBBV Predefined. */ 5387 5388 /* TC1_CCABV Predefined. */ 5389 /* TC1_CCABV Predefined. */ 5390 5391 /* TC1_PERBV Predefined. */ 5392 /* TC1_PERBV Predefined. */ 5393 5394 /* TC1.INTFLAGS bit masks and bit positions */ 5395 #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5396 #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5397 5398 #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5399 #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5400 5401 #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5402 #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5403 5404 #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5405 #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5406 5407 /* AWEX - Timer/Counter Advanced Waveform Extension */ 5408 /* AWEX.CTRL bit masks and bit positions */ 5409 #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ 5410 #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ 5411 5412 #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ 5413 #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ 5414 5415 #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ 5416 #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ 5417 5418 #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ 5419 #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ 5420 5421 #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ 5422 #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ 5423 5424 #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ 5425 #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ 5426 5427 /* AWEX.FDCTRL bit masks and bit positions */ 5428 #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ 5429 #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ 5430 5431 #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ 5432 #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ 5433 5434 #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ 5435 #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ 5436 #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ 5437 #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ 5438 #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ 5439 #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ 5440 5441 /* AWEX.STATUS bit masks and bit positions */ 5442 #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ 5443 #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ 5444 5445 #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ 5446 #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ 5447 5448 #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ 5449 #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ 5450 5451 /* AWEX.STATUSSET bit masks and bit positions */ 5452 /* AWEX_FDF Predefined. */ 5453 /* AWEX_FDF Predefined. */ 5454 5455 /* AWEX_DTHSBUFV Predefined. */ 5456 /* AWEX_DTHSBUFV Predefined. */ 5457 5458 /* AWEX_DTLSBUFV Predefined. */ 5459 /* AWEX_DTLSBUFV Predefined. */ 5460 5461 /* HIRES - Timer/Counter High-Resolution Extension */ 5462 /* HIRES.CTRLA bit masks and bit positions */ 5463 #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ 5464 #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ 5465 #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ 5466 #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ 5467 #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ 5468 #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ 5469 5470 /* USART - Universal Asynchronous Receiver-Transmitter */ 5471 /* USART.STATUS bit masks and bit positions */ 5472 #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ 5473 #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ 5474 5475 #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ 5476 #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ 5477 5478 #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ 5479 #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ 5480 5481 #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ 5482 #define USART_FERR_bp 4 /* Frame Error bit position. */ 5483 5484 #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ 5485 #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ 5486 5487 #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ 5488 #define USART_PERR_bp 2 /* Parity Error bit position. */ 5489 5490 #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ 5491 #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ 5492 5493 /* USART.CTRLA bit masks and bit positions */ 5494 #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ 5495 #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ 5496 #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ 5497 #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ 5498 #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ 5499 #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ 5500 5501 #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ 5502 #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ 5503 #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ 5504 #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ 5505 #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ 5506 #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ 5507 5508 #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ 5509 #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ 5510 #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ 5511 #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ 5512 #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ 5513 #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ 5514 5515 /* USART.CTRLB bit masks and bit positions */ 5516 #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ 5517 #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ 5518 5519 #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ 5520 #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ 5521 5522 #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ 5523 #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ 5524 5525 #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ 5526 #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ 5527 5528 #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ 5529 #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ 5530 5531 /* USART.CTRLC bit masks and bit positions */ 5532 #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ 5533 #define USART_CMODE_gp 6 /* Communication Mode group position. */ 5534 #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ 5535 #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ 5536 #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ 5537 #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ 5538 5539 #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ 5540 #define USART_PMODE_gp 4 /* Parity Mode group position. */ 5541 #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ 5542 #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ 5543 #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ 5544 #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ 5545 5546 #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ 5547 #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ 5548 5549 #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ 5550 #define USART_CHSIZE_gp 0 /* Character Size group position. */ 5551 #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ 5552 #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ 5553 #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ 5554 #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ 5555 #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ 5556 #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ 5557 5558 /* USART.BAUDCTRLA bit masks and bit positions */ 5559 #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ 5560 #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ 5561 #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ 5562 #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ 5563 #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ 5564 #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ 5565 #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ 5566 #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ 5567 #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ 5568 #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ 5569 #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ 5570 #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ 5571 #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ 5572 #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ 5573 #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ 5574 #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ 5575 #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ 5576 #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ 5577 5578 /* USART.BAUDCTRLB bit masks and bit positions */ 5579 #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ 5580 #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ 5581 #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ 5582 #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ 5583 #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ 5584 #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ 5585 #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ 5586 #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ 5587 #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ 5588 #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ 5589 5590 /* USART_BSEL Predefined. */ 5591 /* USART_BSEL Predefined. */ 5592 5593 /* SPI - Serial Peripheral Interface */ 5594 /* SPI.CTRL bit masks and bit positions */ 5595 #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ 5596 #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ 5597 5598 #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ 5599 #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ 5600 5601 #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ 5602 #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ 5603 5604 #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ 5605 #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ 5606 5607 #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ 5608 #define SPI_MODE_gp 2 /* SPI Mode group position. */ 5609 #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ 5610 #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ 5611 #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ 5612 #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ 5613 5614 #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ 5615 #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ 5616 #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ 5617 #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ 5618 #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ 5619 #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ 5620 5621 /* SPI.INTCTRL bit masks and bit positions */ 5622 #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ 5623 #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ 5624 #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 5625 #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 5626 #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 5627 #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 5628 5629 /* SPI.STATUS bit masks and bit positions */ 5630 #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ 5631 #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ 5632 5633 #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ 5634 #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ 5635 5636 /* IRCOM - IR Communication Module */ 5637 /* IRCOM.CTRL bit masks and bit positions */ 5638 #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ 5639 #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ 5640 #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ 5641 #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ 5642 #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ 5643 #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ 5644 #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ 5645 #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ 5646 #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ 5647 #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ 5648 5649 /* LCD - LCD Controller */ 5650 /* LCD.CTRLA bit masks and bit positions */ 5651 #define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ 5652 #define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ 5653 5654 #define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ 5655 #define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ 5656 5657 #define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ 5658 #define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ 5659 5660 #define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ 5661 #define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ 5662 5663 #define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ 5664 #define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ 5665 5666 #define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ 5667 #define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ 5668 5669 #define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ 5670 #define LCD_SEGON_bp 1 /* Segments On bit position. */ 5671 5672 #define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ 5673 #define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ 5674 5675 /* LCD.CTRLB bit masks and bit positions */ 5676 #define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ 5677 #define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ 5678 5679 #define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ 5680 #define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ 5681 #define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ 5682 #define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ 5683 #define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ 5684 #define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ 5685 #define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ 5686 #define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ 5687 5688 #define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ 5689 #define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ 5690 5691 #define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ 5692 #define LCD_DUTY_gp 0 /* Duty Select group position. */ 5693 #define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ 5694 #define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ 5695 #define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ 5696 #define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ 5697 5698 /* LCD.CTRLC bit masks and bit positions */ 5699 #define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ 5700 #define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ 5701 #define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ 5702 #define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ 5703 #define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ 5704 #define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ 5705 #define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ 5706 #define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ 5707 #define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ 5708 #define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ 5709 #define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ 5710 #define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ 5711 #define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ 5712 #define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ 5713 5714 /* LCD.INTCTRL bit masks and bit positions */ 5715 #define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ 5716 #define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ 5717 #define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ 5718 #define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ 5719 #define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ 5720 #define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ 5721 #define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ 5722 #define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ 5723 #define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ 5724 #define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ 5725 #define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ 5726 #define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ 5727 5728 #define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ 5729 #define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ 5730 #define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 5731 #define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 5732 #define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 5733 #define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 5734 5735 /* LCD.INTFLAG bit masks and bit positions */ 5736 #define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ 5737 #define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ 5738 5739 /* LCD.CTRLD bit masks and bit positions */ 5740 #define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ 5741 #define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ 5742 5743 #define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ 5744 #define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ 5745 #define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ 5746 #define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ 5747 #define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ 5748 #define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ 5749 5750 /* LCD.CTRLE bit masks and bit positions */ 5751 #define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ 5752 #define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ 5753 #define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ 5754 #define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ 5755 #define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ 5756 #define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ 5757 #define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ 5758 #define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ 5759 #define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ 5760 #define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ 5761 5762 #define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ 5763 #define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ 5764 #define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ 5765 #define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ 5766 #define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ 5767 #define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ 5768 #define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ 5769 #define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ 5770 #define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ 5771 #define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ 5772 5773 /* LCD.CTRLF bit masks and bit positions */ 5774 #define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ 5775 #define LCD_FCONT_gp 0 /* Fine Contrast group position. */ 5776 #define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ 5777 #define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ 5778 #define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ 5779 #define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ 5780 #define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ 5781 #define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ 5782 #define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ 5783 #define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ 5784 #define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ 5785 #define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ 5786 #define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ 5787 #define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ 5788 5789 /* LCD.CTRLG bit masks and bit positions */ 5790 #define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ 5791 #define LCD_TDG_gp 6 /* Type of Digit group position. */ 5792 #define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ 5793 #define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ 5794 #define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ 5795 #define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ 5796 5797 #define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ 5798 #define LCD_STSEG_gp 0 /* Start Segment group position. */ 5799 #define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ 5800 #define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ 5801 #define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ 5802 #define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ 5803 #define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ 5804 #define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ 5805 #define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ 5806 #define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ 5807 #define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ 5808 #define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ 5809 #define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ 5810 #define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ 5811 5812 /* LCD.CTRLH bit masks and bit positions */ 5813 #define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ 5814 #define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ 5815 5816 #define LCD_DCODE_gm 0x7F /* Display Code group mask. */ 5817 #define LCD_DCODE_gp 0 /* Display Code group position. */ 5818 #define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ 5819 #define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ 5820 #define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ 5821 #define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ 5822 #define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ 5823 #define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ 5824 #define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ 5825 #define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ 5826 #define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ 5827 #define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ 5828 #define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ 5829 #define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ 5830 #define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ 5831 #define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ 5832 5833 /* FUSE - Fuses and Lockbits */ 5834 /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ 5835 #define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ 5836 #define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ 5837 #define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ 5838 #define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ 5839 #define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ 5840 #define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ 5841 #define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ 5842 #define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ 5843 #define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ 5844 #define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ 5845 #define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ 5846 #define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ 5847 #define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ 5848 #define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ 5849 #define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ 5850 #define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ 5851 #define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ 5852 #define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ 5853 5854 /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ 5855 #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ 5856 #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ 5857 #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ 5858 #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ 5859 #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ 5860 #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ 5861 #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ 5862 #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ 5863 #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ 5864 #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ 5865 5866 #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ 5867 #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ 5868 #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ 5869 #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ 5870 #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ 5871 #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ 5872 #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ 5873 #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ 5874 #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ 5875 #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ 5876 5877 /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ 5878 #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ 5879 #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ 5880 5881 #define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ 5882 #define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ 5883 5884 #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ 5885 #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ 5886 #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ 5887 #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ 5888 #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ 5889 #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ 5890 5891 /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ 5892 #define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ 5893 #define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ 5894 5895 #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ 5896 #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ 5897 #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ 5898 #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ 5899 #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ 5900 #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ 5901 5902 #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ 5903 #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ 5904 5905 #define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ 5906 #define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ 5907 5908 /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ 5909 #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ 5910 #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ 5911 #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ 5912 #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ 5913 #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ 5914 #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ 5915 5916 #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ 5917 #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ 5918 5919 #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ 5920 #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ 5921 #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ 5922 #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ 5923 #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ 5924 #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ 5925 #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ 5926 #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ 5927 5928 /* LOCKBIT - Fuses and Lockbits */ 5929 /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ 5930 #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 5931 #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 5932 #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 5933 #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 5934 #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 5935 #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 5936 5937 #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 5938 #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 5939 #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 5940 #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 5941 #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 5942 #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 5943 5944 #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 5945 #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 5946 #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 5947 #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 5948 #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 5949 #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 5950 5951 #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ 5952 #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ 5953 #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 5954 #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ 5955 #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 5956 #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ 5957 5958 5959 5960 // Generic Port Pins 5961 5962 #define PIN0_bm 0x01 5963 #define PIN0_bp 0 5964 #define PIN1_bm 0x02 5965 #define PIN1_bp 1 5966 #define PIN2_bm 0x04 5967 #define PIN2_bp 2 5968 #define PIN3_bm 0x08 5969 #define PIN3_bp 3 5970 #define PIN4_bm 0x10 5971 #define PIN4_bp 4 5972 #define PIN5_bm 0x20 5973 #define PIN5_bp 5 5974 #define PIN6_bm 0x40 5975 #define PIN6_bp 6 5976 #define PIN7_bm 0x80 5977 #define PIN7_bp 7 5978 5979 /* ========== Interrupt Vector Definitions ========== */ 5980 /* Vector 0 is the reset vector */ 5981 5982 /* OSC interrupt vectors */ 5983 #define OSC_OSCF_vect_num 1 5984 #define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ 5985 5986 /* PORTC interrupt vectors */ 5987 #define PORTC_INT0_vect_num 2 5988 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ 5989 #define PORTC_INT1_vect_num 3 5990 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ 5991 5992 /* PORTR interrupt vectors */ 5993 #define PORTR_INT0_vect_num 4 5994 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ 5995 #define PORTR_INT1_vect_num 5 5996 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ 5997 5998 /* DMA interrupt vectors */ 5999 #define DMA_CH0_vect_num 6 6000 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ 6001 #define DMA_CH1_vect_num 7 6002 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ 6003 6004 /* RTC interrupt vectors */ 6005 #define RTC_OVF_vect_num 10 6006 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ 6007 #define RTC_COMP_vect_num 11 6008 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ 6009 6010 /* TWIC interrupt vectors */ 6011 #define TWIC_TWIS_vect_num 12 6012 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ 6013 #define TWIC_TWIM_vect_num 13 6014 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ 6015 6016 /* TCC0 interrupt vectors */ 6017 #define TCC0_OVF_vect_num 14 6018 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ 6019 #define TCC0_ERR_vect_num 15 6020 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ 6021 #define TCC0_CCA_vect_num 16 6022 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ 6023 #define TCC0_CCB_vect_num 17 6024 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ 6025 #define TCC0_CCC_vect_num 18 6026 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ 6027 #define TCC0_CCD_vect_num 19 6028 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ 6029 6030 /* TCC1 interrupt vectors */ 6031 #define TCC1_OVF_vect_num 20 6032 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ 6033 #define TCC1_ERR_vect_num 21 6034 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ 6035 #define TCC1_CCA_vect_num 22 6036 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ 6037 #define TCC1_CCB_vect_num 23 6038 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ 6039 6040 /* SPIC interrupt vectors */ 6041 #define SPIC_INT_vect_num 24 6042 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ 6043 6044 /* USARTC0 interrupt vectors */ 6045 #define USARTC0_RXC_vect_num 25 6046 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ 6047 #define USARTC0_DRE_vect_num 26 6048 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ 6049 #define USARTC0_TXC_vect_num 27 6050 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ 6051 6052 /* USB interrupt vectors */ 6053 #define USB_BUSEVENT_vect_num 31 6054 #define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ 6055 #define USB_TRNCOMPL_vect_num 32 6056 #define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ 6057 6058 /* LCD interrupt vectors */ 6059 #define LCD_INT_vect_num 35 6060 #define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ 6061 6062 /* AES interrupt vectors */ 6063 #define AES_INT_vect_num 36 6064 #define AES_INT_vect _VECTOR(36) /* AES Interrupt */ 6065 6066 /* NVM interrupt vectors */ 6067 #define NVM_EE_vect_num 37 6068 #define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ 6069 #define NVM_SPM_vect_num 38 6070 #define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ 6071 6072 /* PORTB interrupt vectors */ 6073 #define PORTB_INT0_vect_num 39 6074 #define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ 6075 #define PORTB_INT1_vect_num 40 6076 #define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ 6077 6078 /* ACB interrupt vectors */ 6079 #define ACB_AC0_vect_num 41 6080 #define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ 6081 #define ACB_AC1_vect_num 42 6082 #define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ 6083 #define ACB_ACW_vect_num 43 6084 #define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ 6085 6086 /* ADCB interrupt vectors */ 6087 #define ADCB_CH0_vect_num 44 6088 #define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ 6089 6090 /* PORTD interrupt vectors */ 6091 #define PORTD_INT0_vect_num 48 6092 #define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ 6093 #define PORTD_INT1_vect_num 49 6094 #define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ 6095 6096 /* PORTG interrupt vectors */ 6097 #define PORTG_INT0_vect_num 50 6098 #define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ 6099 #define PORTG_INT1_vect_num 51 6100 #define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ 6101 6102 /* PORTM interrupt vectors */ 6103 #define PORTM_INT0_vect_num 52 6104 #define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ 6105 #define PORTM_INT1_vect_num 53 6106 #define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ 6107 6108 #define _VECTOR_SIZE 4 /* Size of individual vector. */ 6109 #define _VECTORS_SIZE (54 * _VECTOR_SIZE) 6110 6111 6112 /* ========== Constants ========== */ 6113 6114 #define PROGMEM_START (0x0000) 6115 #define PROGMEM_SIZE (139264) 6116 #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) 6117 6118 #define APP_SECTION_START (0x0000) 6119 #define APP_SECTION_SIZE (131072) 6120 #define APP_SECTION_PAGE_SIZE (256) 6121 #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) 6122 6123 #define APPTABLE_SECTION_START (0x1E000) 6124 #define APPTABLE_SECTION_SIZE (8192) 6125 #define APPTABLE_SECTION_PAGE_SIZE (256) 6126 #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) 6127 6128 #define BOOT_SECTION_START (0x20000) 6129 #define BOOT_SECTION_SIZE (8192) 6130 #define BOOT_SECTION_PAGE_SIZE (256) 6131 #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) 6132 6133 #define DATAMEM_START (0x0000) 6134 #define DATAMEM_SIZE (16384) 6135 #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) 6136 6137 #define IO_START (0x0000) 6138 #define IO_SIZE (4096) 6139 #define IO_PAGE_SIZE (0) 6140 #define IO_END (IO_START + IO_SIZE - 1) 6141 6142 #define MAPPED_EEPROM_START (0x1000) 6143 #define MAPPED_EEPROM_SIZE (2048) 6144 #define MAPPED_EEPROM_PAGE_SIZE (0) 6145 #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) 6146 6147 #define INTERNAL_SRAM_START (0x2000) 6148 #define INTERNAL_SRAM_SIZE (8192) 6149 #define INTERNAL_SRAM_PAGE_SIZE (0) 6150 #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) 6151 6152 #define EEPROM_START (0x0000) 6153 #define EEPROM_SIZE (2048) 6154 #define EEPROM_PAGE_SIZE (32) 6155 #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) 6156 6157 #define SIGNATURES_START (0x0000) 6158 #define SIGNATURES_SIZE (3) 6159 #define SIGNATURES_PAGE_SIZE (0) 6160 #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) 6161 6162 #define FUSES_START (0x0000) 6163 #define FUSES_SIZE (6) 6164 #define FUSES_PAGE_SIZE (0) 6165 #define FUSES_END (FUSES_START + FUSES_SIZE - 1) 6166 6167 #define LOCKBITS_START (0x0000) 6168 #define LOCKBITS_SIZE (1) 6169 #define LOCKBITS_PAGE_SIZE (0) 6170 #define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) 6171 6172 #define USER_SIGNATURES_START (0x0000) 6173 #define USER_SIGNATURES_SIZE (256) 6174 #define USER_SIGNATURES_PAGE_SIZE (256) 6175 #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) 6176 6177 #define PROD_SIGNATURES_START (0x0000) 6178 #define PROD_SIGNATURES_SIZE (52) 6179 #define PROD_SIGNATURES_PAGE_SIZE (256) 6180 #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) 6181 6182 #define FLASHSTART PROGMEM_START 6183 #define FLASHEND PROGMEM_END 6184 #define SPM_PAGESIZE 256 6185 #define RAMSTART INTERNAL_SRAM_START 6186 #define RAMSIZE INTERNAL_SRAM_SIZE 6187 #define RAMEND INTERNAL_SRAM_END 6188 #define E2END EEPROM_END 6189 #define E2PAGESIZE EEPROM_PAGE_SIZE 6190 6191 6192 /* ========== Fuses ========== */ 6193 #define FUSE_MEMORY_SIZE 6 6194 6195 /* Fuse Byte 0 */ 6196 #define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ 6197 #define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ 6198 #define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ 6199 #define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ 6200 #define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ 6201 #define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ 6202 #define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ 6203 #define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ 6204 #define FUSE0_DEFAULT (0xFF) 6205 6206 /* Fuse Byte 1 */ 6207 #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ 6208 #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ 6209 #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ 6210 #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ 6211 #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ 6212 #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ 6213 #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ 6214 #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ 6215 #define FUSE1_DEFAULT (0xFF) 6216 6217 /* Fuse Byte 2 */ 6218 #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ 6219 #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ 6220 #define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ 6221 #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ 6222 #define FUSE2_DEFAULT (0xFF) 6223 6224 /* Fuse Byte 3 Reserved */ 6225 6226 /* Fuse Byte 4 */ 6227 #define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ 6228 #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ 6229 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ 6230 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ 6231 #define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ 6232 #define FUSE4_DEFAULT (0xFF) 6233 6234 /* Fuse Byte 5 */ 6235 #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ 6236 #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ 6237 #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ 6238 #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ 6239 #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ 6240 #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ 6241 #define FUSE5_DEFAULT (0xFF) 6242 6243 /* ========== Lock Bits ========== */ 6244 #define __LOCK_BITS_EXIST 6245 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST 6246 #define __BOOT_LOCK_APPLICATION_BITS_EXIST 6247 #define __BOOT_LOCK_BOOT_BITS_EXIST 6248 6249 /* ========== Signature ========== */ 6250 #define SIGNATURE_0 0x1E 6251 #define SIGNATURE_1 0x97 6252 #define SIGNATURE_2 0x4B 6253 6254 /* ========== Power Reduction Condition Definitions ========== */ 6255 6256 /* PR.PRGEN */ 6257 #define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) 6258 #define __AVR_HAVE_PRGEN_LCD 6259 #define __AVR_HAVE_PRGEN_USB 6260 #define __AVR_HAVE_PRGEN_AES 6261 #define __AVR_HAVE_PRGEN_RTC 6262 #define __AVR_HAVE_PRGEN_EVSYS 6263 #define __AVR_HAVE_PRGEN_DMA 6264 6265 /* PR.PRPA */ 6266 #define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) 6267 #define __AVR_HAVE_PRPA_ADC 6268 #define __AVR_HAVE_PRPA_AC 6269 6270 /* PR.PRPB */ 6271 #define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) 6272 #define __AVR_HAVE_PRPB_ADC 6273 #define __AVR_HAVE_PRPB_AC 6274 6275 /* PR.PRPC */ 6276 #define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 6277 #define __AVR_HAVE_PRPC_TWI 6278 #define __AVR_HAVE_PRPC_USART0 6279 #define __AVR_HAVE_PRPC_SPI 6280 #define __AVR_HAVE_PRPC_HIRES 6281 #define __AVR_HAVE_PRPC_TC1 6282 #define __AVR_HAVE_PRPC_TC0 6283 6284 /* PR.PRPE */ 6285 #define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) 6286 #define __AVR_HAVE_PRPE_USART0 6287 #define __AVR_HAVE_PRPE_TC0 6288 6289 6290 #endif /* #ifdef _AVR_ATXMEGA128B3_H_INCLUDED */ 6291 6292