1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2005-01-11 10:30 ******* Source: AT90S1200.xml *********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "1200def.inc" 8;* Title : Register/Bit Definitions for the AT90S1200 9;* Date : 2005-01-11 10;* Version : 2.14 11;* Support E-mail : avr@atmel.com 12;* Target MCU : AT90S1200 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _1200DEF_INC_ 41#define _1200DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device AT90S1200 48#pragma AVRPART ADMIN PART_NAME AT90S1200 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x90 51.equ SIGNATURE_002 = 0x01 52 53#pragma AVRPART CORE CORE_VERSION V0 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ SREG = 0x3f 61.equ GIMSK = 0x3b 62.equ TIMSK = 0x39 63.equ TIFR = 0x38 64.equ MCUCR = 0x35 65.equ TCCR0 = 0x33 66.equ TCNT0 = 0x32 67.equ WDTCR = 0x21 68.equ EEAR = 0x1e 69.equ EEDR = 0x1d 70.equ EECR = 0x1c 71.equ PORTB = 0x18 72.equ DDRB = 0x17 73.equ PINB = 0x16 74.equ PORTD = 0x12 75.equ DDRD = 0x11 76.equ PIND = 0x10 77.equ ACSR = 0x08 78 79 80; ***** BIT DEFINITIONS ************************************************** 81 82; ***** TIMER_COUNTER_0 ************** 83; TIMSK - Timer/Counter Interrupt Mask Register 84.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable 85 86; TIFR - Timer/Counter Interrupt Flag register 87.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag 88 89; TCCR0 - Timer/Counter0 Control Register 90.equ CS00 = 0 ; Clock Select0 bit 0 91.equ CS01 = 1 ; Clock Select0 bit 1 92.equ CS02 = 2 ; Clock Select0 bit 2 93 94; TCNT0 - Timer Counter 0 95.equ TCNT00 = 0 ; Timer Counter 0 bit 0 96.equ TCNT01 = 1 ; Timer Counter 0 bit 1 97.equ TCNT02 = 2 ; Timer Counter 0 bit 2 98.equ TCNT03 = 3 ; Timer Counter 0 bit 3 99.equ TCNT04 = 4 ; Timer Counter 0 bit 4 100.equ TCNT05 = 5 ; Timer Counter 0 bit 5 101.equ TCNT06 = 6 ; Timer Counter 0 bit 6 102.equ TCNT07 = 7 ; Timer Counter 0 bit 7 103 104 105; ***** WATCHDOG ********************* 106; WDTCR - Watchdog Timer Control Register 107.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 108.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 109.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 110.equ WDE = 3 ; Watch Dog Enable 111 112 113; ***** PORTB ************************ 114; PORTB - Port B Data Register 115.equ PORTB0 = 0 ; Port B Data Register bit 0 116.equ PB0 = 0 ; For compatibility 117.equ PORTB1 = 1 ; Port B Data Register bit 1 118.equ PB1 = 1 ; For compatibility 119.equ PORTB2 = 2 ; Port B Data Register bit 2 120.equ PB2 = 2 ; For compatibility 121.equ PORTB3 = 3 ; Port B Data Register bit 3 122.equ PB3 = 3 ; For compatibility 123.equ PORTB4 = 4 ; Port B Data Register bit 4 124.equ PB4 = 4 ; For compatibility 125.equ PORTB5 = 5 ; Port B Data Register bit 5 126.equ PB5 = 5 ; For compatibility 127.equ PORTB6 = 6 ; Port B Data Register bit 6 128.equ PB6 = 6 ; For compatibility 129.equ PORTB7 = 7 ; Port B Data Register bit 7 130.equ PB7 = 7 ; For compatibility 131 132; DDRB - Port B Data Direction Register 133.equ DDB0 = 0 ; Port B Data Direction Register bit 0 134.equ DDB1 = 1 ; Port B Data Direction Register bit 1 135.equ DDB2 = 2 ; Port B Data Direction Register bit 2 136.equ DDB3 = 3 ; Port B Data Direction Register bit 3 137.equ DDB4 = 4 ; Port B Data Direction Register bit 4 138.equ DDB5 = 5 ; Port B Data Direction Register bit 5 139.equ DDB6 = 6 ; Port B Data Direction Register bit 6 140.equ DDB7 = 7 ; Port B Data Direction Register bit 7 141 142; PINB - Port B Input Pins 143.equ PINB0 = 0 ; Port B Input Pins bit 0 144.equ PINB1 = 1 ; Port B Input Pins bit 1 145.equ PINB2 = 2 ; Port B Input Pins bit 2 146.equ PINB3 = 3 ; Port B Input Pins bit 3 147.equ PINB4 = 4 ; Port B Input Pins bit 4 148.equ PINB5 = 5 ; Port B Input Pins bit 5 149.equ PINB6 = 6 ; Port B Input Pins bit 6 150.equ PINB7 = 7 ; Port B Input Pins bit 7 151 152 153; ***** PORTD ************************ 154; PORTD - Data Register, Port D 155.equ PORTD0 = 0 ; 156.equ PD0 = 0 ; For compatibility 157.equ PORTD1 = 1 ; 158.equ PD1 = 1 ; For compatibility 159.equ PORTD2 = 2 ; 160.equ PD2 = 2 ; For compatibility 161.equ PORTD3 = 3 ; 162.equ PD3 = 3 ; For compatibility 163.equ PORTD4 = 4 ; 164.equ PD4 = 4 ; For compatibility 165.equ PORTD5 = 5 ; 166.equ PD5 = 5 ; For compatibility 167.equ PORTD6 = 6 ; 168.equ PD6 = 6 ; For compatibility 169 170; DDRD 171.equ DDD0 = 0 ; 172.equ DDD1 = 1 ; 173.equ DDD2 = 2 ; 174.equ DDD3 = 3 ; 175.equ DDD4 = 4 ; 176.equ DDD5 = 5 ; 177.equ DDD6 = 6 ; 178 179; PIND - Input Pins, Port D 180.equ PIND0 = 0 ; 181.equ PIND1 = 1 ; 182.equ PIND2 = 2 ; 183.equ PIND3 = 3 ; 184.equ PIND4 = 4 ; 185.equ PIND5 = 5 ; 186.equ PIND6 = 6 ; 187 188 189; ***** ANALOG_COMPARATOR ************ 190; ACSR - Analog Comparator Control And Status Register 191.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 192.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 193.equ ACIE = 3 ; Analog Comparator Interrupt Enable 194.equ ACI = 4 ; Analog Comparator Interrupt Flag 195.equ ACO = 5 ; Analog Comparator Output 196.equ ACD = 7 ; Analog Comparator Disable 197 198 199; ***** CPU ************************** 200; SREG - Status Register 201.equ SREG_C = 0 ; Carry Flag 202.equ SREG_Z = 1 ; Zero Flag 203.equ SREG_N = 2 ; Negative Flag 204.equ SREG_V = 3 ; Two's Complement Overflow Flag 205.equ SREG_S = 4 ; Sign Bit 206.equ SREG_H = 5 ; Half Carry Flag 207.equ SREG_T = 6 ; Bit Copy Storage 208.equ SREG_I = 7 ; Global Interrupt Enable 209 210; MCUCR - MCU Control Register 211.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 212.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 213.equ SM = 4 ; Sleep Mode 214.equ SE = 5 ; Sleep Enable 215 216 217; ***** EXTERNAL_INTERRUPT *********** 218; GIMSK - General Interrupt Mask Register 219.equ INT0 = 6 ; External Interrupt Request 0 Enable 220 221 222; ***** EEPROM *********************** 223; EEAR - EEPROM Read/Write Access 224.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 225.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 226.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 227.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 228.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 229.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 230.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 231 232; EEDR - EEPROM Data Register 233.equ EEDR0 = 0 ; EEPROM Data Register bit 0 234.equ EEDR1 = 1 ; EEPROM Data Register bit 1 235.equ EEDR2 = 2 ; EEPROM Data Register bit 2 236.equ EEDR3 = 3 ; EEPROM Data Register bit 3 237.equ EEDR4 = 4 ; EEPROM Data Register bit 4 238.equ EEDR5 = 5 ; EEPROM Data Register bit 5 239.equ EEDR6 = 6 ; EEPROM Data Register bit 6 240.equ EEDR7 = 7 ; EEPROM Data Register bit 7 241 242; EECR - EEPROM Control Register 243.equ EERE = 0 ; EEPROM Read Enable 244.equ EEWE = 1 ; EEPROM Write Enable 245 246 247 248; ***** LOCKSBITS ******************************************************** 249.equ LB1 = 0 ; Lockbit 250.equ LB2 = 1 ; Lockbit 251 252 253; ***** FUSES ************************************************************ 254; LOW fuse bits 255 256 257 258; ***** CPU REGISTER DEFINITIONS ***************************************** 259.def XH = r27 260.def XL = r26 261.def YH = r29 262.def YL = r28 263.def ZH = r31 264.def ZL = r30 265 266 267 268; ***** DATA MEMORY DECLARATIONS ***************************************** 269.equ FLASHEND = 0x01ff ; Note: Word address 270.equ IOEND = 0x003f 271.equ SRAM_SIZE = 0 272.equ RAMEND = 0x0000 273.equ XRAMEND = 0x0000 274.equ E2END = 0x003f 275.equ EEPROMEND = 0x003f 276.equ EEADRBITS = 6 277#pragma AVRPART MEMORY PROG_FLASH 1024 278#pragma AVRPART MEMORY EEPROM 64 279#pragma AVRPART MEMORY INT_SRAM SIZE 0 280#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0 281 282 283 284 285 286; ***** INTERRUPT VECTORS ************************************************ 287.equ INT0addr = 0x0001 ; External Interrupt 0 288.equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow 289.equ ACIaddr = 0x0003 ; Analog Comparator 290 291.equ INT_VECTORS_SIZE = 4 ; size in words 292 293#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break 294 295#endif /* _1200DEF_INC_ */ 296 297; ***** END OF FILE ****************************************************** 298