1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2005-01-11 10:30 ******* Source: ATmega169.xml *********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "m169def.inc" 8;* Title : Register/Bit Definitions for the ATmega169 9;* Date : 2005-01-11 10;* Version : 2.14 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATmega169 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _M169DEF_INC_ 41#define _M169DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATmega169 48#pragma AVRPART ADMIN PART_NAME ATmega169 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x94 51.equ SIGNATURE_002 = 0x05 52 53#pragma AVRPART CORE CORE_VERSION V2E 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ LCDDR18 = 0xfe ; MEMORY MAPPED 61.equ LCDDR17 = 0xfd ; MEMORY MAPPED 62.equ LCDDR16 = 0xfc ; MEMORY MAPPED 63.equ LCDDR15 = 0xfb ; MEMORY MAPPED 64.equ LCDDR13 = 0xf9 ; MEMORY MAPPED 65.equ LCDDR12 = 0xf8 ; MEMORY MAPPED 66.equ LCDDR11 = 0xf7 ; MEMORY MAPPED 67.equ LCDDR10 = 0xf6 ; MEMORY MAPPED 68.equ LCDDR8 = 0xf4 ; MEMORY MAPPED 69.equ LCDDR7 = 0xf3 ; MEMORY MAPPED 70.equ LCDDR6 = 0xf2 ; MEMORY MAPPED 71.equ LCDDR5 = 0xf1 ; MEMORY MAPPED 72.equ LCDDR3 = 0xef ; MEMORY MAPPED 73.equ LCDDR2 = 0xee ; MEMORY MAPPED 74.equ LCDDR1 = 0xed ; MEMORY MAPPED 75.equ LCDDR0 = 0xec ; MEMORY MAPPED 76.equ LCDCCR = 0xe7 ; MEMORY MAPPED 77.equ LCDFRR = 0xe6 ; MEMORY MAPPED 78.equ LCDCRB = 0xe5 ; MEMORY MAPPED 79.equ LCDCRA = 0xe4 ; MEMORY MAPPED 80.equ UDR = 0xc6 ; MEMORY MAPPED 81.equ UBRRH = 0xc5 ; MEMORY MAPPED 82.equ UBRRL = 0xc4 ; MEMORY MAPPED 83.equ UCSRC = 0xc2 ; MEMORY MAPPED 84.equ UCSRB = 0xc1 ; MEMORY MAPPED 85.equ UCSRA = 0xc0 ; MEMORY MAPPED 86.equ USIDR = 0xba ; MEMORY MAPPED 87.equ USISR = 0xb9 ; MEMORY MAPPED 88.equ USICR = 0xb8 ; MEMORY MAPPED 89.equ ASSR = 0xb6 ; MEMORY MAPPED 90.equ OCR2A = 0xb3 ; MEMORY MAPPED 91.equ TCNT2 = 0xb2 ; MEMORY MAPPED 92.equ TCCR2B = 0xb1 ; MEMORY MAPPED 93.equ TCCR2A = 0xb0 ; MEMORY MAPPED 94.equ OCR1BH = 0x8b ; MEMORY MAPPED 95.equ OCR1BL = 0x8a ; MEMORY MAPPED 96.equ OCR1AH = 0x89 ; MEMORY MAPPED 97.equ OCR1AL = 0x88 ; MEMORY MAPPED 98.equ ICR1H = 0x87 ; MEMORY MAPPED 99.equ ICR1L = 0x86 ; MEMORY MAPPED 100.equ TCNT1H = 0x85 ; MEMORY MAPPED 101.equ TCNT1L = 0x84 ; MEMORY MAPPED 102.equ TCCR1C = 0x82 ; MEMORY MAPPED 103.equ TCCR1B = 0x81 ; MEMORY MAPPED 104.equ TCCR1A = 0x80 ; MEMORY MAPPED 105.equ DIDR1 = 0x7f ; MEMORY MAPPED 106.equ DIDR0 = 0x7e ; MEMORY MAPPED 107.equ ADMUX = 0x7c ; MEMORY MAPPED 108.equ ADCSRB = 0x7b ; MEMORY MAPPED 109.equ ADCSRA = 0x7a ; MEMORY MAPPED 110.equ ADCH = 0x79 ; MEMORY MAPPED 111.equ ADCL = 0x78 ; MEMORY MAPPED 112.equ TIMSK2 = 0x70 ; MEMORY MAPPED 113.equ TIMSK1 = 0x6f ; MEMORY MAPPED 114.equ TIMSK0 = 0x6e ; MEMORY MAPPED 115.equ PCMSK1 = 0x6c ; MEMORY MAPPED 116.equ PCMSK0 = 0x6b ; MEMORY MAPPED 117.equ EICRA = 0x69 ; MEMORY MAPPED 118.equ OSCCAL = 0x66 ; MEMORY MAPPED 119.equ PRR = 0x64 ; MEMORY MAPPED 120.equ CLKPR = 0x61 ; MEMORY MAPPED 121.equ WDTCR = 0x60 ; MEMORY MAPPED 122.equ SREG = 0x3f 123.equ SPH = 0x3e 124.equ SPL = 0x3d 125.equ SPMCSR = 0x37 126.equ MCUCR = 0x35 127.equ MCUSR = 0x34 128.equ SMCR = 0x33 129.equ OCDR = 0x31 130.equ ACSR = 0x30 131.equ SPDR = 0x2e 132.equ SPSR = 0x2d 133.equ SPCR = 0x2c 134.equ GPIOR2 = 0x2b 135.equ GPIOR1 = 0x2a 136.equ OCR0A = 0x27 137.equ TCNT0 = 0x26 138.equ TCCR0A = 0x24 139.equ GTCCR = 0x23 140.equ EEARH = 0x22 141.equ EEARL = 0x21 142.equ EEDR = 0x20 143.equ EECR = 0x1f 144.equ GPIOR0 = 0x1e 145.equ EIMSK = 0x1d 146.equ EIFR = 0x1c 147.equ TIFR2 = 0x17 148.equ TIFR1 = 0x16 149.equ TIFR0 = 0x15 150.equ PORTG = 0x14 151.equ DDRG = 0x13 152.equ PING = 0x12 153.equ PORTF = 0x11 154.equ DDRF = 0x10 155.equ PINF = 0x0f 156.equ PORTE = 0x0e 157.equ DDRE = 0x0d 158.equ PINE = 0x0c 159.equ PORTD = 0x0b 160.equ DDRD = 0x0a 161.equ PIND = 0x09 162.equ PORTC = 0x08 163.equ DDRC = 0x07 164.equ PINC = 0x06 165.equ PORTB = 0x05 166.equ DDRB = 0x04 167.equ PINB = 0x03 168.equ PORTA = 0x02 169.equ DDRA = 0x01 170.equ PINA = 0x00 171 172 173; ***** BIT DEFINITIONS ************************************************** 174 175; ***** TIMER_COUNTER_0 ************** 176; TCCR0A - Timer/Counter0 Control Register 177.equ CS00 = 0 ; Clock Select 1 178.equ CS01 = 1 ; Clock Select 1 179.equ CS02 = 2 ; Clock Select 2 180.equ WGM01 = 3 ; Waveform Generation Mode 1 181.equ COM0A0 = 4 ; Compare match Output Mode 0 182.equ COM0A1 = 5 ; Compare Match Output Mode 1 183.equ WGM00 = 6 ; Waveform Generation Mode 0 184.equ FOC0A = 7 ; Force Output Compare 185 186; TCNT0 - Timer/Counter0 187.equ TCNT0_0 = 0 ; 188.equ TCNT0_1 = 1 ; 189.equ TCNT0_2 = 2 ; 190.equ TCNT0_3 = 3 ; 191.equ TCNT0_4 = 4 ; 192.equ TCNT0_5 = 5 ; 193.equ TCNT0_6 = 6 ; 194.equ TCNT0_7 = 7 ; 195 196; OCR0A - Timer/Counter0 Output Compare Register 197.equ OCR0A0 = 0 ; 198.equ OCR0A1 = 1 ; 199.equ OCR0A2 = 2 ; 200.equ OCR0A3 = 3 ; 201.equ OCR0A4 = 4 ; 202.equ OCR0A5 = 5 ; 203.equ OCR0A6 = 6 ; 204.equ OCR0A7 = 7 ; 205 206; TIMSK0 - Timer/Counter0 Interrupt Mask Register 207.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 208.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable 209 210; TIFR0 - Timer/Counter0 Interrupt Flag register 211.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 212.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 213 214; GTCCR - General Timer/Control Register 215.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 216.equ PSR10 = PSR310 ; For compatibility 217.equ PSR0 = PSR310 ; For compatibility 218.equ PSR1 = PSR310 ; For compatibility 219.equ PSR3 = PSR310 ; For compatibility 220.equ TSM = 7 ; Timer/Counter Synchronization Mode 221 222 223; ***** TIMER_COUNTER_1 ************** 224; TIMSK1 - Timer/Counter1 Interrupt Mask Register 225.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 226.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable 227.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable 228.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 229 230; TIFR1 - Timer/Counter1 Interrupt Flag register 231.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 232.equ OCF1A = 1 ; Output Compare Flag 1A 233.equ OCF1B = 2 ; Output Compare Flag 1B 234.equ ICF1 = 5 ; Input Capture Flag 1 235 236; TCCR1A - Timer/Counter1 Control Register A 237.equ WGM10 = 0 ; Waveform Generation Mode 238.equ WGM11 = 1 ; Waveform Generation Mode 239.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 240.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 241.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 242.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 243 244; TCCR1B - Timer/Counter1 Control Register B 245.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 246.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 247.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 248.equ WGM12 = 3 ; Waveform Generation Mode 249.equ WGM13 = 4 ; Waveform Generation Mode 250.equ ICES1 = 6 ; Input Capture 1 Edge Select 251.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 252 253; TCCR1C - Timer/Counter 1 Control Register C 254.equ FOC1B = 6 ; Force Output Compare 1B 255.equ FOC1A = 7 ; Force Output Compare 1A 256 257 258; ***** TIMER_COUNTER_2 ************** 259; TIMSK2 - Timer/Counter2 Interrupt Mask register 260.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable 261.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable 262 263; TIFR2 - Timer/Counter2 Interrupt Flag Register 264.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag 265.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 266 267; TCCR2A - Timer/Counter2 Control Register 268.equ CS20 = 0 ; Clock Select bit 0 269.equ CS21 = 1 ; Clock Select bit 1 270.equ CS22 = 2 ; Clock Select bit 2 271.equ WGM21 = 3 ; Waveform Generation Mode 272.equ COM2A0 = 4 ; Compare Output Mode bit 0 273.equ COM2A1 = 5 ; Compare Output Mode bit 1 274.equ WGM20 = 6 ; Waveform Generation Mode 275.equ FOC2A = 7 ; Force Output Compare A 276 277; TCNT2 - Timer/Counter2 278.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 279.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 280.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 281.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 282.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 283.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 284.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 285.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 286 287; OCR2A - Timer/Counter2 Output Compare Register 288.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 289.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 290.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 291.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 292.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 293.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 294.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 295.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 296 297; GTCCR - General Timer/Counter Control Register 298.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 299 300; ASSR - Asynchronous Status Register 301.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy 302.equ OCR2UB = 1 ; Output Compare Register2 Update Busy 303.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy 304.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 305.equ EXCLK = 4 ; Enable External Clock Interrupt 306 307 308; ***** WATCHDOG ********************* 309; WDTCR - Watchdog Timer Control Register 310.equ WDTCSR = WDTCR ; For compatibility 311.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 312.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 313.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 314.equ WDE = 3 ; Watch Dog Enable 315.equ WDCE = 4 ; Watchdog Change Enable 316.equ WDTOE = WDCE ; For compatibility 317 318 319; ***** EEPROM *********************** 320; EEDR - EEPROM Data Register 321.equ EEDR0 = 0 ; EEPROM Data Register bit 0 322.equ EEDR1 = 1 ; EEPROM Data Register bit 1 323.equ EEDR2 = 2 ; EEPROM Data Register bit 2 324.equ EEDR3 = 3 ; EEPROM Data Register bit 3 325.equ EEDR4 = 4 ; EEPROM Data Register bit 4 326.equ EEDR5 = 5 ; EEPROM Data Register bit 5 327.equ EEDR6 = 6 ; EEPROM Data Register bit 6 328.equ EEDR7 = 7 ; EEPROM Data Register bit 7 329 330; EECR - EEPROM Control Register 331.equ EERE = 0 ; EEPROM Read Enable 332.equ EEWE = 1 ; EEPROM Write Enable 333.equ EEMWE = 2 ; EEPROM Master Write Enable 334.equ EEWEE = EEMWE ; For compatibility 335.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 336 337 338; ***** SPI ************************** 339; SPDR - SPI Data Register 340.equ SPDR0 = 0 ; SPI Data Register bit 0 341.equ SPDR1 = 1 ; SPI Data Register bit 1 342.equ SPDR2 = 2 ; SPI Data Register bit 2 343.equ SPDR3 = 3 ; SPI Data Register bit 3 344.equ SPDR4 = 4 ; SPI Data Register bit 4 345.equ SPDR5 = 5 ; SPI Data Register bit 5 346.equ SPDR6 = 6 ; SPI Data Register bit 6 347.equ SPDR7 = 7 ; SPI Data Register bit 7 348 349; SPSR - SPI Status Register 350.equ SPI2X = 0 ; Double SPI Speed Bit 351.equ WCOL = 6 ; Write Collision Flag 352.equ SPIF = 7 ; SPI Interrupt Flag 353 354; SPCR - SPI Control Register 355.equ SPR0 = 0 ; SPI Clock Rate Select 0 356.equ SPR1 = 1 ; SPI Clock Rate Select 1 357.equ CPHA = 2 ; Clock Phase 358.equ CPOL = 3 ; Clock polarity 359.equ MSTR = 4 ; Master/Slave Select 360.equ DORD = 5 ; Data Order 361.equ SPE = 6 ; SPI Enable 362.equ SPIE = 7 ; SPI Interrupt Enable 363 364 365; ***** PORTA ************************ 366; PORTA - Port A Data Register 367.equ PORTA0 = 0 ; Port A Data Register bit 0 368.equ PA0 = 0 ; For compatibility 369.equ PORTA1 = 1 ; Port A Data Register bit 1 370.equ PA1 = 1 ; For compatibility 371.equ PORTA2 = 2 ; Port A Data Register bit 2 372.equ PA2 = 2 ; For compatibility 373.equ PORTA3 = 3 ; Port A Data Register bit 3 374.equ PA3 = 3 ; For compatibility 375.equ PORTA4 = 4 ; Port A Data Register bit 4 376.equ PA4 = 4 ; For compatibility 377.equ PORTA5 = 5 ; Port A Data Register bit 5 378.equ PA5 = 5 ; For compatibility 379.equ PORTA6 = 6 ; Port A Data Register bit 6 380.equ PA6 = 6 ; For compatibility 381.equ PORTA7 = 7 ; Port A Data Register bit 7 382.equ PA7 = 7 ; For compatibility 383 384; DDRA - Port A Data Direction Register 385.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 386.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 387.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 388.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 389.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 390.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 391.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 392.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 393 394; PINA - Port A Input Pins 395.equ PINA0 = 0 ; Input Pins, Port A bit 0 396.equ PINA1 = 1 ; Input Pins, Port A bit 1 397.equ PINA2 = 2 ; Input Pins, Port A bit 2 398.equ PINA3 = 3 ; Input Pins, Port A bit 3 399.equ PINA4 = 4 ; Input Pins, Port A bit 4 400.equ PINA5 = 5 ; Input Pins, Port A bit 5 401.equ PINA6 = 6 ; Input Pins, Port A bit 6 402.equ PINA7 = 7 ; Input Pins, Port A bit 7 403 404 405; ***** PORTB ************************ 406; PORTB - Port B Data Register 407.equ PORTB0 = 0 ; Port B Data Register bit 0 408.equ PB0 = 0 ; For compatibility 409.equ PORTB1 = 1 ; Port B Data Register bit 1 410.equ PB1 = 1 ; For compatibility 411.equ PORTB2 = 2 ; Port B Data Register bit 2 412.equ PB2 = 2 ; For compatibility 413.equ PORTB3 = 3 ; Port B Data Register bit 3 414.equ PB3 = 3 ; For compatibility 415.equ PORTB4 = 4 ; Port B Data Register bit 4 416.equ PB4 = 4 ; For compatibility 417.equ PORTB5 = 5 ; Port B Data Register bit 5 418.equ PB5 = 5 ; For compatibility 419.equ PORTB6 = 6 ; Port B Data Register bit 6 420.equ PB6 = 6 ; For compatibility 421.equ PORTB7 = 7 ; Port B Data Register bit 7 422.equ PB7 = 7 ; For compatibility 423 424; DDRB - Port B Data Direction Register 425.equ DDB0 = 0 ; Port B Data Direction Register bit 0 426.equ DDB1 = 1 ; Port B Data Direction Register bit 1 427.equ DDB2 = 2 ; Port B Data Direction Register bit 2 428.equ DDB3 = 3 ; Port B Data Direction Register bit 3 429.equ DDB4 = 4 ; Port B Data Direction Register bit 4 430.equ DDB5 = 5 ; Port B Data Direction Register bit 5 431.equ DDB6 = 6 ; Port B Data Direction Register bit 6 432.equ DDB7 = 7 ; Port B Data Direction Register bit 7 433 434; PINB - Port B Input Pins 435.equ PINB0 = 0 ; Port B Input Pins bit 0 436.equ PINB1 = 1 ; Port B Input Pins bit 1 437.equ PINB2 = 2 ; Port B Input Pins bit 2 438.equ PINB3 = 3 ; Port B Input Pins bit 3 439.equ PINB4 = 4 ; Port B Input Pins bit 4 440.equ PINB5 = 5 ; Port B Input Pins bit 5 441.equ PINB6 = 6 ; Port B Input Pins bit 6 442.equ PINB7 = 7 ; Port B Input Pins bit 7 443 444 445; ***** PORTC ************************ 446; PORTC - Port C Data Register 447.equ PORTC0 = 0 ; Port C Data Register bit 0 448.equ PC0 = 0 ; For compatibility 449.equ PORTC1 = 1 ; Port C Data Register bit 1 450.equ PC1 = 1 ; For compatibility 451.equ PORTC2 = 2 ; Port C Data Register bit 2 452.equ PC2 = 2 ; For compatibility 453.equ PORTC3 = 3 ; Port C Data Register bit 3 454.equ PC3 = 3 ; For compatibility 455.equ PORTC4 = 4 ; Port C Data Register bit 4 456.equ PC4 = 4 ; For compatibility 457.equ PORTC5 = 5 ; Port C Data Register bit 5 458.equ PC5 = 5 ; For compatibility 459.equ PORTC6 = 6 ; Port C Data Register bit 6 460.equ PC6 = 6 ; For compatibility 461.equ PORTC7 = 7 ; Port C Data Register bit 7 462.equ PC7 = 7 ; For compatibility 463 464; DDRC - Port C Data Direction Register 465.equ DDC0 = 0 ; Port C Data Direction Register bit 0 466.equ DDC1 = 1 ; Port C Data Direction Register bit 1 467.equ DDC2 = 2 ; Port C Data Direction Register bit 2 468.equ DDC3 = 3 ; Port C Data Direction Register bit 3 469.equ DDC4 = 4 ; Port C Data Direction Register bit 4 470.equ DDC5 = 5 ; Port C Data Direction Register bit 5 471.equ DDC6 = 6 ; Port C Data Direction Register bit 6 472.equ DDC7 = 7 ; Port C Data Direction Register bit 7 473 474; PINC - Port C Input Pins 475.equ PINC0 = 0 ; Port C Input Pins bit 0 476.equ PINC1 = 1 ; Port C Input Pins bit 1 477.equ PINC2 = 2 ; Port C Input Pins bit 2 478.equ PINC3 = 3 ; Port C Input Pins bit 3 479.equ PINC4 = 4 ; Port C Input Pins bit 4 480.equ PINC5 = 5 ; Port C Input Pins bit 5 481.equ PINC6 = 6 ; Port C Input Pins bit 6 482.equ PINC7 = 7 ; Port C Input Pins bit 7 483 484 485; ***** PORTD ************************ 486; PORTD - Port D Data Register 487.equ PORTD0 = 0 ; Port D Data Register bit 0 488.equ PD0 = 0 ; For compatibility 489.equ PORTD1 = 1 ; Port D Data Register bit 1 490.equ PD1 = 1 ; For compatibility 491.equ PORTD2 = 2 ; Port D Data Register bit 2 492.equ PD2 = 2 ; For compatibility 493.equ PORTD3 = 3 ; Port D Data Register bit 3 494.equ PD3 = 3 ; For compatibility 495.equ PORTD4 = 4 ; Port D Data Register bit 4 496.equ PD4 = 4 ; For compatibility 497.equ PORTD5 = 5 ; Port D Data Register bit 5 498.equ PD5 = 5 ; For compatibility 499.equ PORTD6 = 6 ; Port D Data Register bit 6 500.equ PD6 = 6 ; For compatibility 501.equ PORTD7 = 7 ; Port D Data Register bit 7 502.equ PD7 = 7 ; For compatibility 503 504; DDRD - Port D Data Direction Register 505.equ DDD0 = 0 ; Port D Data Direction Register bit 0 506.equ DDD1 = 1 ; Port D Data Direction Register bit 1 507.equ DDD2 = 2 ; Port D Data Direction Register bit 2 508.equ DDD3 = 3 ; Port D Data Direction Register bit 3 509.equ DDD4 = 4 ; Port D Data Direction Register bit 4 510.equ DDD5 = 5 ; Port D Data Direction Register bit 5 511.equ DDD6 = 6 ; Port D Data Direction Register bit 6 512.equ DDD7 = 7 ; Port D Data Direction Register bit 7 513 514; PIND - Port D Input Pins 515.equ PIND0 = 0 ; Port D Input Pins bit 0 516.equ PIND1 = 1 ; Port D Input Pins bit 1 517.equ PIND2 = 2 ; Port D Input Pins bit 2 518.equ PIND3 = 3 ; Port D Input Pins bit 3 519.equ PIND4 = 4 ; Port D Input Pins bit 4 520.equ PIND5 = 5 ; Port D Input Pins bit 5 521.equ PIND6 = 6 ; Port D Input Pins bit 6 522.equ PIND7 = 7 ; Port D Input Pins bit 7 523 524 525; ***** ANALOG_COMPARATOR ************ 526; ADCSRB - ADC Control and Status Register B 527.equ ACME = 6 ; Analog Comparator Multiplexer Enable 528 529; ACSR - Analog Comparator Control And Status Register 530.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 531.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 532.equ ACIC = 2 ; Analog Comparator Input Capture Enable 533.equ ACIE = 3 ; Analog Comparator Interrupt Enable 534.equ ACI = 4 ; Analog Comparator Interrupt Flag 535.equ ACO = 5 ; Analog Compare Output 536.equ ACBG = 6 ; Analog Comparator Bandgap Select 537.equ ACD = 7 ; Analog Comparator Disable 538 539; DIDR1 - Digital Input Disable Register 1 540.equ AIN0D = 0 ; AIN0 Digital Input Disable 541.equ AIN1D = 1 ; AIN1 Digital Input Disable 542 543 544; ***** PORTE ************************ 545; PORTE - Data Register, Port E 546.equ PORTE0 = 0 ; 547.equ PE0 = 0 ; For compatibility 548.equ PORTE1 = 1 ; 549.equ PE1 = 1 ; For compatibility 550.equ PORTE2 = 2 ; 551.equ PE2 = 2 ; For compatibility 552.equ PORTE3 = 3 ; 553.equ PE3 = 3 ; For compatibility 554.equ PORTE4 = 4 ; 555.equ PE4 = 4 ; For compatibility 556.equ PORTE5 = 5 ; 557.equ PE5 = 5 ; For compatibility 558.equ PORTE6 = 6 ; 559.equ PE6 = 6 ; For compatibility 560.equ PORTE7 = 7 ; 561.equ PE7 = 7 ; For compatibility 562 563; DDRE - Data Direction Register, Port E 564.equ DDE0 = 0 ; 565.equ DDE1 = 1 ; 566.equ DDE2 = 2 ; 567.equ DDE3 = 3 ; 568.equ DDE4 = 4 ; 569.equ DDE5 = 5 ; 570.equ DDE6 = 6 ; 571.equ DDE7 = 7 ; 572 573; PINE - Input Pins, Port E 574.equ PINE0 = 0 ; 575.equ PINE1 = 1 ; 576.equ PINE2 = 2 ; 577.equ PINE3 = 3 ; 578.equ PINE4 = 4 ; 579.equ PINE5 = 5 ; 580.equ PINE6 = 6 ; 581.equ PINE7 = 7 ; 582 583 584; ***** PORTF ************************ 585; PORTF - Data Register, Port F 586.equ PORTF0 = 0 ; 587.equ PF0 = 0 ; For compatibility 588.equ PORTF1 = 1 ; 589.equ PF1 = 1 ; For compatibility 590.equ PORTF2 = 2 ; 591.equ PF2 = 2 ; For compatibility 592.equ PORTF3 = 3 ; 593.equ PF3 = 3 ; For compatibility 594.equ PORTF4 = 4 ; 595.equ PF4 = 4 ; For compatibility 596.equ PORTF5 = 5 ; 597.equ PF5 = 5 ; For compatibility 598.equ PORTF6 = 6 ; 599.equ PF6 = 6 ; For compatibility 600.equ PORTF7 = 7 ; 601.equ PF7 = 7 ; For compatibility 602 603; DDRF - Data Direction Register, Port F 604.equ DDF0 = 0 ; 605.equ DDF1 = 1 ; 606.equ DDF2 = 2 ; 607.equ DDF3 = 3 ; 608.equ DDF4 = 4 ; 609.equ DDF5 = 5 ; 610.equ DDF6 = 6 ; 611.equ DDF7 = 7 ; 612 613; PINF - Input Pins, Port F 614.equ PINF0 = 0 ; 615.equ PINF1 = 1 ; 616.equ PINF2 = 2 ; 617.equ PINF3 = 3 ; 618.equ PINF4 = 4 ; 619.equ PINF5 = 5 ; 620.equ PINF6 = 6 ; 621.equ PINF7 = 7 ; 622 623 624; ***** PORTG ************************ 625; PORTG - Port G Data Register 626.equ PORTG0 = 0 ; 627.equ PG0 = 0 ; For compatibility 628.equ PORTG1 = 1 ; 629.equ PG1 = 1 ; For compatibility 630.equ PORTG2 = 2 ; 631.equ PG2 = 2 ; For compatibility 632.equ PORTG3 = 3 ; 633.equ PG3 = 3 ; For compatibility 634.equ PORTG4 = 4 ; 635.equ PG4 = 4 ; For compatibility 636 637; DDRG - Port G Data Direction Register 638.equ DDG0 = 0 ; 639.equ DDG1 = 1 ; 640.equ DDG2 = 2 ; 641.equ DDG3 = 3 ; 642.equ DDG4 = 4 ; 643 644; PING - Port G Input Pins 645.equ PING0 = 0 ; 646.equ PING1 = 1 ; 647.equ PING2 = 2 ; 648.equ PING3 = 3 ; 649.equ PING4 = 4 ; 650.equ PING5 = 5 ; 651 652 653; ***** JTAG ************************* 654; OCDR - On-Chip Debug Related Register in I/O Memory 655.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 656.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 657.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 658.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 659.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 660.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 661.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 662.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 663.equ IDRD = OCDR7 ; For compatibility 664 665; MCUCR - MCU Control Register 666.equ JTD = 7 ; JTAG Interface Disable 667 668; MCUSR - MCU Status Register 669.equ JTRF = 4 ; JTAG Reset Flag 670 671 672; ***** MISC ************************* 673; LCDCRA - LCD Control Register A 674.equ LCDBL = 0 ; LCD Blanking 675.equ LCDIE = 3 ; LCD Interrupt Enable 676.equ LCDIF = 4 ; LCD Interrupt Flag 677.equ LCDAB = 6 ; LCD A or B waveform 678.equ LCDEN = 7 ; LCD Enable 679 680; LCDCRB - LCD Control and Status Register B 681.equ LCDPM0 = 0 ; LCD Port Mask 0 682.equ LCDPM1 = 1 ; LCD Port Mask 1 683.equ LCDPM2 = 2 ; LCD Port Mask 2 684.equ LCDMUX0 = 4 ; LCD Mux Select 0 685.equ LCDMUX1 = 5 ; LCD Mux Select 1 686.equ LCD2B = 6 ; LCD 1/2 Bias Select 687.equ LCDCS = 7 ; LCD CLock Select 688 689; LCDFRR - LCD Frame Rate Register 690.equ LCDCD0 = 0 ; LCD Clock Divider 0 691.equ LCDCD1 = 1 ; LCD Clock Divider 1 692.equ LCDCD2 = 2 ; LCD Clock Divider 2 693.equ LCDPS0 = 4 ; LCD Prescaler Select 0 694.equ LCDPS1 = 5 ; LCD Prescaler Select 1 695.equ LCDPS2 = 6 ; LCD Prescaler Select 2 696 697; LCDCCR - LCD Contrast Control Register 698.equ LCDCC0 = 0 ; LCD Contrast Control 0 699.equ LCDCC1 = 1 ; LCD Contrast Control 1 700.equ LCDCC2 = 2 ; LCD Contrast Control 2 701.equ LCDCC3 = 3 ; LCD Contrast Control 3 702.equ LCDDC0 = 5 ; LCD Display Configuration Bit 0 703.equ LCDDC1 = 6 ; LCD Display Configuration Bit 1 704.equ LCDDC2 = 7 ; LCD Display Configuration Bit 2 705 706; LCDDR18 - LCD Data Register 18 707.equ SEG324 = 0 ; 708 709; LCDDR17 - LCD Data Register 17 710.equ SEG316 = 0 ; 711.equ SEG317 = 1 ; 712.equ SEG318 = 2 ; 713.equ SEG319 = 3 ; 714.equ SEG320 = 4 ; 715.equ SEG321 = 5 ; 716.equ SEG322 = 6 ; 717.equ SEG323 = 7 ; 718 719; LCDDR16 - LCD Data Register 16 720.equ SEG308 = 0 ; 721.equ SEG309 = 1 ; 722.equ SEG310 = 2 ; 723.equ SEG311 = 3 ; 724.equ SEG312 = 4 ; 725.equ SEG313 = 5 ; 726.equ SEG314 = 6 ; 727.equ SEG315 = 7 ; 728 729; LCDDR15 - LCD Data Register 15 730.equ SEG300 = 0 ; 731.equ SEG301 = 1 ; 732.equ SEG302 = 2 ; 733.equ SEG303 = 3 ; 734.equ SEG304 = 4 ; 735.equ SEG305 = 5 ; 736.equ SEG306 = 6 ; 737.equ SEG307 = 7 ; 738 739; LCDDR13 - LCD Data Register 13 740.equ SEG224 = 0 ; 741 742; LCDDR12 - LCD Data Register 12 743.equ SEG216 = 0 ; 744.equ SEG217 = 1 ; 745.equ SEG218 = 2 ; 746.equ SEG219 = 3 ; 747.equ SEG220 = 4 ; 748.equ SEG221 = 5 ; 749.equ SEG222 = 6 ; 750.equ SEG223 = 7 ; 751 752; LCDDR11 - LCD Data Register 11 753.equ SEG208 = 0 ; 754.equ SEG209 = 1 ; 755.equ SEG210 = 2 ; 756.equ SEG211 = 3 ; 757.equ SEG212 = 4 ; 758.equ SEG213 = 5 ; 759.equ SEG214 = 6 ; 760.equ SEG215 = 7 ; 761 762; LCDDR10 - LCD Data Register 10 763.equ SEG200 = 0 ; 764.equ SEG201 = 1 ; 765.equ SEG202 = 2 ; 766.equ SEG203 = 3 ; 767.equ SEG204 = 4 ; 768.equ SEG205 = 5 ; 769.equ SEG206 = 6 ; 770.equ SEG207 = 7 ; 771 772; LCDDR8 - LCD Data Register 8 773.equ SEG124 = 0 ; 774 775; LCDDR7 - LCD Data Register 7 776.equ SEG116 = 0 ; 777.equ SEG117 = 1 ; 778.equ SEG118 = 2 ; 779.equ SEG119 = 3 ; 780.equ SEG120 = 4 ; 781.equ SEG121 = 5 ; 782.equ SEG122 = 6 ; 783.equ SEG123 = 7 ; 784 785; LCDDR6 - LCD Data Register 6 786.equ SEG108 = 0 ; 787.equ SEG109 = 1 ; 788.equ SEG110 = 2 ; 789.equ SEG111 = 3 ; 790.equ SEG112 = 4 ; 791.equ SEG113 = 5 ; 792.equ SEG114 = 6 ; 793.equ SEG115 = 7 ; 794 795; LCDDR5 - LCD Data Register 5 796.equ SEG100 = 0 ; 797.equ SEG101 = 1 ; 798.equ SEG102 = 2 ; 799.equ SEG103 = 3 ; 800.equ SEG104 = 4 ; 801.equ SEG105 = 5 ; 802.equ SEG106 = 6 ; 803.equ SEG107 = 7 ; 804 805; LCDDR3 - LCD Data Register 3 806.equ SEG024 = 0 ; 807 808; LCDDR2 - LCD Data Register 2 809.equ SEG016 = 0 ; 810.equ SEG017 = 1 ; 811.equ SEG018 = 2 ; 812.equ SEG019 = 3 ; 813.equ SEG020 = 4 ; 814.equ SEG021 = 5 ; 815.equ SEG022 = 6 ; 816.equ SEG023 = 7 ; 817 818; LCDDR1 - LCD Data Register 1 819.equ SEG008 = 0 ; 820.equ SEG009 = 1 ; 821.equ SEG010 = 2 ; 822.equ SEG011 = 3 ; 823.equ SEG012 = 4 ; 824.equ SEG013 = 5 ; 825.equ SEG014 = 6 ; 826.equ SEG015 = 7 ; 827 828; LCDDR0 - LCD Data Register 0 829.equ SEG000 = 0 ; 830.equ SEG001 = 1 ; 831.equ SEG002 = 2 ; 832.equ SEG003 = 3 ; 833.equ SEG004 = 4 ; 834.equ SEG005 = 5 ; 835.equ SEG006 = 6 ; 836.equ SEG007 = 7 ; 837 838 839; ***** EXTERNAL_INTERRUPT *********** 840; EICRA - External Interrupt Control Register 841.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 842.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 843 844; EIMSK - External Interrupt Mask Register 845.equ INT0 = 0 ; External Interrupt Request 0 Enable 846.equ PCIE0 = 6 ; Pin Change Interrupt Enable 0 847.equ PCIE1 = 7 ; Pin Change Interrupt Enable 1 848 849; EIFR - External Interrupt Flag Register 850.equ INTF0 = 0 ; External Interrupt Flag 0 851.equ PCIF0 = 6 ; Pin Change Interrupt Flag 0 852.equ PCIF1 = 7 ; Pin Change Interrupt Flag 1 853 854; PCMSK1 - Pin Change Mask Register 1 855.equ PCINT8 = 0 ; Pin Change Enable Mask 8 856.equ PCINT9 = 1 ; Pin Change Enable Mask 9 857.equ PCINT10 = 2 ; Pin Change Enable Mask 10 858.equ PCINT11 = 3 ; Pin Change Enable Mask 11 859.equ PCINT12 = 4 ; Pin Change Enable Mask 12 860.equ PCINT13 = 5 ; Pin Change Enable Mask 13 861.equ PCINT14 = 6 ; Pin Change Enable Mask 14 862.equ PCINT15 = 7 ; Pin Change Enable Mask 15 863 864; PCMSK0 - Pin Change Mask Register 0 865.equ PCINT0 = 0 ; Pin Change Enable Mask 0 866.equ PCINT1 = 1 ; Pin Change Enable Mask 1 867.equ PCINT2 = 2 ; Pin Change Enable Mask 2 868.equ PCINT3 = 3 ; Pin Change Enable Mask 3 869.equ PCINT4 = 4 ; Pin Change Enable Mask 4 870.equ PCINT5 = 5 ; Pin Change Enable Mask 5 871.equ PCINT6 = 6 ; Pin Change Enable Mask 6 872.equ PCINT7 = 7 ; Pin Change Enable Mask 7 873 874 875; ***** CPU ************************** 876; SREG - Status Register 877.equ SREG_C = 0 ; Carry Flag 878.equ SREG_Z = 1 ; Zero Flag 879.equ SREG_N = 2 ; Negative Flag 880.equ SREG_V = 3 ; Two's Complement Overflow Flag 881.equ SREG_S = 4 ; Sign Bit 882.equ SREG_H = 5 ; Half Carry Flag 883.equ SREG_T = 6 ; Bit Copy Storage 884.equ SREG_I = 7 ; Global Interrupt Enable 885 886; MCUCR - MCU Control Register 887.equ IVCE = 0 ; Interrupt Vector Change Enable 888.equ IVSEL = 1 ; Interrupt Vector Select 889.equ PUD = 4 ; Pull-up disable 890 891; MCUSR - MCU Status Register 892.equ PORF = 0 ; Power-on reset flag 893.equ EXTRF = 1 ; External Reset Flag 894.equ BORF = 2 ; Brown-out Reset Flag 895.equ WDRF = 3 ; Watchdog Reset Flag 896;.equ JTRF = 4 ; JTAG Reset Flag 897 898; OSCCAL - Oscillator Calibration Value 899.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 900.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 901.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 902.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 903.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 904.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 905.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 906.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 907 908; CLKPR - Clock Prescale Register 909.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 910.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 911.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 912.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 913.equ CLKPCE = 7 ; Clock Prescaler Change Enable 914 915; PRR - Power Reduction Register 916.equ PRADC = 0 ; Power Reduction ADC 917.equ PRUSART0 = 1 ; Power Reduction USART 918.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface 919.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 920.equ PRLCD = 4 ; Power Reduction LCD 921 922; SMCR - Sleep Mode Control Register 923.equ SE = 0 ; Sleep Enable 924.equ SM0 = 1 ; Sleep Mode Select bit 0 925.equ SM1 = 2 ; Sleep Mode Select bit 1 926.equ SM2 = 3 ; Sleep Mode Select bit 2 927 928; GPIOR2 - General Purpose IO Register 2 929.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 930.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 931.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 932.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 933.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 934.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 935.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 936.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 937 938; GPIOR1 - General Purpose IO Register 1 939.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 940.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 941.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 942.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 943.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 944.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 945.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 946.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 947 948; GPIOR0 - General Purpose IO Register 0 949.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 950.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 951.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 952.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 953.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 954.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 955.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 956.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 957 958 959; ***** USI ************************** 960; USIDR - USI Data Register 961.equ USIDR0 = 0 ; USI Data Register bit 0 962.equ USIDR1 = 1 ; USI Data Register bit 1 963.equ USIDR2 = 2 ; USI Data Register bit 2 964.equ USIDR3 = 3 ; USI Data Register bit 3 965.equ USIDR4 = 4 ; USI Data Register bit 4 966.equ USIDR5 = 5 ; USI Data Register bit 5 967.equ USIDR6 = 6 ; USI Data Register bit 6 968.equ USIDR7 = 7 ; USI Data Register bit 7 969 970; USISR - USI Status Register 971.equ USICNT0 = 0 ; USI Counter Value Bit 0 972.equ USICNT1 = 1 ; USI Counter Value Bit 1 973.equ USICNT2 = 2 ; USI Counter Value Bit 2 974.equ USICNT3 = 3 ; USI Counter Value Bit 3 975.equ USIDC = 4 ; Data Output Collision 976.equ USIPF = 5 ; Stop Condition Flag 977.equ USIOIF = 6 ; Counter Overflow Interrupt Flag 978.equ USISIF = 7 ; Start Condition Interrupt Flag 979 980; USICR - USI Control Register 981.equ USITC = 0 ; Toggle Clock Port Pin 982.equ USICLK = 1 ; Clock Strobe 983.equ USICS0 = 2 ; USI Clock Source Select Bit 0 984.equ USICS1 = 3 ; USI Clock Source Select Bit 1 985.equ USIWM0 = 4 ; USI Wire Mode Bit 0 986.equ USIWM1 = 5 ; USI Wire Mode Bit 1 987.equ USIOIE = 6 ; Counter Overflow Interrupt Enable 988.equ USISIE = 7 ; Start Condition Interrupt Enable 989 990 991; ***** AD_CONVERTER ***************** 992; ADMUX - The ADC multiplexer Selection Register 993.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 994.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 995.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 996.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 997.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits 998.equ ADLAR = 5 ; Left Adjust Result 999.equ REFS0 = 6 ; Reference Selection Bit 0 1000.equ REFS1 = 7 ; Reference Selection Bit 1 1001 1002; ADCSRA - The ADC Control and Status register 1003.equ ADPS0 = 0 ; ADC Prescaler Select Bits 1004.equ ADPS1 = 1 ; ADC Prescaler Select Bits 1005.equ ADPS2 = 2 ; ADC Prescaler Select Bits 1006.equ ADIE = 3 ; ADC Interrupt Enable 1007.equ ADIF = 4 ; ADC Interrupt Flag 1008.equ ADATE = 5 ; ADC Auto Trigger Enable 1009.equ ADSC = 6 ; ADC Start Conversion 1010.equ ADEN = 7 ; ADC Enable 1011 1012; ADCH - ADC Data Register High Byte 1013.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 1014.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 1015.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 1016.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 1017.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 1018.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 1019.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 1020.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 1021 1022; ADCL - ADC Data Register Low Byte 1023.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 1024.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 1025.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 1026.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 1027.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 1028.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 1029.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 1030.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 1031 1032; ADCSRB - ADC Control and Status Register B 1033.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 1034.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 1035.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 1036 1037; DIDR0 - Digital Input Disable Register 0 1038.equ ADC0D = 0 ; ADC0 Digital input Disable 1039.equ ADC1D = 1 ; ADC1 Digital input Disable 1040.equ ADC2D = 2 ; ADC2 Digital input Disable 1041.equ ADC3D = 3 ; ADC3 Digital input Disable 1042.equ ADC4D = 4 ; ADC4 Digital input Disable 1043.equ ADC5D = 5 ; ADC5 Digital input Disable 1044.equ ADC6D = 6 ; ADC6 Digital input Disable 1045.equ ADC7D = 7 ; ADC7 Digital input Disable 1046 1047 1048; ***** BOOT_LOAD ******************** 1049; SPMCSR - Store Program Memory Control Register 1050.equ SPMCR = SPMCSR ; For compatibility 1051.equ SPMEN = 0 ; Store Program Memory Enable 1052.equ PGERS = 1 ; Page Erase 1053.equ PGWRT = 2 ; Page Write 1054.equ BLBSET = 3 ; Boot Lock Bit Set 1055.equ RWWSRE = 4 ; Read While Write section read enable 1056.equ ASRE = RWWSRE ; For compatibility 1057.equ RWWSB = 6 ; Read While Write Section Busy 1058.equ ASB = RWWSB ; For compatibility 1059.equ SPMIE = 7 ; SPM Interrupt Enable 1060 1061 1062; ***** USART0 *********************** 1063; UDR - USART I/O Data Register 1064.equ UDR0 = UDR ; For compatibility 1065.equ UDR00 = 0 ; USART I/O Data Register bit 0 1066.equ UDR01 = 1 ; USART I/O Data Register bit 1 1067.equ UDR02 = 2 ; USART I/O Data Register bit 2 1068.equ UDR03 = 3 ; USART I/O Data Register bit 3 1069.equ UDR04 = 4 ; USART I/O Data Register bit 4 1070.equ UDR05 = 5 ; USART I/O Data Register bit 5 1071.equ UDR06 = 6 ; USART I/O Data Register bit 6 1072.equ UDR07 = 7 ; USART I/O Data Register bit 7 1073 1074; UCSRA - USART Control and Status Register A 1075.equ UCSR0A = UCSRA ; For compatibility 1076.equ USR = UCSRA ; For compatibility 1077.equ MPCM = 0 ; Multi-processor Communication Mode 1078.equ MPCM0 = MPCM ; For compatibility 1079.equ U2X = 1 ; Double the USART Transmission Speed 1080.equ U2X0 = U2X ; For compatibility 1081.equ UPE = 2 ; USART Parity Error 1082.equ UPE0 = UPE ; For compatibility 1083.equ DOR = 3 ; Data OverRun 1084.equ DOR0 = DOR ; For compatibility 1085.equ FE = 4 ; Framing Error 1086.equ FE0 = FE ; For compatibility 1087.equ UDRE = 5 ; USART Data Register Empty 1088.equ UDRE0 = UDRE ; For compatibility 1089.equ TXC = 6 ; USART Transmit Complete 1090.equ TXC0 = TXC ; For compatibility 1091.equ RXC = 7 ; USART Receive Complete 1092.equ RXC0 = RXC ; For compatibility 1093 1094; UCSRB - USART Control and Status Register B 1095.equ UCSR0B = UCSRB ; For compatibility 1096.equ UCR = UCSRB ; For compatibility 1097.equ TXB8 = 0 ; Transmit Data Bit 8 1098.equ TXB80 = TXB8 ; For compatibility 1099.equ RXB8 = 1 ; Receive Data Bit 8 1100.equ RXB80 = RXB8 ; For compatibility 1101.equ UCSZ2 = 2 ; Character Size 1102.equ UCSZ02 = UCSZ2 ; For compatibility 1103.equ TXEN = 3 ; Transmitter Enable 1104.equ TXEN0 = TXEN ; For compatibility 1105.equ RXEN = 4 ; Receiver Enable 1106.equ RXEN0 = RXEN ; For compatibility 1107.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable 1108.equ UDRIE0 = UDRIE ; For compatibility 1109.equ TXCIE = 6 ; TX Complete Interrupt Enable 1110.equ TXCIE0 = TXCIE ; For compatibility 1111.equ RXCIE = 7 ; RX Complete Interrupt Enable 1112.equ RXCIE0 = RXCIE ; For compatibility 1113 1114; UCSRC - USART Control and Status Register C 1115.equ UCSR0C = UCSRC ; For compatibility 1116.equ UCPOL = 0 ; Clock Polarity 1117.equ UCPOL0 = UCPOL ; For compatibility 1118.equ UCSZ0 = 1 ; Character Size 1119.equ UCSZ00 = UCSZ0 ; For compatibility 1120.equ UCSZ1 = 2 ; Character Size 1121.equ UCSZ01 = UCSZ1 ; For compatibility 1122.equ USBS = 3 ; Stop Bit Select 1123.equ USBS0 = USBS ; For compatibility 1124.equ UPM0 = 4 ; Parity Mode Bit 0 1125.equ UPM00 = UPM0 ; For compatibility 1126.equ UPM1 = 5 ; Parity Mode Bit 1 1127.equ UPM01 = UPM1 ; For compatibility 1128.equ UMSEL = 6 ; USART Mode Select 1129.equ UMSEL0 = UMSEL ; For compatibility 1130 1131.equ UBRR0H = UBRRH ; For compatibility 1132.equ UBRR0L = UBRRL ; For compatibility 1133.equ UBRR0 = UBRRL ; For compatibility 1134.equ UBRR = UBRRL ; For compatibility 1135 1136 1137; ***** LOCKSBITS ******************************************************** 1138.equ LB1 = 0 ; Lock bit 1139.equ LB2 = 1 ; Lock bit 1140.equ BLB01 = 2 ; Boot Lock bit 1141.equ BLB02 = 3 ; Boot Lock bit 1142.equ BLB11 = 4 ; Boot lock bit 1143.equ BLB12 = 5 ; Boot lock bit 1144 1145 1146; ***** FUSES ************************************************************ 1147; LOW fuse bits 1148.equ CKSEL0 = 0 ; Select Clock Source 1149.equ CKSEL1 = 1 ; Select Clock Source 1150.equ CKSEL2 = 2 ; Select Clock Source 1151.equ CKSEL3 = 3 ; Select Clock Source 1152.equ SUT0 = 4 ; Select start-up time 1153.equ SUT1 = 5 ; Select start-up time 1154.equ CKOUT = 6 ; Oscillator options 1155.equ CLKDIV8 = 7 ; Divide clock by 8 1156 1157; HIGH fuse bits 1158.equ BOOTRST = 0 ; Select Reset Vector 1159.equ BOOTSZ0 = 1 ; Select Boot Size 1160.equ BOOTSZ1 = 2 ; Select Boot Size 1161.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 1162.equ WDTON = 4 ; Watchdog timer always on 1163.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 1164.equ JTAGEN = 6 ; Enable JTAG 1165.equ OCDEN = 7 ; Enable OCD 1166 1167; EXTENDED fuse bits 1168.equ RESERVED = 0 ; Reserved for future use 1169.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level 1170.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level 1171.equ BODLEVEL2 = 3 ; Brown out detector trigger level 1172 1173 1174 1175; ***** CPU REGISTER DEFINITIONS ***************************************** 1176.def XH = r27 1177.def XL = r26 1178.def YH = r29 1179.def YL = r28 1180.def ZH = r31 1181.def ZL = r30 1182 1183 1184 1185; ***** DATA MEMORY DECLARATIONS ***************************************** 1186.equ FLASHEND = 0x1fff ; Note: Word address 1187.equ IOEND = 0x00ff 1188.equ SRAM_START = 0x0100 1189.equ SRAM_SIZE = 1024 1190.equ RAMEND = 0x04ff 1191.equ XRAMEND = 0x0000 1192.equ E2END = 0x01ff 1193.equ EEPROMEND = 0x01ff 1194.equ EEADRBITS = 9 1195#pragma AVRPART MEMORY PROG_FLASH 16384 1196#pragma AVRPART MEMORY EEPROM 512 1197#pragma AVRPART MEMORY INT_SRAM SIZE 1024 1198#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 1199 1200 1201 1202; ***** BOOTLOADER DECLARATIONS ****************************************** 1203.equ NRWW_START_ADDR = 0x1c00 1204.equ NRWW_STOP_ADDR = 0x1fff 1205.equ RWW_START_ADDR = 0x0 1206.equ RWW_STOP_ADDR = 0x1bff 1207.equ PAGESIZE = 64 1208.equ FIRSTBOOTSTART = 0x1f80 1209.equ SECONDBOOTSTART = 0x1f00 1210.equ THIRDBOOTSTART = 0x1e00 1211.equ FOURTHBOOTSTART = 0x1c00 1212.equ SMALLBOOTSTART = FIRSTBOOTSTART 1213.equ LARGEBOOTSTART = FOURTHBOOTSTART 1214 1215 1216 1217; ***** INTERRUPT VECTORS ************************************************ 1218.equ INT0addr = 0x0002 ; External Interrupt Request 0 1219.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 1220.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 1221.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match 1222.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow 1223.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event 1224.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A 1225.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B 1226.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow 1227.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match 1228.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow 1229.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete 1230.equ URXC0addr = 0x001a ; USART0, Rx Complete 1231.equ URXCaddr = 0x001a ; For compatibility 1232.equ UDRE0addr = 0x001c ; USART0 Data register Empty 1233.equ UDREaddr = 0x001c ; For compatibility 1234.equ UTXC0addr = 0x001e ; USART0, Tx Complete 1235.equ UTXCaddr = 0x001e ; For compatibility 1236.equ USI_STARTaddr = 0x0020 ; USI Start Condition 1237.equ USI_OVFaddr = 0x0022 ; USI Overflow 1238.equ ACIaddr = 0x0024 ; Analog Comparator 1239.equ ADCCaddr = 0x0026 ; ADC Conversion Complete 1240.equ ERDYaddr = 0x0028 ; EEPROM Ready 1241.equ SPMRaddr = 0x002a ; Store Program Memory Read 1242.equ LCDSFaddr = 0x002c ; LCD Start of Frame 1243 1244.equ INT_VECTORS_SIZE = 46 ; size in words 1245 1246#endif /* _M169DEF_INC_ */ 1247 1248; ***** END OF FILE ****************************************************** 1249