1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2005-01-11 10:31 ******* Source: ATmega323.xml *********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "m323def.inc" 8;* Title : Register/Bit Definitions for the ATmega323 9;* Date : 2005-01-11 10;* Version : 2.14 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATmega323 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _M323DEF_INC_ 41#define _M323DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATmega323 48#pragma AVRPART ADMIN PART_NAME ATmega323 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x95 51.equ SIGNATURE_002 = 0x01 52 53#pragma AVRPART CORE CORE_VERSION V2E 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ SREG = 0x3f 61.equ SPH = 0x3e 62.equ SPL = 0x3d 63.equ OCR0 = 0x3c 64.equ GICR = 0x3b 65.equ GIFR = 0x3a 66.equ TIMSK = 0x39 67.equ TIFR = 0x38 68.equ SPMCR = 0x37 69.equ TWCR = 0x36 70.equ MCUCR = 0x35 71.equ MCUCSR = 0x34 72.equ TCCR0 = 0x33 73.equ TCNT0 = 0x32 74.equ OSCCAL = 0x31 75.equ OCDR = 0x31 76.equ SFIOR = 0x30 77.equ TCCR1A = 0x2f 78.equ TCCR1B = 0x2e 79.equ TCNT1H = 0x2d 80.equ TCNT1L = 0x2c 81.equ OCR1AH = 0x2b 82.equ OCR1AL = 0x2a 83.equ OCR1BH = 0x29 84.equ OCR1BL = 0x28 85.equ ICR1H = 0x27 86.equ ICR1L = 0x26 87.equ TCCR2 = 0x25 88.equ TCNT2 = 0x24 89.equ OCR2 = 0x23 90.equ ASSR = 0x22 91.equ WDTCR = 0x21 92.equ UBRRH = 0x20 93.equ UCSRC = 0x20 94.equ EEARH = 0x1f 95.equ EEARL = 0x1e 96.equ EEDR = 0x1d 97.equ EECR = 0x1c 98.equ PORTA = 0x1b 99.equ DDRA = 0x1a 100.equ PINA = 0x19 101.equ PORTB = 0x18 102.equ DDRB = 0x17 103.equ PINB = 0x16 104.equ PORTC = 0x15 105.equ DDRC = 0x14 106.equ PINC = 0x13 107.equ PORTD = 0x12 108.equ DDRD = 0x11 109.equ PIND = 0x10 110.equ SPDR = 0x0f 111.equ SPSR = 0x0e 112.equ SPCR = 0x0d 113.equ UDR = 0x0c 114.equ UCSRA = 0x0b 115.equ UCSRB = 0x0a 116.equ UBRRL = 0x09 117.equ ACSR = 0x08 118.equ ADMUX = 0x07 119.equ ADCSR = 0x06 120.equ ADCH = 0x05 121.equ ADCL = 0x04 122.equ TWDR = 0x03 123.equ TWAR = 0x02 124.equ TWSR = 0x01 125.equ TWBR = 0x00 126 127 128; ***** BIT DEFINITIONS ************************************************** 129 130; ***** PORTA ************************ 131; PORTA - Port A Data Register 132.equ PORTA0 = 0 ; Port A Data Register bit 0 133.equ PA0 = 0 ; For compatibility 134.equ PORTA1 = 1 ; Port A Data Register bit 1 135.equ PA1 = 1 ; For compatibility 136.equ PORTA2 = 2 ; Port A Data Register bit 2 137.equ PA2 = 2 ; For compatibility 138.equ PORTA3 = 3 ; Port A Data Register bit 3 139.equ PA3 = 3 ; For compatibility 140.equ PORTA4 = 4 ; Port A Data Register bit 4 141.equ PA4 = 4 ; For compatibility 142.equ PORTA5 = 5 ; Port A Data Register bit 5 143.equ PA5 = 5 ; For compatibility 144.equ PORTA6 = 6 ; Port A Data Register bit 6 145.equ PA6 = 6 ; For compatibility 146.equ PORTA7 = 7 ; Port A Data Register bit 7 147.equ PA7 = 7 ; For compatibility 148 149; DDRA - Port A Data Direction Register 150.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 151.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 152.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 153.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 154.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 155.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 156.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 157.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 158 159; PINA - Port A Input Pins 160.equ PINA0 = 0 ; Input Pins, Port A bit 0 161.equ PINA1 = 1 ; Input Pins, Port A bit 1 162.equ PINA2 = 2 ; Input Pins, Port A bit 2 163.equ PINA3 = 3 ; Input Pins, Port A bit 3 164.equ PINA4 = 4 ; Input Pins, Port A bit 4 165.equ PINA5 = 5 ; Input Pins, Port A bit 5 166.equ PINA6 = 6 ; Input Pins, Port A bit 6 167.equ PINA7 = 7 ; Input Pins, Port A bit 7 168 169 170; ***** PORTB ************************ 171; PORTB - Port B Data Register 172.equ PORTB0 = 0 ; Port B Data Register bit 0 173.equ PB0 = 0 ; For compatibility 174.equ PORTB1 = 1 ; Port B Data Register bit 1 175.equ PB1 = 1 ; For compatibility 176.equ PORTB2 = 2 ; Port B Data Register bit 2 177.equ PB2 = 2 ; For compatibility 178.equ PORTB3 = 3 ; Port B Data Register bit 3 179.equ PB3 = 3 ; For compatibility 180.equ PORTB4 = 4 ; Port B Data Register bit 4 181.equ PB4 = 4 ; For compatibility 182.equ PORTB5 = 5 ; Port B Data Register bit 5 183.equ PB5 = 5 ; For compatibility 184.equ PORTB6 = 6 ; Port B Data Register bit 6 185.equ PB6 = 6 ; For compatibility 186.equ PORTB7 = 7 ; Port B Data Register bit 7 187.equ PB7 = 7 ; For compatibility 188 189; DDRB - Port B Data Direction Register 190.equ DDB0 = 0 ; Port B Data Direction Register bit 0 191.equ DDB1 = 1 ; Port B Data Direction Register bit 1 192.equ DDB2 = 2 ; Port B Data Direction Register bit 2 193.equ DDB3 = 3 ; Port B Data Direction Register bit 3 194.equ DDB4 = 4 ; Port B Data Direction Register bit 4 195.equ DDB5 = 5 ; Port B Data Direction Register bit 5 196.equ DDB6 = 6 ; Port B Data Direction Register bit 6 197.equ DDB7 = 7 ; Port B Data Direction Register bit 7 198 199; PINB - Port B Input Pins 200.equ PINB0 = 0 ; Port B Input Pins bit 0 201.equ PINB1 = 1 ; Port B Input Pins bit 1 202.equ PINB2 = 2 ; Port B Input Pins bit 2 203.equ PINB3 = 3 ; Port B Input Pins bit 3 204.equ PINB4 = 4 ; Port B Input Pins bit 4 205.equ PINB5 = 5 ; Port B Input Pins bit 5 206.equ PINB6 = 6 ; Port B Input Pins bit 6 207.equ PINB7 = 7 ; Port B Input Pins bit 7 208 209 210; ***** PORTC ************************ 211; PORTC - Port C Data Register 212.equ PORTC0 = 0 ; Port C Data Register bit 0 213.equ PC0 = 0 ; For compatibility 214.equ PORTC1 = 1 ; Port C Data Register bit 1 215.equ PC1 = 1 ; For compatibility 216.equ PORTC2 = 2 ; Port C Data Register bit 2 217.equ PC2 = 2 ; For compatibility 218.equ PORTC3 = 3 ; Port C Data Register bit 3 219.equ PC3 = 3 ; For compatibility 220.equ PORTC4 = 4 ; Port C Data Register bit 4 221.equ PC4 = 4 ; For compatibility 222.equ PORTC5 = 5 ; Port C Data Register bit 5 223.equ PC5 = 5 ; For compatibility 224.equ PORTC6 = 6 ; Port C Data Register bit 6 225.equ PC6 = 6 ; For compatibility 226.equ PORTC7 = 7 ; Port C Data Register bit 7 227.equ PC7 = 7 ; For compatibility 228 229; DDRC - Port C Data Direction Register 230.equ DDC0 = 0 ; Port C Data Direction Register bit 0 231.equ DDC1 = 1 ; Port C Data Direction Register bit 1 232.equ DDC2 = 2 ; Port C Data Direction Register bit 2 233.equ DDC3 = 3 ; Port C Data Direction Register bit 3 234.equ DDC4 = 4 ; Port C Data Direction Register bit 4 235.equ DDC5 = 5 ; Port C Data Direction Register bit 5 236.equ DDC6 = 6 ; Port C Data Direction Register bit 6 237.equ DDC7 = 7 ; Port C Data Direction Register bit 7 238 239; PINC - Port C Input Pins 240.equ PINC0 = 0 ; Port C Input Pins bit 0 241.equ PINC1 = 1 ; Port C Input Pins bit 1 242.equ PINC2 = 2 ; Port C Input Pins bit 2 243.equ PINC3 = 3 ; Port C Input Pins bit 3 244.equ PINC4 = 4 ; Port C Input Pins bit 4 245.equ PINC5 = 5 ; Port C Input Pins bit 5 246.equ PINC6 = 6 ; Port C Input Pins bit 6 247.equ PINC7 = 7 ; Port C Input Pins bit 7 248 249 250; ***** PORTD ************************ 251; PORTD - Port D Data Register 252.equ PORTD0 = 0 ; Port D Data Register bit 0 253.equ PD0 = 0 ; For compatibility 254.equ PORTD1 = 1 ; Port D Data Register bit 1 255.equ PD1 = 1 ; For compatibility 256.equ PORTD2 = 2 ; Port D Data Register bit 2 257.equ PD2 = 2 ; For compatibility 258.equ PORTD3 = 3 ; Port D Data Register bit 3 259.equ PD3 = 3 ; For compatibility 260.equ PORTD4 = 4 ; Port D Data Register bit 4 261.equ PD4 = 4 ; For compatibility 262.equ PORTD5 = 5 ; Port D Data Register bit 5 263.equ PD5 = 5 ; For compatibility 264.equ PORTD6 = 6 ; Port D Data Register bit 6 265.equ PD6 = 6 ; For compatibility 266.equ PORTD7 = 7 ; Port D Data Register bit 7 267.equ PD7 = 7 ; For compatibility 268 269; DDRD - Port D Data Direction Register 270.equ DDD0 = 0 ; Port D Data Direction Register bit 0 271.equ DDD1 = 1 ; Port D Data Direction Register bit 1 272.equ DDD2 = 2 ; Port D Data Direction Register bit 2 273.equ DDD3 = 3 ; Port D Data Direction Register bit 3 274.equ DDD4 = 4 ; Port D Data Direction Register bit 4 275.equ DDD5 = 5 ; Port D Data Direction Register bit 5 276.equ DDD6 = 6 ; Port D Data Direction Register bit 6 277.equ DDD7 = 7 ; Port D Data Direction Register bit 7 278 279; PIND - Port D Input Pins 280.equ PIND0 = 0 ; Port D Input Pins bit 0 281.equ PIND1 = 1 ; Port D Input Pins bit 1 282.equ PIND2 = 2 ; Port D Input Pins bit 2 283.equ PIND3 = 3 ; Port D Input Pins bit 3 284.equ PIND4 = 4 ; Port D Input Pins bit 4 285.equ PIND5 = 5 ; Port D Input Pins bit 5 286.equ PIND6 = 6 ; Port D Input Pins bit 6 287.equ PIND7 = 7 ; Port D Input Pins bit 7 288 289 290; ***** WATCHDOG ********************* 291; WDTCR - Watchdog Timer Control Register 292.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 293.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 294.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 295.equ WDE = 3 ; Watch Dog Enable 296.equ WDTOE = 4 ; RW 297.equ WDDE = WDTOE ; For compatibility 298 299 300; ***** SPI ************************** 301; SPDR - SPI Data Register 302.equ SPDR0 = 0 ; SPI Data Register bit 0 303.equ SPDR1 = 1 ; SPI Data Register bit 1 304.equ SPDR2 = 2 ; SPI Data Register bit 2 305.equ SPDR3 = 3 ; SPI Data Register bit 3 306.equ SPDR4 = 4 ; SPI Data Register bit 4 307.equ SPDR5 = 5 ; SPI Data Register bit 5 308.equ SPDR6 = 6 ; SPI Data Register bit 6 309.equ SPDR7 = 7 ; SPI Data Register bit 7 310 311; SPSR - SPI Status Register 312.equ SPI2X = 0 ; Double SPI Speed Bit 313.equ WCOL = 6 ; Write Collision Flag 314.equ SPIF = 7 ; SPI Interrupt Flag 315 316; SPCR - SPI Control Register 317.equ SPR0 = 0 ; SPI Clock Rate Select 0 318.equ SPR1 = 1 ; SPI Clock Rate Select 1 319.equ CPHA = 2 ; Clock Phase 320.equ CPOL = 3 ; Clock polarity 321.equ MSTR = 4 ; Master/Slave Select 322.equ DORD = 5 ; Data Order 323.equ SPE = 6 ; SPI Enable 324.equ SPIE = 7 ; SPI Interrupt Enable 325 326 327; ***** USART ************************ 328; UDR - USART I/O Data Register 329.equ UDR0 = 0 ; USART I/O Data Register bit 0 330.equ UDR1 = 1 ; USART I/O Data Register bit 1 331.equ UDR2 = 2 ; USART I/O Data Register bit 2 332.equ UDR3 = 3 ; USART I/O Data Register bit 3 333.equ UDR4 = 4 ; USART I/O Data Register bit 4 334.equ UDR5 = 5 ; USART I/O Data Register bit 5 335.equ UDR6 = 6 ; USART I/O Data Register bit 6 336.equ UDR7 = 7 ; USART I/O Data Register bit 7 337 338; UCSRA - USART Control and Status Register A 339.equ USR = UCSRA ; For compatibility 340.equ MPCM = 0 ; Multi-processor Communication Mode 341.equ U2X = 1 ; Double the USART transmission speed 342.equ UPE = 2 ; Parity Error 343.equ PE = UPE ; For compatibility 344.equ DOR = 3 ; Data overRun 345.equ FE = 4 ; Framing Error 346.equ UDRE = 5 ; USART Data Register Empty 347.equ TXC = 6 ; USART Transmitt Complete 348.equ RXC = 7 ; USART Receive Complete 349 350; UCSRB - USART Control and Status Register B 351.equ UCR = UCSRB ; For compatibility 352.equ TXB8 = 0 ; Transmit Data Bit 8 353.equ RXB8 = 1 ; Receive Data Bit 8 354.equ UCSZ2 = 2 ; Character Size 355.equ CHR9 = UCSZ2 ; For compatibility 356.equ TXEN = 3 ; Transmitter Enable 357.equ RXEN = 4 ; Receiver Enable 358.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable 359.equ TXCIE = 6 ; TX Complete Interrupt Enable 360.equ RXCIE = 7 ; RX Complete Interrupt Enable 361 362; UCSRC - USART Control and Status Register C 363.equ UCPOL = 0 ; Clock Polarity 364.equ UCSZ0 = 1 ; Character Size 365.equ UCSZ1 = 2 ; Character Size 366.equ USBS = 3 ; Stop Bit Select 367.equ UPM0 = 4 ; Parity Mode Bit 0 368.equ UPM1 = 5 ; Parity Mode Bit 1 369.equ UMSEL = 6 ; USART Mode Select 370.equ URSEL = 7 ; Register Select 371 372.equ UBRRHI = UBRRH ; For compatibility 373 374; ***** AD_CONVERTER ***************** 375; ADMUX - The ADC multiplexer Selection Register 376.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 377.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 378.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 379.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 380.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits 381.equ ADLAR = 5 ; Left Adjust Result 382.equ REFS0 = 6 ; Reference Selection Bit 0 383.equ REFS1 = 7 ; Reference Selection Bit 1 384 385; ADCSR - The ADC Control and Status register 386.equ ADPS0 = 0 ; ADC Prescaler Select Bits 387.equ ADPS1 = 1 ; ADC Prescaler Select Bits 388.equ ADPS2 = 2 ; ADC Prescaler Select Bits 389.equ ADIE = 3 ; ADC Interrupt Enable 390.equ ADIF = 4 ; ADC Interrupt Flag 391.equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. 392.equ ADSC = 6 ; ADC Start Conversion 393.equ ADEN = 7 ; ADC Enable 394 395; ADCH - ADC Data Register High Byte 396.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 397.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 398.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 399.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 400.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 401.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 402.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 403.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 404 405; ADCL - ADC Data Register Low Byte 406.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 407.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 408.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 409.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 410.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 411.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 412.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 413.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 414 415 416; ***** ANALOG_COMPARATOR ************ 417; SFIOR - Special Function IO Register 418.equ ACME = 3 ; Analog Comparator Multiplexer Enable 419 420; ACSR - Analog Comparator Control And Status Register 421.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 422.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 423.equ ACIC = 2 ; Analog Comparator Input Capture Enable 424.equ ACIE = 3 ; Analog Comparator Interrupt Enable 425.equ ACI = 4 ; Analog Comparator Interrupt Flag 426.equ ACO = 5 ; Analog Compare Output 427.equ ACBG = 6 ; Analog Comparator Bandgap Select 428.equ ACD = 7 ; Analog Comparator Disable 429 430 431; ***** TWI ************************** 432; TWBR - TWI Bit Rate register 433.equ TWBR0 = 0 ; 434.equ TWBR1 = 1 ; 435.equ TWBR2 = 2 ; 436.equ TWBR3 = 3 ; 437.equ TWBR4 = 4 ; 438.equ TWBR5 = 5 ; 439.equ TWBR6 = 6 ; 440.equ TWBR7 = 7 ; 441 442; TWCR - TWI Control Register 443.equ TWIE = 0 ; TWI Interrupt Enable 444.equ TWEN = 2 ; TWI Enable Bit 445.equ TWWC = 3 ; TWI Write Collition Flag 446.equ TWSTO = 4 ; TWI Stop Condition Bit 447.equ TWSTA = 5 ; TWI Start Condition Bit 448.equ TWEA = 6 ; TWI Enable Acknowledge Bit 449.equ TWINT = 7 ; TWI Interrupt Flag 450 451; TWSR - TWI Status Register 452.equ TWS3 = 3 ; TWI Status 453.equ TWS4 = 4 ; TWI Status 454.equ TWS5 = 5 ; TWI Status 455.equ TWS6 = 6 ; TWI Status 456.equ TWS7 = 7 ; TWI Status 457 458; TWDR - TWI Data register 459.equ TWD0 = 0 ; TWI Data Register Bit 0 460.equ TWD1 = 1 ; TWI Data Register Bit 1 461.equ TWD2 = 2 ; TWI Data Register Bit 2 462.equ TWD3 = 3 ; TWI Data Register Bit 3 463.equ TWD4 = 4 ; TWI Data Register Bit 4 464.equ TWD5 = 5 ; TWI Data Register Bit 5 465.equ TWD6 = 6 ; TWI Data Register Bit 6 466.equ TWD7 = 7 ; TWI Data Register Bit 7 467 468; TWAR - TWI (Slave) Address register 469.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit 470.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 471.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 472.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 473.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 474.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 475.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 476.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 477 478 479; ***** EEPROM *********************** 480; EEDR - EEPROM Data Register 481.equ EEDR0 = 0 ; EEPROM Data Register bit 0 482.equ EEDR1 = 1 ; EEPROM Data Register bit 1 483.equ EEDR2 = 2 ; EEPROM Data Register bit 2 484.equ EEDR3 = 3 ; EEPROM Data Register bit 3 485.equ EEDR4 = 4 ; EEPROM Data Register bit 4 486.equ EEDR5 = 5 ; EEPROM Data Register bit 5 487.equ EEDR6 = 6 ; EEPROM Data Register bit 6 488.equ EEDR7 = 7 ; EEPROM Data Register bit 7 489 490; EECR - EEPROM Control Register 491.equ EERE = 0 ; EEPROM Read Enable 492.equ EEWE = 1 ; EEPROM Write Enable 493.equ EEMWE = 2 ; EEPROM Master Write Enable 494.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 495 496 497; ***** CPU ************************** 498; SREG - Status Register 499.equ SREG_C = 0 ; Carry Flag 500.equ SREG_Z = 1 ; Zero Flag 501.equ SREG_N = 2 ; Negative Flag 502.equ SREG_V = 3 ; Two's Complement Overflow Flag 503.equ SREG_S = 4 ; Sign Bit 504.equ SREG_H = 5 ; Half Carry Flag 505.equ SREG_T = 6 ; Bit Copy Storage 506.equ SREG_I = 7 ; Global Interrupt Enable 507 508; MCUCR - MCU Control Register 509.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 510.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 511.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 512.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 513.equ SM0 = 4 ; Sleep Mode Select 514.equ SM1 = 5 ; Sleep Mode Select 515.equ SM2 = 6 ; Sleep Mode Select 516.equ SE = 7 ; Sleep Enable 517 518; MCUCSR - MCU Control And Status Register 519.equ PORF = 0 ; Power-on reset flag 520.equ EXTRF = 1 ; External Reset Flag 521.equ BORF = 2 ; Brown-out Reset Flag 522.equ WDRF = 3 ; Watchdog Reset Flag 523.equ JTRF = 4 ; JTAG Reset Flag 524.equ ISC2 = 6 ; Interrupt Sense Control 2 525.equ JDT = 7 ; 526 527; OSCCAL - Oscillator Calibration Value 528.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 529.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 530.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 531.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 532.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 533.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 534.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 535.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 536 537; SPMCR - Store Program Memory Control Register 538.equ SPMEN = 0 ; Store Program Memory Enable 539.equ PGERS = 1 ; Page Erase 540.equ PGWRT = 2 ; Page Write 541.equ BLBSET = 3 542.equ ASRE = 4 ; Application Section Read Enable 543.equ ASB = 6 ; Applcaiton Section Busy 544 545; SFIOR - Special Function IO Register 546.equ PSR10 = 0 ; 547.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 548.equ PUD = 2 ; Pull-up Disable 549;.equ ACME = 3 ; 550 551 552; ***** TIMER_COUNTER_0 ************** 553; TCCR0 - Timer/Counter Control Register 554.equ CS00 = 0 ; Clock Select 1 555.equ CS01 = 1 ; Clock Select 1 556.equ CS02 = 2 ; Clock Select 2 557.equ WGM01 = 3 ; Waveform Generation Mode 1 558.equ COM00 = 4 ; Compare match Output Mode 0 559.equ COM01 = 5 ; Compare Match Output Mode 1 560.equ PWM0 = 6 ; Pulse Width Modulator Enable 561.equ FOC0 = 7 ; Force Output Compare 562 563; TCNT0 - Timer/Counter Register 564.equ TCNT0_0 = 0 ; 565.equ TCNT0_1 = 1 ; 566.equ TCNT0_2 = 2 ; 567.equ TCNT0_3 = 3 ; 568.equ TCNT0_4 = 4 ; 569.equ TCNT0_5 = 5 ; 570.equ TCNT0_6 = 6 ; 571.equ TCNT0_7 = 7 ; 572 573; OCR0 - Output Compare Register 574.equ OCR0_0 = 0 ; 575.equ OCR0_1 = 1 ; 576.equ OCR0_2 = 2 ; 577.equ OCR0_3 = 3 ; 578.equ OCR0_4 = 4 ; 579.equ OCR0_5 = 5 ; 580.equ OCR0_6 = 6 ; 581.equ OCR0_7 = 7 ; 582 583; TIMSK - Timer/Counter Interrupt Mask Register 584.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 585.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register 586 587; TIFR - Timer/Counter Interrupt Flag register 588.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 589.equ OCF0 = 1 ; Output Compare Flag 0 590 591; SFIOR - Special Function IO Register 592;.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 593 594 595; ***** EXTERNAL_INTERRUPT *********** 596; GICR - General Interrupt Control Register 597.equ GIMSK = GICR ; For compatibility 598.equ IVCE = 0 ; Interrupt Vector Change Enable 599.equ IVSEL = 1 ; Interrupt Vector Select 600.equ INT2 = 5 ; External Interrupt Request 2 Enable 601.equ INT0 = 6 ; External Interrupt Request 0 Enable 602.equ INT1 = 7 ; External Interrupt Request 1 Enable 603 604; GIFR - General Interrupt Flag Register 605.equ INTF2 = 5 ; External Interrupt Flag 2 606.equ INTF0 = 6 ; External Interrupt Flag 0 607.equ INTF1 = 7 ; External Interrupt Flag 1 608 609; MCUCR - General Interrupt Control Register 610;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 611;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 612;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 613;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 614 615; MCUCSR - MCU Control And Status Register 616;.equ ISC2 = 6 ; Interrupt Sense Control 2 617 618 619; ***** TIMER_COUNTER_1 ************** 620; TIMSK - Timer/Counter Interrupt Mask Register 621.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable 622.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable 623.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable 624.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 625 626; TIFR - Timer/Counter Interrupt Flag register 627.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag 628.equ OCF1B = 3 ; Output Compare Flag 1B 629.equ OCF1A = 4 ; Output Compare Flag 1A 630.equ ICF1 = 5 ; Input Capture Flag 1 631 632; TCCR1A - Timer/Counter1 Control Register A 633.equ WGM10 = 0 ; Waveform Generation Mode 634.equ WGM11 = 1 ; Waveform Generation Mode 635.equ FOC1B = 2 ; Force Output Compare 1B 636.equ FOC1A = 3 ; Force Output Compare 1A 637.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 638.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 639.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 640.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 641 642; TCCR1B - Timer/Counter1 Control Register B 643.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 644.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 645.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 646.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match 647.equ ICES1 = 6 ; Input Capture 1 Edge Select 648.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 649 650 651; ***** TIMER_COUNTER_2 ************** 652; TIMSK - Timer/Counter Interrupt Mask register 653.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable 654.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable 655 656; TIFR - Timer/Counter Interrupt Flag Register 657.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag 658.equ OCF2 = 7 ; Output Compare Flag 2 659 660; TCCR2 - Timer/Counter2 Control Register 661.equ CS20 = 0 ; Clock Select bit 0 662.equ CS21 = 1 ; Clock Select bit 1 663.equ CS22 = 2 ; Clock Select bit 2 664.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match 665.equ COM20 = 4 ; Compare Output Mode bit 0 666.equ COM21 = 5 ; Compare Output Mode bit 1 667.equ PWM2 = 6 ; Pulse Width Modulator Enable 668.equ FOC2 = 7 ; Force Output Compare 669 670; TCNT2 - Timer/Counter2 671.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 672.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 673.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 674.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 675.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 676.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 677.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 678.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 679 680; OCR2 - Timer/Counter2 Output Compare Register 681.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 682.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 683.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 684.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 685.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 686.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 687.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 688.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 689 690; ASSR - Asynchronous Status Register 691.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy 692.equ OCR2UB = 1 ; Output Compare Register2 Update Busy 693.equ TCN2UB = 2 ; Timer/Counter2 Update Busy 694.equ AS2 = 3 ; Asynchronous Timer/counter2 695 696 697 698; ***** LOCKSBITS ******************************************************** 699.equ LB1 = 0 ; Lock bit 700.equ LB2 = 1 ; Lock bit 701.equ BLB01 = 2 ; Boot Lock bit 702.equ BLB02 = 3 ; Boot Lock bit 703.equ BLB11 = 4 ; Boot lock bit 704.equ BLB12 = 5 ; Boot lock bit 705 706 707; ***** FUSES ************************************************************ 708; LOW fuse bits 709.equ CKSEL0 = 0 ; Select Clock Source 710.equ CKSEL1 = 1 ; Select Clock Source 711.equ CKSEL2 = 2 ; Select Clock Source 712.equ CKSEL3 = 3 ; Select Clock Source 713.equ BODEN = 6 ; Brown out detector enable 714.equ BODLEVEL = 7 ; Brown out detector trigger level 715 716; HIGH fuse bits 717.equ BOOTRST = 0 ; Select Reset Vector 718.equ BOOTSZ0 = 1 ; Select Boot Size 719.equ BOOTSZ1 = 2 ; Select Boot Size 720.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 721.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 722.equ JTAGEN = 6 ; Enable JTAG 723.equ OCDEN = 7 ; Enable OCD 724 725 726 727; ***** CPU REGISTER DEFINITIONS ***************************************** 728.def XH = r27 729.def XL = r26 730.def YH = r29 731.def YL = r28 732.def ZH = r31 733.def ZL = r30 734 735 736 737; ***** DATA MEMORY DECLARATIONS ***************************************** 738.equ FLASHEND = 0x3fff ; Note: Word address 739.equ IOEND = 0x003f 740.equ SRAM_START = 0x0060 741.equ SRAM_SIZE = 2048 742.equ RAMEND = 0x085f 743.equ XRAMEND = 0x0000 744.equ E2END = 0x03ff 745.equ EEPROMEND = 0x03ff 746.equ EEADRBITS = 10 747#pragma AVRPART MEMORY PROG_FLASH 32768 748#pragma AVRPART MEMORY EEPROM 1024 749#pragma AVRPART MEMORY INT_SRAM SIZE 2048 750#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 751 752 753 754; ***** BOOTLOADER DECLARATIONS ****************************************** 755.equ NRWW_START_ADDR = 0x0 756.equ NRWW_STOP_ADDR = 0x3fff 757.equ PAGESIZE = 64 758.equ FIRSTBOOTSTART = 0x3f00 759.equ SECONDBOOTSTART = 0x3e00 760.equ THIRDBOOTSTART = 0x3c00 761.equ FOURTHBOOTSTART = 0x3800 762.equ SMALLBOOTSTART = FIRSTBOOTSTART 763.equ LARGEBOOTSTART = FOURTHBOOTSTART 764 765 766 767; ***** INTERRUPT VECTORS ************************************************ 768.equ INT0addr = 0x0002 ; External Interrupt Request 0 769.equ INT1addr = 0x0004 ; External Interrupt Request 1 770.equ INT2addr = 0x0006 ; External Interrupt Request 2 771.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match 772.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow 773.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event 774.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A 775.equ OC1Baddr = 0x0010 ; Timer/Counter1 Compare Match B 776.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow 777.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match 778.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow 779.equ SPIaddr = 0x0018 ; Serial Transfer Complete 780.equ URXCaddr = 0x001a ; USART, Rx Complete 781.equ UDREaddr = 0x001c ; USART Data Register Empty 782.equ UTXCaddr = 0x001e ; USART, Tx Complete 783.equ ADCCaddr = 0x0020 ; ADC Conversion Complete 784.equ ERDYaddr = 0x0022 ; EEPROM Ready 785.equ ACIaddr = 0x0024 ; Analog Comparator 786.equ TWIaddr = 0x0026 ; 2-wire Serial Interface 787.equ SPMRaddr = 0x0028 ; Store Program Memory Ready 788 789.equ INT_VECTORS_SIZE = 42 ; size in words 790 791#endif /* _M323DEF_INC_ */ 792 793; ***** END OF FILE ****************************************************** 794