1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2005-01-11 10:31 ******* Source: ATmega3290.xml ********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "m3290def.inc" 8;* Title : Register/Bit Definitions for the ATmega3290 9;* Date : 2005-01-11 10;* Version : 2.14 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATmega3290 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _M3290DEF_INC_ 41#define _M3290DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATmega3290 48#pragma AVRPART ADMIN PART_NAME ATmega3290 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x95 51.equ SIGNATURE_002 = 0x04 52 53#pragma AVRPART CORE CORE_VERSION V2E 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ LCDDR19 = 0xff ; MEMORY MAPPED 61.equ LCDDR18 = 0xfe ; MEMORY MAPPED 62.equ LCDDR17 = 0xfd ; MEMORY MAPPED 63.equ LCDDR16 = 0xfc ; MEMORY MAPPED 64.equ LCDDR15 = 0xfb ; MEMORY MAPPED 65.equ LCDDR14 = 0xfa ; MEMORY MAPPED 66.equ LCDDR13 = 0xf9 ; MEMORY MAPPED 67.equ LCDDR12 = 0xf8 ; MEMORY MAPPED 68.equ LCDDR11 = 0xf7 ; MEMORY MAPPED 69.equ LCDDR10 = 0xf6 ; MEMORY MAPPED 70.equ LCDDR9 = 0xf5 ; MEMORY MAPPED 71.equ LCDDR8 = 0xf4 ; MEMORY MAPPED 72.equ LCDDR7 = 0xf3 ; MEMORY MAPPED 73.equ LCDDR6 = 0xf2 ; MEMORY MAPPED 74.equ LCDDR5 = 0xf1 ; MEMORY MAPPED 75.equ LCDDR4 = 0xf0 ; MEMORY MAPPED 76.equ LCDDR3 = 0xef ; MEMORY MAPPED 77.equ LCDDR2 = 0xee ; MEMORY MAPPED 78.equ LCDDR1 = 0xed ; MEMORY MAPPED 79.equ LCDDR0 = 0xec ; MEMORY MAPPED 80.equ LCDCCR = 0xe7 ; MEMORY MAPPED 81.equ LCDFRR = 0xe6 ; MEMORY MAPPED 82.equ LCDCRB = 0xe5 ; MEMORY MAPPED 83.equ LCDCRA = 0xe4 ; MEMORY MAPPED 84.equ PORTJ = 0xdd ; MEMORY MAPPED 85.equ DDRJ = 0xdc ; MEMORY MAPPED 86.equ PINJ = 0xdb ; MEMORY MAPPED 87.equ PORTH = 0xda ; MEMORY MAPPED 88.equ DDRH = 0xd9 ; MEMORY MAPPED 89.equ PINH = 0xd8 ; MEMORY MAPPED 90.equ UDR = 0xc6 ; MEMORY MAPPED 91.equ UBRRH = 0xc5 ; MEMORY MAPPED 92.equ UBRRL = 0xc4 ; MEMORY MAPPED 93.equ UCSRC = 0xc2 ; MEMORY MAPPED 94.equ UCSRB = 0xc1 ; MEMORY MAPPED 95.equ UCSRA = 0xc0 ; MEMORY MAPPED 96.equ USIDR = 0xba ; MEMORY MAPPED 97.equ USISR = 0xb9 ; MEMORY MAPPED 98.equ USICR = 0xb8 ; MEMORY MAPPED 99.equ ASSR = 0xb6 ; MEMORY MAPPED 100.equ OCR2A = 0xb3 ; MEMORY MAPPED 101.equ TCNT2 = 0xb2 ; MEMORY MAPPED 102.equ TCCR2A = 0xb0 ; MEMORY MAPPED 103.equ OCR1BH = 0x8b ; MEMORY MAPPED 104.equ OCR1BL = 0x8a ; MEMORY MAPPED 105.equ OCR1AH = 0x89 ; MEMORY MAPPED 106.equ OCR1AL = 0x88 ; MEMORY MAPPED 107.equ ICR1H = 0x87 ; MEMORY MAPPED 108.equ ICR1L = 0x86 ; MEMORY MAPPED 109.equ TCNT1H = 0x85 ; MEMORY MAPPED 110.equ TCNT1L = 0x84 ; MEMORY MAPPED 111.equ TCCR1C = 0x82 ; MEMORY MAPPED 112.equ TCCR1B = 0x81 ; MEMORY MAPPED 113.equ TCCR1A = 0x80 ; MEMORY MAPPED 114.equ DIDR1 = 0x7f ; MEMORY MAPPED 115.equ DIDR0 = 0x7e ; MEMORY MAPPED 116.equ ADMUX = 0x7c ; MEMORY MAPPED 117.equ ADCSRB = 0x7b ; MEMORY MAPPED 118.equ ADCSRA = 0x7a ; MEMORY MAPPED 119.equ ADCH = 0x79 ; MEMORY MAPPED 120.equ ADCL = 0x78 ; MEMORY MAPPED 121.equ PCMSK3 = 0x73 ; MEMORY MAPPED 122.equ TIMSK2 = 0x70 ; MEMORY MAPPED 123.equ TIMSK1 = 0x6f ; MEMORY MAPPED 124.equ TIMSK0 = 0x6e ; MEMORY MAPPED 125.equ PCMSK2 = 0x6d ; MEMORY MAPPED 126.equ PCMSK1 = 0x6c ; MEMORY MAPPED 127.equ PCMSK0 = 0x6b ; MEMORY MAPPED 128.equ EICRA = 0x69 ; MEMORY MAPPED 129.equ OSCCAL = 0x66 ; MEMORY MAPPED 130.equ PRR = 0x64 ; MEMORY MAPPED 131.equ CLKPR = 0x61 ; MEMORY MAPPED 132.equ WDTCR = 0x60 ; MEMORY MAPPED 133.equ SREG = 0x3f 134.equ SPH = 0x3e 135.equ SPL = 0x3d 136.equ SPMCSR = 0x37 137.equ MCUCR = 0x35 138.equ MCUSR = 0x34 139.equ SMCR = 0x33 140.equ OCDR = 0x31 141.equ ACSR = 0x30 142.equ SPDR = 0x2e 143.equ SPSR = 0x2d 144.equ SPCR = 0x2c 145.equ GPIOR2 = 0x2b 146.equ GPIOR1 = 0x2a 147.equ OCR0A = 0x27 148.equ TCNT0 = 0x26 149.equ TCCR0A = 0x24 150.equ GTCCR = 0x23 151.equ EEARH = 0x22 152.equ EEARL = 0x21 153.equ EEDR = 0x20 154.equ EECR = 0x1f 155.equ GPIOR0 = 0x1e 156.equ EIMSK = 0x1d 157.equ EIFR = 0x1c 158.equ TIFR2 = 0x17 159.equ TIFR1 = 0x16 160.equ TIFR0 = 0x15 161.equ PORTG = 0x14 162.equ DDRG = 0x13 163.equ PING = 0x12 164.equ PORTF = 0x11 165.equ DDRF = 0x10 166.equ PINF = 0x0f 167.equ PORTE = 0x0e 168.equ DDRE = 0x0d 169.equ PINE = 0x0c 170.equ PORTD = 0x0b 171.equ DDRD = 0x0a 172.equ PIND = 0x09 173.equ PORTC = 0x08 174.equ DDRC = 0x07 175.equ PINC = 0x06 176.equ PORTB = 0x05 177.equ DDRB = 0x04 178.equ PINB = 0x03 179.equ PORTA = 0x02 180.equ DDRA = 0x01 181.equ PINA = 0x00 182 183 184; ***** BIT DEFINITIONS ************************************************** 185 186; ***** TIMER_COUNTER_0 ************** 187; TCCR0A - Timer/Counter0 Control Register 188.equ CS00 = 0 ; Clock Select 1 189.equ CS01 = 1 ; Clock Select 1 190.equ CS02 = 2 ; Clock Select 2 191.equ WGM01 = 3 ; Waveform Generation Mode 1 192.equ COM0A0 = 4 ; Compare match Output Mode 0 193.equ COM0A1 = 5 ; Compare Match Output Mode 1 194.equ WGM00 = 6 ; Waveform Generation Mode 0 195.equ FOC0A = 7 ; Force Output Compare 196 197; TCNT0 - Timer/Counter0 198.equ TCNT0_0 = 0 ; 199.equ TCNT0_1 = 1 ; 200.equ TCNT0_2 = 2 ; 201.equ TCNT0_3 = 3 ; 202.equ TCNT0_4 = 4 ; 203.equ TCNT0_5 = 5 ; 204.equ TCNT0_6 = 6 ; 205.equ TCNT0_7 = 7 ; 206 207; OCR0A - Timer/Counter0 Output Compare Register 208.equ OCR0A0 = 0 ; 209.equ OCR0A1 = 1 ; 210.equ OCR0A2 = 2 ; 211.equ OCR0A3 = 3 ; 212.equ OCR0A4 = 4 ; 213.equ OCR0A5 = 5 ; 214.equ OCR0A6 = 6 ; 215.equ OCR0A7 = 7 ; 216 217; TIMSK0 - Timer/Counter0 Interrupt Mask Register 218.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable 219.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable 220 221; TIFR0 - Timer/Counter0 Interrupt Flag register 222.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag 223.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 224 225; GTCCR - General Timer/Control Register 226.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 227.equ PSR10 = PSR310 ; For compatibility 228.equ PSR0 = PSR310 ; For compatibility 229.equ PSR1 = PSR310 ; For compatibility 230.equ PSR3 = PSR310 ; For compatibility 231.equ TSM = 7 ; Timer/Counter Synchronization Mode 232 233 234; ***** TIMER_COUNTER_1 ************** 235; TIMSK1 - Timer/Counter1 Interrupt Mask Register 236.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 237.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable 238.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable 239.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable 240 241; TIFR1 - Timer/Counter1 Interrupt Flag register 242.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 243.equ OCF1A = 1 ; Output Compare Flag 1A 244.equ OCF1B = 2 ; Output Compare Flag 1B 245.equ ICF1 = 5 ; Input Capture Flag 1 246 247; TCCR1A - Timer/Counter1 Control Register A 248.equ WGM10 = 0 ; Waveform Generation Mode 249.equ WGM11 = 1 ; Waveform Generation Mode 250.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 251.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 252.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 253.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 254 255; TCCR1B - Timer/Counter1 Control Register B 256.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 257.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 258.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 259.equ WGM12 = 3 ; Waveform Generation Mode 260.equ WGM13 = 4 ; Waveform Generation Mode 261.equ ICES1 = 6 ; Input Capture 1 Edge Select 262.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler 263 264; TCCR1C - Timer/Counter 1 Control Register C 265.equ FOC1B = 6 ; Force Output Compare 1B 266.equ FOC1A = 7 ; Force Output Compare 1A 267 268 269; ***** TIMER_COUNTER_2 ************** 270; TIMSK2 - Timer/Counter2 Interrupt Mask register 271.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable 272.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable 273 274; TIFR2 - Timer/Counter2 Interrupt Flag Register 275.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag 276.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 277 278; TCCR2A - Timer/Counter2 Control Register 279.equ CS20 = 0 ; Clock Select bit 0 280.equ CS21 = 1 ; Clock Select bit 1 281.equ CS22 = 2 ; Clock Select bit 2 282.equ WGM21 = 3 ; Waveform Generation Mode 283.equ COM2A0 = 4 ; Compare Output Mode bit 0 284.equ COM2A1 = 5 ; Compare Output Mode bit 1 285.equ WGM20 = 6 ; Waveform Generation Mode 286.equ FOC2A = 7 ; Force Output Compare A 287 288; TCNT2 - Timer/Counter2 289.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 290.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 291.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 292.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 293.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 294.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 295.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 296.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 297 298; OCR2A - Timer/Counter2 Output Compare Register 299.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 300.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 301.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 302.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 303.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 304.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 305.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 306.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 307 308; GTCCR - General Timer/Counter Control Register 309.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 310 311; ASSR - Asynchronous Status Register 312.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy 313.equ OCR2UB = 1 ; Output Compare Register2 Update Busy 314.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy 315.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 316.equ EXCLK = 4 ; Enable External Clock Interrupt 317 318 319; ***** WATCHDOG ********************* 320; WDTCR - Watchdog Timer Control Register 321.equ WDTCSR = WDTCR ; For compatibility 322.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 323.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 324.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 325.equ WDE = 3 ; Watch Dog Enable 326.equ WDCE = 4 ; Watchdog Change Enable 327.equ WDTOE = WDCE ; For compatibility 328 329 330; ***** EEPROM *********************** 331; EEDR - EEPROM Data Register 332.equ EEDR0 = 0 ; EEPROM Data Register bit 0 333.equ EEDR1 = 1 ; EEPROM Data Register bit 1 334.equ EEDR2 = 2 ; EEPROM Data Register bit 2 335.equ EEDR3 = 3 ; EEPROM Data Register bit 3 336.equ EEDR4 = 4 ; EEPROM Data Register bit 4 337.equ EEDR5 = 5 ; EEPROM Data Register bit 5 338.equ EEDR6 = 6 ; EEPROM Data Register bit 6 339.equ EEDR7 = 7 ; EEPROM Data Register bit 7 340 341; EECR - EEPROM Control Register 342.equ EERE = 0 ; EEPROM Read Enable 343.equ EEWE = 1 ; EEPROM Write Enable 344.equ EEMWE = 2 ; EEPROM Master Write Enable 345.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 346 347 348; ***** SPI ************************** 349; SPDR - SPI Data Register 350.equ SPDR0 = 0 ; SPI Data Register bit 0 351.equ SPDR1 = 1 ; SPI Data Register bit 1 352.equ SPDR2 = 2 ; SPI Data Register bit 2 353.equ SPDR3 = 3 ; SPI Data Register bit 3 354.equ SPDR4 = 4 ; SPI Data Register bit 4 355.equ SPDR5 = 5 ; SPI Data Register bit 5 356.equ SPDR6 = 6 ; SPI Data Register bit 6 357.equ SPDR7 = 7 ; SPI Data Register bit 7 358 359; SPSR - SPI Status Register 360.equ SPI2X = 0 ; Double SPI Speed Bit 361.equ WCOL = 6 ; Write Collision Flag 362.equ SPIF = 7 ; SPI Interrupt Flag 363 364; SPCR - SPI Control Register 365.equ SPR0 = 0 ; SPI Clock Rate Select 0 366.equ SPR1 = 1 ; SPI Clock Rate Select 1 367.equ CPHA = 2 ; Clock Phase 368.equ CPOL = 3 ; Clock polarity 369.equ MSTR = 4 ; Master/Slave Select 370.equ DORD = 5 ; Data Order 371.equ SPE = 6 ; SPI Enable 372.equ SPIE = 7 ; SPI Interrupt Enable 373 374 375; ***** PORTA ************************ 376; PORTA - Port A Data Register 377.equ PORTA0 = 0 ; Port A Data Register bit 0 378.equ PA0 = 0 ; For compatibility 379.equ PORTA1 = 1 ; Port A Data Register bit 1 380.equ PA1 = 1 ; For compatibility 381.equ PORTA2 = 2 ; Port A Data Register bit 2 382.equ PA2 = 2 ; For compatibility 383.equ PORTA3 = 3 ; Port A Data Register bit 3 384.equ PA3 = 3 ; For compatibility 385.equ PORTA4 = 4 ; Port A Data Register bit 4 386.equ PA4 = 4 ; For compatibility 387.equ PORTA5 = 5 ; Port A Data Register bit 5 388.equ PA5 = 5 ; For compatibility 389.equ PORTA6 = 6 ; Port A Data Register bit 6 390.equ PA6 = 6 ; For compatibility 391.equ PORTA7 = 7 ; Port A Data Register bit 7 392.equ PA7 = 7 ; For compatibility 393 394; DDRA - Port A Data Direction Register 395.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 396.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 397.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 398.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 399.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 400.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 401.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 402.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 403 404; PINA - Port A Input Pins 405.equ PINA0 = 0 ; Input Pins, Port A bit 0 406.equ PINA1 = 1 ; Input Pins, Port A bit 1 407.equ PINA2 = 2 ; Input Pins, Port A bit 2 408.equ PINA3 = 3 ; Input Pins, Port A bit 3 409.equ PINA4 = 4 ; Input Pins, Port A bit 4 410.equ PINA5 = 5 ; Input Pins, Port A bit 5 411.equ PINA6 = 6 ; Input Pins, Port A bit 6 412.equ PINA7 = 7 ; Input Pins, Port A bit 7 413 414 415; ***** PORTB ************************ 416; PORTB - Port B Data Register 417.equ PORTB0 = 0 ; Port B Data Register bit 0 418.equ PB0 = 0 ; For compatibility 419.equ PORTB1 = 1 ; Port B Data Register bit 1 420.equ PB1 = 1 ; For compatibility 421.equ PORTB2 = 2 ; Port B Data Register bit 2 422.equ PB2 = 2 ; For compatibility 423.equ PORTB3 = 3 ; Port B Data Register bit 3 424.equ PB3 = 3 ; For compatibility 425.equ PORTB4 = 4 ; Port B Data Register bit 4 426.equ PB4 = 4 ; For compatibility 427.equ PORTB5 = 5 ; Port B Data Register bit 5 428.equ PB5 = 5 ; For compatibility 429.equ PORTB6 = 6 ; Port B Data Register bit 6 430.equ PB6 = 6 ; For compatibility 431.equ PORTB7 = 7 ; Port B Data Register bit 7 432.equ PB7 = 7 ; For compatibility 433 434; DDRB - Port B Data Direction Register 435.equ DDB0 = 0 ; Port B Data Direction Register bit 0 436.equ DDB1 = 1 ; Port B Data Direction Register bit 1 437.equ DDB2 = 2 ; Port B Data Direction Register bit 2 438.equ DDB3 = 3 ; Port B Data Direction Register bit 3 439.equ DDB4 = 4 ; Port B Data Direction Register bit 4 440.equ DDB5 = 5 ; Port B Data Direction Register bit 5 441.equ DDB6 = 6 ; Port B Data Direction Register bit 6 442.equ DDB7 = 7 ; Port B Data Direction Register bit 7 443 444; PINB - Port B Input Pins 445.equ PINB0 = 0 ; Port B Input Pins bit 0 446.equ PINB1 = 1 ; Port B Input Pins bit 1 447.equ PINB2 = 2 ; Port B Input Pins bit 2 448.equ PINB3 = 3 ; Port B Input Pins bit 3 449.equ PINB4 = 4 ; Port B Input Pins bit 4 450.equ PINB5 = 5 ; Port B Input Pins bit 5 451.equ PINB6 = 6 ; Port B Input Pins bit 6 452.equ PINB7 = 7 ; Port B Input Pins bit 7 453 454 455; ***** PORTC ************************ 456; PORTC - Port C Data Register 457.equ PORTC0 = 0 ; Port C Data Register bit 0 458.equ PC0 = 0 ; For compatibility 459.equ PORTC1 = 1 ; Port C Data Register bit 1 460.equ PC1 = 1 ; For compatibility 461.equ PORTC2 = 2 ; Port C Data Register bit 2 462.equ PC2 = 2 ; For compatibility 463.equ PORTC3 = 3 ; Port C Data Register bit 3 464.equ PC3 = 3 ; For compatibility 465.equ PORTC4 = 4 ; Port C Data Register bit 4 466.equ PC4 = 4 ; For compatibility 467.equ PORTC5 = 5 ; Port C Data Register bit 5 468.equ PC5 = 5 ; For compatibility 469.equ PORTC6 = 6 ; Port C Data Register bit 6 470.equ PC6 = 6 ; For compatibility 471.equ PORTC7 = 7 ; Port C Data Register bit 7 472.equ PC7 = 7 ; For compatibility 473 474; DDRC - Port C Data Direction Register 475.equ DDC0 = 0 ; Port C Data Direction Register bit 0 476.equ DDC1 = 1 ; Port C Data Direction Register bit 1 477.equ DDC2 = 2 ; Port C Data Direction Register bit 2 478.equ DDC3 = 3 ; Port C Data Direction Register bit 3 479.equ DDC4 = 4 ; Port C Data Direction Register bit 4 480.equ DDC5 = 5 ; Port C Data Direction Register bit 5 481.equ DDC6 = 6 ; Port C Data Direction Register bit 6 482.equ DDC7 = 7 ; Port C Data Direction Register bit 7 483 484; PINC - Port C Input Pins 485.equ PINC0 = 0 ; Port C Input Pins bit 0 486.equ PINC1 = 1 ; Port C Input Pins bit 1 487.equ PINC2 = 2 ; Port C Input Pins bit 2 488.equ PINC3 = 3 ; Port C Input Pins bit 3 489.equ PINC4 = 4 ; Port C Input Pins bit 4 490.equ PINC5 = 5 ; Port C Input Pins bit 5 491.equ PINC6 = 6 ; Port C Input Pins bit 6 492.equ PINC7 = 7 ; Port C Input Pins bit 7 493 494 495; ***** PORTD ************************ 496; PORTD - Port D Data Register 497.equ PORTD0 = 0 ; Port D Data Register bit 0 498.equ PD0 = 0 ; For compatibility 499.equ PORTD1 = 1 ; Port D Data Register bit 1 500.equ PD1 = 1 ; For compatibility 501.equ PORTD2 = 2 ; Port D Data Register bit 2 502.equ PD2 = 2 ; For compatibility 503.equ PORTD3 = 3 ; Port D Data Register bit 3 504.equ PD3 = 3 ; For compatibility 505.equ PORTD4 = 4 ; Port D Data Register bit 4 506.equ PD4 = 4 ; For compatibility 507.equ PORTD5 = 5 ; Port D Data Register bit 5 508.equ PD5 = 5 ; For compatibility 509.equ PORTD6 = 6 ; Port D Data Register bit 6 510.equ PD6 = 6 ; For compatibility 511.equ PORTD7 = 7 ; Port D Data Register bit 7 512.equ PD7 = 7 ; For compatibility 513 514; DDRD - Port D Data Direction Register 515.equ DDD0 = 0 ; Port D Data Direction Register bit 0 516.equ DDD1 = 1 ; Port D Data Direction Register bit 1 517.equ DDD2 = 2 ; Port D Data Direction Register bit 2 518.equ DDD3 = 3 ; Port D Data Direction Register bit 3 519.equ DDD4 = 4 ; Port D Data Direction Register bit 4 520.equ DDD5 = 5 ; Port D Data Direction Register bit 5 521.equ DDD6 = 6 ; Port D Data Direction Register bit 6 522.equ DDD7 = 7 ; Port D Data Direction Register bit 7 523 524; PIND - Port D Input Pins 525.equ PIND0 = 0 ; Port D Input Pins bit 0 526.equ PIND1 = 1 ; Port D Input Pins bit 1 527.equ PIND2 = 2 ; Port D Input Pins bit 2 528.equ PIND3 = 3 ; Port D Input Pins bit 3 529.equ PIND4 = 4 ; Port D Input Pins bit 4 530.equ PIND5 = 5 ; Port D Input Pins bit 5 531.equ PIND6 = 6 ; Port D Input Pins bit 6 532.equ PIND7 = 7 ; Port D Input Pins bit 7 533 534 535; ***** ANALOG_COMPARATOR ************ 536; ADCSRB - ADC Control and Status Register B 537.equ ACME = 6 ; Analog Comparator Multiplexer Enable 538 539; ACSR - Analog Comparator Control And Status Register 540.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 541.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 542.equ ACIC = 2 ; Analog Comparator Input Capture Enable 543.equ ACIE = 3 ; Analog Comparator Interrupt Enable 544.equ ACI = 4 ; Analog Comparator Interrupt Flag 545.equ ACO = 5 ; Analog Compare Output 546.equ ACBG = 6 ; Analog Comparator Bandgap Select 547.equ ACD = 7 ; Analog Comparator Disable 548 549; DIDR1 - Digital Input Disable Register 1 550.equ AIN0D = 0 ; AIN0 Digital Input Disable 551.equ AIN1D = 1 ; AIN1 Digital Input Disable 552 553 554; ***** PORTE ************************ 555; PORTE - Data Register, Port E 556.equ PORTE0 = 0 ; 557.equ PE0 = 0 ; For compatibility 558.equ PORTE1 = 1 ; 559.equ PE1 = 1 ; For compatibility 560.equ PORTE2 = 2 ; 561.equ PE2 = 2 ; For compatibility 562.equ PORTE3 = 3 ; 563.equ PE3 = 3 ; For compatibility 564.equ PORTE4 = 4 ; 565.equ PE4 = 4 ; For compatibility 566.equ PORTE5 = 5 ; 567.equ PE5 = 5 ; For compatibility 568.equ PORTE6 = 6 ; 569.equ PE6 = 6 ; For compatibility 570.equ PORTE7 = 7 ; 571.equ PE7 = 7 ; For compatibility 572 573; DDRE - Data Direction Register, Port E 574.equ DDE0 = 0 ; 575.equ DDE1 = 1 ; 576.equ DDE2 = 2 ; 577.equ DDE3 = 3 ; 578.equ DDE4 = 4 ; 579.equ DDE5 = 5 ; 580.equ DDE6 = 6 ; 581.equ DDE7 = 7 ; 582 583; PINE - Input Pins, Port E 584.equ PINE0 = 0 ; 585.equ PINE1 = 1 ; 586.equ PINE2 = 2 ; 587.equ PINE3 = 3 ; 588.equ PINE4 = 4 ; 589.equ PINE5 = 5 ; 590.equ PINE6 = 6 ; 591.equ PINE7 = 7 ; 592 593 594; ***** PORTF ************************ 595; PORTF - Data Register, Port F 596.equ PORTF0 = 0 ; 597.equ PF0 = 0 ; For compatibility 598.equ PORTF1 = 1 ; 599.equ PF1 = 1 ; For compatibility 600.equ PORTF2 = 2 ; 601.equ PF2 = 2 ; For compatibility 602.equ PORTF3 = 3 ; 603.equ PF3 = 3 ; For compatibility 604.equ PORTF4 = 4 ; 605.equ PF4 = 4 ; For compatibility 606.equ PORTF5 = 5 ; 607.equ PF5 = 5 ; For compatibility 608.equ PORTF6 = 6 ; 609.equ PF6 = 6 ; For compatibility 610.equ PORTF7 = 7 ; 611.equ PF7 = 7 ; For compatibility 612 613; DDRF - Data Direction Register, Port F 614.equ DDF0 = 0 ; 615.equ DDF1 = 1 ; 616.equ DDF2 = 2 ; 617.equ DDF3 = 3 ; 618.equ DDF4 = 4 ; 619.equ DDF5 = 5 ; 620.equ DDF6 = 6 ; 621.equ DDF7 = 7 ; 622 623; PINF - Input Pins, Port F 624.equ PINF0 = 0 ; 625.equ PINF1 = 1 ; 626.equ PINF2 = 2 ; 627.equ PINF3 = 3 ; 628.equ PINF4 = 4 ; 629.equ PINF5 = 5 ; 630.equ PINF6 = 6 ; 631.equ PINF7 = 7 ; 632 633 634; ***** PORTG ************************ 635; PORTG - Port G Data Register 636.equ PORTG0 = 0 ; 637.equ PG0 = 0 ; For compatibility 638.equ PORTG1 = 1 ; 639.equ PG1 = 1 ; For compatibility 640.equ PORTG2 = 2 ; 641.equ PG2 = 2 ; For compatibility 642.equ PORTG3 = 3 ; 643.equ PG3 = 3 ; For compatibility 644.equ PORTG4 = 4 ; 645.equ PG4 = 4 ; For compatibility 646 647; DDRG - Port G Data Direction Register 648.equ DDG0 = 0 ; 649.equ DDG1 = 1 ; 650.equ DDG2 = 2 ; 651.equ DDG3 = 3 ; 652.equ DDG4 = 4 ; 653 654; PING - Port G Input Pins 655.equ PING0 = 0 ; 656.equ PING1 = 1 ; 657.equ PING2 = 2 ; 658.equ PING3 = 3 ; 659.equ PING4 = 4 ; 660.equ PING5 = 5 ; 661 662 663; ***** JTAG ************************* 664; OCDR - On-Chip Debug Related Register in I/O Memory 665.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 666.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 667.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 668.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 669.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 670.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 671.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 672.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 673.equ IDRD = OCDR7 ; For compatibility 674 675; MCUCR - MCU Control Register 676.equ JTD = 7 ; JTAG Interface Disable 677 678; MCUSR - MCU Status Register 679.equ JTRF = 4 ; JTAG Reset Flag 680 681 682; ***** MISC ************************* 683; LCDCRA - LCD Control and Status Register A 684.equ LCDBL = 0 ; LCD Blanking 685.equ LCDIE = 3 ; LCD Interrupt Enable 686.equ LCDIF = 4 ; LCD Interrupt Flag 687.equ LCDAB = 6 ; LCD A or B waveform 688.equ LCDEN = 7 ; LCD Enable 689 690; LCDCRB - LCD Control and Status Register B 691.equ LCDPM0 = 0 ; LCD Port Mask 0 692.equ LCDPM1 = 1 ; LCD Port Mask 1 693.equ LCDPM2 = 2 ; LCD Port Mask 2 694.equ LCDPM3 = 3 ; LCD Port Mask 3 695.equ LCDMUX0 = 4 ; LCD Mux Select 0 696.equ LCDMUX1 = 5 ; LCD Mux Select 1 697.equ LCD2B = 6 ; LCD 1/2 Bias Select 698.equ LCDCS = 7 ; LCD CLock Select 699 700; LCDFRR - LCD Frame Rate Register 701.equ LCDCD0 = 0 ; LCD Clock Divider 0 702.equ LCDCD1 = 1 ; LCD Clock Divider 1 703.equ LCDCD2 = 2 ; LCD Clock Divider 2 704.equ LCDPS0 = 4 ; LCD Prescaler Select 0 705.equ LCDPS1 = 5 ; LCD Prescaler Select 1 706.equ LCDPS2 = 6 ; LCD Prescaler Select 2 707 708; LCDCCR - LCD Contrast Control Register 709.equ LCDCC0 = 0 ; LCD Contrast Control 0 710.equ LCDCC1 = 1 ; LCD Contrast Control 1 711.equ LCDCC2 = 2 ; LCD Contrast Control 2 712.equ LCDCC3 = 3 ; LCD Contrast Control 3 713.equ LCDDC0 = 5 ; LCD Display Configuration 0 714.equ LCDDC1 = 6 ; LCD Display Configuration 1 715.equ LCDDC2 = 7 ; LCD Display Configuration 2 716 717; LCDDR19 - LCD Data Register 19 718.equ SEG332 = 0 ; 719.equ SEG333 = 1 ; 720.equ SEG334 = 2 ; 721.equ SEG335 = 3 ; 722.equ SEG336 = 4 ; 723.equ SEG337 = 5 ; 724.equ SEG338 = 6 ; 725.equ SEG339 = 7 ; 726 727; LCDDR18 - LCD Data Register 18 728.equ SEG324 = 0 ; 729.equ SEG325 = 1 ; 730.equ SEG326 = 2 ; 731.equ SEG327 = 3 ; 732.equ SEG328 = 4 ; 733.equ SEG329 = 5 ; 734.equ SEG330 = 6 ; 735.equ SEG331 = 7 ; 736 737; LCDDR17 - LCD Data Register 17 738.equ SEG316 = 0 ; 739.equ SEG317 = 1 ; 740.equ SEG318 = 2 ; 741.equ SEG319 = 3 ; 742.equ SEG320 = 4 ; 743.equ SEG321 = 5 ; 744.equ SEG322 = 6 ; 745.equ SEG323 = 7 ; 746 747; LCDDR16 - LCD Data Register 16 748.equ SEG308 = 0 ; 749.equ SEG309 = 1 ; 750.equ SEG310 = 2 ; 751.equ SEG311 = 3 ; 752.equ SEG312 = 4 ; 753.equ SEG313 = 5 ; 754.equ SEG314 = 6 ; 755.equ SEG315 = 7 ; 756 757; LCDDR15 - LCD Data Register 15 758.equ SEG300 = 0 ; 759.equ SEG301 = 1 ; 760.equ SEG302 = 2 ; 761.equ SEG303 = 3 ; 762.equ SEG304 = 4 ; 763.equ SEG305 = 5 ; 764.equ SEG306 = 6 ; 765.equ SEG307 = 7 ; 766 767; LCDDR14 - LCD Data Register 14 768.equ SEG232 = 0 ; 769.equ SEG233 = 1 ; 770.equ SEG234 = 2 ; 771.equ SEG235 = 3 ; 772.equ SEG236 = 4 ; 773.equ SEG237 = 5 ; 774.equ SEG238 = 6 ; 775.equ SEG239 = 7 ; 776 777; LCDDR13 - LCD Data Register 13 778.equ SEG224 = 0 ; 779.equ SEG225 = 1 ; 780.equ SEG226 = 2 ; 781.equ SEG227 = 3 ; 782.equ SEG228 = 4 ; 783.equ SEG229 = 5 ; 784.equ SEG230 = 6 ; 785.equ SEG231 = 7 ; 786 787; LCDDR12 - LCD Data Register 12 788.equ SEG216 = 0 ; 789.equ SEG217 = 1 ; 790.equ SEG218 = 2 ; 791.equ SEG219 = 3 ; 792.equ SEG220 = 4 ; 793.equ SEG221 = 5 ; 794.equ SEG222 = 6 ; 795.equ SEG223 = 7 ; 796 797; LCDDR11 - LCD Data Register 11 798.equ SEG208 = 0 ; 799.equ SEG209 = 1 ; 800.equ SEG210 = 2 ; 801.equ SEG211 = 3 ; 802.equ SEG212 = 4 ; 803.equ SEG213 = 5 ; 804.equ SEG214 = 6 ; 805.equ SEG215 = 7 ; 806 807; LCDDR10 - LCD Data Register 10 808.equ SEG200 = 0 ; 809.equ SEG201 = 1 ; 810.equ SEG202 = 2 ; 811.equ SEG203 = 3 ; 812.equ SEG204 = 4 ; 813.equ SEG205 = 5 ; 814.equ SEG206 = 6 ; 815.equ SEG207 = 7 ; 816 817; LCDDR9 - LCD Data Register 9 818.equ SEG132 = 0 ; 819.equ SEG133 = 1 ; 820.equ SEG134 = 2 ; 821.equ SEG135 = 3 ; 822.equ SEG136 = 4 ; 823.equ SEG137 = 5 ; 824.equ SEG138 = 6 ; 825.equ SEG139 = 7 ; 826 827; LCDDR8 - LCD Data Register 8 828.equ SEG124 = 0 ; 829.equ SEG125 = 1 ; 830.equ SEG126 = 2 ; 831.equ SEG127 = 3 ; 832.equ SEG128 = 4 ; 833.equ SEG129 = 5 ; 834.equ SEG130 = 6 ; 835.equ SEG131 = 7 ; 836 837; LCDDR7 - LCD Data Register 7 838.equ SEG116 = 0 ; 839.equ SEG117 = 1 ; 840.equ SEG118 = 2 ; 841.equ SEG119 = 3 ; 842.equ SEG120 = 4 ; 843.equ SEG121 = 5 ; 844.equ SEG122 = 6 ; 845.equ SEG123 = 7 ; 846 847; LCDDR6 - LCD Data Register 6 848.equ SEG108 = 0 ; 849.equ SEG109 = 1 ; 850.equ SEG110 = 2 ; 851.equ SEG111 = 3 ; 852.equ SEG112 = 4 ; 853.equ SEG113 = 5 ; 854.equ SEG114 = 6 ; 855.equ SEG115 = 7 ; 856 857; LCDDR5 - LCD Data Register 5 858.equ SEG100 = 0 ; 859.equ SEG101 = 1 ; 860.equ SEG102 = 2 ; 861.equ SEG103 = 3 ; 862.equ SEG104 = 4 ; 863.equ SEG105 = 5 ; 864.equ SEG106 = 6 ; 865.equ SEG107 = 7 ; 866 867; LCDDR4 - LCD Data Register 4 868.equ SEG032 = 0 ; 869.equ SEG033 = 1 ; 870.equ SEG034 = 2 ; 871.equ SEG035 = 3 ; 872.equ SEG036 = 4 ; 873.equ SEG037 = 5 ; 874.equ SEG038 = 6 ; 875.equ SEG039 = 7 ; 876 877; LCDDR3 - LCD Data Register 3 878.equ SEG024 = 0 ; 879.equ SEG025 = 1 ; 880.equ SEG026 = 2 ; 881.equ SEG027 = 3 ; 882.equ SEG028 = 4 ; 883.equ SEG029 = 5 ; 884.equ SEG030 = 6 ; 885.equ SEG031 = 7 ; 886 887; LCDDR2 - LCD Data Register 2 888.equ SEG016 = 0 ; 889.equ SEG017 = 1 ; 890.equ SEG018 = 2 ; 891.equ SEG019 = 3 ; 892.equ SEG020 = 4 ; 893.equ SEG021 = 5 ; 894.equ SEG022 = 6 ; 895.equ SEG023 = 7 ; 896 897; LCDDR1 - LCD Data Register 1 898.equ SEG008 = 0 ; 899.equ SEG009 = 1 ; 900.equ SEG010 = 2 ; 901.equ SEG011 = 3 ; 902.equ SEG012 = 4 ; 903.equ SEG013 = 5 ; 904.equ SEG014 = 6 ; 905.equ SEG015 = 7 ; 906 907; LCDDR0 - LCD Data Register 0 908.equ SEG000 = 0 ; 909.equ SEG001 = 1 ; 910.equ SEG002 = 2 ; 911.equ SEG003 = 3 ; 912.equ SEG004 = 4 ; 913.equ SEG005 = 5 ; 914.equ SEG006 = 6 ; 915.equ SEG007 = 7 ; 916 917 918; ***** EXTERNAL_INTERRUPT *********** 919; EICRA - External Interrupt Control Register A 920.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 921.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 922 923; EIMSK - External Interrupt Mask Register 924.equ INT0 = 0 ; External Interrupt Request 0 Enable 925.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0 926.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1 927.equ PCIE2 = 6 ; Pin Change Interrupt Enable 2 928.equ PCIE3 = 7 ; Pin Change Interrupt Enable 3 929 930; EIFR - External Interrupt Flag Register 931.equ INTF0 = 0 ; External Interrupt Flag 0 932.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0 933.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1 934.equ PCIF2 = 6 ; Pin Change Interrupt Flag 2 935.equ PCIF3 = 7 ; Pin Change Interrupt Flag 3 936 937; PCMSK3 - Pin Change Mask Register 3 938.equ PCINT24 = 0 ; Pin Change Enable Mask 24 939.equ PCINT25 = 1 ; Pin Change Enable Mask 25 940.equ PCINT26 = 2 ; Pin Change Enable Mask 26 941.equ PCINT27 = 3 ; Pin Change Enable Mask 27 942.equ PCINT28 = 4 ; Pin Change Enable Mask 28 943.equ PCINT29 = 5 ; Pin Change Enable Mask 29 944.equ PCINT30 = 6 ; Pin Change Enable Mask 30 945 946; PCMSK2 - Pin Change Mask Register 2 947.equ PCINT16 = 0 ; Pin Change Enable Mask 16 948.equ PCINT17 = 1 ; Pin Change Enable Mask 17 949.equ PCINT18 = 2 ; Pin Change Enable Mask 18 950.equ PCINT19 = 3 ; Pin Change Enable Mask 19 951.equ PCINT20 = 4 ; Pin Change Enable Mask 20 952.equ PCINT21 = 5 ; Pin Change Enable Mask 21 953.equ PCINT22 = 6 ; Pin Change Enable Mask 22 954.equ PCINT23 = 7 ; Pin Change Enable Mask 23 955 956; PCMSK1 - Pin Change Mask Register 1 957.equ PCINT8 = 0 ; Pin Change Enable Mask 8 958.equ PCINT9 = 1 ; Pin Change Enable Mask 9 959.equ PCINT10 = 2 ; Pin Change Enable Mask 10 960.equ PCINT11 = 3 ; Pin Change Enable Mask 11 961.equ PCINT12 = 4 ; Pin Change Enable Mask 12 962.equ PCINT13 = 5 ; Pin Change Enable Mask 13 963.equ PCINT14 = 6 ; Pin Change Enable Mask 14 964.equ PCINT15 = 7 ; Pin Change Enable Mask 15 965 966; PCMSK0 - Pin Change Mask Register 0 967.equ PCINT0 = 0 ; Pin Change Enable Mask 0 968.equ PCINT1 = 1 ; Pin Change Enable Mask 1 969.equ PCINT2 = 2 ; Pin Change Enable Mask 2 970.equ PCINT3 = 3 ; Pin Change Enable Mask 3 971.equ PCINT4 = 4 ; Pin Change Enable Mask 4 972.equ PCINT5 = 5 ; Pin Change Enable Mask 5 973.equ PCINT6 = 6 ; Pin Change Enable Mask 6 974.equ PCINT7 = 7 ; Pin Change Enable Mask 7 975 976 977; ***** CPU ************************** 978; SREG - Status Register 979.equ SREG_C = 0 ; Carry Flag 980.equ SREG_Z = 1 ; Zero Flag 981.equ SREG_N = 2 ; Negative Flag 982.equ SREG_V = 3 ; Two's Complement Overflow Flag 983.equ SREG_S = 4 ; Sign Bit 984.equ SREG_H = 5 ; Half Carry Flag 985.equ SREG_T = 6 ; Bit Copy Storage 986.equ SREG_I = 7 ; Global Interrupt Enable 987 988; MCUCR - MCU Control Register 989.equ IVCE = 0 ; Interrupt Vector Change Enable 990.equ IVSEL = 1 ; Interrupt Vector Select 991.equ PUD = 4 ; Pull-up disable 992 993; MCUSR - MCU Status Register 994.equ PORF = 0 ; Power-on reset flag 995.equ EXTRF = 1 ; External Reset Flag 996.equ BORF = 2 ; Brown-out Reset Flag 997.equ WDRF = 3 ; Watchdog Reset Flag 998;.equ JTRF = 4 ; JTAG Reset Flag 999 1000; OSCCAL - Oscillator Calibration Value 1001.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 1002.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 1003.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 1004.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 1005.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 1006.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 1007.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 1008.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 1009 1010; CLKPR - Clock Prescale Register 1011.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 1012.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 1013.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 1014.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 1015.equ CLKPCE = 7 ; Clock Prescaler Change Enable 1016 1017; PRR - Power Reduction Register 1018.equ PRADC = 0 ; Power Reduction ADC 1019.equ PRUSART0 = 1 ; Power Reduction USART 1020.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface 1021.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 1022.equ PRLCD = 4 ; Power Reduction LCD 1023 1024; SMCR - Sleep Mode Control Register 1025.equ SE = 0 ; Sleep Enable 1026.equ SM0 = 1 ; Sleep Mode Select bit 0 1027.equ SM1 = 2 ; Sleep Mode Select bit 1 1028.equ SM2 = 3 ; Sleep Mode Select bit 2 1029 1030; GPIOR2 - General Purpose IO Register 2 1031.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 1032.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 1033.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 1034.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 1035.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 1036.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 1037.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 1038.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 1039 1040; GPIOR1 - General Purpose IO Register 1 1041.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 1042.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 1043.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 1044.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 1045.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 1046.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 1047.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 1048.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 1049 1050; GPIOR0 - General Purpose IO Register 0 1051.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 1052.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 1053.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 1054.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 1055.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 1056.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 1057.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 1058.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 1059 1060 1061; ***** USI ************************** 1062; USIDR - USI Data Register 1063.equ USIDR0 = 0 ; USI Data Register bit 0 1064.equ USIDR1 = 1 ; USI Data Register bit 1 1065.equ USIDR2 = 2 ; USI Data Register bit 2 1066.equ USIDR3 = 3 ; USI Data Register bit 3 1067.equ USIDR4 = 4 ; USI Data Register bit 4 1068.equ USIDR5 = 5 ; USI Data Register bit 5 1069.equ USIDR6 = 6 ; USI Data Register bit 6 1070.equ USIDR7 = 7 ; USI Data Register bit 7 1071 1072; USISR - USI Status Register 1073.equ USICNT0 = 0 ; USI Counter Value Bit 0 1074.equ USICNT1 = 1 ; USI Counter Value Bit 1 1075.equ USICNT2 = 2 ; USI Counter Value Bit 2 1076.equ USICNT3 = 3 ; USI Counter Value Bit 3 1077.equ USIDC = 4 ; Data Output Collision 1078.equ USIPF = 5 ; Stop Condition Flag 1079.equ USIOIF = 6 ; Counter Overflow Interrupt Flag 1080.equ USISIF = 7 ; Start Condition Interrupt Flag 1081 1082; USICR - USI Control Register 1083.equ USITC = 0 ; Toggle Clock Port Pin 1084.equ USICLK = 1 ; Clock Strobe 1085.equ USICS0 = 2 ; USI Clock Source Select Bit 0 1086.equ USICS1 = 3 ; USI Clock Source Select Bit 1 1087.equ USIWM0 = 4 ; USI Wire Mode Bit 0 1088.equ USIWM1 = 5 ; USI Wire Mode Bit 1 1089.equ USIOIE = 6 ; Counter Overflow Interrupt Enable 1090.equ USISIE = 7 ; Start Condition Interrupt Enable 1091 1092 1093; ***** AD_CONVERTER ***************** 1094; ADMUX - The ADC multiplexer Selection Register 1095.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 1096.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 1097.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 1098.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 1099.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits 1100.equ ADLAR = 5 ; Left Adjust Result 1101.equ REFS0 = 6 ; Reference Selection Bit 0 1102.equ REFS1 = 7 ; Reference Selection Bit 1 1103 1104; ADCSRA - The ADC Control and Status register 1105.equ ADPS0 = 0 ; ADC Prescaler Select Bits 1106.equ ADPS1 = 1 ; ADC Prescaler Select Bits 1107.equ ADPS2 = 2 ; ADC Prescaler Select Bits 1108.equ ADIE = 3 ; ADC Interrupt Enable 1109.equ ADIF = 4 ; ADC Interrupt Flag 1110.equ ADATE = 5 ; ADC Auto Trigger Enable 1111.equ ADSC = 6 ; ADC Start Conversion 1112.equ ADEN = 7 ; ADC Enable 1113 1114; ADCH - ADC Data Register High Byte 1115.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 1116.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 1117.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 1118.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 1119.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 1120.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 1121.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 1122.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 1123 1124; ADCL - ADC Data Register Low Byte 1125.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 1126.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 1127.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 1128.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 1129.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 1130.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 1131.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 1132.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 1133 1134; ADCSRB - ADC Control and Status Register B 1135.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 1136.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 1137.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 1138 1139; DIDR0 - Digital Input Disable Register 0 1140.equ ADC0D = 0 ; ADC0 Digital input Disable 1141.equ ADC1D = 1 ; ADC1 Digital input Disable 1142.equ ADC2D = 2 ; ADC2 Digital input Disable 1143.equ ADC3D = 3 ; ADC3 Digital input Disable 1144.equ ADC4D = 4 ; ADC4 Digital input Disable 1145.equ ADC5D = 5 ; ADC5 Digital input Disable 1146.equ ADC6D = 6 ; ADC6 Digital input Disable 1147.equ ADC7D = 7 ; ADC7 Digital input Disable 1148 1149 1150; ***** BOOT_LOAD ******************** 1151; SPMCSR - Store Program Memory Control Register 1152.equ SPMCR = SPMCSR ; For compatibility 1153.equ SPMEN = 0 ; Store Program Memory Enable 1154.equ PGERS = 1 ; Page Erase 1155.equ PGWRT = 2 ; Page Write 1156.equ BLBSET = 3 ; Boot Lock Bit Set 1157.equ RWWSRE = 4 ; Read While Write section read enable 1158.equ ASRE = RWWSRE ; For compatibility 1159.equ RWWSB = 6 ; Read While Write Section Busy 1160.equ ASB = RWWSB ; For compatibility 1161.equ SPMIE = 7 ; SPM Interrupt Enable 1162 1163 1164; ***** USART0 *********************** 1165; UDR - USART I/O Data Register 1166.equ UDR0 = UDR ; For compatibility 1167.equ UDR00 = 0 ; USART I/O Data Register bit 0 1168.equ UDR01 = 1 ; USART I/O Data Register bit 1 1169.equ UDR02 = 2 ; USART I/O Data Register bit 2 1170.equ UDR03 = 3 ; USART I/O Data Register bit 3 1171.equ UDR04 = 4 ; USART I/O Data Register bit 4 1172.equ UDR05 = 5 ; USART I/O Data Register bit 5 1173.equ UDR06 = 6 ; USART I/O Data Register bit 6 1174.equ UDR07 = 7 ; USART I/O Data Register bit 7 1175 1176; UCSRA - USART Control and Status Register A 1177.equ UCSR0A = UCSRA ; For compatibility 1178.equ USR = UCSRA ; For compatibility 1179.equ MPCM = 0 ; Multi-processor Communication Mode 1180.equ MPCM0 = MPCM ; For compatibility 1181.equ U2X = 1 ; Double the USART Transmission Speed 1182.equ U2X0 = U2X ; For compatibility 1183.equ UPE = 2 ; USART Parity Error 1184.equ UPE0 = UPE ; For compatibility 1185.equ DOR = 3 ; Data OverRun 1186.equ DOR0 = DOR ; For compatibility 1187.equ FE = 4 ; Framing Error 1188.equ FE0 = FE ; For compatibility 1189.equ UDRE = 5 ; USART Data Register Empty 1190.equ UDRE0 = UDRE ; For compatibility 1191.equ TXC = 6 ; USART Transmit Complete 1192.equ TXC0 = TXC ; For compatibility 1193.equ RXC = 7 ; USART Receive Complete 1194.equ RXC0 = RXC ; For compatibility 1195 1196; UCSRB - USART Control and Status Register B 1197.equ UCSR0B = UCSRB ; For compatibility 1198.equ UCR = UCSRB ; For compatibility 1199.equ TXB8 = 0 ; Transmit Data Bit 8 1200.equ TXB80 = TXB8 ; For compatibility 1201.equ RXB8 = 1 ; Receive Data Bit 8 1202.equ RXB80 = RXB8 ; For compatibility 1203.equ UCSZ2 = 2 ; Character Size 1204.equ UCSZ02 = UCSZ2 ; For compatibility 1205.equ TXEN = 3 ; Transmitter Enable 1206.equ TXEN0 = TXEN ; For compatibility 1207.equ RXEN = 4 ; Receiver Enable 1208.equ RXEN0 = RXEN ; For compatibility 1209.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable 1210.equ UDRIE0 = UDRIE ; For compatibility 1211.equ TXCIE = 6 ; TX Complete Interrupt Enable 1212.equ TXCIE0 = TXCIE ; For compatibility 1213.equ RXCIE = 7 ; RX Complete Interrupt Enable 1214.equ RXCIE0 = RXCIE ; For compatibility 1215 1216; UCSRC - USART Control and Status Register C 1217.equ UCSR0C = UCSRC ; For compatibility 1218.equ UCPOL = 0 ; Clock Polarity 1219.equ UCPOL0 = UCPOL ; For compatibility 1220.equ UCSZ0 = 1 ; Character Size 1221.equ UCSZ00 = UCSZ0 ; For compatibility 1222.equ UCSZ1 = 2 ; Character Size 1223.equ UCSZ01 = UCSZ1 ; For compatibility 1224.equ USBS = 3 ; Stop Bit Select 1225.equ USBS0 = USBS ; For compatibility 1226.equ UPM0 = 4 ; Parity Mode Bit 0 1227.equ UPM00 = UPM0 ; For compatibility 1228.equ UPM1 = 5 ; Parity Mode Bit 1 1229.equ UPM01 = UPM1 ; For compatibility 1230.equ UMSEL = 6 ; USART Mode Select 1231.equ UMSEL0 = UMSEL ; For compatibility 1232 1233.equ UBRR0H = UBRRH ; For compatibility 1234.equ UBRR0L = UBRRL ; For compatibility 1235.equ UBRR0 = UBRRL ; For compatibility 1236.equ UBRR = UBRRL ; For compatibility 1237 1238; ***** PORTH ************************ 1239; PORTH - PORT H Data Register 1240.equ PORTH0 = 0 ; PORT H Data Register bit 0 1241.equ PH0 = 0 ; For compatibility 1242.equ PORTH1 = 1 ; PORT H Data Register bit 1 1243.equ PH1 = 1 ; For compatibility 1244.equ PORTH2 = 2 ; PORT H Data Register bit 2 1245.equ PH2 = 2 ; For compatibility 1246.equ PORTH3 = 3 ; PORT H Data Register bit 3 1247.equ PH3 = 3 ; For compatibility 1248.equ PORTH4 = 4 ; PORT H Data Register bit 4 1249.equ PH4 = 4 ; For compatibility 1250.equ PORTH5 = 5 ; PORT H Data Register bit 5 1251.equ PH5 = 5 ; For compatibility 1252.equ PORTH6 = 6 ; PORT H Data Register bit 6 1253.equ PH6 = 6 ; For compatibility 1254.equ PORTH7 = 7 ; PORT H Data Register bit 7 1255.equ PH7 = 7 ; For compatibility 1256 1257; DDRH - PORT H Data Direction Register 1258.equ DDH0 = 0 ; PORT H Data Direction Register bit 0 1259.equ DDH1 = 1 ; PORT H Data Direction Register bit 1 1260.equ DDH2 = 2 ; PORT H Data Direction Register bit 2 1261.equ DDH3 = 3 ; PORT H Data Direction Register bit 3 1262.equ DDH4 = 4 ; PORT H Data Direction Register bit 4 1263.equ DDH5 = 5 ; PORT H Data Direction Register bit 5 1264.equ DDH6 = 6 ; PORT H Data Direction Register bit 6 1265.equ DDH7 = 7 ; PORT H Data Direction Register bit 7 1266 1267; PINH - PORT H Input Pins 1268.equ PINH0 = 0 ; PORT H Input Pins bit 0 1269.equ PINH1 = 1 ; PORT H Input Pins bit 1 1270.equ PINH2 = 2 ; PORT H Input Pins bit 2 1271.equ PINH3 = 3 ; PORT H Input Pins bit 3 1272.equ PINH4 = 4 ; PORT H Input Pins bit 4 1273.equ PINH5 = 5 ; PORT H Input Pins bit 5 1274.equ PINH6 = 6 ; PORT H Input Pins bit 6 1275.equ PINH7 = 7 ; PORT H Input Pins bit 7 1276 1277 1278; ***** PORTJ ************************ 1279; PORTJ - PORT J Data Register 1280.equ PORTJ0 = 0 ; PORT J Data Register bit 0 1281.equ PJ0 = 0 ; For compatibility 1282.equ PORTJ1 = 1 ; PORT J Data Register bit 1 1283.equ PJ1 = 1 ; For compatibility 1284.equ PORTJ2 = 2 ; PORT J Data Register bit 2 1285.equ PJ2 = 2 ; For compatibility 1286.equ PORTJ3 = 3 ; PORT J Data Register bit 3 1287.equ PJ3 = 3 ; For compatibility 1288.equ PORTJ4 = 4 ; PORT J Data Register bit 4 1289.equ PJ4 = 4 ; For compatibility 1290.equ PORTJ5 = 5 ; PORT J Data Register bit 5 1291.equ PJ5 = 5 ; For compatibility 1292.equ PORTJ6 = 6 ; PORT J Data Register bit 6 1293.equ PJ6 = 6 ; For compatibility 1294 1295; DDRJ - PORT J Data Direction Register 1296.equ DDJ0 = 0 ; PORT J Data Direction Register bit 0 1297.equ DDJ1 = 1 ; PORT J Data Direction Register bit 1 1298.equ DDJ2 = 2 ; PORT J Data Direction Register bit 2 1299.equ DDJ3 = 3 ; PORT J Data Direction Register bit 3 1300.equ DDJ4 = 4 ; PORT J Data Direction Register bit 4 1301.equ DDJ5 = 5 ; PORT J Data Direction Register bit 5 1302.equ DDJ6 = 6 ; PORT J Data Direction Register bit 6 1303 1304; PINJ - PORT J Input Pins 1305.equ PINJ0 = 0 ; PORT J Input Pins bit 0 1306.equ PINJ1 = 1 ; PORT J Input Pins bit 1 1307.equ PINJ2 = 2 ; PORT J Input Pins bit 2 1308.equ PINJ3 = 3 ; PORT J Input Pins bit 3 1309.equ PINJ4 = 4 ; PORT J Input Pins bit 4 1310.equ PINJ5 = 5 ; PORT J Input Pins bit 5 1311.equ PINJ6 = 6 ; PORT J Input Pins bit 6 1312 1313 1314 1315; ***** LOCKSBITS ******************************************************** 1316.equ LB1 = 0 ; Lock bit 1317.equ LB2 = 1 ; Lock bit 1318.equ BLB01 = 2 ; Boot Lock bit 1319.equ BLB02 = 3 ; Boot Lock bit 1320.equ BLB11 = 4 ; Boot lock bit 1321.equ BLB12 = 5 ; Boot lock bit 1322 1323 1324; ***** FUSES ************************************************************ 1325; LOW fuse bits 1326.equ CKSEL0 = 0 ; Select Clock Source 1327.equ CKSEL1 = 1 ; Select Clock Source 1328.equ CKSEL2 = 2 ; Select Clock Source 1329.equ CKSEL3 = 3 ; Select Clock Source 1330.equ SUT0 = 4 ; Select start-up time 1331.equ SUT1 = 5 ; Select start-up time 1332.equ CKOUT = 6 ; Oscillator options 1333.equ CLKDIV8 = 7 ; Divide clock by 8 1334 1335; HIGH fuse bits 1336.equ BOOTRST = 0 ; Select Reset Vector 1337.equ BOOTSZ0 = 1 ; Select Boot Size 1338.equ BOOTSZ1 = 2 ; Select Boot Size 1339.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase 1340.equ WDTON = 4 ; Watchdog timer always on 1341.equ SPIEN = 5 ; Enable Serial programming and Data Downloading 1342.equ JTAGEN = 6 ; Enable JTAG 1343.equ OCDEN = 7 ; Enable OCD 1344 1345; EXTENDED fuse bits 1346.equ RSTDISBL = 0 ; External Reset Disable 1347.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level 1348.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level 1349 1350 1351 1352; ***** CPU REGISTER DEFINITIONS ***************************************** 1353.def XH = r27 1354.def XL = r26 1355.def YH = r29 1356.def YL = r28 1357.def ZH = r31 1358.def ZL = r30 1359 1360 1361 1362; ***** DATA MEMORY DECLARATIONS ***************************************** 1363.equ FLASHEND = 0x3fff ; Note: Word address 1364.equ IOEND = 0x00ff 1365.equ SRAM_START = 0x0100 1366.equ SRAM_SIZE = 2048 1367.equ RAMEND = 0x08ff 1368.equ XRAMEND = 0x0000 1369.equ E2END = 0x03ff 1370.equ EEPROMEND = 0x03ff 1371.equ EEADRBITS = 10 1372#pragma AVRPART MEMORY PROG_FLASH 32768 1373#pragma AVRPART MEMORY EEPROM 1024 1374#pragma AVRPART MEMORY INT_SRAM SIZE 2048 1375#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 1376 1377 1378 1379; ***** BOOTLOADER DECLARATIONS ****************************************** 1380.equ NRWW_START_ADDR = 0x3800 1381.equ NRWW_STOP_ADDR = 0x3fff 1382.equ RWW_START_ADDR = 0x0 1383.equ RWW_STOP_ADDR = 0x37ff 1384.equ PAGESIZE = 64 1385.equ FIRSTBOOTSTART = 0x3f00 1386.equ SECONDBOOTSTART = 0x3e00 1387.equ THIRDBOOTSTART = 0x3c00 1388.equ FOURTHBOOTSTART = 0x3800 1389.equ SMALLBOOTSTART = FIRSTBOOTSTART 1390.equ LARGEBOOTSTART = FOURTHBOOTSTART 1391 1392 1393 1394; ***** INTERRUPT VECTORS ************************************************ 1395.equ INT0addr = 0x0002 ; External Interrupt Request 0 1396.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 1397.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 1398.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match 1399.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow 1400.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event 1401.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A 1402.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B 1403.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow 1404.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match 1405.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow 1406.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete 1407.equ URXCaddr = 0x001a ; USART, Rx Complete 1408.equ URXC0addr = 0x001a ; For compatibility 1409.equ UDREaddr = 0x001c ; USART Data register Empty 1410.equ UDRE0addr = 0x001c ; For compatibility 1411.equ UTXC0addr = 0x001e ; USART0, Tx Complete 1412.equ UTXCaddr = 0x001e ; For compatibility 1413.equ USI_STARTaddr = 0x0020 ; USI Start Condition 1414.equ USI_OVFaddr = 0x0022 ; USI Overflow 1415.equ ACIaddr = 0x0024 ; Analog Comparator 1416.equ ADCCaddr = 0x0026 ; ADC Conversion Complete 1417.equ ERDYaddr = 0x0028 ; EEPROM Ready 1418.equ SPMRaddr = 0x002a ; Store Program Memory Read 1419.equ LCDSFaddr = 0x002c ; LCD Start of Frame 1420.equ PCI2addr = 0x002e ; Pin Change Interrupt Request 2 1421.equ PCI3addr = 0x0030 ; Pin Change Interrupt Request 3 1422 1423.equ INT_VECTORS_SIZE = 50 ; size in words 1424 1425#endif /* _M3290DEF_INC_ */ 1426 1427; ***** END OF FILE ****************************************************** 1428