1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2005-01-11 10:31 ******* Source: ATmega406.xml *********** 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "m406def.inc" 8;* Title : Register/Bit Definitions for the ATmega406 9;* Date : 2005-01-11 10;* Version : 2.14 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATmega406 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _M406DEF_INC_ 41#define _M406DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATmega406 48#pragma AVRPART ADMIN PART_NAME ATmega406 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x95 51.equ SIGNATURE_002 = 0x07 52 53#pragma AVRPART CORE CORE_VERSION V2E 54 55 56; ***** I/O REGISTER DEFINITIONS ***************************************** 57; NOTE: 58; Definitions marked "MEMORY MAPPED"are extended I/O ports 59; and cannot be used with IN/OUT instructions 60.equ BPPLR = 0xf8 ; MEMORY MAPPED 61.equ BPCR = 0xf7 ; MEMORY MAPPED 62.equ CBPTR = 0xf6 ; MEMORY MAPPED 63.equ BPOCD = 0xf5 ; MEMORY MAPPED 64.equ BPSCD = 0xf4 ; MEMORY MAPPED 65.equ BPDUV = 0xf3 ; MEMORY MAPPED 66.equ BPIR = 0xf2 ; MEMORY MAPPED 67.equ CBCR = 0xf1 ; MEMORY MAPPED 68.equ FCSR = 0xf0 ; MEMORY MAPPED 69.equ CADICH = 0xe9 ; MEMORY MAPPED 70.equ CADICL = 0xe8 ; MEMORY MAPPED 71.equ CADRDC = 0xe7 ; MEMORY MAPPED 72.equ CADRCC = 0xe6 ; MEMORY MAPPED 73.equ CADCSRB = 0xe5 ; MEMORY MAPPED 74.equ CADCSRA = 0xe4 ; MEMORY MAPPED 75.equ CADAC3 = 0xe3 ; MEMORY MAPPED 76.equ CADAC2 = 0xe2 ; MEMORY MAPPED 77.equ CADAC1 = 0xe1 ; MEMORY MAPPED 78.equ CADAC0 = 0xe0 ; MEMORY MAPPED 79.equ BGCRR = 0xd1 ; MEMORY MAPPED 80.equ BGCCR = 0xd0 ; MEMORY MAPPED 81.equ CCSR = 0xc0 ; MEMORY MAPPED 82.equ TWBCSR = 0xbe ; MEMORY MAPPED 83.equ TWAMR = 0xbd ; MEMORY MAPPED 84.equ TWCR = 0xbc ; MEMORY MAPPED 85.equ TWDR = 0xbb ; MEMORY MAPPED 86.equ TWAR = 0xba ; MEMORY MAPPED 87.equ TWSR = 0xb9 ; MEMORY MAPPED 88.equ TWBR = 0xb8 ; MEMORY MAPPED 89.equ OCR1AH = 0x89 ; MEMORY MAPPED 90.equ OCR1AL = 0x88 ; MEMORY MAPPED 91.equ TCNT1H = 0x85 ; MEMORY MAPPED 92.equ TCNT1L = 0x84 ; MEMORY MAPPED 93.equ TCCR1B = 0x81 ; MEMORY MAPPED 94.equ DIDR0 = 0x7e ; MEMORY MAPPED 95.equ VADMUX = 0x7c ; MEMORY MAPPED 96.equ VADCSR = 0x7a ; MEMORY MAPPED 97.equ VADCH = 0x79 ; MEMORY MAPPED 98.equ VADCL = 0x78 ; MEMORY MAPPED 99.equ TIMSK1 = 0x6f ; MEMORY MAPPED 100.equ TIMSK0 = 0x6e ; MEMORY MAPPED 101.equ PCMSK1 = 0x6c ; MEMORY MAPPED 102.equ PCMSK0 = 0x6b ; MEMORY MAPPED 103.equ EICRA = 0x69 ; MEMORY MAPPED 104.equ PCICR = 0x68 ; MEMORY MAPPED 105.equ FOSCCAL = 0x66 ; MEMORY MAPPED 106.equ PRR0 = 0x64 ; MEMORY MAPPED 107.equ WUTCSR = 0x62 ; MEMORY MAPPED 108.equ WDTCSR = 0x60 ; MEMORY MAPPED 109.equ SREG = 0x3f 110.equ SPH = 0x3e 111.equ SPL = 0x3d 112.equ SPMCSR = 0x37 113.equ MCUCR = 0x35 114.equ MCUSR = 0x34 115.equ SMCR = 0x33 116.equ OCDR = 0x31 117.equ GPIOR2 = 0x2b 118.equ GPIOR1 = 0x2a 119.equ OCR0B = 0x28 120.equ OCR0A = 0x27 121.equ TCNT0 = 0x26 122.equ TCCR0B = 0x25 123.equ TCCR0A = 0x24 124.equ GTCCR = 0x23 125.equ EEARH = 0x22 126.equ EEARL = 0x21 127.equ EEDR = 0x20 128.equ EECR = 0x1f 129.equ GPIOR0 = 0x1e 130.equ EIMSK = 0x1d 131.equ EIFR = 0x1c 132.equ PCIFR = 0x1b 133.equ TIFR1 = 0x16 134.equ TIFR0 = 0x15 135.equ PORTD = 0x0b 136.equ DDRD = 0x0a 137.equ PIND = 0x09 138.equ PORTC = 0x08 139.equ PORTB = 0x05 140.equ DDRB = 0x04 141.equ PINB = 0x03 142.equ PORTA = 0x02 143.equ DDRA = 0x01 144.equ PINA = 0x00 145 146 147; ***** BIT DEFINITIONS ************************************************** 148 149; ***** AD_CONVERTER ***************** 150; VADMUX - The VADC multiplexer Selection Register 151.equ VADMUX0 = 0 ; Analog Channel and Gain Selection Bits 152.equ VADMUX1 = 1 ; Analog Channel and Gain Selection Bits 153.equ VADMUX2 = 2 ; Analog Channel and Gain Selection Bits 154.equ VADMUX3 = 3 ; Analog Channel and Gain Selection Bits 155 156; VADCSR - The VADC Control and Status register 157.equ VADCCIE = 0 ; VADC Conversion Complete Interrupt Enable 158.equ VADCCIF = 1 ; VADC Conversion Complete Interrupt Flag 159.equ VADSC = 2 ; VADC Satrt Conversion 160.equ VADEN = 3 ; VADC Enable 161 162 163; ***** EXTERNAL_INTERRUPT *********** 164; EICRA - External Interrupt Control Register 165.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 166.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 167.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 168.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 169.equ ISC20 = 4 ; External Interrupt Sense Control 2 Bit 0 170.equ ISC21 = 5 ; External Interrupt Sense Control 2 Bit 1 171.equ ISC30 = 6 ; External Interrupt Sense Control 3 Bit 0 172.equ ISC31 = 7 ; External Interrupt Sense Control 3 Bit 1 173 174; EIMSK - External Interrupt Mask Register 175.equ INT0 = 0 ; External Interrupt Request 0 Enable 176.equ INT1 = 1 ; External Interrupt Request 1 Enable 177.equ INT2 = 2 ; External Interrupt Request 1 Enable 178.equ INT3 = 3 ; External Interrupt Request 1 Enable 179 180; EIFR - External Interrupt Flag Register 181.equ INTF0 = 0 ; External Interrupt Flag 0 182.equ INTF1 = 1 ; External Interrupt Flag 1 183.equ INTF2 = 2 ; External Interrupt Flag 2 184.equ INTF3 = 3 ; External Interrupt Flag 3 185 186; PCICR - Pin Change Interrupt Control Register 187.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 188.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 189 190; PCIFR - Pin Change Interrupt Flag Register 191.equ PCIF0 = 0 ; Pin Change Interrupt Flag 1 192.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 193 194 195; ***** TIMER_COUNTER_1 ************** 196; TCCR1B - Timer/Counter1 Control Register B 197.equ CS10 = 0 ; Clock Select1 bit 0 198.equ CS11 = 1 ; Clock Select1 bit 1 199.equ CS12 = 2 ; Clock Select1 bit 2 200.equ CTC1 = 3 ; Clear Timer/Counter on Compare Match 201 202; TIMSK1 - Timer/Counter Interrupt Mask Register 203.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable 204.equ OCIE1A = 1 ; Timer/Counter1 Output Compare Interrupt Enable 205 206; TIFR1 - Timer/Counter Interrupt Flag register 207.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag 208.equ OCF1A = 1 ; Timer/Counter1 Output Compare Flag A 209 210; GTCCR - General Timer/Counter Control Register 211.equ PSRSYNC = 0 ; Prescaler Reset 212.equ PSRASY = 1 ; 213.equ TSM = 7 ; Timer/Counter Synchronization Mode 214 215 216; ***** WAKEUP_TIMER ***************** 217; WUTCSR - Wake-up Timer Control Register 218.equ WUTP0 = 0 ; Wake-up Timer Prescaler Bit 0 219.equ WUTP1 = 1 ; Wake-up Timer Prescaler Bit 1 220.equ WUTP2 = 2 ; Wake-up Timer Prescaler Bit 2 221.equ WUTE = 3 ; Wake-up Timer Enable 222.equ WUTR = 4 ; Wake-up Timer Reset 223.equ WUTCF = 5 ; Wake-up timer Calibration Flag 224.equ WUTIE = 6 ; Wake-up Timer Interrupt Enable 225.equ WUTIF = 7 ; Wake-up Timer Interrupt Flag 226 227 228; ***** BATTERY_PROTECTION *********** 229; BPPLR - Battery Protection Parameter Lock Register 230.equ BPPL = 0 ; Battery Protection Parameter Lock 231.equ BPPLE = 1 ; Battery Protection Parameter Lock Enable 232 233; BPCR - Battery Protection Control Register 234.equ CCD = 0 ; 235.equ DCD = 1 ; 236.equ SCD = 2 ; 237.equ DUVD = 3 ; 238 239; CBPTR - Current Battery Protection Timing Register 240.equ OCPT0 = 0 ; 241.equ OCPT1 = 1 ; 242.equ OCPT2 = 2 ; 243.equ OCPT3 = 3 ; 244.equ SCPT0 = 4 ; 245.equ SCPT1 = 5 ; 246.equ SCPT2 = 6 ; 247.equ SCPT3 = 7 ; 248 249; BPOCD - Battery Protection OverCurrent Detection Level Register 250.equ CCDL0 = 0 ; 251.equ CCDL1 = 1 ; 252.equ CCDL2 = 2 ; 253.equ CCDL3 = 3 ; 254.equ DCDL0 = 4 ; 255.equ DCDL1 = 5 ; 256.equ DCDL2 = 6 ; 257.equ DCDL3 = 7 ; 258 259; BPSCD - Battery Protection Short-Circuit Detection Level Register 260.equ SCDL0 = 0 ; 261.equ SCDL1 = 1 ; 262.equ SCDL2 = 2 ; 263.equ SCDL3 = 3 ; 264 265; BPDUV - Battery Protection Deep Under Voltage Register 266.equ DUDL0 = 0 ; 267.equ DUDL1 = 1 ; 268.equ DUDL2 = 2 ; 269.equ DUDL3 = 3 ; 270.equ DUVT0 = 4 ; 271.equ DUVT1 = 5 ; 272 273; BPIR - Battery Protection Interrupt Register 274.equ SCIE = 0 ; 275.equ DOCIE = 1 ; 276.equ COCIE = 2 ; 277.equ DUVIE = 3 ; Deep Under-voltage Early Warning Interrupt Enable 278.equ SCIF = 4 ; 279.equ DOCIF = 5 ; 280.equ COCIF = 6 ; Charge Over-current Protection Activated Interrupt Flag 281.equ DUVIF = 7 ; Deep Under-voltage Early Warning Interrupt Flag 282 283 284; ***** FET ************************** 285; FCSR - 286.equ PFD = 0 ; Precharge FET disable 287.equ CFE = 1 ; Charge FET Enable 288.equ DFE = 2 ; Discharge FET Enable 289.equ CPS = 3 ; Current Protection Status 290.equ PWMOPC = 4 ; Pulse Width Modulation Modulation of OPC output 291.equ PWMOC = 5 ; Pulse Width Modulation of OC output 292 293 294; ***** COULOMB_COUNTER ************** 295; CADCSRA - CC-ADC Control and Status Register A 296.equ CADSE = 0 ; When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. 297.equ CADSI0 = 1 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. 298.equ CADSI1 = 2 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. 299.equ CADAS0 = 3 ; CC_ADC Accumulate Current Select Bit 0 300.equ CADAS1 = 4 ; CC_ADC Accumulate Current Select Bit 1 301.equ CADUB = 5 ; CC_ADC Update Busy 302.equ CADEN = 7 ; When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. 303 304; CADCSRB - CC-ADC Control and Status Register B 305.equ CADICIF = 0 ; CC-ADC Instantaneous Current Interrupt Flag 306.equ CADRCIF = 1 ; CC-ADC Accumulate Current Interrupt Flag 307.equ CADACIF = 2 ; CC-ADC Accumulate Current Interrupt Flag 308.equ CADICIE = 4 ; CAD Instantenous Current Interrupt Enable 309.equ CADRCIE = 5 ; Regular Current Interrupt Enable 310.equ CADACIE = 6 ; 311 312; CADAC3 - ADC Accumulate Current 313.equ CADAC24 = 0 ; 314.equ CADAC25 = 1 ; 315.equ CADAC26 = 2 ; 316.equ CADAC27 = 3 ; 317.equ CADAC28 = 4 ; 318.equ CADAC29 = 5 ; 319.equ CADAC30 = 6 ; 320.equ CADAC31 = 7 ; 321 322; CADAC2 - ADC Accumulate Current 323.equ CADAC16 = 0 ; 324.equ CADAC17 = 1 ; 325.equ CADAC18 = 2 ; 326.equ CADAC19 = 3 ; 327.equ CADAC20 = 4 ; 328.equ CADAC21 = 5 ; 329.equ CADAC22 = 6 ; 330.equ CADAC23 = 7 ; 331 332; CADAC1 - ADC Accumulate Current 333.equ CADAC08 = 0 ; 334.equ CADAC09 = 1 ; 335.equ CADAC10 = 2 ; 336.equ CADAC11 = 3 ; 337.equ CADAC12 = 4 ; 338.equ CADAC13 = 5 ; 339.equ CADAC14 = 6 ; 340.equ CADAC15 = 7 ; 341 342; CADAC0 - ADC Accumulate Current 343.equ CADAC00 = 0 ; 344.equ CADAC01 = 1 ; 345.equ CADAC02 = 2 ; 346.equ CADAC03 = 3 ; 347.equ CADAC04 = 4 ; 348.equ CADAC05 = 5 ; 349.equ CADAC06 = 6 ; 350.equ CADAC07 = 7 ; 351 352; CADRCC - CC-ADC Regular Charge Current 353.equ CADRCC0 = 0 ; When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. 354.equ CADRCC1 = 1 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. 355.equ CADRCC2 = 2 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. 356.equ CADRCC3 = 3 ; The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. 357.equ CADRCC4 = 4 ; The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. 358.equ CADRCC5 = 5 ; 359.equ CADRCC6 = 6 ; 360.equ CADRCC7 = 7 ; When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. 361 362; CADRDC - CC-ADC Regular Discharge Current 363.equ CADRDC0 = 0 ; When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. 364.equ CADRDC1 = 1 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. 365.equ CADRDC2 = 2 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. 366.equ CADRDC3 = 3 ; The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. 367.equ CADRDC4 = 4 ; The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. 368.equ CADRDC5 = 5 ; 369.equ CADRDC6 = 6 ; 370.equ CADRDC7 = 7 ; When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. 371 372 373; ***** CELL_BALANCING *************** 374; CBCR - Cell Balancing Control Register 375.equ CBE1 = 0 ; Battery Protection Parameter Lock 376.equ CBE2 = 1 ; Cell Balancing Enable 2 377.equ CBE3 = 2 ; Cell Balancing Enable 4 378.equ CBE4 = 3 ; Cell Balancing Enable 4 379 380 381; ***** CPU ************************** 382; SREG - Status Register 383.equ SREG_C = 0 ; Carry Flag 384.equ SREG_Z = 1 ; Zero Flag 385.equ SREG_N = 2 ; Negative Flag 386.equ SREG_V = 3 ; Two's Complement Overflow Flag 387.equ SREG_S = 4 ; Sign Bit 388.equ SREG_H = 5 ; Half Carry Flag 389.equ SREG_T = 6 ; Bit Copy Storage 390.equ SREG_I = 7 ; Global Interrupt Enable 391 392; MCUCR - MCU Control Register 393.equ IVCE = 0 ; Interrupt Vector Change Enable 394.equ IVSEL = 1 ; Interrupt Vector Select 395.equ PUD = 4 ; Pull-up disable 396.equ JTD = 7 ; JTAG Disable 397 398; MCUSR - MCU Status Register 399.equ PORF = 0 ; Power-on reset flag 400.equ EXTRF = 1 ; External Reset Flag 401.equ BODRF = 2 ; Brown-out Reset Flag 402.equ WDRF = 3 ; Watchdog Reset Flag 403.equ JTRF = 4 ; JTAG Reset Flag 404 405; FOSCCAL - Fast Oscillator Calibration Value 406.equ FCAL0 = 0 ; Oscillator Calibration Value Bit0 407.equ FCAL1 = 1 ; Oscillator Calibration Value Bit1 408.equ FCAL2 = 2 ; Oscillator Calibration Value Bit2 409.equ FCAL3 = 3 ; Oscillator Calibration Value Bit3 410.equ FCAL4 = 4 ; Oscillator Calibration Value Bit4 411.equ FCAL5 = 5 ; Oscillator Calibration Value Bit5 412.equ FCAL6 = 6 ; Oscillator Calibration Value Bit6 413.equ FCAL7 = 7 ; Oscillator Calibration Value Bit7 414 415; SMCR - Sleep Mode Control Register 416.equ SE = 0 ; Sleep Enable 417.equ SM0 = 1 ; Sleep Mode Select bit 0 418.equ SM1 = 2 ; Sleep Mode Select bit 1 419.equ SM2 = 3 ; Sleep Mode Select bit 2 420 421; GPIOR2 - General Purpose IO Register 2 422.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 423.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 424.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 425.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 426.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 427.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 428.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 429.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 430 431; GPIOR1 - General Purpose IO Register 1 432.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 433.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 434.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 435.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 436.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 437.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 438.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 439.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 440 441; GPIOR0 - General Purpose IO Register 0 442.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 443.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 444.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 445.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 446.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 447.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 448.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 449.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 450 451; CCSR - Clock Control and Status Register 452.equ ACS = 0 ; Asynchronous Clock Select 453.equ XOE = 1 ; 32 kHz Crystal Oscillator Enable 454 455; DIDR0 - Digital Input Disable Register 456.equ VADC0D = 0 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. 457.equ VADC1D = 1 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. 458.equ VADC2D = 2 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. 459.equ VADC3D = 3 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. 460 461; PRR0 - Power Reduction Register 0 462.equ PRVADC = 0 ; Power Reduction V-ADC 463.equ PRTIM0 = 1 ; Power Reduction Timer/Counter0 464.equ PRTIM1 = 2 ; Power Reduction Timer/Counter1 465.equ PRTWI = 3 ; Power Reduction TWI 466 467 468; ***** WATCHDOG ********************* 469; WDTCSR - Watchdog Timer Control Register 470.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 471.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 472.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 473.equ WDE = 3 ; Watch Dog Enable 474.equ WDCE = 4 ; Watchdog Change Enable 475.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 476.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 477.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 478 479 480; ***** TIMER_COUNTER_0 ************** 481; TCCR0A - Timer/Counter0 Control Register 482.equ WGM00 = 0 ; Clock Select0 bit 0 483.equ WGM01 = 1 ; Clock Select0 bit 1 484.equ COM0B0 = 4 ; 485.equ COM0B1 = 5 ; 486.equ COM0A0 = 6 ; Waveform Generation Mode 487.equ COM0A1 = 7 ; Force Output Compare 488 489; TCCR0B - Timer/Counter0 Control Register 490.equ CS00 = 0 ; Clock Select0 bit 0 491.equ CS01 = 1 ; Clock Select0 bit 1 492.equ CS02 = 2 ; Clock Select0 bit 2 493.equ WGM02 = 3 ; 494.equ FOC0B = 6 ; Waveform Generation Mode 495.equ FOC0A = 7 ; Force Output Compare 496 497; TCNT0 - Timer Counter 0 498.equ TCNT00 = 0 ; Timer Counter 0 bit 0 499.equ TCNT01 = 1 ; Timer Counter 0 bit 1 500.equ TCNT02 = 2 ; Timer Counter 0 bit 2 501.equ TCNT03 = 3 ; Timer Counter 0 bit 3 502.equ TCNT04 = 4 ; Timer Counter 0 bit 4 503.equ TCNT05 = 5 ; Timer Counter 0 bit 5 504.equ TCNT06 = 6 ; Timer Counter 0 bit 6 505.equ TCNT07 = 7 ; Timer Counter 0 bit 7 506 507; OCR0A - Output compare Register A 508.equ OCR0A0 = 0 ; 509.equ OCR0A1 = 1 ; 510.equ OCR0A2 = 2 ; 511.equ OCR0A3 = 3 ; 512.equ OCR0A4 = 4 ; 513.equ OCR0A5 = 5 ; 514.equ OCR0A6 = 6 ; 515.equ OCR0A7 = 7 ; 516 517; OCR0B - Output compare Register B 518.equ OCR0B0 = 0 ; 519.equ OCR0B1 = 1 ; 520.equ OCR0B2 = 2 ; 521.equ OCR0B3 = 3 ; 522.equ OCR0B4 = 4 ; 523.equ OCR0B5 = 5 ; 524.equ OCR0B6 = 6 ; 525.equ OCR0B7 = 7 ; 526 527; TIMSK0 - Timer/Counter Interrupt Mask Register 528.equ TOIE0 = 0 ; Overflow Interrupt Enable 529.equ OCIE0A = 1 ; Output Compare Interrupt Enable 530.equ OCIE0B = 2 ; Output Compare Interrupt Enable 531 532; TIFR0 - Timer/Counter Interrupt Flag register 533.equ TOV0 = 0 ; Overflow Flag 534.equ OCF0A = 1 ; Output Compare Flag 535.equ OCF0B = 2 ; Output Compare Flag 536 537 538; ***** PORTA ************************ 539; PORTA - Port A Data Register 540.equ PORTA0 = 0 ; Port A Data Register bit 0 541.equ PA0 = 0 ; For compatibility 542.equ PORTA1 = 1 ; Port A Data Register bit 1 543.equ PA1 = 1 ; For compatibility 544.equ PORTA2 = 2 ; Port A Data Register bit 2 545.equ PA2 = 2 ; For compatibility 546.equ PORTA3 = 3 ; Port A Data Register bit 3 547.equ PA3 = 3 ; For compatibility 548.equ PORTA4 = 4 ; Port A Data Register bit 4 549.equ PA4 = 4 ; For compatibility 550.equ PORTA5 = 5 ; Port A Data Register bit 5 551.equ PA5 = 5 ; For compatibility 552.equ PORTA6 = 6 ; Port A Data Register bit 6 553.equ PA6 = 6 ; For compatibility 554.equ PORTA7 = 7 ; Port A Data Register bit 7 555.equ PA7 = 7 ; For compatibility 556 557; DDRA - Port A Data Direction Register 558.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 559.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 560.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 561.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 562.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 563.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 564.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 565.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 566 567; PINA - Port A Input Pins 568.equ PINA0 = 0 ; Input Pins, Port A bit 0 569.equ PINA1 = 1 ; Input Pins, Port A bit 1 570.equ PINA2 = 2 ; Input Pins, Port A bit 2 571.equ PINA3 = 3 ; Input Pins, Port A bit 3 572.equ PINA4 = 4 ; Input Pins, Port A bit 4 573.equ PINA5 = 5 ; Input Pins, Port A bit 5 574.equ PINA6 = 6 ; Input Pins, Port A bit 6 575.equ PINA7 = 7 ; Input Pins, Port A bit 7 576 577 578; ***** PORTB ************************ 579; PORTB - Port B Data Register 580.equ PORTB0 = 0 ; Port B Data Register bit 0 581.equ PB0 = 0 ; For compatibility 582.equ PORTB1 = 1 ; Port B Data Register bit 1 583.equ PB1 = 1 ; For compatibility 584.equ PORTB2 = 2 ; Port B Data Register bit 2 585.equ PB2 = 2 ; For compatibility 586.equ PORTB3 = 3 ; Port B Data Register bit 3 587.equ PB3 = 3 ; For compatibility 588.equ PORTB4 = 4 ; Port B Data Register bit 4 589.equ PB4 = 4 ; For compatibility 590.equ PORTB5 = 5 ; Port B Data Register bit 5 591.equ PB5 = 5 ; For compatibility 592.equ PORTB6 = 6 ; Port B Data Register bit 6 593.equ PB6 = 6 ; For compatibility 594.equ PORTB7 = 7 ; Port B Data Register bit 7 595.equ PB7 = 7 ; For compatibility 596 597; DDRB - Port B Data Direction Register 598.equ DDB0 = 0 ; Port B Data Direction Register bit 0 599.equ DDB1 = 1 ; Port B Data Direction Register bit 1 600.equ DDB2 = 2 ; Port B Data Direction Register bit 2 601.equ DDB3 = 3 ; Port B Data Direction Register bit 3 602.equ DDB4 = 4 ; Port B Data Direction Register bit 4 603.equ DDB5 = 5 ; Port B Data Direction Register bit 5 604.equ DDB6 = 6 ; Port B Data Direction Register bit 6 605.equ DDB7 = 7 ; Port B Data Direction Register bit 7 606 607; PINB - Port B Input Pins 608.equ PINB0 = 0 ; Port B Input Pins bit 0 609.equ PINB1 = 1 ; Port B Input Pins bit 1 610.equ PINB2 = 2 ; Port B Input Pins bit 2 611.equ PINB3 = 3 ; Port B Input Pins bit 3 612.equ PINB4 = 4 ; Port B Input Pins bit 4 613.equ PINB5 = 5 ; Port B Input Pins bit 5 614.equ PINB6 = 6 ; Port B Input Pins bit 6 615.equ PINB7 = 7 ; Port B Input Pins bit 7 616 617 618; ***** PORTC ************************ 619; PORTC - Port C Data Register 620.equ PORTC0 = 0 ; Port C Data Register bit 0 621.equ PC0 = 0 ; For compatibility 622 623 624; ***** PORTD ************************ 625; PORTD - Data Register, Port D 626.equ PORTD0 = 0 ; 627.equ PD0 = 0 ; For compatibility 628.equ PORTD1 = 1 ; 629.equ PD1 = 1 ; For compatibility 630 631; DDRD 632.equ DDD0 = 0 ; 633.equ DDD1 = 1 ; 634 635; PIND - Input Pins, Port D 636.equ PIND0 = 0 ; 637.equ PIND1 = 1 ; 638 639 640; ***** BOOT_LOAD ******************** 641; SPMCSR - Store Program Memory Control Register 642.equ SPMEN = 0 ; Store Program Memory Enable 643.equ PGERS = 1 ; Page Erase 644.equ PGWRT = 2 ; Page Write 645.equ BLBSET = 3 ; Boot Lock Bit Set 646.equ RWWSRE = 4 ; Read While Write section read enable 647.equ SIGRD = 5 ; Signature Row Read 648.equ RWWSB = 6 ; Read While Write Section Busy 649.equ SPMIE = 7 ; SPM Interrupt Enable 650 651 652; ***** TWI ************************** 653; TWBCSR - TWI Bus Control and Status Register 654.equ TWBCIP = 0 ; TWI Bus Connect/Disconnect Interrupt Polarity 655.equ TWBDT0 = 1 ; TWI Bus Disconnect Time-out Period 656.equ TWBDT1 = 2 ; TWI Bus Disconnect Time-out Period 657.equ TWBCIE = 6 ; TWI Bus Connect/Disconnect Interrupt Enable 658.equ TWBCIF = 7 ; TWI Bus Connect/Disconnect Interrupt Flag 659 660; TWAMR - TWI (Slave) Address Mask Register 661.equ TWAM0 = 1 ; 662.equ TWAM1 = 2 ; 663.equ TWAM2 = 3 ; 664.equ TWAM3 = 4 ; 665.equ TWAM4 = 5 ; 666.equ TWAM5 = 6 ; 667.equ TWAM6 = 7 ; 668 669; TWBR - TWI Bit Rate register 670.equ TWBR0 = 0 ; 671.equ TWBR1 = 1 ; 672.equ TWBR2 = 2 ; 673.equ TWBR3 = 3 ; 674.equ TWBR4 = 4 ; 675.equ TWBR5 = 5 ; 676.equ TWBR6 = 6 ; 677.equ TWBR7 = 7 ; 678 679; TWCR - TWI Control Register 680.equ TWIE = 0 ; TWI Interrupt Enable 681.equ TWEN = 2 ; TWI Enable Bit 682.equ TWWC = 3 ; TWI Write Collition Flag 683.equ TWSTO = 4 ; TWI Stop Condition Bit 684.equ TWSTA = 5 ; TWI Start Condition Bit 685.equ TWEA = 6 ; TWI Enable Acknowledge Bit 686.equ TWINT = 7 ; TWI Interrupt Flag 687 688; TWSR - TWI Status Register 689.equ TWPS0 = 0 ; TWI Prescaler 690.equ TWPS1 = 1 ; TWI Prescaler 691.equ TWS3 = 3 ; TWI Status 692.equ TWS4 = 4 ; TWI Status 693.equ TWS5 = 5 ; TWI Status 694.equ TWS6 = 6 ; TWI Status 695.equ TWS7 = 7 ; TWI Status 696 697; TWDR - TWI Data register 698.equ TWD0 = 0 ; TWI Data Register Bit 0 699.equ TWD1 = 1 ; TWI Data Register Bit 1 700.equ TWD2 = 2 ; TWI Data Register Bit 2 701.equ TWD3 = 3 ; TWI Data Register Bit 3 702.equ TWD4 = 4 ; TWI Data Register Bit 4 703.equ TWD5 = 5 ; TWI Data Register Bit 5 704.equ TWD6 = 6 ; TWI Data Register Bit 6 705.equ TWD7 = 7 ; TWI Data Register Bit 7 706 707; TWAR - TWI (Slave) Address register 708.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit 709.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 710.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 711.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 712.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 713.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 714.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 715.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 716 717 718; ***** BANDGAP ********************** 719; BGCRR - Bandgap Calibration of Resistor Ladder 720.equ BGCR0 = 0 ; Bandgap Calibration of Resistor Ladder Bit 0 721.equ BGCR1 = 1 ; Bandgap Calibration of Resistor Ladder Bit 1 722.equ BGCR2 = 2 ; Bandgap Calibration of Resistor Ladder Bit 2 723.equ BGCR3 = 3 ; Bandgap Calibration of Resistor Ladder Bit 3 724.equ BGCR4 = 4 ; Bandgap Calibration of Resistor Ladder Bit 4 725.equ BGCR5 = 5 ; Bandgap Calibration of Resistor Ladder Bit 5 726.equ BGCR6 = 6 ; Bandgap Calibration of Resistor Ladder Bit 6 727.equ BGCR7 = 7 ; Bandgap Calibration of Resistor Ladder Bit 7 728 729; BGCCR - Bandgap Calibration Register 730.equ BGCC0 = 0 ; BG Calibration of PTAT Current Bit 0 731.equ BGCC1 = 1 ; BG Calibration of PTAT Current Bit 1 732.equ BGCC2 = 2 ; BG Calibration of PTAT Current Bit 2 733.equ BGCC3 = 3 ; BG Calibration of PTAT Current Bit 3 734.equ BGCC4 = 4 ; BG Calibration of PTAT Current Bit 4 735.equ BGCC5 = 5 ; BG Calibration of PTAT Current Bit 5 736.equ BGEN = 7 ; Setting the BGEN bit to one will enable the bandgap voltage reference. This bit must be set before enabling the CC_ADC or V_ADC, and must remain set while either ADC is enabled. 737 738 739; ***** EEPROM *********************** 740; EEDR - EEPROM Data Register 741.equ EEDR0 = 0 ; EEPROM Data Register bit 0 742.equ EEDR1 = 1 ; EEPROM Data Register bit 1 743.equ EEDR2 = 2 ; EEPROM Data Register bit 2 744.equ EEDR3 = 3 ; EEPROM Data Register bit 3 745.equ EEDR4 = 4 ; EEPROM Data Register bit 4 746.equ EEDR5 = 5 ; EEPROM Data Register bit 5 747.equ EEDR6 = 6 ; EEPROM Data Register bit 6 748.equ EEDR7 = 7 ; EEPROM Data Register bit 7 749 750; EECR - EEPROM Control Register 751.equ EERE = 0 ; EEPROM Read Enable 752.equ EEWE = 1 ; EEPROM Write Enable 753.equ EEMWE = 2 ; EEPROM Master Write Enable 754.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 755.equ EEPM0 = 4 ; EEPROM Programming Mode Bits 756.equ EEPM1 = 5 ; EEPROM Programming Mode Bits 757 758 759 760; ***** LOCKSBITS ******************************************************** 761.equ LB1 = 0 ; Lock bit 762.equ LB2 = 1 ; Lock bit 763.equ BLB01 = 2 ; Boot Lock bit 764.equ BLB02 = 3 ; Boot Lock bit 765.equ BLB11 = 4 ; Boot lock bit 766.equ BLB12 = 5 ; Boot lock bit 767 768 769; ***** FUSES ************************************************************ 770; LOW fuse bits 771.equ SUT0 = 1 ; Select start-up time 772.equ SUT1 = 2 ; Select start-up time 773.equ BOOTRST = 3 ; Select reset vector 774.equ BOOTSZ0 = 4 ; Select boot size 775.equ BOOTSZ1 = 5 ; Select boot size 776.equ EESAVE = 6 ; EEPROM memory is preserved through chip erase 777.equ WDTON = 7 ; Watchdog Timer Always On 778 779; HIGH fuse bits 780.equ JTAGEN = 0 ; Enable JTAG 781.equ OCDEN = 1 ; Enable OCD 782 783 784 785; ***** CPU REGISTER DEFINITIONS ***************************************** 786.def XH = r27 787.def XL = r26 788.def YH = r29 789.def YL = r28 790.def ZH = r31 791.def ZL = r30 792 793 794 795; ***** DATA MEMORY DECLARATIONS ***************************************** 796.equ FLASHEND = 0x4fff ; Note: Word address 797.equ IOEND = 0x00ff 798.equ SRAM_START = 0x0100 799.equ SRAM_SIZE = 2048 800.equ RAMEND = 0x08ff 801.equ XRAMEND = 0x07ff 802.equ E2END = 0x01ff 803.equ EEPROMEND = 0x01ff 804.equ EEADRBITS = 9 805#pragma AVRPART MEMORY PROG_FLASH 40960 806#pragma AVRPART MEMORY EEPROM 512 807#pragma AVRPART MEMORY INT_SRAM SIZE 2048 808#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 809 810 811 812; ***** BOOTLOADER DECLARATIONS ****************************************** 813.equ NRWW_START_ADDR = 0x4800 814.equ NRWW_STOP_ADDR = 0x4fff 815.equ RWW_START_ADDR = 0x0 816.equ RWW_STOP_ADDR = 0x47ff 817.equ PAGESIZE = 32 818.equ FIRSTBOOTSTART = 0x4f00 819.equ SECONDBOOTSTART = 0x4e00 820.equ THIRDBOOTSTART = 0x4c00 821.equ FOURTHBOOTSTART = 0x4800 822.equ SMALLBOOTSTART = FIRSTBOOTSTART 823.equ LARGEBOOTSTART = FOURTHBOOTSTART 824 825 826 827; ***** INTERRUPT VECTORS ************************************************ 828.equ BPINTaddr = 0x0002 ; Battery Protection Interrupt 829.equ INT0addr = 0x0004 ; External Interrupt Request 0 830.equ INT1addr = 0x0006 ; External Interrupt Request 1 831.equ INT2addr = 0x0008 ; External Interrupt Request 2 832.equ INT3addr = 0x000a ; External Interrupt Request 3 833.equ PCI0addr = 0x000c ; Pin Change Interrupt 0 834.equ PCI1addr = 0x000e ; Pin Change Interrupt 1 835.equ WDTaddr = 0x0010 ; Watchdog Timeout Interrupt 836.equ WUTaddr = 0x0012 ; Wakeup timer overflow 837.equ OC1addr = 0x0014 ; Timer/Counter 1 Compare Match 838.equ OVF1addr = 0x0016 ; Timer/Counter 1 Overflow 839.equ OC0Aaddr = 0x0018 ; Timer/Counter0 Compare A Match 840.equ OC0Baddr = 0x001a ; Timer/Counter0 Compare B Match 841.equ OVF0addr = 0x001c ; Timer/Counter0 Overflow 842.equ TWICDaddr = 0x001e ; Two-Wire Bus Connect/Disconnect 843.equ TWIaddr = 0x0020 ; Two-Wire Serial Interface 844.equ VADCaddr = 0x0022 ; Voltage ADC Conversion Complete 845.equ CADICaddr = 0x0024 ; Coulomb Counter ADC Conversion Complete 846.equ CADRCaddr = 0x0026 ; Coloumb Counter ADC Regular Current 847.equ CADACaddr = 0x0028 ; Coloumb Counter ADC Accumulator 848.equ ERDYaddr = 0x002a ; EEPROM Ready 849.equ SPMRaddr = 0x002c ; Store Program Memory Ready 850 851.equ INT_VECTORS_SIZE = 46 ; size in words 852 853#endif /* _M406DEF_INC_ */ 854 855; ***** END OF FILE ****************************************************** 856