1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
2;***** Created: 2005-01-11 10:30 ******* Source: AT90PWM2.xml ************
3;*************************************************************************
4;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
5;*
6;* Number            : AVR000
7;* File Name         : "pwm2def.inc"
8;* Title             : Register/Bit Definitions for the AT90PWM2
9;* Date              : 2005-01-11
10;* Version           : 2.14
11;* Support E-mail    : avr@atmel.com
12;* Target MCU        : AT90PWM2
13;*
14;* DESCRIPTION
15;* When including this file in the assembly program file, all I/O register
16;* names and I/O register bit names appearing in the data book can be used.
17;* In addition, the six registers forming the three data pointers X, Y and
18;* Z have been assigned names XL - ZH. Highest RAM address for Internal
19;* SRAM is also defined
20;*
21;* The Register names are represented by their hexadecimal address.
22;*
23;* The Register Bit names are represented by their bit number (0-7).
24;*
25;* Please observe the difference in using the bit names with instructions
26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
27;* (skip if bit in register set/cleared). The following example illustrates
28;* this:
29;*
30;* in    r16,PORTB             ;read PORTB latch
31;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
32;* out   PORTB,r16             ;output to PORTB
33;*
34;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
35;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
36;* rjmp  TOV0_is_set           ;jump if set
37;* ...                         ;otherwise do something else
38;*************************************************************************
39
40#ifndef _PWM2DEF_INC_
41#define _PWM2DEF_INC_
42
43
44#pragma partinc 0
45
46; ***** SPECIFY DEVICE ***************************************************
47.device AT90PWM2
48#pragma AVRPART ADMIN PART_NAME AT90PWM2
49.equ	SIGNATURE_000	= 0x1e
50.equ	SIGNATURE_001	= 0x93
51.equ	SIGNATURE_002	= 0x81
52
53#pragma AVRPART CORE CORE_VERSION V2E
54
55
56; ***** I/O REGISTER DEFINITIONS *****************************************
57; NOTE:
58; Definitions marked "MEMORY MAPPED"are extended I/O ports
59; and cannot be used with IN/OUT instructions
60.equ	PICR2H	= 0xff	; MEMORY MAPPED
61.equ	PICR2L	= 0xfe	; MEMORY MAPPED
62.equ	PFRC2B	= 0xfd	; MEMORY MAPPED
63.equ	PFRC2A	= 0xfc	; MEMORY MAPPED
64.equ	PCTL2	= 0xfb	; MEMORY MAPPED
65.equ	PCNF2	= 0xfa	; MEMORY MAPPED
66.equ	OCR2RBH	= 0xf9	; MEMORY MAPPED
67.equ	OCR2RBL	= 0xf8	; MEMORY MAPPED
68.equ	OCR2SBH	= 0xf7	; MEMORY MAPPED
69.equ	OCR2SBL	= 0xf6	; MEMORY MAPPED
70.equ	OCR2RAH	= 0xf5	; MEMORY MAPPED
71.equ	OCR2RAL	= 0xf4	; MEMORY MAPPED
72.equ	OCR2SAH	= 0xf3	; MEMORY MAPPED
73.equ	OCR2SAL	= 0xf2	; MEMORY MAPPED
74.equ	POM2	= 0xf1	; MEMORY MAPPED
75.equ	PSOC2	= 0xf0	; MEMORY MAPPED
76.equ	PICR1H	= 0xef	; MEMORY MAPPED
77.equ	PICR1L	= 0xee	; MEMORY MAPPED
78.equ	PFRC1B	= 0xed	; MEMORY MAPPED
79.equ	PFRC1A	= 0xec	; MEMORY MAPPED
80.equ	PCTL1	= 0xeb	; MEMORY MAPPED
81.equ	PCNF1	= 0xea	; MEMORY MAPPED
82.equ	OCR1RBH	= 0xe9	; MEMORY MAPPED
83.equ	OCR1RBL	= 0xe8	; MEMORY MAPPED
84.equ	OCR1SBH	= 0xe7	; MEMORY MAPPED
85.equ	OCR1SBL	= 0xe6	; MEMORY MAPPED
86.equ	OCR1RAH	= 0xe5	; MEMORY MAPPED
87.equ	OCR1RAL	= 0xe4	; MEMORY MAPPED
88.equ	OCR1SAH	= 0xe3	; MEMORY MAPPED
89.equ	OCR1SAL	= 0xe2	; MEMORY MAPPED
90.equ	PSOC1	= 0xe0	; MEMORY MAPPED
91.equ	PICR0H	= 0xdf	; MEMORY MAPPED
92.equ	PICR0L	= 0xde	; MEMORY MAPPED
93.equ	PFRC0B	= 0xdd	; MEMORY MAPPED
94.equ	PFRC0A	= 0xdc	; MEMORY MAPPED
95.equ	PCTL0	= 0xdb	; MEMORY MAPPED
96.equ	PCNF0	= 0xda	; MEMORY MAPPED
97.equ	OCR0RBH	= 0xd9	; MEMORY MAPPED
98.equ	OCR0RBL	= 0xd8	; MEMORY MAPPED
99.equ	OCR0SBH	= 0xd7	; MEMORY MAPPED
100.equ	OCR0SBL	= 0xd6	; MEMORY MAPPED
101.equ	OCR0RAH	= 0xd5	; MEMORY MAPPED
102.equ	OCR0RAL	= 0xd4	; MEMORY MAPPED
103.equ	OCR0SAH	= 0xd3	; MEMORY MAPPED
104.equ	OCR0SAL	= 0xd2	; MEMORY MAPPED
105.equ	PSOC0	= 0xd0	; MEMORY MAPPED
106.equ	EUDR	= 0xce	; MEMORY MAPPED
107.equ	MUBRRH	= 0xcd	; MEMORY MAPPED
108.equ	MUBRRL	= 0xcc	; MEMORY MAPPED
109.equ	EUCSRC	= 0xca	; MEMORY MAPPED
110.equ	EUCSRB	= 0xc9	; MEMORY MAPPED
111.equ	EUCSRA	= 0xc8	; MEMORY MAPPED
112.equ	UDR	= 0xc6	; MEMORY MAPPED
113.equ	UBRRH	= 0xc5	; MEMORY MAPPED
114.equ	UBRRL	= 0xc4	; MEMORY MAPPED
115.equ	UCSRC	= 0xc2	; MEMORY MAPPED
116.equ	UCSRB	= 0xc1	; MEMORY MAPPED
117.equ	UCSRA	= 0xc0	; MEMORY MAPPED
118.equ	AC2CON	= 0xaf	; MEMORY MAPPED
119.equ	AC1CON	= 0xae	; MEMORY MAPPED
120.equ	AC0CON	= 0xad	; MEMORY MAPPED
121.equ	DACH	= 0xac	; MEMORY MAPPED
122.equ	DACL	= 0xab	; MEMORY MAPPED
123.equ	DACON	= 0xaa	; MEMORY MAPPED
124.equ	PIM2	= 0xa5	; MEMORY MAPPED
125.equ	PIFR2	= 0xa4	; MEMORY MAPPED
126.equ	PIM1	= 0xa3	; MEMORY MAPPED
127.equ	PIFR1	= 0xa2	; MEMORY MAPPED
128.equ	PIM0	= 0xa1	; MEMORY MAPPED
129.equ	PIFR0	= 0xa0	; MEMORY MAPPED
130.equ	OCR1BH	= 0x8b	; MEMORY MAPPED
131.equ	OCR1BL	= 0x8a	; MEMORY MAPPED
132.equ	OCR1AH	= 0x89	; MEMORY MAPPED
133.equ	OCR1AL	= 0x88	; MEMORY MAPPED
134.equ	ICR1H	= 0x87	; MEMORY MAPPED
135.equ	ICR1L	= 0x86	; MEMORY MAPPED
136.equ	TCNT1H	= 0x85	; MEMORY MAPPED
137.equ	TCNT1L	= 0x84	; MEMORY MAPPED
138.equ	TCCR1C	= 0x82	; MEMORY MAPPED
139.equ	TCCR1B	= 0x81	; MEMORY MAPPED
140.equ	TCCR1A	= 0x80	; MEMORY MAPPED
141.equ	DIDR1	= 0x7f	; MEMORY MAPPED
142.equ	DIDR0	= 0x7e	; MEMORY MAPPED
143.equ	ADMUX	= 0x7c	; MEMORY MAPPED
144.equ	ADCSRB	= 0x7b	; MEMORY MAPPED
145.equ	ADCSRA	= 0x7a	; MEMORY MAPPED
146.equ	ADCH	= 0x79	; MEMORY MAPPED
147.equ	ADCL	= 0x78	; MEMORY MAPPED
148.equ	AMP1CSR	= 0x77	; MEMORY MAPPED
149.equ	AMP0CSR	= 0x76	; MEMORY MAPPED
150.equ	TIMSK1	= 0x6f	; MEMORY MAPPED
151.equ	TIMSK0	= 0x6e	; MEMORY MAPPED
152.equ	EICRA	= 0x69	; MEMORY MAPPED
153.equ	OSCCAL	= 0x66	; MEMORY MAPPED
154.equ	PRR	= 0x64	; MEMORY MAPPED
155.equ	CLKPR	= 0x61	; MEMORY MAPPED
156.equ	WDTCSR	= 0x60	; MEMORY MAPPED
157.equ	SREG	= 0x3f
158.equ	SPH	= 0x3e
159.equ	SPL	= 0x3d
160.equ	SPMCSR	= 0x37
161.equ	MCUCR	= 0x35
162.equ	MCUSR	= 0x34
163.equ	SMCR	= 0x33
164.equ	ACSR	= 0x30
165.equ	SPDR	= 0x2e
166.equ	SPSR	= 0x2d
167.equ	SPCR	= 0x2c
168.equ	PLLCSR	= 0x29
169.equ	OCR0B	= 0x28
170.equ	OCR0A	= 0x27
171.equ	TCNT0	= 0x26
172.equ	TCCR0B	= 0x25
173.equ	TCCR0A	= 0x24
174.equ	GTCCR	= 0x23
175.equ	EEARH	= 0x22
176.equ	EEARL	= 0x21
177.equ	EEDR	= 0x20
178.equ	EECR	= 0x1f
179.equ	GPIOR0	= 0x1e
180.equ	EIMSK	= 0x1d
181.equ	EIFR	= 0x1c
182.equ	GPIOR3	= 0x1b
183.equ	GPIOR2	= 0x1a
184.equ	GPIOR1	= 0x19
185.equ	TIFR1	= 0x16
186.equ	TIFR0	= 0x15
187.equ	PORTE	= 0x0e
188.equ	DDRE	= 0x0d
189.equ	PINE	= 0x0c
190.equ	PORTD	= 0x0b
191.equ	DDRD	= 0x0a
192.equ	PIND	= 0x09
193.equ	PORTC	= 0x08
194.equ	DDRC	= 0x07
195.equ	PINC	= 0x06
196.equ	PORTB	= 0x05
197.equ	DDRB	= 0x04
198.equ	PINB	= 0x03
199
200
201; ***** BIT DEFINITIONS **************************************************
202
203; ***** PORTB ************************
204; PORTB - Port B Data Register
205.equ	PORTB0	= 0	; Port B Data Register bit 0
206.equ	PB0	= 0	; For compatibility
207.equ	PORTB1	= 1	; Port B Data Register bit 1
208.equ	PB1	= 1	; For compatibility
209.equ	PORTB2	= 2	; Port B Data Register bit 2
210.equ	PB2	= 2	; For compatibility
211.equ	PORTB3	= 3	; Port B Data Register bit 3
212.equ	PB3	= 3	; For compatibility
213.equ	PORTB4	= 4	; Port B Data Register bit 4
214.equ	PB4	= 4	; For compatibility
215.equ	PORTB5	= 5	; Port B Data Register bit 5
216.equ	PB5	= 5	; For compatibility
217.equ	PORTB6	= 6	; Port B Data Register bit 6
218.equ	PB6	= 6	; For compatibility
219.equ	PORTB7	= 7	; Port B Data Register bit 7
220.equ	PB7	= 7	; For compatibility
221
222; DDRB - Port B Data Direction Register
223.equ	DDB0	= 0	; Port B Data Direction Register bit 0
224.equ	DDB1	= 1	; Port B Data Direction Register bit 1
225.equ	DDB2	= 2	; Port B Data Direction Register bit 2
226.equ	DDB3	= 3	; Port B Data Direction Register bit 3
227.equ	DDB4	= 4	; Port B Data Direction Register bit 4
228.equ	DDB5	= 5	; Port B Data Direction Register bit 5
229.equ	DDB6	= 6	; Port B Data Direction Register bit 6
230.equ	DDB7	= 7	; Port B Data Direction Register bit 7
231
232; PINB - Port B Input Pins
233.equ	PINB0	= 0	; Port B Input Pins bit 0
234.equ	PINB1	= 1	; Port B Input Pins bit 1
235.equ	PINB2	= 2	; Port B Input Pins bit 2
236.equ	PINB3	= 3	; Port B Input Pins bit 3
237.equ	PINB4	= 4	; Port B Input Pins bit 4
238.equ	PINB5	= 5	; Port B Input Pins bit 5
239.equ	PINB6	= 6	; Port B Input Pins bit 6
240.equ	PINB7	= 7	; Port B Input Pins bit 7
241
242
243; ***** PORTD ************************
244; PORTD - Port D Data Register
245.equ	PORTD0	= 0	; Port D Data Register bit 0
246.equ	PD0	= 0	; For compatibility
247.equ	PORTD1	= 1	; Port D Data Register bit 1
248.equ	PD1	= 1	; For compatibility
249.equ	PORTD2	= 2	; Port D Data Register bit 2
250.equ	PD2	= 2	; For compatibility
251.equ	PORTD3	= 3	; Port D Data Register bit 3
252.equ	PD3	= 3	; For compatibility
253.equ	PORTD4	= 4	; Port D Data Register bit 4
254.equ	PD4	= 4	; For compatibility
255.equ	PORTD5	= 5	; Port D Data Register bit 5
256.equ	PD5	= 5	; For compatibility
257.equ	PORTD6	= 6	; Port D Data Register bit 6
258.equ	PD6	= 6	; For compatibility
259.equ	PORTD7	= 7	; Port D Data Register bit 7
260.equ	PD7	= 7	; For compatibility
261
262; DDRD - Port D Data Direction Register
263.equ	DDD0	= 0	; Port D Data Direction Register bit 0
264.equ	DDD1	= 1	; Port D Data Direction Register bit 1
265.equ	DDD2	= 2	; Port D Data Direction Register bit 2
266.equ	DDD3	= 3	; Port D Data Direction Register bit 3
267.equ	DDD4	= 4	; Port D Data Direction Register bit 4
268.equ	DDD5	= 5	; Port D Data Direction Register bit 5
269.equ	DDD6	= 6	; Port D Data Direction Register bit 6
270.equ	DDD7	= 7	; Port D Data Direction Register bit 7
271
272; PIND - Port D Input Pins
273.equ	PIND0	= 0	; Port D Input Pins bit 0
274.equ	PIND1	= 1	; Port D Input Pins bit 1
275.equ	PIND2	= 2	; Port D Input Pins bit 2
276.equ	PIND3	= 3	; Port D Input Pins bit 3
277.equ	PIND4	= 4	; Port D Input Pins bit 4
278.equ	PIND5	= 5	; Port D Input Pins bit 5
279.equ	PIND6	= 6	; Port D Input Pins bit 6
280.equ	PIND7	= 7	; Port D Input Pins bit 7
281
282
283; ***** BOOT_LOAD ********************
284; SPMCSR - Store Program Memory Control Register
285.equ	SPMCR	= SPMCSR	; For compatibility
286.equ	SPMEN	= 0	; Store Program Memory Enable
287.equ	PGERS	= 1	; Page Erase
288.equ	PGWRT	= 2	; Page Write
289.equ	BLBSET	= 3	; Boot Lock Bit Set
290.equ	RWWSRE	= 4	; Read While Write section read enable
291.equ	ASRE	= RWWSRE	; For compatibility
292.equ	RWWSB	= 6	; Read While Write Section Busy
293.equ	ASB	= RWWSB	; For compatibility
294.equ	SPMIE	= 7	; SPM Interrupt Enable
295
296
297; ***** EEPROM ***********************
298; EEDR - EEPROM Data Register
299.equ	EEDR0	= 0	; EEPROM Data Register bit 0
300.equ	EEDR1	= 1	; EEPROM Data Register bit 1
301.equ	EEDR2	= 2	; EEPROM Data Register bit 2
302.equ	EEDR3	= 3	; EEPROM Data Register bit 3
303.equ	EEDR4	= 4	; EEPROM Data Register bit 4
304.equ	EEDR5	= 5	; EEPROM Data Register bit 5
305.equ	EEDR6	= 6	; EEPROM Data Register bit 6
306.equ	EEDR7	= 7	; EEPROM Data Register bit 7
307
308; EECR - EEPROM Control Register
309.equ	EERE	= 0	; EEPROM Read Enable
310.equ	EEWE	= 1	; EEPROM Write Enable
311.equ	EEMWE	= 2	; EEPROM Master Write Enable
312.equ	EERIE	= 3	; EEPROM Ready Interrupt Enable
313
314
315; ***** PSC0 *************************
316; PICR0H - PSC 0 Input Capture Register High
317.equ	PICR0_8	= 0	;
318.equ	PICR0_9	= 1	;
319.equ	PICR0_10	= 2	;
320.equ	PICR0_11	= 3	;
321
322; PICR0L - PSC 0 Input Capture Register Low
323.equ	PICR0_0	= 0	;
324.equ	PICR0_1	= 1	;
325.equ	PICR0_2	= 2	;
326.equ	PICR0_3	= 3	;
327.equ	PICR0_4	= 4	;
328.equ	PICR0_5	= 5	;
329.equ	PICR0_6	= 6	;
330.equ	PICR0_7	= 7	;
331
332; PFRC0B - PSC 0 Input B Control
333.equ	PRFM0B0	= 0	; PSC 0 Retrigger and Fault Mode for Part B
334.equ	PRFM0B1	= 1	; PSC 0 Retrigger and Fault Mode for Part B
335.equ	PRFM0B2	= 2	; PSC 0 Retrigger and Fault Mode for Part B
336.equ	PRFM0B3	= 3	; PSC 0 Retrigger and Fault Mode for Part B
337.equ	PFLTE0B	= 4	; PSC 0 Filter Enable on Input Part B
338.equ	PELEV0B	= 5	; PSC 0 Edge Level Selector on Input Part B
339.equ	PISEL0B	= 6	; PSC 0 Input Select for Part B
340.equ	PCAE0B	= 7	; PSC 0 Capture Enable Input Part B
341
342; PFRC0A - PSC 0 Input A Control
343.equ	PRFM0A0	= 0	; PSC 0 Retrigger and Fault Mode for Part A
344.equ	PRFM0A1	= 1	; PSC 0 Retrigger and Fault Mode for Part A
345.equ	PRFM0A2	= 2	; PSC 0 Retrigger and Fault Mode for Part A
346.equ	PRFM0A3	= 3	; PSC 0 Retrigger and Fault Mode for Part A
347.equ	PFLTE0A	= 4	; PSC 0 Filter Enable on Input Part A
348.equ	PELEV0A	= 5	; PSC 0 Edge Level Selector on Input Part A
349.equ	PISEL0A	= 6	; PSC 0 Input Select for Part A
350.equ	PCAE0A	= 7	; PSC 0 Capture Enable Input Part A
351
352; PCTL0 - PSC 0 Control Register
353.equ	PRUN0	= 0	; PSC 0 Run
354.equ	PCCYC0	= 1	; PSC0 Complete Cycle
355.equ	PARUN0	= 2	; PSC0 Auto Run
356.equ	PAOC0A	= 3	; PSC 0 Asynchronous Output Control A
357.equ	PAOC0B	= 4	; PSC 0 Asynchronous Output Control B
358.equ	PBFM0	= 5	; PSC 0 Balance Flank Width Modulation
359.equ	PPRE00	= 6	; PSC 0 Prescaler Select 0
360.equ	PPRE01	= 7	; PSC 0 Prescaler Select 1
361
362; PCNF0 - PSC 0 Configuration Register
363.equ	PCLKSEL0	= 1	; PSC 0 Input Clock Select
364.equ	POP0	= 2	; PSC 0 Output Polarity
365.equ	PMODE00	= 3	; PSC 0 Mode
366.equ	PMODE01	= 4	; PSC 0 Mode
367.equ	PLOCK0	= 5	; PSC 0 Lock
368.equ	PALOCK0	= 6	; PSC 0 Autolock
369.equ	PFIFTY0	= 7	; PSC 0 Fifty
370
371; OCR0RBH - Output Compare RB Register High
372.equ	OCR0RB_8	= 0	;
373.equ	OCR0RB_9	= 1	;
374.equ	OCR0RB_00	= 2	;
375.equ	OCR0RB_01	= 3	;
376.equ	OCR0RB_02	= 4	;
377.equ	OCR0RB_03	= 5	;
378.equ	OCR0RB_04	= 6	;
379.equ	OCR0RB_05	= 7	;
380
381; OCR0RBL - Output Compare RB Register Low
382.equ	OCR0RB_0	= 0	;
383.equ	OCR0RB_1	= 1	;
384.equ	OCR0RB_2	= 2	;
385.equ	OCR0RB_3	= 3	;
386.equ	OCR0RB_4	= 4	;
387.equ	OCR0RB_5	= 5	;
388.equ	OCR0RB_6	= 6	;
389.equ	OCR0RB_7	= 7	;
390
391; OCR0SBH - Output Compare SB Register High
392.equ	OCR0SB_8	= 0	;
393.equ	OCR0SB_9	= 1	;
394.equ	OCR0SB_00	= 2	;
395.equ	OCR0SB_01	= 3	;
396
397; OCR0SBL - Output Compare SB Register Low
398.equ	OCR0SB_0	= 0	;
399.equ	OCR0SB_1	= 1	;
400.equ	OCR0SB_2	= 2	;
401.equ	OCR0SB_3	= 3	;
402.equ	OCR0SB_4	= 4	;
403.equ	OCR0SB_5	= 5	;
404.equ	OCR0SB_6	= 6	;
405.equ	OCR0SB_7	= 7	;
406
407; OCR0RAH - Output Compare RA Register High
408.equ	OCR0RA_8	= 0	;
409.equ	OCR0RA_9	= 1	;
410.equ	OCR0RA_00	= 2	;
411.equ	OCR0RA_01	= 3	;
412
413; OCR0RAL - Output Compare RA Register Low
414.equ	OCR0RA_0	= 0	;
415.equ	OCR0RA_1	= 1	;
416.equ	OCR0RA_2	= 2	;
417.equ	OCR0RA_3	= 3	;
418.equ	OCR0RA_4	= 4	;
419.equ	OCR0RA_5	= 5	;
420.equ	OCR0RA_6	= 6	;
421.equ	OCR0RA_7	= 7	;
422
423; OCR0SAH - Output Compare SA Register High
424.equ	OCR0SA_8	= 0	;
425.equ	OCR0SA_9	= 1	;
426.equ	OCR0SA_00	= 2	;
427.equ	OCR0SA_01	= 3	;
428
429; OCR0SAL - Output Compare SA Register Low
430.equ	OCR0SA_0	= 0	;
431.equ	OCR0SA_1	= 1	;
432.equ	OCR0SA_2	= 2	;
433.equ	OCR0SA_3	= 3	;
434.equ	OCR0SA_4	= 4	;
435.equ	OCR0SA_5	= 5	;
436.equ	OCR0SA_6	= 6	;
437.equ	OCR0SA_7	= 7	;
438
439; PSOC0 - PSC0 Synchro and Output Configuration
440.equ	POEN0A	= 0	; PSCOUT00 Output Enable
441.equ	POEN0B	= 2	; PSCOUT01 Output Enable
442.equ	PSYNC00	= 4	; Synchronization Out for ADC Selection
443.equ	PSYNC01	= 5	; Synchronization Out for ADC Selection
444
445; PIM0 - PSC0 Interrupt Mask Register
446.equ	PEOPE0	= 0	; End of Cycle Interrupt Enable
447.equ	PEVE0A	= 3	; External Event A Interrupt Enable
448.equ	PEVE0B	= 4	; External Event B Interrupt Enable
449.equ	PSEIE0	= 5	; PSC 0 Synchro Error Interrupt Enable
450
451; PIFR0 - PSC0 Interrupt Flag Register
452.equ	PEOP0	= 0	; End of PSC0 Interrupt
453.equ	PRN00	= 1	; Ramp Number
454.equ	PRN01	= 2	; Ramp Number
455.equ	PEV0A	= 3	; External Event A Interrupt
456.equ	PEV0B	= 4	; External Event B Interrupt
457.equ	PSEI0	= 5	; PSC 0 Synchro Error Interrupt
458
459
460; ***** PSC2 *************************
461; PICR2H - PSC 2 Input Capture Register High
462.equ	PICR2_8	= 0	;
463.equ	PICR2_9	= 1	;
464.equ	PICR2_10	= 2	;
465.equ	PICR2_11	= 3	;
466
467; PICR2L - PSC 2 Input Capture Register Low
468.equ	PICR2_0	= 0	;
469.equ	PICR2_1	= 1	;
470.equ	PICR2_2	= 2	;
471.equ	PICR2_3	= 3	;
472.equ	PICR2_4	= 4	;
473.equ	PICR2_5	= 5	;
474.equ	PICR2_6	= 6	;
475.equ	PICR2_7	= 7	;
476
477; PFRC2B - PSC 2 Input B Control
478.equ	PRFM2B0	= 0	; PSC 2 Retrigger and Fault Mode for Part B
479.equ	PRFM2B1	= 1	; PSC 2 Retrigger and Fault Mode for Part B
480.equ	PRFM2B2	= 2	; PSC 2 Retrigger and Fault Mode for Part B
481.equ	PRFM2B3	= 3	; PSC 2 Retrigger and Fault Mode for Part B
482.equ	PFLTE2B	= 4	; PSC 2 Filter Enable on Input Part B
483.equ	PELEV2B	= 5	; PSC 2 Edge Level Selector on Input Part B
484.equ	PISEL2B	= 6	; PSC 2 Input Select for Part B
485.equ	PCAE2B	= 7	; PSC 2 Capture Enable Input Part B
486
487; PFRC2A - PSC 2 Input B Control
488.equ	PRFM2A0	= 0	; PSC 2 Retrigger and Fault Mode for Part A
489.equ	PRFM2A1	= 1	; PSC 2 Retrigger and Fault Mode for Part A
490.equ	PRFM2A2	= 2	; PSC 2 Retrigger and Fault Mode for Part A
491.equ	PRFM2A3	= 3	; PSC 2 Retrigger and Fault Mode for Part A
492.equ	PFLTE2A	= 4	; PSC 2 Filter Enable on Input Part A
493.equ	PELEV2A	= 5	; PSC 2 Edge Level Selector on Input Part A
494.equ	PISEL2A	= 6	; PSC 2 Input Select for Part A
495.equ	PCAE2A	= 7	; PSC 2 Capture Enable Input Part A
496
497; PCTL2 - PSC 2 Control Register
498.equ	PRUN2	= 0	; PSC 2 Run
499.equ	PCCYC2	= 1	; PSC2 Complete Cycle
500.equ	PARUN2	= 2	; PSC2 Auto Run
501.equ	PAOC2A	= 3	; PSC 2 Asynchronous Output Control A
502.equ	PAOC2B	= 4	; PSC 2 Asynchronous Output Control B
503.equ	PBFM2	= 5	; Balance Flank Width Modulation
504.equ	PPRE20	= 6	; PSC 2 Prescaler Select 0
505.equ	PPRE21	= 7	; PSC 2 Prescaler Select 1
506
507; PCNF2 - PSC 2 Configuration Register
508.equ	POME2	= 0	; PSC 2 Output Matrix Enable
509.equ	PCLKSEL2	= 1	; PSC 2 Input Clock Select
510.equ	POP2	= 2	; PSC 2 Output Polarity
511.equ	PMODE20	= 3	; PSC 2 Mode
512.equ	PMODE21	= 4	; PSC 2 Mode
513.equ	PLOCK2	= 5	; PSC 2 Lock
514.equ	PALOCK2	= 6	; PSC 2 Autolock
515.equ	PFIFTY2	= 7	; PSC 2 Fifty
516
517; OCR2RBH - Output Compare RB Register High
518.equ	OCR2RB_8	= 0	;
519.equ	OCR2RB_9	= 1	;
520.equ	OCR2RB_10	= 2	;
521.equ	OCR2RB_11	= 3	;
522.equ	OCR2RB_12	= 4	;
523.equ	OCR2RB_13	= 5	;
524.equ	OCR2RB_14	= 6	;
525.equ	OCR2RB_15	= 7	;
526
527; OCR2RBL - Output Compare RB Register Low
528.equ	OCR2RB_0	= 0	;
529.equ	OCR2RB_1	= 1	;
530.equ	OCR2RB_2	= 2	;
531.equ	OCR2RB_3	= 3	;
532.equ	OCR2RB_4	= 4	;
533.equ	OCR2RB_5	= 5	;
534.equ	OCR2RB_6	= 6	;
535.equ	OCR2RB_7	= 7	;
536
537; OCR2SBH - Output Compare SB Register High
538.equ	OCR2SB_8	= 0	;
539.equ	OCR2SB_9	= 1	;
540.equ	OCR2SB_10	= 2	;
541.equ	OCR2SB_11	= 3	;
542
543; OCR2SBL - Output Compare SB Register Low
544.equ	OCR2SB_0	= 0	;
545.equ	OCR2SB_1	= 1	;
546.equ	OCR2SB_2	= 2	;
547.equ	OCR2SB_3	= 3	;
548.equ	OCR2SB_4	= 4	;
549.equ	OCR2SB_5	= 5	;
550.equ	OCR2SB_6	= 6	;
551.equ	OCR2SB_7	= 7	;
552
553; OCR2RAH - Output Compare RA Register High
554.equ	OCR2RA_8	= 0	;
555.equ	OCR2RA_9	= 1	;
556.equ	OCR2RA_10	= 2	;
557.equ	OCR2RA_11	= 3	;
558
559; OCR2RAL - Output Compare RA Register Low
560.equ	OCR2RA_0	= 0	;
561.equ	OCR2RA_1	= 1	;
562.equ	OCR2RA_2	= 2	;
563.equ	OCR2RA_3	= 3	;
564.equ	OCR2RA_4	= 4	;
565.equ	OCR2RA_5	= 5	;
566.equ	OCR2RA_6	= 6	;
567.equ	OCR2RA_7	= 7	;
568
569; OCR2SAH - Output Compare SA Register High
570.equ	OCR2SA_8	= 0	;
571.equ	OCR2SA_9	= 1	;
572.equ	OCR2SA_10	= 2	;
573.equ	OCR2SA_11	= 3	;
574
575; OCR2SAL - Output Compare SA Register Low
576.equ	OCR2SA_0	= 0	;
577.equ	OCR2SA_1	= 1	;
578.equ	OCR2SA_2	= 2	;
579.equ	OCR2SA_3	= 3	;
580.equ	OCR2SA_4	= 4	;
581.equ	OCR2SA_5	= 5	;
582.equ	OCR2SA_6	= 6	;
583.equ	OCR2SA_7	= 7	;
584
585; POM2 - PSC 2 Output Matrix
586.equ	POMV2A0	= 0	; Output Matrix Output A Ramp 0
587.equ	POMV2A1	= 1	; Output Matrix Output A Ramp 1
588.equ	POMV2A2	= 2	; Output Matrix Output A Ramp 2
589.equ	POMV2A3	= 3	; Output Matrix Output A Ramp 3
590.equ	POMV2B0	= 4	; Output Matrix Output B Ramp 0
591.equ	POMV2B1	= 5	; Output Matrix Output B Ramp 2
592.equ	POMV2B2	= 6	; Output Matrix Output B Ramp 2
593.equ	POMV2B3	= 7	; Output Matrix Output B Ramp 3
594
595; PSOC2 - PSC2 Synchro and Output Configuration
596.equ	POEN2A	= 0	; PSCOUT20 Output Enable
597.equ	POEN2C	= 1	; PSCOUT22 Output Enable
598.equ	POEN2B	= 2	; PSCOUT21 Output Enable
599.equ	POEN2D	= 3	; PSCOUT23 Output Enable
600.equ	PSYNC2_0	= 4	; Synchronization Out for ADC Selection
601.equ	PSYNC2_1	= 5	; Synchronization Out for ADC Selection
602.equ	POS22	= 6	; PSC 2 Output 22 Select
603.equ	POS23	= 7	; PSC 2 Output 23 Select
604
605; PIM2 - PSC2 Interrupt Mask Register
606.equ	PEOPE2	= 0	; End of Cycle Interrupt Enable
607.equ	PEVE2A	= 3	; External Event A Interrupt Enable
608.equ	PEVE2B	= 4	; External Event B Interrupt Enable
609.equ	PSEIE2	= 5	; PSC 2 Synchro Error Interrupt Enable
610
611; PIFR2 - PSC2 Interrupt Flag Register
612.equ	PEOP2	= 0	; End of PSC2 Interrupt
613.equ	PRN20	= 1	; Ramp Number
614.equ	PRN21	= 2	; Ramp Number
615.equ	PEV2A	= 3	; External Event A Interrupt
616.equ	PEV2B	= 4	; External Event B Interrupt
617.equ	PSEI2	= 5	; PSC 2 Synchro Error Interrupt
618
619
620; ***** EUSART ***********************
621; EUDR - EUSART I/O Data Register
622.equ	EUDR0	= 0	; EUSART I/O Data Register bit 0
623.equ	EUDR1	= 1	; EUSART I/O Data Register bit 1
624.equ	EUDR2	= 2	; EUSART I/O Data Register bit 2
625.equ	EUDR3	= 3	; EUSART I/O Data Register bit 3
626.equ	EUDR4	= 4	; EUSART I/O Data Register bit 4
627.equ	EUDR5	= 5	; EUSART I/O Data Register bit 5
628.equ	EUDR6	= 6	; EUSART I/O Data Register bit 6
629.equ	EUDR7	= 7	; EUSART I/O Data Register bit 7
630
631; EUCSRA - EUSART Control and Status Register A
632.equ	URxS0	= 0	; EUSART Control and Status Register A Bit 0
633.equ	URxS1	= 1	; EUSART Control and Status Register A Bit 1
634.equ	URxS2	= 2	; EUSART Control and Status Register A Bit 2
635.equ	URxS3	= 3	; EUSART Control and Status Register A Bit 3
636.equ	UTxS0	= 4	; EUSART Control and Status Register A Bit 4
637.equ	UTxS1	= 5	; EUSART Control and Status Register A Bit 5
638.equ	UTxS2	= 6	; EUSART Control and Status Register A Bit 6
639.equ	UTxS3	= 7	; EUSART Control and Status Register A Bit 7
640
641; EUCSRB - EUSART Control Register B
642.equ	BODR	= 0	; Order Bit
643.equ	EMCH	= 1	; Manchester Mode Bit
644.equ	EUSBS	= 3	; EUSBS Enable Bit
645.equ	EUSART	= 4	; EUSART Enable Bit
646
647; EUCSRC - EUSART Status Register C
648.equ	STP0	= 0	; Stop Bit 0
649.equ	STP1	= 1	; Stop Bit 1
650.equ	F1617	= 2	; F1617 Bit
651.equ	FEM	= 3	; Frame Error Manchester Bit
652
653; MUBRRH - Manchester Receiver Baud Rate Register High Byte
654.equ	MUBRR8	= 0	; Manchester Receiver Baud Rate Register Bit 8
655.equ	MUBRR9	= 1	; Manchester Receiver Baud Rate Register Bit 9
656.equ	MUBRR10	= 2	; Manchester Receiver Baud Rate Register Bit 10
657.equ	MUBRR11	= 3	; Manchester Receiver Baud Rate Register Bit 11
658.equ	MUBRR12	= 4	; Manchester Receiver Baud Rate Register Bit 12
659.equ	MUBRR13	= 5	; Manchester Receiver Baud Rate Register Bit 13
660.equ	MUBRR14	= 6	; Manchester Receiver Baud Rate Register Bit 14
661.equ	MUBRR15	= 7	; Manchester Receiver Baud Rate Register Bit 15
662
663; MUBRRL - Manchester Receiver Baud Rate Register Low Byte
664.equ	MUBRR0	= 0	; Manchester Receiver Baud Rate Register Bit 0
665.equ	MUBRR1	= 1	; Manchester Receiver Baud Rate Register Bit 1
666.equ	MUBRR2	= 2	; Manchester Receiver Baud Rate Register Bit 2
667.equ	MUBRR3	= 3	; Manchester Receiver Baud Rate Register Bit 3
668.equ	MUBRR4	= 4	; Manchester Receiver Baud Rate Register Bit 4
669.equ	MUBRR5	= 5	; Manchester Receiver Baud Rate Register Bit 5
670.equ	MUBRR6	= 6	; Manchester Receiver Baud Rate Register Bit 6
671.equ	MUBRR7	= 7	; Manchester Receiver Baud Rate Register Bit 7
672
673
674; ***** ANALOG_COMPARATOR ************
675; AC0CON - Analog Comparator 0 Control Register
676.equ	AC0M0	= 0	; Analog Comparator 0 Multiplexer Register
677.equ	AC0M1	= 1	; Analog Comparator 0 Multiplexer Regsiter
678.equ	AC0M2	= 2	; Analog Comparator 0 Multiplexer Register
679.equ	AC0IS0	= 4	; Analog Comparator 0 Interrupt Select Bit
680.equ	AC0IS1	= 5	; Analog Comparator 0  Interrupt Select Bit
681.equ	AC0IE	= 6	; Analog Comparator 0 Interrupt Enable Bit
682.equ	AC0EN	= 7	; Analog Comparator 0 Enable Bit
683
684; AC1CON - Analog Comparator 1 Control Register
685.equ	AC1M0	= 0	; Analog Comparator 1 Multiplexer Register
686.equ	AC1M1	= 1	; Analog Comparator 1 Multiplexer Regsiter
687.equ	AC1M2	= 2	; Analog Comparator 1 Multiplexer Register
688.equ	AC1ICE	= 3	; Analog Comparator 1 Interrupt Capture Enable Bit
689.equ	AC1IS0	= 4	; Analog Comparator 1 Interrupt Select Bit
690.equ	AC1IS1	= 5	; Analog Comparator 1  Interrupt Select Bit
691.equ	AC1IE	= 6	; Analog Comparator 1 Interrupt Enable Bit
692.equ	AC1EN	= 7	; Analog Comparator 1 Enable Bit
693
694; AC2CON - Analog Comparator 2 Control Register
695.equ	AC2M0	= 0	; Analog Comparator 2 Multiplexer Register
696.equ	AC2M1	= 1	; Analog Comparator 2 Multiplexer Regsiter
697.equ	AC2M2	= 2	; Analog Comparator 2 Multiplexer Register
698.equ	AC2SADE	= 3	; Analog Comparator 2 Start A/D Conversion Enable Bit
699.equ	AC2IS0	= 4	; Analog Comparator 2 Interrupt Select Bit
700.equ	AC2IS1	= 5	; Analog Comparator 2  Interrupt Select Bit
701.equ	AC2IE	= 6	; Analog Comparator 2 Interrupt Enable Bit
702.equ	AC2EN	= 7	; Analog Comparator 2 Enable Bit
703
704
705; ***** DA_CONVERTER *****************
706; DACH - DAC Data Register High Byte
707.equ	DACH0	= 0	; DAC Data Register High Byte Bit 0
708.equ	DACH1	= 1	; DAC Data Register High Byte Bit 1
709.equ	DACH2	= 2	; DAC Data Register High Byte Bit 2
710.equ	DACH3	= 3	; DAC Data Register High Byte Bit 3
711.equ	DACH4	= 4	; DAC Data Register High Byte Bit 4
712.equ	DACH5	= 5	; DAC Data Register High Byte Bit 5
713.equ	DACH6	= 6	; DAC Data Register High Byte Bit 6
714.equ	DACH7	= 7	; DAC Data Register High Byte Bit 7
715
716; DACL - DAC Data Register Low Byte
717.equ	DACL1	= 1	; DAC Data Register Low Byte Bit 1
718.equ	DACL2	= 2	; DAC Data Register Low Byte Bit 2
719.equ	DACL3	= 3	; DAC Data Register Low Byte Bit 3
720.equ	DACL4	= 4	; DAC Data Register Low Byte Bit 4
721.equ	DACL5	= 5	; DAC Data Register Low Byte Bit 5
722.equ	DACL6	= 6	; DAC Data Register Low Byte Bit 6
723.equ	DACL7	= 7	; DAC Data Register Low Byte Bit 7
724
725; DACON - DAC Control Register
726.equ	DAEN	= 0	; DAC Enable Bit
727.equ	DAOE	= 1	; DAC Output Enable Bit
728.equ	DALA	= 2	; DAC Left Adjust
729.equ	DATS0	= 4	; DAC Trigger Selection Bit 0
730.equ	DATS1	= 5	; DAC Trigger Selection Bit 1
731.equ	DATS2	= 6	; DAC Trigger Selection Bit 2
732.equ	DAATE	= 7	; DAC Auto Trigger Enable Bit
733
734
735; ***** CPU **************************
736; SREG - Status Register
737.equ	SREG_C	= 0	; Carry Flag
738.equ	SREG_Z	= 1	; Zero Flag
739.equ	SREG_N	= 2	; Negative Flag
740.equ	SREG_V	= 3	; Two's Complement Overflow Flag
741.equ	SREG_S	= 4
742.equ	SREG_H	= 5	; Half Carry Flag
743.equ	SREG_T	= 6	; Bit Copy Storage
744.equ	SREG_I	= 7	; Global Interrupt Enable
745
746; MCUCR - MCU Control Register
747.equ	IVCE	= 0	; Interrupt Vector Change Enable
748.equ	IVSEL	= 1	; Interrupt Vector Select
749.equ	PUD	= 4	; Pull-up disable
750.equ	SPIPS	= 7	; SPI Pin Select
751
752; MCUSR - MCU Status Register
753.equ	PORF	= 0	; Power-on reset flag
754.equ	EXTRF	= 1	; External Reset Flag
755.equ	BORF	= 2	; Brown-out Reset Flag
756.equ	WDRF	= 3	; Watchdog Reset Flag
757
758; OSCCAL - Oscillator Calibration Value
759.equ	CAL0	= 0	; Oscillator Calibration Value Bit0
760.equ	CAL1	= 1	; Oscillator Calibration Value Bit1
761.equ	CAL2	= 2	; Oscillator Calibration Value Bit2
762.equ	CAL3	= 3	; Oscillator Calibration Value Bit3
763.equ	CAL4	= 4	; Oscillator Calibration Value Bit4
764.equ	CAL5	= 5	; Oscillator Calibration Value Bit5
765.equ	CAL6	= 6	; Oscillator Calibration Value Bit6
766
767; CLKPR -
768.equ	CLKPS0	= 0	;
769.equ	CLKPS1	= 1	;
770.equ	CLKPS2	= 2	;
771.equ	CLKPS3	= 3	;
772.equ	CPKPCE	= 7	;
773
774; SMCR - Sleep Mode Control Register
775.equ	SE	= 0	; Sleep Enable
776.equ	SM0	= 1	; Sleep Mode Select bit 0
777.equ	SM1	= 2	; Sleep Mode Select bit 1
778.equ	SM2	= 3	; Sleep Mode Select bit 2
779
780; GPIOR3 - General Purpose IO Register 3
781.equ	GPIOR30	= 0	; General Purpose IO Register 3 bit 0
782.equ	GPIOR31	= 1	; General Purpose IO Register 3 bit 1
783.equ	GPIOR32	= 2	; General Purpose IO Register 3 bit 2
784.equ	GPIOR33	= 3	; General Purpose IO Register 3 bit 3
785.equ	GPIOR34	= 4	; General Purpose IO Register 3 bit 4
786.equ	GPIOR35	= 5	; General Purpose IO Register 3 bit 5
787.equ	GPIOR36	= 6	; General Purpose IO Register 3 bit 6
788.equ	GPIOR37	= 7	; General Purpose IO Register 3 bit 7
789
790; GPIOR2 - General Purpose IO Register 2
791.equ	GPIOR20	= 0	; General Purpose IO Register 2 bit 0
792.equ	GPIOR21	= 1	; General Purpose IO Register 2 bit 1
793.equ	GPIOR22	= 2	; General Purpose IO Register 2 bit 2
794.equ	GPIOR23	= 3	; General Purpose IO Register 2 bit 3
795.equ	GPIOR24	= 4	; General Purpose IO Register 2 bit 4
796.equ	GPIOR25	= 5	; General Purpose IO Register 2 bit 5
797.equ	GPIOR26	= 6	; General Purpose IO Register 2 bit 6
798.equ	GPIOR27	= 7	; General Purpose IO Register 2 bit 7
799
800; GPIOR1 - General Purpose IO Register 1
801.equ	GPIOR10	= 0	; General Purpose IO Register 1 bit 0
802.equ	GPIOR11	= 1	; General Purpose IO Register 1 bit 1
803.equ	GPIOR12	= 2	; General Purpose IO Register 1 bit 2
804.equ	GPIOR13	= 3	; General Purpose IO Register 1 bit 3
805.equ	GPIOR14	= 4	; General Purpose IO Register 1 bit 4
806.equ	GPIOR15	= 5	; General Purpose IO Register 1 bit 5
807.equ	GPIOR16	= 6	; General Purpose IO Register 1 bit 6
808.equ	GPIOR17	= 7	; General Purpose IO Register 1 bit 7
809
810; GPIOR0 - General Purpose IO Register 0
811.equ	GPIOR00	= 0	; General Purpose IO Register 0 bit 0
812.equ	GPIOR01	= 1	; General Purpose IO Register 0 bit 1
813.equ	GPIOR02	= 2	; General Purpose IO Register 0 bit 2
814.equ	GPIOR03	= 3	; General Purpose IO Register 0 bit 3
815.equ	GPIOR04	= 4	; General Purpose IO Register 0 bit 4
816.equ	GPIOR05	= 5	; General Purpose IO Register 0 bit 5
817.equ	GPIOR06	= 6	; General Purpose IO Register 0 bit 6
818.equ	GPIOR07	= 7	; General Purpose IO Register 0 bit 7
819
820; PLLCSR - PLL Control And Status Register
821.equ	PLOCK	= 0	; PLL Lock Detector
822.equ	PLLE	= 1	; PLL Enable
823.equ	PCKE	= 2	; PCK Enable
824
825
826; ***** PORTE ************************
827; PORTE - Port E Data Register
828.equ	PORTE0	= 0	;
829.equ	PE0	= 0	; For compatibility
830.equ	PORTE1	= 1	;
831.equ	PE1	= 1	; For compatibility
832.equ	PORTE2	= 2	;
833.equ	PE2	= 2	; For compatibility
834
835; DDRE - Port E Data Direction Register
836.equ	DDE0	= 0	;
837.equ	DDE1	= 1	;
838.equ	DDE2	= 2	;
839
840; PINE - Port E Input Pins
841.equ	PINE0	= 0	;
842.equ	PINE1	= 1	;
843.equ	PINE2	= 2	;
844
845
846; ***** TIMER_COUNTER_0 **************
847; TIMSK0 - Timer/Counter0 Interrupt Mask Register
848.equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
849.equ	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
850.equ	OCIE0B	= 2	; Timer/Counter0 Output Compare Match B Interrupt Enable
851
852; TIFR0 - Timer/Counter0 Interrupt Flag register
853.equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
854.equ	OCF0A	= 1	; Timer/Counter0 Output Compare Flag 0A
855.equ	OCF0B	= 2	; Timer/Counter0 Output Compare Flag 0B
856
857; TCCR0A - Timer/Counter  Control Register A
858.equ	WGM00	= 0	; Waveform Generation Mode
859.equ	WGM01	= 1	; Waveform Generation Mode
860.equ	COM0B0	= 4	; Compare Output Mode, Fast PWm
861.equ	COM0B1	= 5	; Compare Output Mode, Fast PWm
862.equ	COM0A0	= 6	; Compare Output Mode, Phase Correct PWM Mode
863.equ	COM0A1	= 7	; Compare Output Mode, Phase Correct PWM Mode
864
865; TCCR0B - Timer/Counter Control Register B
866.equ	CS00	= 0	; Clock Select
867.equ	CS01	= 1	; Clock Select
868.equ	CS02	= 2	; Clock Select
869.equ	WGM02	= 3	;
870.equ	FOC0B	= 6	; Force Output Compare B
871.equ	FOC0A	= 7	; Force Output Compare A
872
873; TCNT0 - Timer/Counter0
874.equ	TCNT0_0	= 0	;
875.equ	TCNT0_1	= 1	;
876.equ	TCNT0_2	= 2	;
877.equ	TCNT0_3	= 3	;
878.equ	TCNT0_4	= 4	;
879.equ	TCNT0_5	= 5	;
880.equ	TCNT0_6	= 6	;
881.equ	TCNT0_7	= 7	;
882
883; OCR0A - Timer/Counter0 Output Compare Register
884.equ	OCR0_0	= 0	;
885.equ	OCR0_1	= 1	;
886.equ	OCR0_2	= 2	;
887.equ	OCR0_3	= 3	;
888.equ	OCR0_4	= 4	;
889.equ	OCR0_5	= 5	;
890.equ	OCR0_6	= 6	;
891.equ	OCR0_7	= 7	;
892
893; OCR0B - Timer/Counter0 Output Compare Register
894;.equ	OCR0_0	= 0	;
895;.equ	OCR0_1	= 1	;
896;.equ	OCR0_2	= 2	;
897;.equ	OCR0_3	= 3	;
898;.equ	OCR0_4	= 4	;
899;.equ	OCR0_5	= 5	;
900;.equ	OCR0_6	= 6	;
901;.equ	OCR0_7	= 7	;
902
903; GTCCR - General Timer/Counter Control Register
904.equ	PSR10	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
905.equ	ICPSEL1	= 6	; Timer1 Input Capture Selection Bit
906.equ	TSM	= 7	; Timer/Counter Synchronization Mode
907
908
909; ***** TIMER_COUNTER_1 **************
910; TIMSK1 - Timer/Counter Interrupt Mask Register
911.equ	TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable
912.equ	OCIE1A	= 1	; Timer/Counter1 Output CompareA Match Interrupt Enable
913.equ	OCIE1B	= 2	; Timer/Counter1 Output CompareB Match Interrupt Enable
914.equ	ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable
915
916; TIFR1 - Timer/Counter Interrupt Flag register
917.equ	TOV1	= 0	; Timer/Counter1 Overflow Flag
918.equ	OCF1A	= 1	; Output Compare Flag 1A
919.equ	OCF1B	= 2	; Output Compare Flag 1B
920.equ	ICF1	= 5	; Input Capture Flag 1
921
922; TCCR1A - Timer/Counter1 Control Register A
923.equ	WGM10	= 0	; Waveform Generation Mode
924.equ	WGM11	= 1	; Waveform Generation Mode
925.equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0
926.equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
927.equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
928.equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
929
930; TCCR1B - Timer/Counter1 Control Register B
931.equ	CS10	= 0	; Prescaler source of Timer/Counter 1
932.equ	CS11	= 1	; Prescaler source of Timer/Counter 1
933.equ	CS12	= 2	; Prescaler source of Timer/Counter 1
934.equ	WGM12	= 3	; Waveform Generation Mode
935.equ	WGM13	= 4	; Waveform Generation Mode
936.equ	ICES1	= 6	; Input Capture 1 Edge Select
937.equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
938
939; TCCR1C - Timer/Counter1 Control Register C
940.equ	FOC1B	= 6	;
941.equ	FOC1A	= 7	;
942
943; GTCCR - General Timer/Counter Control Register
944.equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
945;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
946
947
948; ***** AD_CONVERTER *****************
949; ADMUX - The ADC multiplexer Selection Register
950.equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
951.equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
952.equ	MUX2	= 2	; Analog Channel and Gain Selection Bits
953.equ	MUX3	= 3	; Analog Channel and Gain Selection Bits
954.equ	ADLAR	= 5	; Left Adjust Result
955.equ	REFS0	= 6	; Reference Selection Bit 0
956.equ	REFS1	= 7	; Reference Selection Bit 1
957
958; ADCSRA - The ADC Control and Status register
959.equ	ADPS0	= 0	; ADC  Prescaler Select Bits
960.equ	ADPS1	= 1	; ADC  Prescaler Select Bits
961.equ	ADPS2	= 2	; ADC  Prescaler Select Bits
962.equ	ADIE	= 3	; ADC Interrupt Enable
963.equ	ADIF	= 4	; ADC Interrupt Flag
964.equ	ADATE	= 5	; ADC Auto Trigger Enable
965.equ	ADSC	= 6	; ADC Start Conversion
966.equ	ADEN	= 7	; ADC Enable
967
968; ADCH - ADC Data Register High Byte
969.equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
970.equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
971.equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
972.equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
973.equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
974.equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
975.equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
976.equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7
977
978; ADCL - ADC Data Register Low Byte
979.equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
980.equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
981.equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
982.equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
983.equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
984.equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
985.equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
986.equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7
987
988; ADCSRB - ADC Control and Status Register B
989.equ	ADTS0	= 0	; ADC Auto Trigger Source 0
990.equ	ADTS1	= 1	; ADC Auto Trigger Source 1
991.equ	ADTS2	= 2	; ADC Auto Trigger Source 2
992.equ	ADASCR	= 3	;
993.equ	ADAP	= 4	;
994
995; DIDR0 - Digital Input Disable Register 0
996.equ	ADC0D	= 0	; ADC0 Digital input Disable
997.equ	ADC1D	= 1	; ADC1 Digital input Disable
998.equ	ADC2D	= 2	; ADC2 Digital input Disable
999.equ	ADC3D	= 3	; ADC3 Digital input Disable
1000.equ	ADC4D	= 4	; ADC4 Digital input Disable
1001.equ	ADC5D	= 5	; ADC5 Digital input Disable
1002.equ	ADC6D	= 6	; ADC6 Digital input Disable
1003.equ	ADC7D	= 7	; ADC7 Digital input Disable
1004
1005; DIDR1 -
1006.equ	ADC8D	= 0	;
1007.equ	ADC9D	= 1	;
1008.equ	ADC10D	= 2	;
1009.equ	AMP0ND	= 3	;
1010.equ	AMP0PD	= 4	;
1011.equ	ACMP0D	= 5	;
1012
1013
1014; ***** USART ************************
1015; UDR - USART I/O Data Register
1016.equ	UDR0	= 0	; USART I/O Data Register bit 0
1017.equ	UDR1	= 1	; USART I/O Data Register bit 1
1018.equ	UDR2	= 2	; USART I/O Data Register bit 2
1019.equ	UDR3	= 3	; USART I/O Data Register bit 3
1020.equ	UDR4	= 4	; USART I/O Data Register bit 4
1021.equ	UDR5	= 5	; USART I/O Data Register bit 5
1022.equ	UDR6	= 6	; USART I/O Data Register bit 6
1023.equ	UDR7	= 7	; USART I/O Data Register bit 7
1024
1025; UCSRA - USART Control and Status register A
1026.equ	MPCM	= 0	; Multi-processor Communication Mode
1027.equ	U2X	= 1	; Double USART Transmission Bit
1028.equ	UPE	= 2	; USART Parity Error
1029.equ	DOR	= 3	; Data Overrun
1030.equ	FE	= 4	; Framing Error
1031.equ	UDRE	= 5	; USART Data Register Empty
1032.equ	TXC	= 6	; USART Transmitt Complete
1033.equ	RXC	= 7	; USART Receive Complete
1034
1035; UCSRB - USART Control an Status register B
1036.equ	TXB8	= 0	; Transmit Data Bit 8
1037.equ	RXB8	= 1	; Receive Data Bit 8
1038.equ	UCSZ2	= 2	; Character Size
1039.equ	TXEN	= 3	; Transmitter Enable
1040.equ	RXEN	= 4	; Receiver Enable
1041.equ	UDRIE	= 5	; USART Data Register Empty Interrupt Enable
1042.equ	TXCIE	= 6	; TX Complete Interrupt Enable
1043.equ	RXCIE	= 7	; RX Complete Interrupt Enable
1044
1045; UCSRC - USART Control an Status register C
1046.equ	UCPOL	= 0	; Clock Polarity
1047.equ	UCSZ0	= 1	; Character Size Bit 0
1048.equ	UCSZ1	= 2	; Character Size Bit 1
1049.equ	USBS	= 3	; Stop Bit Select
1050.equ	UPM0	= 4	; Parity Mode Bit 0
1051.equ	UPM1	= 5	; Parity Mode Bit 1
1052.equ	UMSEL0	= 6	; USART Mode Select
1053
1054; UBRRH - USART Baud Rate Register High Byte
1055.equ	UBRR8	= 0	; USART Baud Rate Register Bit 8
1056.equ	UBRR9	= 1	; USART Baud Rate Register Bit 9
1057.equ	UBRR10	= 2	; USART Baud Rate Register Bit 10
1058.equ	UBRR11	= 3	; USART Baud Rate Register Bit 11
1059
1060; UBRRL - USART Baud Rate Register Low Byte
1061.equ	UBRR0	= 0	; USART Baud Rate Register bit 0
1062.equ	UBRR1	= 1	; USART Baud Rate Register bit 1
1063.equ	UBRR2	= 2	; USART Baud Rate Register bit 2
1064.equ	UBRR3	= 3	; USART Baud Rate Register bit 3
1065.equ	UBRR4	= 4	; USART Baud Rate Register bit 4
1066.equ	UBRR5	= 5	; USART Baud Rate Register bit 5
1067.equ	UBRR6	= 6	; USART Baud Rate Register bit 6
1068.equ	UBRR7	= 7	; USART Baud Rate Register bit 7
1069
1070
1071; ***** SPI **************************
1072; SPDR - SPI Data Register
1073.equ	SPDR0	= 0	; SPI Data Register bit 0
1074.equ	SPDR1	= 1	; SPI Data Register bit 1
1075.equ	SPDR2	= 2	; SPI Data Register bit 2
1076.equ	SPDR3	= 3	; SPI Data Register bit 3
1077.equ	SPDR4	= 4	; SPI Data Register bit 4
1078.equ	SPDR5	= 5	; SPI Data Register bit 5
1079.equ	SPDR6	= 6	; SPI Data Register bit 6
1080.equ	SPDR7	= 7	; SPI Data Register bit 7
1081
1082; SPSR - SPI Status Register
1083.equ	SPI2X	= 0	; Double SPI Speed Bit
1084.equ	WCOL	= 6	; Write Collision Flag
1085.equ	SPIF	= 7	; SPI Interrupt Flag
1086
1087; SPCR - SPI Control Register
1088.equ	SPR0	= 0	; SPI Clock Rate Select 0
1089.equ	SPR1	= 1	; SPI Clock Rate Select 1
1090.equ	CPHA	= 2	; Clock Phase
1091.equ	CPOL	= 3	; Clock polarity
1092.equ	MSTR	= 4	; Master/Slave Select
1093.equ	DORD	= 5	; Data Order
1094.equ	SPE	= 6	; SPI Enable
1095.equ	SPIE	= 7	; SPI Interrupt Enable
1096
1097
1098; ***** WATCHDOG *********************
1099; WDTCSR - Watchdog Timer Control Register
1100.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
1101.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
1102.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
1103.equ	WDE	= 3	; Watch Dog Enable
1104.equ	WDCE	= 4	; Watchdog Change Enable
1105.equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
1106.equ	WDIE	= 6	; Watchdog Timeout Interrupt Enable
1107.equ	WDIF	= 7	; Watchdog Timeout Interrupt Flag
1108
1109
1110; ***** EXTERNAL_INTERRUPT ***********
1111; EICRA - External Interrupt Control Register A
1112.equ	ISC00	= 0	; External Interrupt Sense Control Bit
1113.equ	ISC01	= 1	; External Interrupt Sense Control Bit
1114.equ	ISC10	= 2	; External Interrupt Sense Control Bit
1115.equ	ISC11	= 3	; External Interrupt Sense Control Bit
1116.equ	ISC20	= 4	; External Interrupt Sense Control Bit
1117.equ	ISC21	= 5	; External Interrupt Sense Control Bit
1118
1119; EIMSK - External Interrupt Mask Register
1120.equ	INT0	= 0	; External Interrupt Request 0 Enable
1121.equ	INT1	= 1	; External Interrupt Request 1 Enable
1122.equ	INT2	= 2	; External Interrupt Request 2 Enable
1123
1124; EIFR - External Interrupt Flag Register
1125.equ	INTF0	= 0	; External Interrupt Flag 0
1126.equ	INTF1	= 1	; External Interrupt Flag 1
1127.equ	INTF2	= 2	; External Interrupt Flag 2
1128
1129
1130
1131; ***** LOCKSBITS ********************************************************
1132.equ	LB1	= 0	; Lock bit
1133.equ	LB2	= 1	; Lock bit
1134.equ	BLB01	= 2	; Boot Lock bit
1135.equ	BLB02	= 3	; Boot Lock bit
1136.equ	BLB11	= 4	; Boot lock bit
1137.equ	BLB12	= 5	; Boot lock bit
1138
1139
1140; ***** FUSES ************************************************************
1141; LOW fuse bits
1142.equ	CKSEL0	= 0	; Select Clock Source
1143.equ	CKSEL1	= 1	; Select Clock Source
1144.equ	CKSEL2	= 2	; Select Clock Source
1145.equ	CKSEL3	= 3	; Select Clock Source
1146.equ	SUT0	= 4	; Select start-up time
1147.equ	SUT1	= 5	; Select start-up time
1148.equ	CKOUT	= 6	; Oscillator output option
1149.equ	CLKDIV8	= 7	; Divide clock by 8
1150
1151; HIGH fuse bits
1152.equ	BOOTRST	= 0	; Select Reset Vector
1153.equ	BOOTSZ0	= 1	; Select Boot Size
1154.equ	BOOTSZ1	= 2	; Select Boot Size
1155.equ	EESAVE	= 3	; EEPROM memory is preserved through chip erase
1156.equ	WDTON	= 4	; Watchdog timer always on
1157.equ	SPIEN	= 5	; Enable Serial programming and Data Downloading
1158.equ	JTAGEN	= 6	; Enable JTAG
1159.equ	OCDEN	= 7	; Enable OCD
1160
1161; EXTENDED fuse bits
1162.equ	TA0SEL	= 0	; (Reserved to factory tests)
1163.equ	BODLEVEL0	= 1	; Brown-out Detector trigger level
1164.equ	BODLEVEL1	= 2	; Brown-out Detector trigger level
1165.equ	BODLEVEL2	= 3	; Brown out detector trigger level
1166
1167
1168
1169; ***** CPU REGISTER DEFINITIONS *****************************************
1170.def	XH	= r27
1171.def	XL	= r26
1172.def	YH	= r29
1173.def	YL	= r28
1174.def	ZH	= r31
1175.def	ZL	= r30
1176
1177
1178
1179; ***** DATA MEMORY DECLARATIONS *****************************************
1180.equ	FLASHEND	= 0x0fff	; Note: Word address
1181.equ	IOEND	= 0x00ff
1182.equ	SRAM_START	= 0x0100
1183.equ	SRAM_SIZE	= 512
1184.equ	RAMEND	= 0x02ff
1185.equ	XRAMEND	= 0x0000
1186.equ	E2END	= 0x01ff
1187.equ	EEPROMEND	= 0x01ff
1188.equ	EEADRBITS	= 9
1189#pragma AVRPART MEMORY PROG_FLASH 8192
1190#pragma AVRPART MEMORY EEPROM 512
1191#pragma AVRPART MEMORY INT_SRAM SIZE 512
1192#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
1193
1194
1195
1196; ***** BOOTLOADER DECLARATIONS ******************************************
1197.equ	NRWW_START_ADDR	= 0xc00
1198.equ	NRWW_STOP_ADDR	= 0xfff
1199.equ	RWW_START_ADDR	= 0x0
1200.equ	RWW_STOP_ADDR	= 0xbff
1201.equ	PAGESIZE	= 32
1202.equ	FIRSTBOOTSTART	= 0xf80
1203.equ	SECONDBOOTSTART	= 0xf00
1204.equ	THIRDBOOTSTART	= 0xe00
1205.equ	FOURTHBOOTSTART	= 0xc00
1206.equ	SMALLBOOTSTART	= FIRSTBOOTSTART
1207.equ	LARGEBOOTSTART	= FOURTHBOOTSTART
1208
1209
1210
1211; ***** INTERRUPT VECTORS ************************************************
1212.equ	PSC2_CAPTaddr	= 0x0001	; PSC2 Capture Event
1213.equ	PSC2_ECaddr	= 0x0002	; PSC2 End Cycle
1214.equ	PSC1_CAPTaddr	= 0x0003	; PSC1 Capture Event
1215.equ	PSC1_ECaddr	= 0x0004	; PSC1 End Cycle
1216.equ	PSC0_CAPTaddr	= 0x0005	; PSC0 Capture Event
1217.equ	PSC0_ECaddr	= 0x0006	; PSC0 End Cycle
1218.equ	ACI0addr	= 0x0007	; Analog Comparator 0
1219.equ	ACI1addr	= 0x0008	; Analog Comparator 1
1220.equ	ACI2addr	= 0x0009	; Analog Comparator 2
1221.equ	INT0addr	= 0x000a	; External Interrupt Request 0
1222.equ	ICP1addr	= 0x000b	; Timer/Counter1 Capture Event
1223.equ	OC1Aaddr	= 0x000c	; Timer/Counter1 Compare Match A
1224.equ	OC1Baddr	= 0x000d	; Timer/Counter Compare Match B
1225.equ	OVF1addr	= 0x000f	; Timer/Counter1 Overflow
1226.equ	OC0Aaddr	= 0x0010	; Timer/Counter0 Compare Match A
1227.equ	OVF0addr	= 0x0011	; Timer/Counter0 Overflow
1228.equ	ADCCaddr	= 0x0012	; ADC Conversion Complete
1229.equ	INT1addr	= 0x0013	; External Interrupt Request 1
1230.equ	SPIaddr	= 0x0014	; SPI Serial Transfer Complete
1231.equ	URXCaddr	= 0x0015	; USART, Rx Complete
1232.equ	UDREaddr	= 0x0016	; USART Data Register Empty
1233.equ	UTXCaddr	= 0x0017	; USART, Tx Complete
1234.equ	INT2addr	= 0x0018	; External Interrupt Request 2
1235.equ	WDTaddr	= 0x0019	; Watchdog Timeout Interrupt
1236.equ	ERDYaddr	= 0x001a	; EEPROM Ready
1237.equ	OC0Baddr	= 0x001b	; Timer Counter 0 Compare Match B
1238.equ	INT3addr	= 0x001c	; External Interrupt Request 3
1239.equ	SPMRaddr	= 0x001f	; Store Program Memory Read
1240
1241.equ	INT_VECTORS_SIZE	= 29	; size in words
1242
1243#endif  /* _PWM2DEF_INC_ */
1244
1245; ***** END OF FILE ******************************************************
1246