1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
2;***** Created: 2011-02-09 12:03 ******* Source: ATtiny13A.xml ***********
3;*************************************************************************
4;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
5;*
6;* Number            : AVR000
7;* File Name         : "tn13Adef.inc"
8;* Title             : Register/Bit Definitions for the ATtiny13A
9;* Date              : 2011-02-09
10;* Version           : 2.35
11;* Support E-mail    : avr@atmel.com
12;* Target MCU        : ATtiny13A
13;*
14;* DESCRIPTION
15;* When including this file in the assembly program file, all I/O register
16;* names and I/O register bit names appearing in the data book can be used.
17;* In addition, the six registers forming the three data pointers X, Y and
18;* Z have been assigned names XL - ZH. Highest RAM address for Internal
19;* SRAM is also defined
20;*
21;* The Register names are represented by their hexadecimal address.
22;*
23;* The Register Bit names are represented by their bit number (0-7).
24;*
25;* Please observe the difference in using the bit names with instructions
26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
27;* (skip if bit in register set/cleared). The following example illustrates
28;* this:
29;*
30;* in    r16,PORTB             ;read PORTB latch
31;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
32;* out   PORTB,r16             ;output to PORTB
33;*
34;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
35;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
36;* rjmp  TOV0_is_set           ;jump if set
37;* ...                         ;otherwise do something else
38;*************************************************************************
39
40#ifndef _TN13ADEF_INC_
41#define _TN13ADEF_INC_
42
43
44#pragma partinc 0
45
46; ***** SPECIFY DEVICE ***************************************************
47.device ATtiny13A
48#pragma AVRPART ADMIN PART_NAME ATtiny13A
49.equ	SIGNATURE_000	= 0x1e
50.equ	SIGNATURE_001	= 0x90
51.equ	SIGNATURE_002	= 0x07
52
53#pragma AVRPART CORE CORE_VERSION V2
54#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
55
56
57; ***** I/O REGISTER DEFINITIONS *****************************************
58; NOTE:
59; Definitions marked "MEMORY MAPPED"are extended I/O ports
60; and cannot be used with IN/OUT instructions
61.equ	SREG	= 0x3f
62.equ	SPL	= 0x3d
63.equ	GIMSK	= 0x3b
64.equ	GIFR	= 0x3a
65.equ	TIMSK0	= 0x39
66.equ	TIFR0	= 0x38
67.equ	SPMCSR	= 0x37
68.equ	OCR0A	= 0x36
69.equ	MCUCR	= 0x35
70.equ	MCUSR	= 0x34
71.equ	TCCR0B	= 0x33
72.equ	TCNT0	= 0x32
73.equ	OSCCAL	= 0x31
74.equ	BODCR	= 0x30
75.equ	TCCR0A	= 0x2f
76.equ	DWDR	= 0x2e
77.equ	OCR0B	= 0x29
78.equ	GTCCR	= 0x28
79.equ	CLKPR	= 0x26
80.equ	PRR	= 0x25
81.equ	WDTCR	= 0x21
82.equ	EEAR	= 0x1e
83.equ	EEDR	= 0x1d
84.equ	EECR	= 0x1c
85.equ	PORTB	= 0x18
86.equ	DDRB	= 0x17
87.equ	PINB	= 0x16
88.equ	PCMSK	= 0x15
89.equ	DIDR0	= 0x14
90.equ	ACSR	= 0x08
91.equ	ADMUX	= 0x07
92.equ	ADCSRA	= 0x06
93.equ	ADCH	= 0x05
94.equ	ADCL	= 0x04
95.equ	ADCSRB	= 0x03
96
97
98; ***** BIT DEFINITIONS **************************************************
99
100; ***** AD_CONVERTER *****************
101; ADMUX - The ADC multiplexer Selection Register
102.equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
103.equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
104.equ	ADLAR	= 5	; Left Adjust Result
105.equ	REFS0	= 6	; Reference Selection Bit 0
106
107; ADCSRA - The ADC Control and Status register
108.equ	ADPS0	= 0	; ADC  Prescaler Select Bits
109.equ	ADPS1	= 1	; ADC  Prescaler Select Bits
110.equ	ADPS2	= 2	; ADC  Prescaler Select Bits
111.equ	ADIE	= 3	; ADC Interrupt Enable
112.equ	ADIF	= 4	; ADC Interrupt Flag
113.equ	ADATE	= 5	; ADC Auto Trigger Enable
114.equ	ADSC	= 6	; ADC Start Conversion
115.equ	ADEN	= 7	; ADC Enable
116
117; ADCH - ADC Data Register High Byte
118.equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
119.equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
120.equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
121.equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
122.equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
123.equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
124.equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
125.equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7
126
127; ADCL - ADC Data Register Low Byte
128.equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
129.equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
130.equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
131.equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
132.equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
133.equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
134.equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
135.equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7
136
137; ADCSRB - ADC Control and Status Register B
138.equ	ADTS0	= 0	; ADC Auto Trigger Source 0
139.equ	ADTS1	= 1	; ADC Auto Trigger Source 1
140.equ	ADTS2	= 2	; ADC Auto Trigger Source 2
141
142; DIDR0 - Digital Input Disable Register 0
143.equ	ADC1D	= 2	; ADC2 Digital input Disable
144.equ	ADC3D	= 3	; ADC3 Digital input Disable
145.equ	ADC2D	= 4	; ADC2 Digital input Disable
146.equ	ADC0D	= 5	; ADC0 Digital input Disable
147
148
149; ***** ANALOG_COMPARATOR ************
150; ADCSRB - ADC Control and Status Register B
151.equ	ACME	= 6	; Analog Comparator Multiplexer Enable
152
153; ACSR - Analog Comparator Control And Status Register
154.equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
155.equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
156.equ	ACIE	= 3	; Analog Comparator Interrupt Enable
157.equ	ACI	= 4	; Analog Comparator Interrupt Flag
158.equ	ACO	= 5	; Analog Compare Output
159.equ	ACBG	= 6	; Analog Comparator Bandgap Select
160.equ	AINBG	= ACBG	; For compatibility
161.equ	ACD	= 7	; Analog Comparator Disable
162
163; DIDR0 -
164.equ	AIN0D	= 0	; AIN0 Digital Input Disable
165.equ	AIN1D	= 1	; AIN1 Digital Input Disable
166
167
168; ***** EEPROM ***********************
169; EEAR - EEPROM Read/Write Access
170.equ	EEARL	= EEAR	; For compatibility
171.equ	EEAR0	= 0	; EEPROM Read/Write Access bit 0
172.equ	EEAR1	= 1	; EEPROM Read/Write Access bit 1
173.equ	EEAR2	= 2	; EEPROM Read/Write Access bit 2
174.equ	EEAR3	= 3	; EEPROM Read/Write Access bit 3
175.equ	EEAR4	= 4	; EEPROM Read/Write Access bit 4
176.equ	EEAR5	= 5	; EEPROM Read/Write Access bit 5
177
178; EEDR - EEPROM Data Register
179.equ	EEDR0	= 0	; EEPROM Data Register bit 0
180.equ	EEDR1	= 1	; EEPROM Data Register bit 1
181.equ	EEDR2	= 2	; EEPROM Data Register bit 2
182.equ	EEDR3	= 3	; EEPROM Data Register bit 3
183.equ	EEDR4	= 4	; EEPROM Data Register bit 4
184.equ	EEDR5	= 5	; EEPROM Data Register bit 5
185.equ	EEDR6	= 6	; EEPROM Data Register bit 6
186.equ	EEDR7	= 7	; EEPROM Data Register bit 7
187
188; EECR - EEPROM Control Register
189.equ	EERE	= 0	; EEPROM Read Enable
190.equ	EEWE	= 1	; EEPROM Write Enable
191.equ	EEPE	= EEWE	; For compatibility
192.equ	EEMWE	= 2	; EEPROM Master Write Enable
193.equ	EEMPE	= EEMWE	; For compatibility
194.equ	EERIE	= 3	; EEProm Ready Interrupt Enable
195.equ	EEPM0	= 4	;
196.equ	EEPM1	= 5	;
197
198
199; ***** PORTB ************************
200; PORTB - Data Register, Port B
201.equ	PORTB0	= 0	;
202.equ	PB0	= 0	; For compatibility
203.equ	PORTB1	= 1	;
204.equ	PB1	= 1	; For compatibility
205.equ	PORTB2	= 2	;
206.equ	PB2	= 2	; For compatibility
207.equ	PORTB3	= 3	;
208.equ	PB3	= 3	; For compatibility
209.equ	PORTB4	= 4	;
210.equ	PB4	= 4	; For compatibility
211.equ	PORTB5	= 5	;
212.equ	PB5	= 5	; For compatibility
213
214; DDRB - Data Direction Register, Port B
215.equ	DDB0	= 0	;
216.equ	DDB1	= 1	;
217.equ	DDB2	= 2	;
218.equ	DDB3	= 3	;
219.equ	DDB4	= 4	;
220.equ	DDB5	= 5	;
221
222; PINB - Input Pins, Port B
223.equ	PINB0	= 0	;
224.equ	PINB1	= 1	;
225.equ	PINB2	= 2	;
226.equ	PINB3	= 3	;
227.equ	PINB4	= 4	;
228.equ	PINB5	= 5	;
229
230
231; ***** EXTERNAL_INTERRUPT ***********
232; MCUCR - MCU Control Register
233.equ	ISC00	= 0	; Interrupt Sense Control 0 Bit 0
234.equ	ISC01	= 1	; Interrupt Sense Control 0 Bit 1
235
236; GIMSK - General Interrupt Mask Register
237.equ	GICR	= GIMSK	; For compatibility
238.equ	PCIE	= 5	; Pin Change Interrupt Enable
239.equ	INT0	= 6	; External Interrupt Request 0 Enable
240
241; GIFR - General Interrupt Flag register
242.equ	PCIF	= 5	; Pin Change Interrupt Flag
243.equ	INTF0	= 6	; External Interrupt Flag 0
244
245; PCMSK - Pin Change Enable Mask
246.equ	PCINT0	= 0	; Pin Change Enable Mask Bit 0
247.equ	PCINT1	= 1	; Pin Change Enable Mask Bit 1
248.equ	PCINT2	= 2	; Pin Change Enable Mask Bit 2
249.equ	PCINT3	= 3	; Pin Change Enable Mask Bit 3
250.equ	PCINT4	= 4	; Pin Change Enable Mask Bit 4
251.equ	PCINT5	= 5	; Pin Change Enable Mask Bit 5
252
253
254; ***** TIMER_COUNTER_0 **************
255; TIMSK0 - Timer/Counter0 Interrupt Mask Register
256.equ	TOIE0	= 1	; Timer/Counter0 Overflow Interrupt Enable
257.equ	OCIE0A	= 2	; Timer/Counter0 Output Compare Match A Interrupt Enable
258.equ	OCIE0B	= 3	; Timer/Counter0 Output Compare Match B Interrupt Enable
259
260; TIFR0 - Timer/Counter0 Interrupt Flag register
261.equ	TOV0	= 1	; Timer/Counter0 Overflow Flag
262.equ	OCF0A	= 2	; Timer/Counter0 Output Compare Flag 0A
263.equ	OCF0B	= 3	; Timer/Counter0 Output Compare Flag 0B
264
265; OCR0A - Timer/Counter0 Output Compare Register
266.equ	OCR0A_0	= 0	;
267.equ	OCR0A_1	= 1	;
268.equ	OCR0A_2	= 2	;
269.equ	OCR0A_3	= 3	;
270.equ	OCR0A_4	= 4	;
271.equ	OCR0A_5	= 5	;
272.equ	OCR0A_6	= 6	;
273.equ	OCR0A_7	= 7	;
274
275; TCCR0A - Timer/Counter  Control Register A
276.equ	WGM00	= 0	; Waveform Generation Mode
277.equ	WGM01	= 1	; Waveform Generation Mode
278.equ	COM0B0	= 4	; Compare Match Output B Mode
279.equ	COM0B1	= 5	; Compare Match Output B Mode
280.equ	COM0A0	= 6	; Compare Match Output A Mode
281.equ	COM0A1	= 7	; Compare Match Output A Mode
282
283; TCNT0 - Timer/Counter0
284.equ	TCNT0_0	= 0	;
285.equ	TCNT0_1	= 1	;
286.equ	TCNT0_2	= 2	;
287.equ	TCNT0_3	= 3	;
288.equ	TCNT0_4	= 4	;
289.equ	TCNT0_5	= 5	;
290.equ	TCNT0_6	= 6	;
291.equ	TCNT0_7	= 7	;
292
293; TCCR0B - Timer/Counter Control Register B
294.equ	CS00	= 0	; Clock Select
295.equ	CS01	= 1	; Clock Select
296.equ	CS02	= 2	; Clock Select
297.equ	WGM02	= 3	; Waveform Generation Mode
298.equ	FOC0B	= 6	; Force Output Compare B
299.equ	FOC0A	= 7	; Force Output Compare A
300
301; OCR0B - Timer/Counter0 Output Compare Register
302.equ	OCR0B_0	= 0	;
303.equ	OCR0B_1	= 1	;
304.equ	OCR0B_2	= 2	;
305.equ	OCR0B_3	= 3	;
306.equ	OCR0B_4	= 4	;
307.equ	OCR0B_5	= 5	;
308.equ	OCR0B_6	= 6	;
309.equ	OCR0B_7	= 7	;
310
311; GTCCR - General Timer Conuter Register
312.equ	PSR10	= 0	; Prescaler Reset Timer/Counter0
313.equ	TSM	= 7	; Timer/Counter Synchronization Mode
314
315
316; ***** WATCHDOG *********************
317; WDTCR - Watchdog Timer Control Register
318.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
319.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
320.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
321.equ	WDE	= 3	; Watch Dog Enable
322.equ	WDCE	= 4	; Watchdog Change Enable
323.equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
324.equ	WDTIE	= 6	; Watchdog Timeout Interrupt Enable
325.equ	WDTIF	= 7	; Watchdog Timeout Interrupt Flag
326
327
328; ***** CPU **************************
329; SREG - Status Register
330.equ	SREG_C	= 0	; Carry Flag
331.equ	SREG_Z	= 1	; Zero Flag
332.equ	SREG_N	= 2	; Negative Flag
333.equ	SREG_V	= 3	; Two's Complement Overflow Flag
334.equ	SREG_S	= 4	; Sign Bit
335.equ	SREG_H	= 5	; Half Carry Flag
336.equ	SREG_T	= 6	; Bit Copy Storage
337.equ	SREG_I	= 7	; Global Interrupt Enable
338
339; SPL - Stack Pointer Low Byte
340.equ	SP0	= 0	; Stack Pointer Bit 0
341.equ	SP1	= 1	; Stack Pointer Bit 1
342.equ	SP2	= 2	; Stack Pointer Bit 2
343.equ	SP3	= 3	; Stack Pointer Bit 3
344.equ	SP4	= 4	; Stack Pointer Bit 4
345.equ	SP5	= 5	; Stack Pointer Bit 5
346.equ	SP6	= 6	; Stack Pointer Bit 6
347.equ	SP7	= 7	; Stack Pointer Bit 7
348
349; MCUCR - MCU Control Register
350;.equ	ISC00	= 0	; Interrupt Sense Control 0 bit 0
351;.equ	ISC01	= 1	; Interrupt Sense Control 0 bit 1
352.equ	SM0	= 3	; Sleep Mode Select Bit 0
353.equ	SM1	= 4	; Sleep Mode Select Bit 1
354.equ	SE	= 5	; Sleep Enable
355.equ	PUD	= 6	; Pull-up Disable
356
357; MCUSR - MCU Status register
358.equ	PORF	= 0	; Power-On Reset Flag
359.equ	EXTRF	= 1	; External Reset Flag
360.equ	BORF	= 2	; Brown-out Reset Flag
361.equ	WDRF	= 3	; Watchdog Reset Flag
362
363; OSCCAL - Oscillator Calibration Register
364.equ	CAL0	= 0	; Oscillatro Calibration Value Bit 0
365.equ	CAL1	= 1	; Oscillatro Calibration Value Bit 1
366.equ	CAL2	= 2	; Oscillatro Calibration Value Bit 2
367.equ	CAL3	= 3	; Oscillatro Calibration Value Bit 3
368.equ	CAL4	= 4	; Oscillatro Calibration Value Bit 4
369.equ	CAL5	= 5	; Oscillatro Calibration Value Bit 5
370.equ	CAL6	= 6	; Oscillatro Calibration Value Bit 6
371
372; CLKPR - Clock Prescale Register
373.equ	CLKPS0	= 0	; Clock Prescaler Select Bit 0
374.equ	CLKPS1	= 1	; Clock Prescaler Select Bit 1
375.equ	CLKPS2	= 2	; Clock Prescaler Select Bit 2
376.equ	CLKPS3	= 3	; Clock Prescaler Select Bit 3
377.equ	CLKPCE	= 7	; Clock Prescaler Change Enable
378
379; DWDR - Debug Wire Data Register
380.equ	DWDR0	= 0	; Debug Wire Data Register Bit 0
381.equ	DWDR1	= 1	; Debug Wire Data Register Bit 1
382.equ	DWDR2	= 2	; Debug Wire Data Register Bit 2
383.equ	DWDR3	= 3	; Debug Wire Data Register Bit 3
384.equ	DWDR4	= 4	; Debug Wire Data Register Bit 4
385.equ	DWDR5	= 5	; Debug Wire Data Register Bit 5
386.equ	DWDR6	= 6	; Debug Wire Data Register Bit 6
387.equ	DWDR7	= 7	; Debug Wire Data Register Bit 7
388
389; SPMCSR - Store Program Memory Control and Status Register
390.equ	SPMEN	= 0	; Store program Memory Enable
391.equ	PGERS	= 1	; Page Erase
392.equ	PGWRT	= 2	; Page Write
393.equ	RFLB	= 3	; Read Fuse and Lock Bits
394.equ	CTPB	= 4	; Clear Temporary Page Buffer
395
396; PRR - Power Reduction Register
397.equ	PRADC	= 0	; Power Reduction ADC
398.equ	PRTIM0	= 1	; Power Reduction Timer/Counter0
399
400; BODCR - BOD Control Register
401.equ	BPDSE	= 0	; BOD Power-Down Sleep Enable
402.equ	BPDS	= 1	; BOD Power-Down in Power-Down Sleep
403
404
405
406; ***** LOCKSBITS ********************************************************
407.equ	LB1	= 0	; Lockbit
408.equ	LB2	= 1	; Lockbit
409
410
411; ***** FUSES ************************************************************
412; LOW fuse bits
413.equ	CKSEL0	= 0	; Select Clock Source
414.equ	CKSEL1	= 1	; Select Clock Source
415.equ	SUT0	= 2	; Select start-up time
416.equ	SUT1	= 3	; Select start-up time
417.equ	CKDIV8	= 4	; Start up with system clock divided by 8
418.equ	WDTON	= 5	; Watch dog timer always on
419.equ	EESAVE	= 6	; Keep EEprom contents during chip erase
420.equ	SPIEN	= 7	; SPI programming enable
421
422; HIGH fuse bits
423.equ	RSTDISBL	= 0	; Disable external reset
424.equ	BODLEVEL0	= 1	; Enable BOD and select level
425.equ	BODLEVEL1	= 2	; Enable BOD and select level
426.equ	DWEN	= 3	; DebugWire Enable
427.equ	SELFPRGEN	= 4	; Self Programming Enable
428
429
430
431; ***** CPU REGISTER DEFINITIONS *****************************************
432.def	XH	= r27
433.def	XL	= r26
434.def	YH	= r29
435.def	YL	= r28
436.def	ZH	= r31
437.def	ZL	= r30
438
439
440
441; ***** DATA MEMORY DECLARATIONS *****************************************
442.equ	FLASHEND	= 0x01ff	; Note: Word address
443.equ	IOEND	= 0x003f
444.equ	SRAM_START	= 0x0060
445.equ	SRAM_SIZE	= 64
446.equ	RAMEND	= 0x009f
447.equ	XRAMEND	= 0x0000
448.equ	E2END	= 0x003f
449.equ	EEPROMEND	= 0x003f
450.equ	EEADRBITS	= 6
451#pragma AVRPART MEMORY PROG_FLASH 1024
452#pragma AVRPART MEMORY EEPROM 64
453#pragma AVRPART MEMORY INT_SRAM SIZE 64
454#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
455
456
457
458; ***** BOOTLOADER DECLARATIONS ******************************************
459.equ	PAGESIZE	= 16
460
461
462
463; ***** INTERRUPT VECTORS ************************************************
464.equ	INT0addr	= 0x0001	; External Interrupt 0
465.equ	PCI0addr	= 0x0002	; External Interrupt Request 0
466.equ	OVF0addr	= 0x0003	; Timer/Counter0 Overflow
467.equ	ERDYaddr	= 0x0004	; EEPROM Ready
468.equ	ACIaddr	= 0x0005	; Analog Comparator
469.equ	OC0Aaddr	= 0x0006	; Timer/Counter Compare Match A
470.equ	OC0Baddr	= 0x0007	; Timer/Counter Compare Match B
471.equ	WDTaddr	= 0x0008	; Watchdog Time-out
472.equ	ADCCaddr	= 0x0009	; ADC Conversion Complete
473
474.equ	INT_VECTORS_SIZE	= 10	; size in words
475
476#endif  /* _TN13ADEF_INC_ */
477
478; ***** END OF FILE ******************************************************
479