1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
2;***** Created: 2011-02-09 12:03 ******* Source: ATtiny20.xml ************
3;*************************************************************************
4;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
5;*
6;* Number            : AVR000
7;* File Name         : "tn20def.inc"
8;* Title             : Register/Bit Definitions for the ATtiny20
9;* Date              : 2011-02-09
10;* Version           : 2.35
11;* Support E-mail    : avr@atmel.com
12;* Target MCU        : ATtiny20
13;*
14;* DESCRIPTION
15;* When including this file in the assembly program file, all I/O register
16;* names and I/O register bit names appearing in the data book can be used.
17;* In addition, the six registers forming the three data pointers X, Y and
18;* Z have been assigned names XL - ZH. Highest RAM address for Internal
19;* SRAM is also defined
20;*
21;* The Register names are represented by their hexadecimal address.
22;*
23;* The Register Bit names are represented by their bit number (0-7).
24;*
25;* Please observe the difference in using the bit names with instructions
26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
27;* (skip if bit in register set/cleared). The following example illustrates
28;* this:
29;*
30;* in    r16,PORTB             ;read PORTB latch
31;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
32;* out   PORTB,r16             ;output to PORTB
33;*
34;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
35;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
36;* rjmp  TOV0_is_set           ;jump if set
37;* ...                         ;otherwise do something else
38;*************************************************************************
39
40#ifndef _TN20DEF_INC_
41#define _TN20DEF_INC_
42
43
44#pragma partinc 0
45
46; ***** SPECIFY DEVICE ***************************************************
47.device ATtiny20
48#pragma AVRPART ADMIN PART_NAME ATtiny20
49.equ	SIGNATURE_000	= 0x1e
50.equ	SIGNATURE_001	= 0x91
51.equ	SIGNATURE_002	= 0x0f
52
53#pragma AVRPART CORE CORE_VERSION AVR8L_0
54
55
56; ***** I/O REGISTER DEFINITIONS *****************************************
57; NOTE:
58; Definitions marked "MEMORY MAPPED"are extended I/O ports
59; and cannot be used with IN/OUT instructions
60.equ	SREG	= 0x3f
61.equ	SPL	= 0x3d
62.equ	SPH	= 0x3e
63.equ	CCP	= 0x3c
64.equ	RSTFLR	= 0x3b
65.equ	MCUCR	= 0x3a
66.equ	OSCCAL	= 0x39
67.equ	CLKMSR	= 0x37
68.equ	CLKPSR	= 0x36
69.equ	PRR	= 0x35
70.equ	QTCSR	= 0x34
71.equ	NVMCMD	= 0x33
72.equ	NVMCSR	= 0x32
73.equ	WDTCSR	= 0x31
74.equ	SPCR	= 0x30
75.equ	SPSR	= 0x2f
76.equ	SPDR	= 0x2e
77.equ	TWSCRA	= 0x2d
78.equ	TWSCRB	= 0x2c
79.equ	TWSSRA	= 0x2b
80.equ	TWSA	= 0x2a
81.equ	TWSAM	= 0x29
82.equ	TWSD	= 0x28
83.equ	GTCCR	= 0x27
84.equ	TIMSK	= 0x26
85.equ	TIFR	= 0x25
86.equ	TCCR1A	= 0x24
87.equ	TCCR1B	= 0x23
88.equ	TCCR1C	= 0x22
89.equ	TCNT1H	= 0x21
90.equ	TCNT1L	= 0x20
91.equ	OCR1AL	= 0x1e
92.equ	OCR1AH	= 0x1f
93.equ	OCR1BL	= 0x1c
94.equ	OCR1BH	= 0x1d
95.equ	ICR1L	= 0x1a
96.equ	ICR1H	= 0x1b
97.equ	TCCR0A	= 0x19
98.equ	TCCR0B	= 0x18
99.equ	TCNT0	= 0x17
100.equ	OCR0A	= 0x16
101.equ	OCR0B	= 0x15
102.equ	ACSRA	= 0x14
103.equ	ACSRB	= 0x13
104.equ	ADCSRA	= 0x12
105.equ	ADCSRB	= 0x11
106.equ	ADMUX	= 0x10
107.equ	ADCH	= 0x0f
108.equ	ADCL	= 0x0e
109.equ	DIDR0	= 0x0d
110.equ	GIMSK	= 0x0c
111.equ	GIFR	= 0x0b
112.equ	PCMSK1	= 0x0a
113.equ	PCMSK0	= 0x09
114.equ	PORTCR	= 0x08
115.equ	PUEB	= 0x07
116.equ	PORTB	= 0x06
117.equ	DDRB	= 0x05
118.equ	PINB	= 0x04
119.equ	PUEA	= 0x03
120.equ	PORTA	= 0x02
121.equ	DDRA	= 0x01
122.equ	PINA	= 0x00
123
124
125; ***** BIT DEFINITIONS **************************************************
126
127; ***** PORTB ************************
128; PORTCR - Port Control Register
129.equ	BBMB	= 1	; Break-Before-Make Mode Enable
130
131; PUEB - Pull-up Enable Control Register
132.equ	PUEB0	= 0	;
133.equ	PUEB1	= 1	;
134.equ	PUEB2	= 2	;
135.equ	PUEB3	= 3	;
136
137; PORTB - Input Pins, Port B
138.equ	PORTB0	= 0	;
139.equ	PB0	= 0	; For compatibility
140.equ	PORTB1	= 1	;
141.equ	PB1	= 1	; For compatibility
142.equ	PORTB2	= 2	;
143.equ	PB2	= 2	; For compatibility
144.equ	PORTB3	= 3	;
145.equ	PB3	= 3	; For compatibility
146
147; DDRB - Data Direction Register, Port B
148.equ	DDB0	= 0	;
149.equ	DDB1	= 1	;
150.equ	DDB2	= 2	;
151.equ	DDB3	= 3	;
152
153; PINB - Port B Data register
154.equ	PINB0	= 0	;
155.equ	PINB1	= 1	;
156.equ	PINB2	= 2	;
157.equ	PINB3	= 3	;
158
159
160; ***** WATCHDOG *********************
161; WDTCSR - Watchdog Timer Control and Status Register
162.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
163.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
164.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
165.equ	WDE	= 3	; Watch Dog Enable
166.equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
167.equ	WDIE	= 6	; Watchdog Timer Interrupt Enable
168.equ	WDIF	= 7	; Watchdog Timer Interrupt Flag
169
170
171; ***** AD_CONVERTER *****************
172; ADMUX - The ADC multiplexer Selection Register
173.equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
174.equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
175.equ	MUX2	= 2	; Analog Channel and Gain Selection Bits
176.equ	MUX3	= 3	; Analog Channel and Gain Selection Bits
177.equ	REFS	= 6	; Reference Selection Bit
178
179; ADCSRA - The ADC Control and Status register
180.equ	ADPS0	= 0	; ADC Prescaler Select Bits
181.equ	ADPS1	= 1	; ADC Prescaler Select Bits
182.equ	ADPS2	= 2	; ADC Prescaler Select Bits
183.equ	ADIE	= 3	; ADC Interrupt Enable
184.equ	ADIF	= 4	; ADC Interrupt Flag
185.equ	ADATE	= 5	; ADC Auto Trigger Enable
186.equ	ADSC	= 6	; ADC Start Conversion
187.equ	ADEN	= 7	; ADC Enable
188
189; ADCH - ADC Data Register High Byte
190.equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
191.equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
192.equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
193.equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
194.equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
195.equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
196.equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
197.equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7
198
199; ADCL - ADC Data Register Low Byte
200.equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
201.equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
202.equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
203.equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
204.equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
205.equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
206.equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
207.equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7
208
209; ADCSRB - ADC Control and Status Register B
210.equ	ADTS0	= 0	; ADC Auto Trigger Source 0
211.equ	ADTS1	= 1	; ADC Auto Trigger Source 1
212.equ	ADTS2	= 2	; ADC Auto Trigger Source 2
213.equ	ADLAR	= 3	;
214
215; DIDR0 - Digital Input Disable Register 0
216.equ	ADC0D	= 0	; ADC0 Digital input Disable
217.equ	ADC1D	= 1	; ADC1 Digital input Disable
218.equ	ADC2D	= 2	; ADC2 Digital input Disable
219.equ	ADC3D	= 3	; AREF Digital Input Disable
220.equ	ADC4D	= 4	; ADC3 Digital input Disable
221.equ	ADC5D	= 5	; ADC4 Digital input Disable
222.equ	ADC6D	= 6	; ADC5 Digital input Disable
223.equ	ADC7D	= 7	; ADC6 Digital input Disable
224
225
226; ***** ANALOG_COMPARATOR ************
227; ACSRA - Analog Comparator Control And Status Register A
228.equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
229.equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
230.equ	ACIC	= 2	; Analog Comparator Input Capture Enable
231.equ	ACIE	= 3	; Analog Comparator Interrupt Enable
232.equ	ACI	= 4	; Analog Comparator Interrupt Flag
233.equ	ACO	= 5	; Analog Compare Output
234.equ	ACBG	= 6	; Analog Comparator Bandgap Select
235.equ	ACD	= 7	; Analog Comparator Disable
236
237; ACSRB - Analog Comparator Control And Status Register B
238.equ	ACME	= 2	; Analog Comparator Multiplexer Enable
239.equ	HLEV	= 6	; Hysteresis Level
240.equ	HSEL	= 7	; Hysteresis Select
241
242
243; ***** CPU **************************
244; CCP - Configuration Change Protection
245.equ	CCP0	= 0	; Configuration Change Protection bit 0
246.equ	CCP1	= 1	; Configuration Change Protection bit 1
247.equ	CCP2	= 2	; Configuration Change Protection bit 2
248.equ	CCP3	= 3	; Configuration Change Protection bit 3
249.equ	CCP4	= 4	; Configuration Change Protection bit 4
250.equ	CCP5	= 5	; Configuration Change Protection bit 5
251.equ	CCP6	= 6	; Configuration Change Protection bit 6
252.equ	CCP7	= 7	; Configuration Change Protection bit 7
253
254; SREG - Status Register
255.equ	SREG_C	= 0	; Carry Flag
256.equ	SREG_Z	= 1	; Zero Flag
257.equ	SREG_N	= 2	; Negative Flag
258.equ	SREG_V	= 3	; Two's Complement Overflow Flag
259.equ	SREG_S	= 4	; Sign Bit
260.equ	SREG_H	= 5	; Half Carry Flag
261.equ	SREG_T	= 6	; Bit Copy Storage
262.equ	SREG_I	= 7	; Global Interrupt Enable
263
264; CLKMSR - Clock Main Settings Register
265.equ	CLKMS0	= 0	; Clock Main Select Bit 0
266.equ	CLKMS1	= 1	; Clock Main Select Bit 1
267
268; CLKPSR - Clock Prescale Register
269.equ	CLKPS0	= 0	; Clock Prescaler Select Bit 0
270.equ	CLKPS1	= 1	; Clock Prescaler Select Bit 1
271.equ	CLKPS2	= 2	; Clock Prescaler Select Bit 2
272.equ	CLKPS3	= 3	; Clock Prescaler Select Bit 3
273
274; OSCCAL - Oscillator Calibration Value
275.equ	CAL0	= 0	; Oscillator Calibration Value Bit0
276.equ	CAL1	= 1	; Oscillator Calibration Value Bit1
277.equ	CAL2	= 2	; Oscillator Calibration Value Bit2
278.equ	CAL3	= 3	; Oscillator Calibration Value Bit3
279.equ	CAL4	= 4	; Oscillator Calibration Value Bit4
280.equ	CAL5	= 5	; Oscillator Calibration Value Bit5
281.equ	CAL6	= 6	; Oscillator Calibration Value Bit6
282.equ	CAL7	= 7	; Oscillator Calibration Value Bit7
283
284; PRR - Power Reduction Register
285.equ	PRADC	= 0	; Power Reduction ADC
286.equ	PRTIM0	= 1	; Power Reduction Timer/Counter0
287.equ	PRTIM1	= 2	; Power Reduction Timer/Counter1
288.equ	PRSPI	= 3	; Power Reduction Serial Peripheral Interface
289.equ	PRTWI	= 4	; Power Reduction TWI
290
291; RSTFLR - Reset Flag Register
292.equ	PORF	= 0	; Power-on Reset Flag
293.equ	EXTRF	= 1	; External Reset Flag
294.equ	WDRF	= 3	; Watchdog Reset Flag
295
296; NVMCSR - Non-Volatile Memory Control and Status Register
297.equ	NVMBSY	= 7	; Non-Volatile Memory Busy
298
299; NVMCMD - Non-Volatile Memory Command
300.equ	NVMCMD0	= 0	;
301.equ	NVMCMD1	= 1	;
302.equ	NVMCMD2	= 2	;
303.equ	NVMCMD3	= 3	;
304.equ	NVMCMD4	= 4	;
305.equ	NVMCMD5	= 5	;
306
307; MCUCR - MCU Control Register
308.equ	SE	= 0	;
309.equ	SM0	= 1	;
310.equ	SM1	= 2	;
311.equ	SM2	= 3	;
312.equ	BODS	= 4	;
313.equ	ISC00	= 6	;
314.equ	ISC01	= 7	;
315
316
317; ***** EXTERNAL_INTERRUPT ***********
318; PCMSK1 - Pin Change Mask Register 1
319.equ	PCINT8	= 0	; Pin Change Enable Mask 8
320.equ	PCINT9	= 1	; Pin Change Enable Mask 9
321.equ	PCINT10	= 2	; Pin Change Enable Mask 10
322.equ	PCINT11	= 3	; Pin Change Enable Mask 11
323
324; PCMSK0 - Pin Change Mask Register 0
325.equ	PCINT0	= 0	; Pin Change Enable Mask 0
326.equ	PCINT1	= 1	; Pin Change Enable Mask 1
327.equ	PCINT2	= 2	; Pin Change Enable Mask 2
328.equ	PCINT3	= 3	; Pin Change Enable Mask 3
329.equ	PCINT4	= 4	; Pin Change Enable Mask 4
330.equ	PCINT5	= 5	; Pin Change Enable Mask 5
331.equ	PCINT6	= 6	; Pin Change Enable Mask 6
332.equ	PCINT7	= 7	; Pin Change Enable Mask 7
333
334; GIFR - General Interrupt Flag Register
335.equ	INTF0	= 0	; External Interrupt Flag 0
336.equ	PCIF0	= 4	; Pin Change Interrupt Flag 0
337.equ	PCIF1	= 5	; Pin Change Interrupt Flag 1
338
339; GIMSK - General Interrupt Mask Register
340.equ	INT0	= 0	; External Interrupt Request 0 Enable
341.equ	PCIE0	= 4	; Pin Change Interrupt Enable 0
342.equ	PCIE1	= 5	; Pin Change Interrupt Enable 1
343
344
345; ***** TIMER_COUNTER_0 **************
346; TCCR0A - Timer/Counter 0 Control Register A
347.equ	WGM00	= 0	; Waveform Generation Mode
348.equ	WGM01	= 1	; Waveform Generation Mode
349.equ	COM0B0	= 4	; Compare Output Mode for Channel B bit 0
350.equ	COM0B1	= 5	; Compare Output Mode for Channel B bit 1
351.equ	COM0A0	= 6	; Compare Output Mode for Channel A bit 0
352.equ	COM0A1	= 7	; Compare Output Mode for Channel A bit 1
353
354; TCCR0B - Timer/Counter 0 Control Register B
355.equ	CS00	= 0	; Clock Select
356.equ	CS01	= 1	; Clock Select
357.equ	CS02	= 2	; Clock Select
358.equ	WGM02	= 3	; Waveform Generation Mode
359.equ	FOC0B	= 6	; Force Output Compare B
360.equ	FOC0A	= 7	; Force Output Compare A
361
362; TIMSK - Timer Interrupt Mask Register
363.equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
364.equ	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
365.equ	OCIE0B	= 2	; Timer/Counter Output Compare Match B Interrupt Enable
366.equ	TOIE1	= 3	; Overflow Interrupt Enable
367.equ	OCIE1A	= 4	; Output Compare A Match Interrupt Enable
368.equ	OCIE1B	= 5	; Output Compare B Match Interrupt Enable
369.equ	ICIE1	= 7	; Input Capture Interrupt Enable
370
371; TIFR - Overflow Interrupt Enable
372.equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
373.equ	OCF0A	= 1	; Output Compare Flag 0 A
374.equ	OCF0B	= 2	; Output Compare Flag 0 B
375.equ	TOV1	= 3	; Timer Overflow Flag
376.equ	OCF1A	= 4	; Timer Output Compare Flag 1A
377.equ	OCF1B	= 5	; Timer Output Compare Flag 1B
378.equ	ICF1	= 7	; Input Capture Flag
379
380; GTCCR - General Timer/Counter Control Register
381.equ	PSR	= 0	; Prescaler Reset
382.equ	TSM	= 7	; Timer Synchronization Mode
383
384; TCNT0 - Timer/Counter0
385.equ	TCNT0_0	= 0	;
386.equ	TCNT0_1	= 1	;
387.equ	TCNT0_2	= 2	;
388.equ	TCNT0_3	= 3	;
389.equ	TCNT0_4	= 4	;
390.equ	TCNT0_5	= 5	;
391.equ	TCNT0_6	= 6	;
392.equ	TCNT0_7	= 7	;
393
394; OCR0A - Timer/Counter0 Output Compare Register
395.equ	OCR0_0	= 0	;
396.equ	OCR0_1	= 1	;
397.equ	OCR0_2	= 2	;
398.equ	OCR0_3	= 3	;
399.equ	OCR0_4	= 4	;
400.equ	OCR0_5	= 5	;
401.equ	OCR0_6	= 6	;
402.equ	OCR0_7	= 7	;
403
404; OCR0B - Timer/Counter0 Output Compare Register
405.equ	OCR0B_0	= 0	;
406.equ	OCR0B_1	= 1	;
407.equ	OCR0B_2	= 2	;
408.equ	OCR0B_3	= 3	;
409.equ	OCR0B_4	= 4	;
410.equ	OCR0B_5	= 5	;
411.equ	OCR0B_6	= 6	;
412.equ	OCR0B_7	= 7	;
413
414
415; ***** TWI **************************
416; TWSCRA - TWI Slave Control Register A
417.equ	TWSME	= 0	; TWI Smart Mode Enable
418.equ	TWPME	= 1	; TWI Promiscuous Mode Enable
419.equ	TWSIE	= 2	; TWI Stop Interrupt Enable
420.equ	TWEN	= 3	; Two-Wire Interface Enable
421.equ	TWASIE	= 4	; TWI Address/Stop Interrupt Enable
422.equ	TWDIE	= 5	; TWI Data Interrupt Enable
423.equ	TWSHE	= 7	; TWI SDA Hold Time Enable
424
425; TWSCRB - TWI Slave Control Register B
426.equ	TWCMD0	= 0	;
427.equ	TWCMD1	= 1	;
428.equ	TWAA	= 2	; TWI Acknowledge Action
429
430; TWSSRA - TWI Slave Status Register A
431.equ	TWAS	= 0	; TWI Address or Stop
432.equ	TWDIR	= 1	; TWI Read/Write Direction
433.equ	TWBE	= 2	; TWI Bus Error
434.equ	TWC	= 3	; TWI Collision
435.equ	TWRA	= 4	; TWI Receive Acknowledge
436.equ	TWCH	= 5	; TWI Clock Hold
437.equ	TWASIF	= 6	; TWI Address/Stop Interrupt Flag
438.equ	TWDIF	= 7	; TWI Data Interrupt Flag.
439
440; TWSA - TWI Slave Address Register
441.equ	TWSA0	= 0	; TWI slave address bit
442.equ	TWSA1	= 1	; TWI slave address bit
443.equ	TWSA2	= 2	; TWI slave address bit
444.equ	TWSA3	= 3	; TWI slave address bit
445.equ	TWSA4	= 4	; TWI slave address bit
446.equ	TWSA5	= 5	; TWI slave address bit
447.equ	TWSA6	= 6	; TWI slave address bit
448.equ	TWSA7	= 7	; TWI slave address bit
449
450; TWSD - TWI Slave Data Register
451.equ	TWSD0	= 0	; TWI slave data bit
452.equ	TWSD1	= 1	; TWI slave data bit
453.equ	TWSD2	= 2	; TWI slave data bit
454.equ	TWSD3	= 3	; TWI slave data bit
455.equ	TWSD4	= 4	; TWI slave data bit
456.equ	TWSD5	= 5	; TWI slave data bit
457.equ	TWSD6	= 6	; TWI slave data bit
458.equ	TWSD7	= 7	; TWI slave data bit
459
460; TWSAM - TWI Slave Address Mask Register
461.equ	TWAE	= 0	; TWI Address Enable
462.equ	TWSAM1	= 1	; TWI Address Mask Bit 1
463.equ	TWSAM2	= 2	; TWI Address Mask Bit 2
464.equ	TWSAM3	= 3	; TWI Address Mask Bit 3
465.equ	TWSAM4	= 4	; TWI Address Mask Bit 4
466.equ	TWSAM5	= 5	; TWI Address Mask Bit 5
467.equ	TWSAM6	= 6	; TWI Address Mask Bit 6
468.equ	TWSAM7	= 7	; TWI Address Mask Bit 7
469
470
471; ***** PORTA ************************
472; PORTCR - Port Control Register
473.equ	BBMA	= 0	; Break-Before-Make Mode Enable
474
475; PUEA - Pull-up Enable Control Register
476.equ	PUEA0	= 0	;
477.equ	PUEA1	= 1	;
478.equ	PUEA2	= 2	;
479.equ	PUEA3	= 3	;
480.equ	PUEA4	= 4	;
481.equ	PUEA5	= 5	;
482.equ	PUEA6	= 6	;
483.equ	PUEA7	= 7	;
484
485; PORTA - Port A Data Register
486.equ	PORTA0	= 0	;
487.equ	PA0	= 0	; For compatibility
488.equ	PORTA1	= 1	;
489.equ	PA1	= 1	; For compatibility
490.equ	PORTA2	= 2	;
491.equ	PA2	= 2	; For compatibility
492.equ	PORTA3	= 3	;
493.equ	PA3	= 3	; For compatibility
494.equ	PORTA4	= 4	;
495.equ	PA4	= 4	; For compatibility
496.equ	PORTA5	= 5	;
497.equ	PA5	= 5	; For compatibility
498.equ	PORTA6	= 6	;
499.equ	PA6	= 6	; For compatibility
500.equ	PORTA7	= 7	;
501.equ	PA7	= 7	; For compatibility
502
503; DDRA - Data Direction Register, Port A
504.equ	DDA0	= 0	;
505.equ	DDA1	= 1	;
506.equ	DDA2	= 2	;
507.equ	DDA3	= 3	;
508.equ	DDA4	= 4	;
509.equ	DDA5	= 5	;
510.equ	DDA6	= 6	;
511.equ	DDA7	= 7	;
512
513; PINA - Port A Input Pins
514.equ	PINA0	= 0	;
515.equ	PINA1	= 1	;
516.equ	PINA2	= 2	;
517.equ	PINA3	= 3	;
518.equ	PINA4	= 4	;
519.equ	PINA5	= 5	;
520.equ	PINA6	= 6	;
521.equ	PINA7	= 7	;
522
523
524; ***** TIMER_COUNTER_1 **************
525; TCCR1A - Timer/Counter1 Control Register A
526.equ	WGM10	= 0	; Waveform Generation Mode Bit 0
527.equ	PWM10	= WGM10	; For compatibility
528.equ	WGM11	= 1	; Waveform Generation Mode Bit 1
529.equ	PWM11	= WGM11	; For compatibility
530.equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0
531.equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
532.equ	COM1A0	= 6	; Compare Ouput Mode 1A, bit 0
533.equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
534
535; TCCR1B - Timer/Counter1 Control Register B
536.equ	CS10	= 0	; Clock Select bit 0
537.equ	CS11	= 1	; Clock Select 1 bit 1
538.equ	CS12	= 2	; Clock Select1 bit 2
539.equ	WGM12	= 3	; Waveform Generation Mode
540.equ	CTC10	= WGM12	; For compatibility
541.equ	WGM13	= 4	; Waveform Generation Mode
542.equ	CTC11	= WGM13	; For compatibility
543.equ	ICES1	= 6	; Input Capture 1 Edge Select
544.equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
545
546; TCCR1C - Timer/Counter1 Control Register C
547.equ	FOC1B	= 6	; Force Output Compare for channel B
548.equ	FOC1A	= 7	; Force Output Compare for channel A
549
550; TCNT1H - Timer/Counter1 High
551.equ	TCNT1_8	= 0	;
552.equ	TCNT1_9	= 1	;
553.equ	TCNT1_10	= 2	;
554.equ	TCNT1_11	= 3	;
555.equ	TCNT1_12	= 4	;
556.equ	TCNT1_13	= 5	;
557.equ	TCNT1_14	= 6	;
558.equ	TCNT1_15	= 7	;
559
560; TCNT1L - Timer/Counter1 Low
561.equ	TCNT1_0	= 0	;
562.equ	TCNT1_1	= 1	;
563.equ	TCNT1_2	= 2	;
564.equ	TCNT1_3	= 3	;
565.equ	TCNT1_4	= 4	;
566.equ	TCNT1_5	= 5	;
567.equ	TCNT1_6	= 6	;
568.equ	TCNT1_7	= 7	;
569
570; TIMSK - Timer Interrupt Mask Register
571;.equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
572;.equ	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
573;.equ	OCIE0B	= 2	; Timer/Counter Output Compare Match B Interrupt Enable
574;.equ	TOIE1	= 3	; Overflow Interrupt Enable
575;.equ	OCIE1A	= 4	; Output Compare A Match Interrupt Enable
576;.equ	OCIE1B	= 5	; Output Compare B Match Interrupt Enable
577;.equ	ICIE1	= 7	; Input Capture Interrupt Enable
578
579; TIFR - Overflow Interrupt Enable
580;.equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
581;.equ	OCF0A	= 1	; Output Compare Flag 0 A
582;.equ	OCF0B	= 2	; Output Compare Flag 0 B
583;.equ	TOV1	= 3	; Timer Overflow Flag
584;.equ	OCF1A	= 4	; Timer Output Compare Flag 1A
585;.equ	OCF1B	= 5	; Timer Output Compare Flag 1B
586;.equ	ICF1	= 7	; Input Capture Flag
587
588; GTCCR - General Timer/Counter Control Register
589;.equ	PSR	= 0	; Prescaler Reset
590;.equ	TSM	= 7	; Timer Synchronization Mode
591
592
593; ***** SPI **************************
594; SPDR - SPI Data Register
595.equ	SPDR0	= 0	; SPI Data Register bit 0
596.equ	SPDR1	= 1	; SPI Data Register bit 1
597.equ	SPDR2	= 2	; SPI Data Register bit 2
598.equ	SPDR3	= 3	; SPI Data Register bit 3
599.equ	SPDR4	= 4	; SPI Data Register bit 4
600.equ	SPDR5	= 5	; SPI Data Register bit 5
601.equ	SPDR6	= 6	; SPI Data Register bit 6
602.equ	SPDR7	= 7	; SPI Data Register bit 7
603
604; SPSR - SPI Status Register
605.equ	SPI2X	= 0	; Double SPI Speed Bit
606.equ	WCOL	= 6	; Write Collision Flag
607.equ	SPIF	= 7	; SPI Interrupt Flag
608
609; SPCR - SPI Control Register
610.equ	SPR0	= 0	; SPI Clock Rate Select 0
611.equ	SPR1	= 1	; SPI Clock Rate Select 1
612.equ	CPHA	= 2	; Clock Phase
613.equ	CPOL	= 3	; Clock polarity
614.equ	MSTR	= 4	; Master/Slave Select
615.equ	DORD	= 5	; Data Order
616.equ	SPE	= 6	; SPI Enable
617.equ	SPIE	= 7	; SPI Interrupt Enable
618
619
620
621; ***** LOCKSBITS ********************************************************
622.equ	LB1	= 0	; Lockbit
623.equ	LB2	= 1	; Lockbit
624
625
626; ***** FUSES ************************************************************
627; BYTE0 fuse bits
628.equ	RSTDISBL	= 0	; Disable external reset
629.equ	WDTON	= 1	; Watch dog timer always on
630.equ	CKOUT	= 2	; Output external clock
631.equ	BODLEVEL0	= 4	; Brown-out Detector trigger level
632.equ	BODLEVEL1	= 5	; Brown-out Detector trigger level
633.equ	BODLEVEL2	= 6	; Brown-out Detector trigger level
634
635
636
637; ***** CPU REGISTER DEFINITIONS *****************************************
638.def	XH	= r27
639.def	XL	= r26
640.def	YH	= r29
641.def	YL	= r28
642.def	ZH	= r31
643.def	ZL	= r30
644
645
646
647; ***** DATA MEMORY DECLARATIONS *****************************************
648.equ	FLASHEND	= 0x03ff	; Note: Word address
649.equ	IOEND	= 0x003f
650.equ	SRAM_START	= 0x0040
651.equ	SRAM_SIZE	= 128
652.equ	RAMEND	= 0x00bf
653.equ	XRAMEND	= 0x0000
654.equ	E2END	= 0x0000
655.equ	EEPROMEND	= 0x0000
656
657; ***** MEMORY MAPPED NVM ************************************************
658.equ	MAPPED_FLASH_START	= 0x4000
659.equ	MAPPED_LOCKBITS_0	= 0x3f00
660.equ	MAPPED_CONFIG_0	= 0x3f40
661.equ	MAPPED_CALIB_0	= 0x3f80
662.equ	MAPPED_SIGN_0	= 0x3fc0
663.equ	MAPPED_SIGN_1	= 0x3fc1
664.equ	MAPPED_SIGN_2	= 0x3fc2
665.equ	MAPPED_FLASH_SIZE	= 0x0800
666.equ	MAPPED_FLASH_END	= 0x47ff
667#pragma AVRPART MEMORY PROG_FLASH 2048
668#pragma AVRPART MEMORY EEPROM 0
669#pragma AVRPART MEMORY INT_SRAM SIZE 128
670#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x40
671
672
673
674; ***** BOOTLOADER DECLARATIONS ******************************************
675.equ	PAGESIZE	= 32
676
677
678
679; ***** INTERRUPT VECTORS ************************************************
680.equ	INT0addr	= 0x0001	; External Interrupt Request 0
681.equ	PCI0addr	= 0x0002	; Pin Change Interrupt Request 0
682.equ	PCI1addr	= 0x0003	; Pin Change Interrupt Request 1
683.equ	WDTaddr	= 0x0004	; Watchdog Time-out
684.equ	ICP1addr	= 0x0005	; Timer/Counter1 Input Capture
685.equ	OC1Aaddr	= 0x0006	; Timer/Counter1 Compare Match A
686.equ	OC1Baddr	= 0x0007	; Timer/Counter1 Compare Match B
687.equ	OVF1addr	= 0x0008	; Timer/Counter1 Overflow
688.equ	OC0Aaddr	= 0x0009	; Timer/Counter0 Compare Match A
689.equ	OC0Baddr	= 0x000a	; Timer/Counter0 Compare Match B
690.equ	OVF0addr	= 0x000b	; Timer/Counter0 Overflow
691.equ	ACIaddr	= 0x000c	; Analog Comparator
692.equ	ADCCaddr	= 0x000d	; Conversion Complete
693.equ	TWIaddr	= 0x000e	; Two-Wire Interface
694.equ	SPIaddr	= 0x000f	; Serial Peripheral Interface
695.equ	QTRIPaddr	= 0x0010	; Touch Sensing
696
697.equ	INT_VECTORS_SIZE	= 17	; size in words
698
699#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
700
701#endif  /* _TN20DEF_INC_ */
702
703; ***** END OF FILE ******************************************************
704