1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** 2;***** Created: 2011-02-09 12:04 ******* Source: ATtiny85.xml ************ 3;************************************************************************* 4;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y 5;* 6;* Number : AVR000 7;* File Name : "tn85def.inc" 8;* Title : Register/Bit Definitions for the ATtiny85 9;* Date : 2011-02-09 10;* Version : 2.35 11;* Support E-mail : avr@atmel.com 12;* Target MCU : ATtiny85 13;* 14;* DESCRIPTION 15;* When including this file in the assembly program file, all I/O register 16;* names and I/O register bit names appearing in the data book can be used. 17;* In addition, the six registers forming the three data pointers X, Y and 18;* Z have been assigned names XL - ZH. Highest RAM address for Internal 19;* SRAM is also defined 20;* 21;* The Register names are represented by their hexadecimal address. 22;* 23;* The Register Bit names are represented by their bit number (0-7). 24;* 25;* Please observe the difference in using the bit names with instructions 26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 27;* (skip if bit in register set/cleared). The following example illustrates 28;* this: 29;* 30;* in r16,PORTB ;read PORTB latch 31;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) 32;* out PORTB,r16 ;output to PORTB 33;* 34;* in r16,TIFR ;read the Timer Interrupt Flag Register 35;* sbrc r16,TOV0 ;test the overflow flag (use bit#) 36;* rjmp TOV0_is_set ;jump if set 37;* ... ;otherwise do something else 38;************************************************************************* 39 40#ifndef _TN85DEF_INC_ 41#define _TN85DEF_INC_ 42 43 44#pragma partinc 0 45 46; ***** SPECIFY DEVICE *************************************************** 47.device ATtiny85 48#pragma AVRPART ADMIN PART_NAME ATtiny85 49.equ SIGNATURE_000 = 0x1e 50.equ SIGNATURE_001 = 0x93 51.equ SIGNATURE_002 = 0x0b 52 53#pragma AVRPART CORE CORE_VERSION V2 54#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ 55 56 57; ***** I/O REGISTER DEFINITIONS ***************************************** 58; NOTE: 59; Definitions marked "MEMORY MAPPED"are extended I/O ports 60; and cannot be used with IN/OUT instructions 61.equ SREG = 0x3f 62.equ SPL = 0x3d 63.equ SPH = 0x3e 64.equ GIMSK = 0x3b 65.equ GIFR = 0x3a 66.equ TIMSK = 0x39 67.equ TIFR = 0x38 68.equ SPMCSR = 0x37 69.equ MCUCR = 0x35 70.equ MCUSR = 0x34 71.equ TCCR0B = 0x33 72.equ TCNT0 = 0x32 73.equ OSCCAL = 0x31 74.equ TCCR1 = 0x30 75.equ TCNT1 = 0x2f 76.equ OCR1A = 0x2e 77.equ OCR1C = 0x2d 78.equ GTCCR = 0x2c 79.equ OCR1B = 0x2b 80.equ TCCR0A = 0x2a 81.equ OCR0A = 0x29 82.equ OCR0B = 0x28 83.equ PLLCSR = 0x27 84.equ CLKPR = 0x26 85.equ DT1A = 0x25 86.equ DT1B = 0x24 87.equ DTPS = 0x23 88.equ DWDR = 0x22 89.equ WDTCR = 0x21 90.equ PRR = 0x20 91.equ EEARH = 0x1f 92.equ EEARL = 0x1e 93.equ EEDR = 0x1d 94.equ EECR = 0x1c 95.equ PORTB = 0x18 96.equ DDRB = 0x17 97.equ PINB = 0x16 98.equ PCMSK = 0x15 99.equ DIDR0 = 0x14 100.equ GPIOR2 = 0x13 101.equ GPIOR1 = 0x12 102.equ GPIOR0 = 0x11 103.equ USIBR = 0x10 104.equ USIDR = 0x0f 105.equ USISR = 0x0e 106.equ USICR = 0x0d 107.equ ACSR = 0x08 108.equ ADMUX = 0x07 109.equ ADCSRA = 0x06 110.equ ADCH = 0x05 111.equ ADCL = 0x04 112.equ ADCSRB = 0x03 113 114 115; ***** BIT DEFINITIONS ************************************************** 116 117; ***** PORTB ************************ 118; PORTB - Data Register, Port B 119.equ PORTB0 = 0 ; 120.equ PB0 = 0 ; For compatibility 121.equ PORTB1 = 1 ; 122.equ PB1 = 1 ; For compatibility 123.equ PORTB2 = 2 ; 124.equ PB2 = 2 ; For compatibility 125.equ PORTB3 = 3 ; 126.equ PB3 = 3 ; For compatibility 127.equ PORTB4 = 4 ; 128.equ PB4 = 4 ; For compatibility 129.equ PORTB5 = 5 ; 130.equ PB5 = 5 ; For compatibility 131 132; DDRB - Data Direction Register, Port B 133.equ DDB0 = 0 ; 134.equ DDB1 = 1 ; 135.equ DDB2 = 2 ; 136.equ DDB3 = 3 ; 137.equ DDB4 = 4 ; 138.equ DDB5 = 5 ; 139 140; PINB - Input Pins, Port B 141.equ PINB0 = 0 ; 142.equ PINB1 = 1 ; 143.equ PINB2 = 2 ; 144.equ PINB3 = 3 ; 145.equ PINB4 = 4 ; 146.equ PINB5 = 5 ; 147 148 149; ***** ANALOG_COMPARATOR ************ 150; ADCSRB - ADC Control and Status Register B 151.equ ACME = 6 ; Analog Comparator Multiplexer Enable 152 153; ACSR - Analog Comparator Control And Status Register 154.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 155.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 156.equ ACIE = 3 ; Analog Comparator Interrupt Enable 157.equ ACI = 4 ; Analog Comparator Interrupt Flag 158.equ ACO = 5 ; Analog Compare Output 159.equ ACBG = 6 ; Analog Comparator Bandgap Select 160.equ AINBG = ACBG ; For compatibility 161.equ ACD = 7 ; Analog Comparator Disable 162 163; DIDR0 - 164.equ AIN0D = 0 ; AIN0 Digital Input Disable 165.equ AIN1D = 1 ; AIN1 Digital Input Disable 166 167 168; ***** AD_CONVERTER ***************** 169; ADMUX - The ADC multiplexer Selection Register 170.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits 171.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits 172.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits 173.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits 174.equ REFS2 = 4 ; Reference Selection Bit 2 175.equ ADLAR = 5 ; Left Adjust Result 176.equ REFS0 = 6 ; Reference Selection Bit 0 177.equ REFS1 = 7 ; Reference Selection Bit 1 178 179; ADCSRA - The ADC Control and Status register 180.equ ADPS0 = 0 ; ADC Prescaler Select Bits 181.equ ADPS1 = 1 ; ADC Prescaler Select Bits 182.equ ADPS2 = 2 ; ADC Prescaler Select Bits 183.equ ADIE = 3 ; ADC Interrupt Enable 184.equ ADIF = 4 ; ADC Interrupt Flag 185.equ ADATE = 5 ; ADC Auto Trigger Enable 186.equ ADSC = 6 ; ADC Start Conversion 187.equ ADEN = 7 ; ADC Enable 188 189; ADCH - ADC Data Register High Byte 190.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 191.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 192.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 193.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 194.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 195.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 196.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 197.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 198 199; ADCL - ADC Data Register Low Byte 200.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 201.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 202.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 203.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 204.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 205.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 206.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 207.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 208 209; ADCSRB - ADC Control and Status Register B 210.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 211.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 212.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 213.equ IPR = 5 ; Input Polarity Mode 214.equ BIN = 7 ; Bipolar Input Mode 215 216; DIDR0 - Digital Input Disable Register 0 217.equ ADC1D = 2 ; ADC1 Digital input Disable 218.equ ADC3D = 3 ; ADC3 Digital input Disable 219.equ ADC2D = 4 ; ADC2 Digital input Disable 220.equ ADC0D = 5 ; ADC0 Digital input Disable 221 222 223; ***** USI ************************** 224; USIBR - USI Buffer Register 225.equ USIBR0 = 0 ; USI Buffer Register bit 0 226.equ USIBR1 = 1 ; USI Buffer Register bit 1 227.equ USIBR2 = 2 ; USI Buffer Register bit 2 228.equ USIBR3 = 3 ; USI Buffer Register bit 3 229.equ USIBR4 = 4 ; USI Buffer Register bit 4 230.equ USIBR5 = 5 ; USI Buffer Register bit 5 231.equ USIBR6 = 6 ; USI Buffer Register bit 6 232.equ USIBR7 = 7 ; USI Buffer Register bit 7 233 234; USIDR - USI Data Register 235.equ USIDR0 = 0 ; USI Data Register bit 0 236.equ USIDR1 = 1 ; USI Data Register bit 1 237.equ USIDR2 = 2 ; USI Data Register bit 2 238.equ USIDR3 = 3 ; USI Data Register bit 3 239.equ USIDR4 = 4 ; USI Data Register bit 4 240.equ USIDR5 = 5 ; USI Data Register bit 5 241.equ USIDR6 = 6 ; USI Data Register bit 6 242.equ USIDR7 = 7 ; USI Data Register bit 7 243 244; USISR - USI Status Register 245.equ USICNT0 = 0 ; USI Counter Value Bit 0 246.equ USICNT1 = 1 ; USI Counter Value Bit 1 247.equ USICNT2 = 2 ; USI Counter Value Bit 2 248.equ USICNT3 = 3 ; USI Counter Value Bit 3 249.equ USIDC = 4 ; Data Output Collision 250.equ USIPF = 5 ; Stop Condition Flag 251.equ USIOIF = 6 ; Counter Overflow Interrupt Flag 252.equ USISIF = 7 ; Start Condition Interrupt Flag 253 254; USICR - USI Control Register 255.equ USITC = 0 ; Toggle Clock Port Pin 256.equ USICLK = 1 ; Clock Strobe 257.equ USICS0 = 2 ; USI Clock Source Select Bit 0 258.equ USICS1 = 3 ; USI Clock Source Select Bit 1 259.equ USIWM0 = 4 ; USI Wire Mode Bit 0 260.equ USIWM1 = 5 ; USI Wire Mode Bit 1 261.equ USIOIE = 6 ; Counter Overflow Interrupt Enable 262.equ USISIE = 7 ; Start Condition Interrupt Enable 263 264 265; ***** EXTERNAL_INTERRUPT *********** 266; MCUCR - MCU Control Register 267.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 268.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 269 270; GIMSK - General Interrupt Mask Register 271.equ GICR = GIMSK ; For compatibility 272.equ PCIE = 5 ; Pin Change Interrupt Enable 273.equ INT0 = 6 ; External Interrupt Request 0 Enable 274 275; GIFR - General Interrupt Flag register 276.equ PCIF = 5 ; Pin Change Interrupt Flag 277.equ INTF0 = 6 ; External Interrupt Flag 0 278 279; PCMSK - Pin Change Enable Mask 280.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0 281.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1 282.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2 283.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3 284.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4 285.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5 286 287 288; ***** EEPROM *********************** 289; EEARL - EEPROM Address Register Low Byte 290.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 291.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 292.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 293.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 294.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 295.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 296.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 297.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 298 299; EEARH - EEPROM Address Register High Byte 300.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0 301 302; EEDR - EEPROM Data Register 303.equ EEDR0 = 0 ; EEPROM Data Register bit 0 304.equ EEDR1 = 1 ; EEPROM Data Register bit 1 305.equ EEDR2 = 2 ; EEPROM Data Register bit 2 306.equ EEDR3 = 3 ; EEPROM Data Register bit 3 307.equ EEDR4 = 4 ; EEPROM Data Register bit 4 308.equ EEDR5 = 5 ; EEPROM Data Register bit 5 309.equ EEDR6 = 6 ; EEPROM Data Register bit 6 310.equ EEDR7 = 7 ; EEPROM Data Register bit 7 311 312; EECR - EEPROM Control Register 313.equ EERE = 0 ; EEPROM Read Enable 314.equ EEPE = 1 ; EEPROM Write Enable 315.equ EEMPE = 2 ; EEPROM Master Write Enable 316.equ EERIE = 3 ; EEPROM Ready Interrupt Enable 317.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 318.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 319 320 321; ***** WATCHDOG ********************* 322; WDTCR - Watchdog Timer Control Register 323.equ WDTCSR = WDTCR ; For compatibility 324.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 325.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 326.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 327.equ WDE = 3 ; Watch Dog Enable 328.equ WDCE = 4 ; Watchdog Change Enable 329.equ WDTOE = WDCE ; For compatibility 330.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 331.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable 332.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag 333 334 335; ***** TIMER_COUNTER_0 ************** 336; TIMSK - Timer/Counter Interrupt Mask Register 337.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable 338.equ OCIE0B = 3 ; Timer/Counter0 Output Compare Match B Interrupt Enable 339.equ OCIE0A = 4 ; Timer/Counter0 Output Compare Match A Interrupt Enable 340 341; TIFR - Timer/Counter0 Interrupt Flag register 342.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag 343.equ OCF0B = 3 ; Timer/Counter0 Output Compare Flag 0B 344.equ OCF0A = 4 ; Timer/Counter0 Output Compare Flag 0A 345 346; TCCR0A - Timer/Counter Control Register A 347.equ WGM00 = 0 ; Waveform Generation Mode 348.equ WGM01 = 1 ; Waveform Generation Mode 349.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm 350.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm 351.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode 352.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode 353 354; TCCR0B - Timer/Counter Control Register B 355.equ CS00 = 0 ; Clock Select 356.equ CS01 = 1 ; Clock Select 357.equ CS02 = 2 ; Clock Select 358.equ WGM02 = 3 ; 359.equ FOC0B = 6 ; Force Output Compare B 360.equ FOC0A = 7 ; Force Output Compare A 361 362; TCNT0 - Timer/Counter0 363.equ TCNT0_0 = 0 ; 364.equ TCNT0_1 = 1 ; 365.equ TCNT0_2 = 2 ; 366.equ TCNT0_3 = 3 ; 367.equ TCNT0_4 = 4 ; 368.equ TCNT0_5 = 5 ; 369.equ TCNT0_6 = 6 ; 370.equ TCNT0_7 = 7 ; 371 372; OCR0A - Timer/Counter0 Output Compare Register 373.equ OCR0_0 = 0 ; 374.equ OCR0_1 = 1 ; 375.equ OCR0_2 = 2 ; 376.equ OCR0_3 = 3 ; 377.equ OCR0_4 = 4 ; 378.equ OCR0_5 = 5 ; 379.equ OCR0_6 = 6 ; 380.equ OCR0_7 = 7 ; 381 382; OCR0B - Timer/Counter0 Output Compare Register 383;.equ OCR0_0 = 0 ; 384;.equ OCR0_1 = 1 ; 385;.equ OCR0_2 = 2 ; 386;.equ OCR0_3 = 3 ; 387;.equ OCR0_4 = 4 ; 388;.equ OCR0_5 = 5 ; 389;.equ OCR0_6 = 6 ; 390;.equ OCR0_7 = 7 ; 391 392; GTCCR - General Timer/Counter Control Register 393.equ PSR0 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 394.equ TSM = 7 ; Timer/Counter Synchronization Mode 395 396 397; ***** TIMER_COUNTER_1 ************** 398; TCCR1 - Timer/Counter Control Register 399.equ CS10 = 0 ; Clock Select Bits 400.equ CS11 = 1 ; Clock Select Bits 401.equ CS12 = 2 ; Clock Select Bits 402.equ CS13 = 3 ; Clock Select Bits 403.equ COM1A0 = 4 ; Compare Output Mode, Bit 1 404.equ COM1A1 = 5 ; Compare Output Mode, Bit 0 405.equ PWM1A = 6 ; Pulse Width Modulator Enable 406.equ CTC1 = 7 ; Clear Timer/Counter on Compare Match 407 408; TCNT1 - Timer/Counter Register 409.equ TCNT1_0 = 0 ; Timer/Counter Register Bit 0 410.equ TCNT1_1 = 1 ; Timer/Counter Register Bit 1 411.equ TCNT1_2 = 2 ; Timer/Counter Register Bit 2 412.equ TCNT1_3 = 3 ; Timer/Counter Register Bit 3 413.equ TCNT1_4 = 4 ; Timer/Counter Register Bit 4 414.equ TCNT1_5 = 5 ; Timer/Counter Register Bit 5 415.equ TCNT1_6 = 6 ; Timer/Counter Register Bit 6 416.equ TCNT1_7 = 7 ; Timer/Counter Register Bit 7 417 418; OCR1A - Output Compare Register 419.equ OCR1A0 = 0 ; Output Compare Register A Bit 0 420.equ OCR1A1 = 1 ; Output Compare Register A Bit 1 421.equ OCR1A2 = 2 ; Output Compare Register A Bit 2 422.equ OCR1A3 = 3 ; Output Compare Register A Bit 3 423.equ OCR1A4 = 4 ; Output Compare Register A Bit 4 424.equ OCR1A5 = 5 ; Output Compare Register A Bit 5 425.equ OCR1A6 = 6 ; Output Compare Register A Bit 6 426.equ OCR1A7 = 7 ; Output Compare Register A Bit 7 427 428; OCR1B - Output Compare Register 429.equ OCR1B0 = 0 ; Output Compare Register B Bit 0 430.equ OCR1B1 = 1 ; Output Compare Register B Bit 1 431.equ OCR1B2 = 2 ; Output Compare Register B Bit 2 432.equ OCR1B3 = 3 ; Output Compare Register B Bit 3 433.equ OCR1B4 = 4 ; Output Compare Register B Bit 4 434.equ OCR1B5 = 5 ; Output Compare Register B Bit 5 435.equ OCR1B6 = 6 ; Output Compare Register B Bit 6 436.equ OCR1B7 = 7 ; Output Compare Register B Bit 7 437 438; OCR1C - Output compare register 439.equ OCR1C0 = 0 ; 440.equ OCR1C1 = 1 ; 441.equ OCR1C2 = 2 ; 442.equ OCR1C3 = 3 ; 443.equ OCR1C4 = 4 ; 444.equ OCR1C5 = 5 ; 445.equ OCR1C6 = 6 ; 446.equ OCR1C7 = 7 ; 447 448; TIMSK - Timer/Counter Interrupt Mask Register 449.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable 450.equ OCIE1B = 5 ; OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable 451.equ OCIE1A = 6 ; OCIE1A: Timer/Counter1 Output Compare Interrupt Enable 452 453; TIFR - Timer/Counter Interrupt Flag Register 454.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag 455.equ OCF1B = 5 ; Timer/Counter1 Output Compare Flag 1B 456.equ OCF1A = 6 ; Timer/Counter1 Output Compare Flag 1A 457 458; GTCCR - Timer counter control register 459.equ PSR1 = 1 ; Prescaler Reset Timer/Counter1 460.equ FOC1A = 2 ; Force Output Compare 1A 461.equ FOC1B = 3 ; Force Output Compare Match 1B 462.equ COM1B0 = 4 ; Comparator B Output Mode 463.equ COM1B1 = 5 ; Comparator B Output Mode 464.equ PWM1B = 6 ; Pulse Width Modulator B Enable 465 466; DTPS - Dead time prescaler register 467.equ DTPS0 = 0 ; 468.equ DTPS1 = 1 ; 469 470; DT1A - Dead time value register 471.equ DTVL0 = 0 ; 472.equ DTVL1 = 1 ; 473.equ DTVL2 = 2 ; 474.equ DTVL3 = 3 ; 475.equ DTVH0 = 4 ; 476.equ DTVH1 = 5 ; 477.equ DTVH2 = 6 ; 478.equ DTVH3 = 7 ; 479 480; DT1B - Dead time value B 481;.equ DTVL0 = 0 ; 482;.equ DTVL1 = 1 ; 483;.equ DTVL2 = 2 ; 484;.equ DTVL3 = 3 ; 485;.equ DTVH0 = 4 ; 486;.equ DTVH1 = 5 ; 487;.equ DTVH2 = 6 ; 488;.equ DTVH3 = 7 ; 489 490 491; ***** BOOT_LOAD ******************** 492; SPMCSR - Store Program Memory Control Register 493.equ SPMEN = 0 ; Store Program Memory Enable 494.equ PGERS = 1 ; Page Erase 495.equ PGWRT = 2 ; Page Write 496.equ RFLB = 3 ; Read fuse and lock bits 497.equ CTPB = 4 ; Clear temporary page buffer 498 499 500; ***** CPU ************************** 501; SREG - Status Register 502.equ SREG_C = 0 ; Carry Flag 503.equ SREG_Z = 1 ; Zero Flag 504.equ SREG_N = 2 ; Negative Flag 505.equ SREG_V = 3 ; Two's Complement Overflow Flag 506.equ SREG_S = 4 ; Sign Bit 507.equ SREG_H = 5 ; Half Carry Flag 508.equ SREG_T = 6 ; Bit Copy Storage 509.equ SREG_I = 7 ; Global Interrupt Enable 510 511; MCUCR - MCU Control Register 512;.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 513;.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 514.equ SM0 = 3 ; Sleep Mode Select Bit 0 515.equ SM1 = 4 ; Sleep Mode Select Bit 1 516.equ SE = 5 ; Sleep Enable 517.equ PUD = 6 ; Pull-up Disable 518 519; MCUSR - MCU Status register 520.equ PORF = 0 ; Power-On Reset Flag 521.equ EXTRF = 1 ; External Reset Flag 522.equ BORF = 2 ; Brown-out Reset Flag 523.equ WDRF = 3 ; Watchdog Reset Flag 524 525; PRR - Power Reduction Register 526.equ PRADC = 0 ; Power Reduction ADC 527.equ PRUSI = 1 ; Power Reduction USI 528.equ PRTIM0 = 2 ; Power Reduction Timer/Counter0 529.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 530 531; OSCCAL - Oscillator Calibration Register 532.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 533.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 534.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 535.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 536.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 537.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 538.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 539.equ CAL7 = 7 ; Oscillatro Calibration Value Bit 7 540 541; PLLCSR - PLL Control and status register 542.equ PLOCK = 0 ; PLL Lock detector 543.equ PLLE = 1 ; PLL Enable 544.equ PCKE = 2 ; PCK Enable 545.equ LSM = 7 ; Low speed mode 546 547; CLKPR - Clock Prescale Register 548.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 549.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 550.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 551.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 552.equ CLKPCE = 7 ; Clock Prescaler Change Enable 553 554; DWDR - debugWire data register 555.equ DWDR0 = 0 ; 556.equ DWDR1 = 1 ; 557.equ DWDR2 = 2 ; 558.equ DWDR3 = 3 ; 559.equ DWDR4 = 4 ; 560.equ DWDR5 = 5 ; 561.equ DWDR6 = 6 ; 562.equ DWDR7 = 7 ; 563 564; GPIOR2 - General Purpose IO register 2 565.equ GPIOR20 = 0 ; 566.equ GPIOR21 = 1 ; 567.equ GPIOR22 = 2 ; 568.equ GPIOR23 = 3 ; 569.equ GPIOR24 = 4 ; 570.equ GPIOR25 = 5 ; 571.equ GPIOR26 = 6 ; 572.equ GPIOR27 = 7 ; 573 574; GPIOR1 - General Purpose register 1 575.equ GPIOR10 = 0 ; 576.equ GPIOR11 = 1 ; 577.equ GPIOR12 = 2 ; 578.equ GPIOR13 = 3 ; 579.equ GPIOR14 = 4 ; 580.equ GPIOR15 = 5 ; 581.equ GPIOR16 = 6 ; 582.equ GPIOR17 = 7 ; 583 584; GPIOR0 - General purpose register 0 585.equ GPIOR00 = 0 ; 586.equ GPIOR01 = 1 ; 587.equ GPIOR02 = 2 ; 588.equ GPIOR03 = 3 ; 589.equ GPIOR04 = 4 ; 590.equ GPIOR05 = 5 ; 591.equ GPIOR06 = 6 ; 592.equ GPIOR07 = 7 ; 593 594 595 596; ***** LOCKSBITS ******************************************************** 597.equ LB1 = 0 ; Lockbit 598.equ LB2 = 1 ; Lockbit 599 600 601; ***** FUSES ************************************************************ 602; LOW fuse bits 603.equ CKSEL0 = 0 ; Select Clock source 604.equ CKSEL1 = 1 ; Select Clock source 605.equ CKSEL2 = 2 ; Select Clock source 606.equ CKSEL3 = 3 ; Select Clock source 607.equ SUT0 = 4 ; Select start-up time 608.equ SUT1 = 5 ; Select start-up time 609.equ CKOUT = 6 ; Clock Output Enable 610.equ CKDIV8 = 7 ; Divide clock by 8 611 612; HIGH fuse bits 613.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level 614.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level 615.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level 616.equ EESAVE = 3 ; EEPROM memory is preserved through the Chip Erase 617.equ WDTON = 4 ; Watchdog Timer always on 618.equ SPIEN = 5 ; Enable Serial Program and Data Downloading 619.equ DWEN = 6 ; DebugWIRE Enable 620.equ RSTDISBL = 7 ; External Reset disable 621 622; EXTENDED fuse bits 623.equ SELFPRGEN = 0 ; Self-Programming Enable 624 625 626 627; ***** CPU REGISTER DEFINITIONS ***************************************** 628.def XH = r27 629.def XL = r26 630.def YH = r29 631.def YL = r28 632.def ZH = r31 633.def ZL = r30 634 635 636 637; ***** DATA MEMORY DECLARATIONS ***************************************** 638.equ FLASHEND = 0x0fff ; Note: Word address 639.equ IOEND = 0x003f 640.equ SRAM_START = 0x0060 641.equ SRAM_SIZE = 512 642.equ RAMEND = 0x025f 643.equ XRAMEND = 0x0000 644.equ E2END = 0x01ff 645.equ EEPROMEND = 0x01ff 646.equ EEADRBITS = 9 647#pragma AVRPART MEMORY PROG_FLASH 8192 648#pragma AVRPART MEMORY EEPROM 512 649#pragma AVRPART MEMORY INT_SRAM SIZE 512 650#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 651 652 653 654; ***** BOOTLOADER DECLARATIONS ****************************************** 655.equ NRWW_START_ADDR = 0x0 656.equ NRWW_STOP_ADDR = 0xfff 657.equ RWW_START_ADDR = 0x0 658.equ RWW_STOP_ADDR = 0x0 659.equ PAGESIZE = 32 660 661 662 663; ***** INTERRUPT VECTORS ************************************************ 664.equ INT0addr = 0x0001 ; External Interrupt 0 665.equ PCI0addr = 0x0002 ; Pin change Interrupt Request 0 666.equ OC1Aaddr = 0x0003 ; Timer/Counter1 Compare Match 1A 667.equ OVF1addr = 0x0004 ; Timer/Counter1 Overflow 668.equ OVF0addr = 0x0005 ; Timer/Counter0 Overflow 669.equ ERDYaddr = 0x0006 ; EEPROM Ready 670.equ ACIaddr = 0x0007 ; Analog comparator 671.equ ADCCaddr = 0x0008 ; ADC Conversion ready 672.equ OC1Baddr = 0x0009 ; Timer/Counter1 Compare Match B 673.equ OC0Aaddr = 0x000a ; Timer/Counter0 Compare Match A 674.equ OC0Baddr = 0x000b ; Timer/Counter0 Compare Match B 675.equ WDTaddr = 0x000c ; Watchdog Time-out 676.equ USI_STARTaddr = 0x000d ; USI START 677.equ USI_OVFaddr = 0x000e ; USI Overflow 678 679.equ INT_VECTORS_SIZE = 15 ; size in words 680 681#endif /* _TN85DEF_INC_ */ 682 683; ***** END OF FILE ****************************************************** 684