1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* CPU data header for iq2000. 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6 Copyright (C) 1996-2021 Free Software Foundation, Inc. 7 8 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24 */ 25 26 #ifndef IQ2000_CPU_H 27 #define IQ2000_CPU_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define CGEN_ARCH iq2000 34 35 /* Given symbol S, return iq2000_cgen_<S>. */ 36 #define CGEN_SYM(s) iq2000##_cgen_##s 37 38 39 /* Selected cpu families. */ 40 #define HAVE_CPU_IQ2000BF 41 #define HAVE_CPU_IQ10BF 42 43 #define CGEN_INSN_LSB0_P 1 44 45 /* Minimum size of any insn (in bytes). */ 46 #define CGEN_MIN_INSN_SIZE 4 47 48 /* Maximum size of any insn (in bytes). */ 49 #define CGEN_MAX_INSN_SIZE 4 50 51 #define CGEN_INT_INSN_P 1 52 53 /* Maximum number of syntax elements in an instruction. */ 54 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 55 56 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 57 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 58 we can't hash on everything up to the space. */ 59 #define CGEN_MNEMONIC_OPERANDS 60 61 /* Maximum number of fields in an instruction. */ 62 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 63 64 /* Enums. */ 65 66 /* Enum declaration for . */ 67 typedef enum gr_names { 68 H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1, H_GR__1 = 1 69 , H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3, H_GR__3 = 3 70 , H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5, H_GR__5 = 5 71 , H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7, H_GR__7 = 7 72 , H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9, H_GR__9 = 9 73 , H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11, H_GR__11 = 11 74 , H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13, H_GR__13 = 13 75 , H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15, H_GR__15 = 15 76 , H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17, H_GR__17 = 17 77 , H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19, H_GR__19 = 19 78 , H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21, H_GR__21 = 21 79 , H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23, H_GR__23 = 23 80 , H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25, H_GR__25 = 25 81 , H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27, H_GR__27 = 27 82 , H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29, H_GR__29 = 29 83 , H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31, H_GR__31 = 31 84 } GR_NAMES; 85 86 /* Enum declaration for primary opcodes. */ 87 typedef enum opcodes { 88 OP_SPECIAL = 0, OP_REGIMM = 1, OP_J = 2, OP_JAL = 3 89 , OP_BEQ = 4, OP_BNE = 5, OP_BLEZ = 6, OP_BGTZ = 7 90 , OP_ADDI = 8, OP_ADDIU = 9, OP_SLTI = 10, OP_SLTIU = 11 91 , OP_ANDI = 12, OP_ORI = 13, OP_XORI = 14, OP_LUI = 15 92 , OP_COP0 = 16, OP_COP1 = 17, OP_COP2 = 18, OP_COP3 = 19 93 , OP_BEQL = 20, OP_BNEL = 21, OP_BLEZL = 22, OP_BGTZL = 23 94 , OP_BMB0 = 24, OP_BMB1 = 25, OP_BMB2 = 26, OP_BMB3 = 27 95 , OP_BBI = 28, OP_BBV = 29, OP_BBIN = 30, OP_BBVN = 31 96 , OP_LB = 32, OP_LH = 33, OP_LW = 35, OP_LBU = 36 97 , OP_LHU = 37, OP_RAM = 39, OP_SB = 40, OP_SH = 41 98 , OP_SW = 43, OP_ANDOI = 44, OP_BMB = 45, OP_ORUI = 47 99 , OP_LDW = 48, OP_SDW = 56, OP_ANDOUI = 63 100 } OPCODES; 101 102 /* Enum declaration for iq10-only primary opcodes. */ 103 typedef enum q10_opcodes { 104 OP10_BMB = 6, OP10_ORUI = 15, OP10_BMBL = 22, OP10_ANDOUI = 47 105 , OP10_BBIL = 60, OP10_BBVL = 61, OP10_BBINL = 62, OP10_BBVNL = 63 106 } Q10_OPCODES; 107 108 /* Enum declaration for branch sub-opcodes. */ 109 typedef enum regimm_functions { 110 FUNC_BLTZ = 0, FUNC_BGEZ = 1, FUNC_BLTZL = 2, FUNC_BGEZL = 3 111 , FUNC_BLEZ = 4, FUNC_BGTZ = 5, FUNC_BLEZL = 6, FUNC_BGTZL = 7 112 , FUNC_BRI = 8, FUNC_BRV = 9, FUNC_BCTX = 12, FUNC_BLTZAL = 16 113 , FUNC_BGEZAL = 17, FUNC_BLTZALL = 18, FUNC_BGEZALL = 19, FUNC_BLEZAL = 20 114 , FUNC_BGTZAL = 21, FUNC_BLEZALL = 22, FUNC_BGTZALL = 23 115 } REGIMM_FUNCTIONS; 116 117 /* Enum declaration for function sub-opcodes. */ 118 typedef enum functions { 119 FUNC_SLL = 0, FUNC_SLMV = 1, FUNC_SRL = 2, FUNC_SRA = 3 120 , FUNC_SLLV = 4, FUNC_SRMV = 5, FUNC_SRLV = 6, FUNC_SRAV = 7 121 , FUNC_JR = 8, FUNC_JALR = 9, FUNC_JCR = 10, FUNC_SYSCALL = 12 122 , FUNC_BREAK = 13, FUNC_SLEEP = 14, FUNC_ADD = 32, FUNC_ADDU = 33 123 , FUNC_SUB = 34, FUNC_SUBU = 35, FUNC_AND = 36, FUNC_OR = 37 124 , FUNC_XOR = 38, FUNC_NOR = 39, FUNC_ADO16 = 41, FUNC_SLT = 42 125 , FUNC_SLTU = 43, FUNC_MRGB = 45 126 } FUNCTIONS; 127 128 /* Enum declaration for iq10-only special function sub-opcodes. */ 129 typedef enum q10s_functions { 130 FUNC10_YIELD = 14, FUNC10_CNT1S = 46 131 } Q10S_FUNCTIONS; 132 133 /* Enum declaration for iq10 function sub-opcodes. */ 134 typedef enum cop_functions { 135 FUNC10_CFC = 0, FUNC10_LOCK = 1, FUNC10_CTC = 2, FUNC10_UNLK = 3 136 , FUNC10_SWRD = 4, FUNC10_SWRDL = 5, FUNC10_SWWR = 6, FUNC10_SWWRU = 7 137 , FUNC10_RBA = 8, FUNC10_RBAL = 9, FUNC10_RBAR = 10, FUNC10_DWRD = 12 138 , FUNC10_DWRDL = 13, FUNC10_WBA = 16, FUNC10_WBAU = 17, FUNC10_WBAC = 18 139 , FUNC10_CRC32 = 20, FUNC10_CRC32B = 21, FUNC10_MCID = 32, FUNC10_DBD = 33 140 , FUNC10_DBA = 34, FUNC10_DPWT = 35, FUNC10_AVAIL = 36, FUNC10_FREE = 37 141 , FUNC10_CHKHDR = 38, FUNC10_TSTOD = 39, FUNC10_PKRLA = 40, FUNC10_PKRLAU = 41 142 , FUNC10_PKRLAH = 42, FUNC10_PKRLAC = 43, FUNC10_CMPHDR = 44, FUNC10_CM64RS = 0 143 , FUNC10_CM64RD = 1, FUNC10_CM64RI = 4, FUNC10_CM64CLR = 5, FUNC10_CM64SS = 8 144 , FUNC10_CM64SD = 9, FUNC10_CM64SI = 12, FUNC10_CM64RA = 16, FUNC10_CM64RIA2 = 20 145 , FUNC10_CM128RIA2 = 21, FUNC10_CM64SA = 24, FUNC10_CM64SIA2 = 28, FUNC10_CM128SIA2 = 29 146 , FUNC10_CM32RS = 32, FUNC10_CM32RD = 33, FUNC10_CM32XOR = 34, FUNC10_CM32ANDN = 35 147 , FUNC10_CM32RI = 36, FUNC10_CM128VSA = 38, FUNC10_CM32SS = 40, FUNC10_CM32SD = 41 148 , FUNC10_CM32OR = 42, FUNC10_CM32AND = 43, FUNC10_CM32SI = 44, FUNC10_CM32RA = 48 149 , FUNC10_CM32SA = 56 150 } COP_FUNCTIONS; 151 152 /* Enum declaration for iq10 function sub-opcodes. */ 153 typedef enum cop_cm128_4functions { 154 FUNC10_CM128RIA3 = 4, FUNC10_CM128SIA3 = 6 155 } COP_CM128_4FUNCTIONS; 156 157 /* Enum declaration for iq10 function sub-opcodes. */ 158 typedef enum cop_cm128_3functions { 159 FUNC10_CM128RIA4 = 6, FUNC10_CM128SIA4 = 7 160 } COP_CM128_3FUNCTIONS; 161 162 /* Enum declaration for iq10 coprocessor sub-opcodes. */ 163 typedef enum cop2_functions { 164 FUNC10_PKRLI = 0, FUNC10_PKRLIU = 1, FUNC10_PKRLIH = 2, FUNC10_PKRLIC = 3 165 , FUNC10_RBIR = 1, FUNC10_RBI = 2, FUNC10_RBIL = 3, FUNC10_WBIC = 5 166 , FUNC10_WBI = 6, FUNC10_WBIU = 7 167 } COP2_FUNCTIONS; 168 169 /* Enum declaration for iq10 coprocessor cam sub-opcodes. */ 170 typedef enum cop3_cam_functions { 171 FUNC10_CAM36 = 16, FUNC10_CAM72 = 17, FUNC10_CAM144 = 18, FUNC10_CAM288 = 19 172 } COP3_CAM_FUNCTIONS; 173 174 /* Attributes. */ 175 176 /* Enum declaration for machine type selection. */ 177 typedef enum mach_attr { 178 MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX 179 } MACH_ATTR; 180 181 /* Enum declaration for instruction set selection. */ 182 typedef enum isa_attr { 183 ISA_IQ2000, ISA_MAX 184 } ISA_ATTR; 185 186 /* Number of architecture variants. */ 187 #define MAX_ISAS 1 188 #define MAX_MACHS ((int) MACH_MAX) 189 190 /* Ifield support. */ 191 192 /* Ifield attribute indices. */ 193 194 /* Enum declaration for cgen_ifld attrs. */ 195 typedef enum cgen_ifld_attr { 196 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 197 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 198 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 199 } CGEN_IFLD_ATTR; 200 201 /* Number of non-boolean elements in cgen_ifld_attr. */ 202 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 203 204 /* cgen_ifld attribute accessor macros. */ 205 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 206 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 207 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 208 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 209 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 210 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 211 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 212 213 /* Enum declaration for iq2000 ifield types. */ 214 typedef enum ifield_type { 215 IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS 216 , IQ2000_F_RT, IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP 217 , IQ2000_F_CP_OP_10, IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM 218 , IQ2000_F_RD_RS, IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG 219 , IQ2000_F_JTARGQ10, IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT 220 , IQ2000_F_INDEX, IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL 221 , IQ2000_F_EXCODE, IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19 222 , IQ2000_F_5, IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z 223 , IQ2000_F_CAM_Y, IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z 224 , IQ2000_F_CM_4Z, IQ2000_F_MAX 225 } IFIELD_TYPE; 226 227 #define MAX_IFLD ((int) IQ2000_F_MAX) 228 229 /* Hardware attribute indices. */ 230 231 /* Enum declaration for cgen_hw attrs. */ 232 typedef enum cgen_hw_attr { 233 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 234 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 235 } CGEN_HW_ATTR; 236 237 /* Number of non-boolean elements in cgen_hw_attr. */ 238 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 239 240 /* cgen_hw attribute accessor macros. */ 241 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 242 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 243 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 244 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 245 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 246 247 /* Enum declaration for iq2000 hardware types. */ 248 typedef enum cgen_hw_type { 249 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 250 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX 251 } CGEN_HW_TYPE; 252 253 #define MAX_HW ((int) HW_MAX) 254 255 /* Operand attribute indices. */ 256 257 /* Enum declaration for cgen_operand attrs. */ 258 typedef enum cgen_operand_attr { 259 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 260 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 261 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS 262 } CGEN_OPERAND_ATTR; 263 264 /* Number of non-boolean elements in cgen_operand_attr. */ 265 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 266 267 /* cgen_operand attribute accessor macros. */ 268 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 269 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 270 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 271 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 272 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 273 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 274 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 275 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 276 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 277 278 /* Enum declaration for iq2000 operand types. */ 279 typedef enum cgen_operand_type { 280 IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD 281 , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT 282 , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG 283 , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT 284 , IQ2000_OPERAND__INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y 285 , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z 286 , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM 287 , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10 288 , IQ2000_OPERAND_MAX 289 } CGEN_OPERAND_TYPE; 290 291 /* Number of operands types. */ 292 #define MAX_OPERANDS 32 293 294 /* Maximum number of operands referenced by any insn. */ 295 #define MAX_OPERAND_INSTANCES 8 296 297 /* Insn attribute indices. */ 298 299 /* Enum declaration for cgen_insn attrs. */ 300 typedef enum cgen_insn_attr { 301 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 302 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 303 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY 304 , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS 305 , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 306 , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS 307 } CGEN_INSN_ATTR; 308 309 /* Number of non-boolean elements in cgen_insn_attr. */ 310 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 311 312 /* cgen_insn attribute accessor macros. */ 313 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 314 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 315 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 316 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 317 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 318 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 319 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 320 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 321 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 322 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 323 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 324 #define CGEN_ATTR_CGEN_INSN_YIELD_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_YIELD_INSN)) != 0) 325 #define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_LOAD_DELAY)) != 0) 326 #define CGEN_ATTR_CGEN_INSN_EVEN_REG_NUM_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_EVEN_REG_NUM)) != 0) 327 #define CGEN_ATTR_CGEN_INSN_UNSUPPORTED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNSUPPORTED)) != 0) 328 #define CGEN_ATTR_CGEN_INSN_USES_RD_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_RD)) != 0) 329 #define CGEN_ATTR_CGEN_INSN_USES_RS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_RS)) != 0) 330 #define CGEN_ATTR_CGEN_INSN_USES_RT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_RT)) != 0) 331 #define CGEN_ATTR_CGEN_INSN_USES_R31_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_R31)) != 0) 332 333 /* cgen.h uses things we just defined. */ 334 #include "opcode/cgen.h" 335 336 extern const struct cgen_ifld iq2000_cgen_ifld_table[]; 337 338 /* Attributes. */ 339 extern const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[]; 340 extern const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[]; 341 extern const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[]; 342 extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[]; 343 344 /* Hardware decls. */ 345 346 extern CGEN_KEYWORD iq2000_cgen_opval_gr_names; 347 348 extern const CGEN_HW_ENTRY iq2000_cgen_hw_table[]; 349 350 351 352 #ifdef __cplusplus 353 } 354 #endif 355 356 #endif /* IQ2000_CPU_H */ 357