1 /* 2 PXA3xx Graphics Controller 3 4 (c) Copyright 2009 The world wide DirectFB Open Source Community (directfb.org) 5 (c) Copyright 2009 Raumfeld GmbH (raumfeld.com) 6 7 All rights reserved. 8 9 Written by Denis Oliver Kropp <dok@directfb.org>, 10 Sven Neumann <s.neumann@raumfeld.com> 11 12 This library is free software; you can redistribute it and/or 13 modify it under the terms of the GNU Lesser General Public 14 License as published by the Free Software Foundation; either 15 version 2 of the License, or (at your option) any later version. 16 17 This library is distributed in the hope that it will be useful, 18 but WITHOUT ANY WARRANTY; without even the implied warranty of 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 Lesser General Public License for more details. 21 22 You should have received a copy of the GNU Lesser General Public 23 License along with this library; if not, write to the 24 Free Software Foundation, Inc., 59 Temple Place - Suite 330, 25 Boston, MA 02111-1307, USA. 26 */ 27 28 #ifndef __PXA3XX__PXA3XX_REGS_H__ 29 #define __PXA3XX__PXA3XX_REGS_H__ 30 31 32 /****************************************************************************** 33 * Register access 34 */ 35 36 #define PXA3XX_LCD_BASE 0x44000000 37 #define PXA3XX_GFX_BASE 0x54000000 38 39 /****************************************************************************** 40 * LCD registers 41 */ 42 43 #define LCCR0 (PXA3XX_LCD_BASE + 0x0000) 44 #define LCCR1 (PXA3XX_LCD_BASE + 0x0004) 45 #define LCCR2 (PXA3XX_LCD_BASE + 0x0008) 46 #define LCCR3 (PXA3XX_LCD_BASE + 0x000C) 47 #define LCCR4 (PXA3XX_LCD_BASE + 0x0010) 48 #define LCCR5 (PXA3XX_LCD_BASE + 0x0014) 49 #define LCCR6 (PXA3XX_LCD_BASE + 0x0018) 50 51 #define FBR0 (PXA3XX_LCD_BASE + 0x0020) 52 #define FBR1 (PXA3XX_LCD_BASE + 0x0024) 53 #define FBR2 (PXA3XX_LCD_BASE + 0x0028) 54 #define FBR3 (PXA3XX_LCD_BASE + 0x002C) 55 #define FBR4 (PXA3XX_LCD_BASE + 0x0030) 56 #define LCSR1 (PXA3XX_LCD_BASE + 0x0034) 57 #define LCSR0 (PXA3XX_LCD_BASE + 0x0038) 58 #define LIIDR (PXA3XX_LCD_BASE + 0x003C) 59 #define TRGBR (PXA3XX_LCD_BASE + 0x0040) 60 #define TCR (PXA3XX_LCD_BASE + 0x0044) 61 62 #define OVL1C1 (PXA3XX_LCD_BASE + 0x0050) 63 #define OVL1C2 (PXA3XX_LCD_BASE + 0x0060) 64 #define OVL2C1 (PXA3XX_LCD_BASE + 0x0070) 65 #define OVL2C2 (PXA3XX_LCD_BASE + 0x0080) 66 67 #define CCR (PXA3XX_LCD_BASE + 0x0090) 68 69 #define CMDCR (PXA3XX_LCD_BASE + 0x0100) 70 #define PRSR (PXA3XX_LCD_BASE + 0x0104) 71 72 #define FBR5 (PXA3XX_LCD_BASE + 0x0110) 73 #define FBR6 (PXA3XX_LCD_BASE + 0x0114) 74 75 #define FDADR0 (PXA3XX_LCD_BASE + 0x0200) 76 #define FSADR0 (PXA3XX_LCD_BASE + 0x0204) 77 #define FIDR0 (PXA3XX_LCD_BASE + 0x0208) 78 #define LDCMD0 (PXA3XX_LCD_BASE + 0x020C) 79 #define FDADR1 (PXA3XX_LCD_BASE + 0x0210) 80 #define FSADR1 (PXA3XX_LCD_BASE + 0x0214) 81 #define FIDR1 (PXA3XX_LCD_BASE + 0x0218) 82 #define LDCMD1 (PXA3XX_LCD_BASE + 0x021C) 83 #define FDADR2 (PXA3XX_LCD_BASE + 0x0220) 84 #define FSADR2 (PXA3XX_LCD_BASE + 0x0224) 85 #define FIDR2 (PXA3XX_LCD_BASE + 0x0228) 86 #define LDCMD2 (PXA3XX_LCD_BASE + 0x022C) 87 #define FDADR3 (PXA3XX_LCD_BASE + 0x0230) 88 #define FSADR3 (PXA3XX_LCD_BASE + 0x0234) 89 #define FIDR3 (PXA3XX_LCD_BASE + 0x0238) 90 #define LDCMD3 (PXA3XX_LCD_BASE + 0x023C) 91 #define FDADR4 (PXA3XX_LCD_BASE + 0x0240) 92 #define FSADR4 (PXA3XX_LCD_BASE + 0x0244) 93 #define FIDR4 (PXA3XX_LCD_BASE + 0x0248) 94 #define LDCMD4 (PXA3XX_LCD_BASE + 0x024C) 95 #define FDADR5 (PXA3XX_LCD_BASE + 0x0250) 96 #define FSADR5 (PXA3XX_LCD_BASE + 0x0254) 97 #define FIDR5 (PXA3XX_LCD_BASE + 0x0258) 98 #define LDCMD5 (PXA3XX_LCD_BASE + 0x025C) 99 #define FDADR6 (PXA3XX_LCD_BASE + 0x0260) 100 #define FSADR6 (PXA3XX_LCD_BASE + 0x0264) 101 #define FIDR6 (PXA3XX_LCD_BASE + 0x0268) 102 #define LDCMD6 (PXA3XX_LCD_BASE + 0x026C) 103 104 105 /****************************************************************************** 106 * Graphics registers 107 */ 108 109 /** Miscelaneous control and Interrupt information 110 *******************************************************/ 111 #define GCCR (PXA3XX_GFX_BASE + 0x0000) 112 #define GCISCR (PXA3XX_GFX_BASE + 0x0004) 113 #define GCIECR (PXA3XX_GFX_BASE + 0x0008) 114 #define GCNOPID (PXA3XX_GFX_BASE + 0x000C) 115 #define GCALPHASET (PXA3XX_GFX_BASE + 0x0010) 116 #define GCTSET (PXA3XX_GFX_BASE + 0x0014) 117 118 /** Ring buffer information 119 *******************************************************/ 120 #define GCRBBR (PXA3XX_GFX_BASE + 0x0020) 121 #define GCRBLR (PXA3XX_GFX_BASE + 0x0024) 122 #define GCRBGR (PXA3XX_GFX_BASE + 0x0028) 123 #define GCRBTR (PXA3XX_GFX_BASE + 0x002C) 124 #define GCRBEXHR (PXA3XX_GFX_BASE + 0x0030) 125 126 /** Batch buffer information 127 *******************************************************/ 128 #define GCBBBR (PXA3XX_GFX_BASE + 0x0040) 129 #define GCBBHR (PXA3XX_GFX_BASE + 0x0044) 130 #define GCBBEXHR (PXA3XX_GFX_BASE + 0x0048) 131 132 /** Destination 0,1 and 2 information 133 *******************************************************/ 134 #define GCD0BR (PXA3XX_GFX_BASE + 0x0060) 135 #define GCD0STP (PXA3XX_GFX_BASE + 0x0064) 136 #define GCD0STR (PXA3XX_GFX_BASE + 0x0068) 137 #define GCD0PF (PXA3XX_GFX_BASE + 0x006C) 138 #define GCD1BR (PXA3XX_GFX_BASE + 0x0070) 139 #define GCD1STP (PXA3XX_GFX_BASE + 0x0074) 140 #define GCD1STR (PXA3XX_GFX_BASE + 0x0078) 141 #define GCD1PF (PXA3XX_GFX_BASE + 0x007C) 142 #define GCD2BR (PXA3XX_GFX_BASE + 0x0080) 143 #define GCD2STP (PXA3XX_GFX_BASE + 0x0084) 144 #define GCD2STR (PXA3XX_GFX_BASE + 0x0088) 145 #define GCD2PF (PXA3XX_GFX_BASE + 0x008C) 146 147 /** Source 0 and 1 information 148 *******************************************************/ 149 #define GCS0BR (PXA3XX_GFX_BASE + 0x00E0) 150 #define GCS0STP (PXA3XX_GFX_BASE + 0x00E4) 151 #define GCS0STR (PXA3XX_GFX_BASE + 0x00E8) 152 #define GCS0PF (PXA3XX_GFX_BASE + 0x00EC) 153 #define GCS1BR (PXA3XX_GFX_BASE + 0x00F0) 154 #define GCS1STP (PXA3XX_GFX_BASE + 0x00F4) 155 #define GCS1STR (PXA3XX_GFX_BASE + 0x00F8) 156 #define GCS1PF (PXA3XX_GFX_BASE + 0x00FC) 157 158 /** Pixel ALU scratch registers 159 *******************************************************/ 160 #define GCSC0WD0 (PXA3XX_GFX_BASE + 0x0160) 161 // ....and more 162 163 /** Abort Bad address storage registers 164 *******************************************************/ 165 #define GCCABADDR (PXA3XX_GFX_BASE + 0x01E0) 166 #define GCTABADDR (PXA3XX_GFX_BASE + 0x01E4) 167 #define GCMABADDR (PXA3XX_GFX_BASE + 0x01E8) 168 169 #endif 170 171 172