12006-05-26 Richard Sandiford <richard@codesourcery.com> 2 3 * m68k.h (mcf_mask): Define. 4 52006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> 6 7 * avr.h (AVR_ISA_PWMx): New. 8 92006-03-28 Nathan Sidwell <nathan@codesourcery.com> 10 11 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, 12 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, 13 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, 14 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, 15 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. 16 172006-03-10 Paul Brook <paul@codesourcery.com> 18 19 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. 20 212006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 22 23 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come 24 first. Correct mask of bb "B" opcode. 25 262006-02-27 H.J. Lu <hongjiu.lu@intel.com> 27 28 * i386.h (i386_optab): Support Intel Merom New Instructions. 29 302006-02-24 Paul Brook <paul@codesourcery.com> 31 32 * arm.h: Add V7 feature bits. 33 342006-02-23 H.J. Lu <hongjiu.lu@intel.com> 35 36 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. 37 382006-01-31 Paul Brook <paul@codesourcery.com> 39 Richard Earnshaw <rearnsha@arm.com> 40 41 * arm.h: Use ARM_CPU_FEATURE. 42 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. 43 (arm_feature_set): Change to a structure. 44 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, 45 ARM_FEATURE): New macros. 46 472005-12-07 Hans-Peter Nilsson <hp@axis.com> 48 49 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) 50 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. 51 (ADD_PC_INCR_OPCODE): Don't define. 52 532005-12-06 H.J. Lu <hongjiu.lu@intel.com> 54 55 PR gas/1874 56 * i386.h (i386_optab): Add 64bit support for monitor and mwait. 57 582005-11-14 David Ung <davidu@mips.com> 59 60 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore 61 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for 62 save/restore encoding of the args field. 63 642005-10-28 Dave Brolley <brolley@redhat.com> 65 66 Contribute the following changes: 67 2005-02-16 Dave Brolley <brolley@redhat.com> 68 69 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename 70 cgen_isa_mask_* to cgen_bitset_*. 71 * cgen.h: Likewise. 72 73 2003-10-21 Richard Sandiford <rsandifo@redhat.com> 74 75 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. 76 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". 77 (CGEN_CPU_TABLE): Make isas a ponter. 78 79 2003-09-29 Dave Brolley <brolley@redhat.com> 80 81 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. 82 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. 83 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. 84 85 2002-12-13 Dave Brolley <brolley@redhat.com> 86 87 * cgen.h (symcat.h): #include it. 88 (cgen-bitset.h): #include it. 89 (CGEN_ATTR_VALUE_TYPE): Now a union. 90 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. 91 (CGEN_ATTR_ENTRY): 'value' now unsigned. 92 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). 93 * cgen-bitset.h: New file. 94 952005-09-30 Catherine Moore <clm@cm00re.com> 96 97 * bfin.h: New file. 98 992005-10-24 Jan Beulich <jbeulich@novell.com> 100 101 * ia64.h (enum ia64_opnd): Move memory operand out of set of 102 indirect operands. 103 1042005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 105 106 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. 107 Add FLAG_STRICT to pa10 ftest opcode. 108 1092005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 110 111 * hppa.h (pa_opcodes): Remove lha entries. 112 1132005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 114 115 * hppa.h (FLAG_STRICT): Revise comment. 116 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants 117 before corresponding pa11 opcodes. Add strict pa10 register-immediate 118 entries for "fdc". 119 1202005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 121 122 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. 123 1242005-09-06 Chao-ying Fu <fu@mips.com> 125 126 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, 127 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New 128 define. 129 Document !, $, *, &, g, +t, +T operand formats for MT instructions. 130 (INSN_ASE_MASK): Update to include INSN_MT. 131 (INSN_MT): New define for MT ASE. 132 1332005-08-25 Chao-ying Fu <fu@mips.com> 134 135 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, 136 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, 137 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, 138 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, 139 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. 140 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP 141 instructions. 142 (INSN_DSP): New define for DSP ASE. 143 1442005-08-18 Alan Modra <amodra@bigpond.net.au> 145 146 * a29k.h: Delete. 147 1482005-08-15 Daniel Jacobowitz <dan@codesourcery.com> 149 150 * ppc.h (PPC_OPCODE_E300): Define. 151 1522005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> 153 154 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. 155 1562005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 157 158 PR gas/336 159 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb 160 and pitlb. 161 1622005-07-27 Jan Beulich <jbeulich@novell.com> 163 164 * i386.h (i386_optab): Add comment to movd. Use LongMem for all 165 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. 166 Add movq-s as 64-bit variants of movd-s. 167 1682005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 169 170 * hppa.h: Fix punctuation in comment. 171 172 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for 173 implicit space-register addressing. Set space-register bits on opcodes 174 using implicit space-register addressing. Add various missing pa20 175 long-immediate opcodes. Remove various opcodes using implicit 3-bit 176 space-register addressing. Use "fE" instead of "fe" in various 177 fstw opcodes. 178 1792005-07-18 Jan Beulich <jbeulich@novell.com> 180 181 * i386.h (i386_optab): Operands of aam and aad are unsigned. 182 1832007-07-15 H.J. Lu <hongjiu.lu@intel.com> 184 185 * i386.h (i386_optab): Support Intel VMX Instructions. 186 1872005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 188 189 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. 190 1912005-07-05 Jan Beulich <jbeulich@novell.com> 192 193 * i386.h (i386_optab): Add new insns. 194 1952005-07-01 Nick Clifton <nickc@redhat.com> 196 197 * sparc.h: Add typedefs to structure declarations. 198 1992005-06-20 H.J. Lu <hongjiu.lu@intel.com> 200 201 PR 1013 202 * i386.h (i386_optab): Update comments for 64bit addressing on 203 mov. Allow 64bit addressing for mov and movq. 204 2052005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 206 207 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, 208 respectively, in various floating-point load and store patterns. 209 2102005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 211 212 * hppa.h (FLAG_STRICT): Correct comment. 213 (pa_opcodes): Update load and store entries to allow both PA 1.X and 214 PA 2.0 mneumonics when equivalent. Entries with cache control 215 completers now require PA 1.1. Adjust whitespace. 216 2172005-05-19 Anton Blanchard <anton@samba.org> 218 219 * ppc.h (PPC_OPCODE_POWER5): Define. 220 2212005-05-10 Nick Clifton <nickc@redhat.com> 222 223 * Update the address and phone number of the FSF organization in 224 the GPL notices in the following files: 225 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, 226 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, 227 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, 228 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, 229 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, 230 tic54x.h, tic80.h, v850.h, vax.h 231 2322005-05-09 Jan Beulich <jbeulich@novell.com> 233 234 * i386.h (i386_optab): Add ht and hnt. 235 2362005-04-18 Mark Kettenis <kettenis@gnu.org> 237 238 * i386.h: Insert hyphens into selected VIA PadLock extensions. 239 Add xcrypt-ctr. Provide aliases without hyphens. 240 2412005-04-13 H.J. Lu <hongjiu.lu@intel.com> 242 243 Moved from ../ChangeLog 244 245 2005-04-12 Paul Brook <paul@codesourcery.com> 246 * m88k.h: Rename psr macros to avoid conflicts. 247 248 2005-03-12 Zack Weinberg <zack@codesourcery.com> 249 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. 250 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, 251 and ARM_ARCH_V6ZKT2. 252 253 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> 254 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. 255 Remove redundant instruction types. 256 (struct argument): X_op - new field. 257 (struct cst4_entry): Remove. 258 (no_op_insn): Declare. 259 260 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> 261 * crx.h (enum argtype): Rename types, remove unused types. 262 263 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> 264 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. 265 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. 266 (enum operand_type): Rearrange operands, edit comments. 267 replace us<N> with ui<N> for unsigned immediate. 268 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped 269 displacements (respectively). 270 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. 271 (instruction type): Add NO_TYPE_INS. 272 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. 273 (operand_entry): New field - 'flags'. 274 (operand flags): New. 275 276 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> 277 * crx.h (operand_type): Remove redundant types i3, i4, 278 i5, i8, i12. 279 Add new unsigned immediate types us3, us4, us5, us16. 280 2812005-04-12 Mark Kettenis <kettenis@gnu.org> 282 283 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and 284 adjust them accordingly. 285 2862005-04-01 Jan Beulich <jbeulich@novell.com> 287 288 * i386.h (i386_optab): Add rdtscp. 289 2902005-03-29 H.J. Lu <hongjiu.lu@intel.com> 291 292 * i386.h (i386_optab): Don't allow the `l' suffix for moving 293 between memory and segment register. Allow movq for moving between 294 general-purpose register and segment register. 295 2962005-02-09 Jan Beulich <jbeulich@novell.com> 297 298 PR gas/707 299 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and 300 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and 301 fnstsw. 302 3032006-02-07 Nathan Sidwell <nathan@codesourcery.com> 304 305 * m68k.h (m68008, m68ec030, m68882): Remove. 306 (m68k_mask): New. 307 (cpu_m68k, cpu_cf): New. 308 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, 309 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. 310 3112005-01-25 Alexandre Oliva <aoliva@redhat.com> 312 313 2004-11-10 Alexandre Oliva <aoliva@redhat.com> 314 * cgen.h (enum cgen_parse_operand_type): Add 315 CGEN_PARSE_OPERAND_SYMBOLIC. 316 3172005-01-21 Fred Fish <fnf@specifixinc.com> 318 319 * mips.h: Change INSN_ALIAS to INSN2_ALIAS. 320 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. 321 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. 322 3232005-01-19 Fred Fish <fnf@specifixinc.com> 324 325 * mips.h (struct mips_opcode): Add new pinfo2 member. 326 (INSN_ALIAS): New define for opcode table entries that are 327 specific instances of another entry, such as 'move' for an 'or' 328 with a zero operand. 329 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. 330 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. 331 3322004-12-09 Ian Lance Taylor <ian@wasabisystems.com> 333 334 * mips.h (CPU_RM9000): Define. 335 (OPCODE_IS_MEMBER): Handle CPU_RM9000. 336 3372004-11-25 Jan Beulich <jbeulich@novell.com> 338 339 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves 340 to/from test registers are illegal in 64-bit mode. Add missing 341 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix 342 (previously one had to explicitly encode a rex64 prefix). Re-enable 343 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings 344 support it there. Add cmpxchg16b as per Intel's 64-bit documentation. 345 3462004-11-23 Jan Beulich <jbeulich@novell.com> 347 348 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are 349 available only with SSE2. Change the MMX additions introduced by SSE 350 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A 351 instructions by their now designated identifier (since combining i686 352 and 3DNow! does not really imply 3DNow!A). 353 3542004-11-19 Alan Modra <amodra@bigpond.net.au> 355 356 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, 357 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. 358 3592004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> 360 Vineet Sharma <vineets@noida.hcltech.com> 361 362 * maxq.h: New file: Disassembly information for the maxq port. 363 3642004-11-05 H.J. Lu <hongjiu.lu@intel.com> 365 366 * i386.h (i386_optab): Put back "movzb". 367 3682004-11-04 Hans-Peter Nilsson <hp@axis.com> 369 370 * cris.h (enum cris_insn_version_usage): Tweak formatting and 371 comments. Remove member cris_ver_sim. Add members 372 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, 373 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. 374 (struct cris_support_reg, struct cris_cond15): New types. 375 (cris_conds15): Declare. 376 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) 377 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) 378 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. 379 (NOP_Z_BITS): Define in terms of NOP_OPCODE. 380 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and 381 SIZE_FIELD_UNSIGNED. 382 3832004-11-04 Jan Beulich <jbeulich@novell.com> 384 385 * i386.h (sldx_Suf): Remove. 386 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. 387 (q_FP): Define, implying no REX64. 388 (x_FP, sl_FP): Imply FloatMF. 389 (i386_optab): Split reg and mem forms of moving from segment registers 390 so that the memory forms can ignore the 16-/32-bit operand size 391 distinction. Adjust a few others for Intel mode. Remove *FP uses from 392 all non-floating-point instructions. Unite 32- and 64-bit forms of 393 movsx, movzx, and movd. Adjust floating point operations for the above 394 changes to the *FP macros. Add DefaultSize to floating point control 395 insns operating on larger memory ranges. Remove left over comments 396 hinting at certain insns being Intel-syntax ones where the ones 397 actually meant are already gone. 398 3992004-10-07 Tomer Levi <Tomer.Levi@nsc.com> 400 401 * crx.h: Add COPS_REG_INS - Coprocessor Special register 402 instruction type. 403 4042004-09-30 Paul Brook <paul@codesourcery.com> 405 406 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. 407 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. 408 4092004-09-11 Theodore A. Roth <troth@openavr.org> 410 411 * avr.h: Add support for 412 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. 413 4142004-09-09 Segher Boessenkool <segher@kernel.crashing.org> 415 416 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. 417 4182004-08-24 Dmitry Diky <diwil@spec.ru> 419 420 * msp430.h (msp430_opc): Add new instructions. 421 (msp430_rcodes): Declare new instructions. 422 (msp430_hcodes): Likewise.. 423 4242004-08-13 Nick Clifton <nickc@redhat.com> 425 426 PR/301 427 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX 428 processors. 429 4302004-08-30 Michal Ludvig <mludvig@suse.cz> 431 432 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. 433 4342004-07-22 H.J. Lu <hongjiu.lu@intel.com> 435 436 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. 437 4382004-07-21 Jan Beulich <jbeulich@novell.com> 439 440 * i386.h: Adjust instruction descriptions to better match the 441 specification. 442 4432004-07-16 Richard Earnshaw <rearnsha@arm.com> 444 445 * arm.h: Remove all old content. Replace with architecture defines 446 from gas/config/tc-arm.c. 447 4482004-07-09 Andreas Schwab <schwab@suse.de> 449 450 * m68k.h: Fix comment. 451 4522004-07-07 Tomer Levi <Tomer.Levi@nsc.com> 453 454 * crx.h: New file. 455 4562004-06-24 Alan Modra <amodra@bigpond.net.au> 457 458 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. 459 4602004-05-24 Peter Barada <peter@the-baradas.com> 461 462 * m68k.h: Add 'size' to m68k_opcode. 463 4642004-05-05 Peter Barada <peter@the-baradas.com> 465 466 * m68k.h: Switch from ColdFire chip name to core variant. 467 4682004-04-22 Peter Barada <peter@the-baradas.com> 469 470 * m68k.h: Add mcfmac/mcfemac definitions. Update operand 471 descriptions for new EMAC cases. 472 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly 473 handle Motorola MAC syntax. 474 Allow disassembly of ColdFire V4e object files. 475 4762004-03-16 Alan Modra <amodra@bigpond.net.au> 477 478 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. 479 4802004-03-12 Jakub Jelinek <jakub@redhat.com> 481 482 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. 483 4842004-03-12 Michal Ludvig <mludvig@suse.cz> 485 486 * i386.h (i386_optab): Added xstore as an alias for xstorerng. 487 4882004-03-12 Michal Ludvig <mludvig@suse.cz> 489 490 * i386.h (i386_optab): Added xstore/xcrypt insns. 491 4922004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> 493 494 * h8300.h (32bit ldc/stc): Add relaxing support. 495 4962004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> 497 498 * h8300.h (BITOP): Pass MEMRELAX flag. 499 5002004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> 501 502 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 503 except for the H8S. 504 505For older changes see ChangeLog-9103 506 507Local Variables: 508mode: change-log 509left-margin: 8 510fill-column: 74 511version-control: never 512End: 513