1This is as.info, produced by makeinfo version 6.7 from as.texi. 2 3This file documents the GNU Assembler "as". 4 5 Copyright (C) 1991-2021 Free Software Foundation, Inc. 6 7 Permission is granted to copy, distribute and/or modify this document 8under the terms of the GNU Free Documentation License, Version 1.3 or 9any later version published by the Free Software Foundation; with no 10Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 11Texts. A copy of the license is included in the section entitled "GNU 12Free Documentation License". 13 14INFO-DIR-SECTION Software development 15START-INFO-DIR-ENTRY 16* As: (as). The GNU assembler. 17* Gas: (as). The GNU assembler. 18END-INFO-DIR-ENTRY 19 20 21File: as.info, Node: Top, Next: Overview, Up: (dir) 22 23Using as 24******** 25 26This file is a user guide to the GNU assembler 'as' (GNU Binutils) 27version 2.37. 28 29 This document is distributed under the terms of the GNU Free 30Documentation License. A copy of the license is included in the section 31entitled "GNU Free Documentation License". 32 33* Menu: 34 35* Overview:: Overview 36* Invoking:: Command-Line Options 37* Syntax:: Syntax 38* Sections:: Sections and Relocation 39* Symbols:: Symbols 40* Expressions:: Expressions 41* Pseudo Ops:: Assembler Directives 42* Object Attributes:: Object Attributes 43* Machine Dependencies:: Machine Dependent Features 44* Reporting Bugs:: Reporting Bugs 45* Acknowledgements:: Who Did What 46* GNU Free Documentation License:: GNU Free Documentation License 47* AS Index:: AS Index 48 49 50File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 51 521 Overview 53********** 54 55Here is a brief summary of how to invoke 'as'. For details, see *note 56Command-Line Options: Invoking. 57 58 as [-a[cdghlns][=FILE]] [-alternate] [-D] 59 [-compress-debug-sections] [-nocompress-debug-sections] 60 [-debug-prefix-map OLD=NEW] 61 [-defsym SYM=VAL] [-f] [-g] [-gstabs] 62 [-gstabs+] [-gdwarf-<N>] [-gdwarf-sections] 63 [-gdwarf-cie-version=VERSION] 64 [-help] [-I DIR] [-J] 65 [-K] [-L] [-listing-lhs-width=NUM] 66 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM] 67 [-listing-cont-lines=NUM] [-keep-locals] 68 [-no-pad-sections] 69 [-o OBJFILE] [-R] 70 [-statistics] 71 [-v] [-version] [-version] 72 [-W] [-warn] [-fatal-warnings] [-w] [-x] 73 [-Z] [@FILE] 74 [-sectname-subst] [-size-check=[error|warning]] 75 [-elf-stt-common=[no|yes]] 76 [-generate-missing-build-notes=[no|yes]] 77 [-target-help] [TARGET-OPTIONS] 78 [-|FILES ...] 79 80 _Target AArch64 options:_ 81 [-EB|-EL] 82 [-mabi=ABI] 83 84 _Target Alpha options:_ 85 [-mCPU] 86 [-mdebug | -no-mdebug] 87 [-replace | -noreplace] 88 [-relax] [-g] [-GSIZE] 89 [-F] [-32addr] 90 91 _Target ARC options:_ 92 [-mcpu=CPU] 93 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS] 94 [-mcode-density] 95 [-mrelax] 96 [-EB|-EL] 97 98 _Target ARM options:_ 99 [-mcpu=PROCESSOR[+EXTENSION...]] 100 [-march=ARCHITECTURE[+EXTENSION...]] 101 [-mfpu=FLOATING-POINT-FORMAT] 102 [-mfloat-abi=ABI] 103 [-meabi=VER] 104 [-mthumb] 105 [-EB|-EL] 106 [-mapcs-32|-mapcs-26|-mapcs-float| 107 -mapcs-reentrant] 108 [-mthumb-interwork] [-k] 109 110 _Target Blackfin options:_ 111 [-mcpu=PROCESSOR[-SIREVISION]] 112 [-mfdpic] 113 [-mno-fdpic] 114 [-mnopic] 115 116 _Target BPF options:_ 117 [-EL] [-EB] 118 119 _Target CRIS options:_ 120 [-underscore | -no-underscore] 121 [-pic] [-N] 122 [-emulation=criself | -emulation=crisaout] 123 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32] 124 125 _Target C-SKY options:_ 126 [-march=ARCH] [-mcpu=CPU] 127 [-EL] [-mlittle-endian] [-EB] [-mbig-endian] 128 [-fpic] [-pic] 129 [-mljump] [-mno-ljump] 130 [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr] 131 [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr] 132 [-mnolrw ] [-mno-lrw] 133 [-melrw] [-mno-elrw] 134 [-mlaf ] [-mliterals-after-func] 135 [-mno-laf] [-mno-literals-after-func] 136 [-mlabr] [-mliterals-after-br] 137 [-mno-labr] [-mnoliterals-after-br] 138 [-mistack] [-mno-istack] 139 [-mhard-float] [-mmp] [-mcp] [-mcache] 140 [-msecurity] [-mtrust] 141 [-mdsp] [-medsp] [-mvdsp] 142 143 _Target D10V options:_ 144 [-O] 145 146 _Target D30V options:_ 147 [-O|-n|-N] 148 149 _Target EPIPHANY options:_ 150 [-mepiphany|-mepiphany16] 151 152 _Target H8/300 options:_ 153 [-h-tick-hex] 154 155 _Target i386 options:_ 156 [-32|-x32|-64] [-n] 157 [-march=CPU[+EXTENSION...]] [-mtune=CPU] 158 159 _Target IA-64 options:_ 160 [-mconstant-gp|-mauto-pic] 161 [-milp32|-milp64|-mlp64|-mp64] 162 [-mle|mbe] 163 [-mtune=itanium1|-mtune=itanium2] 164 [-munwind-check=warning|-munwind-check=error] 165 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] 166 [-x|-xexplicit] [-xauto] [-xdebug] 167 168 _Target IP2K options:_ 169 [-mip2022|-mip2022ext] 170 171 _Target M32C options:_ 172 [-m32c|-m16c] [-relax] [-h-tick-hex] 173 174 _Target M32R options:_ 175 [-m32rx|-[no-]warn-explicit-parallel-conflicts| 176 -W[n]p] 177 178 _Target M680X0 options:_ 179 [-l] [-m68000|-m68010|-m68020|...] 180 181 _Target M68HC11 options:_ 182 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg] 183 [-mshort|-mlong] 184 [-mshort-double|-mlong-double] 185 [-force-long-branches] [-short-branches] 186 [-strict-direct-mode] [-print-insn-syntax] 187 [-print-opcodes] [-generate-example] 188 189 _Target MCORE options:_ 190 [-jsri2bsr] [-sifilter] [-relax] 191 [-mcpu=[210|340]] 192 193 _Target Meta options:_ 194 [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU] 195 _Target MICROBLAZE options:_ 196 197 _Target MIPS options:_ 198 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] 199 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] 200 [-non_shared] [-xgot [-mvxworks-pic] 201 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] 202 [-mfp64] [-mgp64] [-mfpxx] 203 [-modd-spreg] [-mno-odd-spreg] 204 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] 205 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] 206 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2] 207 [-mips64r3] [-mips64r5] [-mips64r6] 208 [-construct-floats] [-no-construct-floats] 209 [-mignore-branch-isa] [-mno-ignore-branch-isa] 210 [-mnan=ENCODING] 211 [-trap] [-no-break] [-break] [-no-trap] 212 [-mips16] [-no-mips16] 213 [-mmips16e2] [-mno-mips16e2] 214 [-mmicromips] [-mno-micromips] 215 [-msmartmips] [-mno-smartmips] 216 [-mips3d] [-no-mips3d] 217 [-mdmx] [-no-mdmx] 218 [-mdsp] [-mno-dsp] 219 [-mdspr2] [-mno-dspr2] 220 [-mdspr3] [-mno-dspr3] 221 [-mmsa] [-mno-msa] 222 [-mxpa] [-mno-xpa] 223 [-mmt] [-mno-mt] 224 [-mmcu] [-mno-mcu] 225 [-mcrc] [-mno-crc] 226 [-mginv] [-mno-ginv] 227 [-mloongson-mmi] [-mno-loongson-mmi] 228 [-mloongson-cam] [-mno-loongson-cam] 229 [-mloongson-ext] [-mno-loongson-ext] 230 [-mloongson-ext2] [-mno-loongson-ext2] 231 [-minsn32] [-mno-insn32] 232 [-mfix7000] [-mno-fix7000] 233 [-mfix-rm7000] [-mno-fix-rm7000] 234 [-mfix-vr4120] [-mno-fix-vr4120] 235 [-mfix-vr4130] [-mno-fix-vr4130] 236 [-mfix-r5900] [-mno-fix-r5900] 237 [-mdebug] [-no-mdebug] 238 [-mpdr] [-mno-pdr] 239 240 _Target MMIX options:_ 241 [-fixed-special-register-names] [-globalize-symbols] 242 [-gnu-syntax] [-relax] [-no-predefined-symbols] 243 [-no-expand] [-no-merge-gregs] [-x] 244 [-linker-allocated-gregs] 245 246 _Target Nios II options:_ 247 [-relax-all] [-relax-section] [-no-relax] 248 [-EB] [-EL] 249 250 _Target NDS32 options:_ 251 [-EL] [-EB] [-O] [-Os] [-mcpu=CPU] 252 [-misa=ISA] [-mabi=ABI] [-mall-ext] 253 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext] 254 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div] 255 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext] 256 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs] 257 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax] 258 [-mb2bb] 259 260 _Target PDP11 options:_ 261 [-mpic|-mno-pic] [-mall] [-mno-extensions] 262 [-mEXTENSION|-mno-EXTENSION] 263 [-mCPU] [-mMACHINE] 264 265 _Target picoJava options:_ 266 [-mb|-me] 267 268 _Target PowerPC options:_ 269 [-a32|-a64] 270 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| 271 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko| 272 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500| 273 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x| 274 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2| 275 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom] 276 [-many] [-maltivec|-mvsx|-mhtm|-mvle] 277 [-mregnames|-mno-regnames] 278 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] 279 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] 280 [-msolaris|-mno-solaris] 281 [-nops=COUNT] 282 283 _Target PRU options:_ 284 [-link-relax] 285 [-mnolink-relax] 286 [-mno-warn-regname-label] 287 288 _Target RISC-V options:_ 289 [-fpic|-fPIC|-fno-pic] 290 [-march=ISA] 291 [-mabi=ABI] 292 [-mlittle-endian|-mbig-endian] 293 294 _Target RL78 options:_ 295 [-mg10] 296 [-m32bit-doubles|-m64bit-doubles] 297 298 _Target RX options:_ 299 [-mlittle-endian|-mbig-endian] 300 [-m32bit-doubles|-m64bit-doubles] 301 [-muse-conventional-section-names] 302 [-msmall-data-limit] 303 [-mpid] 304 [-mrelax] 305 [-mint-register=NUMBER] 306 [-mgcc-abi|-mrx-abi] 307 308 _Target s390 options:_ 309 [-m31|-m64] [-mesa|-mzarch] [-march=CPU] 310 [-mregnames|-mno-regnames] 311 [-mwarn-areg-zero] 312 313 _Target SCORE options:_ 314 [-EB][-EL][-FIXDD][-NWARN] 315 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] 316 [-march=score7][-march=score3] 317 [-USE_R1][-KPIC][-O0][-G NUM][-V] 318 319 _Target SPARC options:_ 320 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite 321 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd 322 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c 323 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis 324 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3 325 -Asparcvisr|-Asparc5] 326 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc 327 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9 328 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e 329 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis 330 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima 331 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5 332 -bump] 333 [-32|-64] 334 [-enforce-aligned-data][-dcti-couples-detect] 335 336 _Target TIC54X options:_ 337 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] 338 [-merrors-to-file <FILENAME>|-me <FILENAME>] 339 340 _Target TIC6X options:_ 341 [-march=ARCH] [-mbig-endian|-mlittle-endian] 342 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] 343 [-mpic|-mno-pic] 344 345 _Target TILE-Gx options:_ 346 [-m32|-m64][-EB][-EL] 347 348 _Target Visium options:_ 349 [-mtune=ARCH] 350 351 _Target Xtensa options:_ 352 [-[no-]text-section-literals] [-[no-]auto-litpools] 353 [-[no-]absolute-literals] 354 [-[no-]target-align] [-[no-]longcalls] 355 [-[no-]transform] 356 [-rename-section OLDNAME=NEWNAME] 357 [-[no-]trampolines] 358 [-abi-windowed|-abi-call0] 359 360 _Target Z80 options:_ 361 [-march=CPU[-EXT][+EXT]] 362 [-local-prefix=PREFIX] 363 [-colonless] 364 [-sdcc] 365 [-fp-s=FORMAT] 366 [-fp-d=FORMAT] 367 368 369 370'@FILE' 371 Read command-line options from FILE. The options read are inserted 372 in place of the original @FILE option. If FILE does not exist, or 373 cannot be read, then the option will be treated literally, and not 374 removed. 375 376 Options in FILE are separated by whitespace. A whitespace 377 character may be included in an option by surrounding the entire 378 option in either single or double quotes. Any character (including 379 a backslash) may be included by prefixing the character to be 380 included with a backslash. The FILE may itself contain additional 381 @FILE options; any such options will be processed recursively. 382 383'-a[cdghlmns]' 384 Turn on listings, in any of a variety of ways: 385 386 '-ac' 387 omit false conditionals 388 389 '-ad' 390 omit debugging directives 391 392 '-ag' 393 include general information, like as version and options 394 passed 395 396 '-ah' 397 include high-level source 398 399 '-al' 400 include assembly 401 402 '-am' 403 include macro expansions 404 405 '-an' 406 omit forms processing 407 408 '-as' 409 include symbols 410 411 '=file' 412 set the name of the listing file 413 414 You may combine these options; for example, use '-aln' for assembly 415 listing without forms processing. The '=file' option, if used, 416 must be the last one. By itself, '-a' defaults to '-ahls'. 417 418'--alternate' 419 Begin in alternate macro mode. *Note '.altmacro': Altmacro. 420 421'--compress-debug-sections' 422 Compress DWARF debug sections using zlib with SHF_COMPRESSED from 423 the ELF ABI. The resulting object file may not be compatible with 424 older linkers and object file utilities. Note if compression would 425 make a given section _larger_ then it is not compressed. 426 427'--compress-debug-sections=none' 428'--compress-debug-sections=zlib' 429'--compress-debug-sections=zlib-gnu' 430'--compress-debug-sections=zlib-gabi' 431 These options control how DWARF debug sections are compressed. 432 '--compress-debug-sections=none' is equivalent to 433 '--nocompress-debug-sections'. '--compress-debug-sections=zlib' 434 and '--compress-debug-sections=zlib-gabi' are equivalent to 435 '--compress-debug-sections'. '--compress-debug-sections=zlib-gnu' 436 compresses DWARF debug sections using zlib. The debug sections are 437 renamed to begin with '.zdebug'. Note if compression would make a 438 given section _larger_ then it is not compressed nor renamed. 439 440'--nocompress-debug-sections' 441 Do not compress DWARF debug sections. This is usually the default 442 for all targets except the x86/x86_64, but a configure time option 443 can be used to override this. 444 445'-D' 446 Ignored. This option is accepted for script compatibility with 447 calls to other assemblers. 448 449'--debug-prefix-map OLD=NEW' 450 When assembling files in directory 'OLD', record debugging 451 information describing them as in 'NEW' instead. 452 453'--defsym SYM=VALUE' 454 Define the symbol SYM to be VALUE before assembling the input file. 455 VALUE must be an integer constant. As in C, a leading '0x' 456 indicates a hexadecimal value, and a leading '0' indicates an octal 457 value. The value of the symbol can be overridden inside a source 458 file via the use of a '.set' pseudo-op. 459 460'-f' 461 "fast"--skip whitespace and comment preprocessing (assume source is 462 compiler output). 463 464'-g' 465'--gen-debug' 466 Generate debugging information for each assembler source line using 467 whichever debug format is preferred by the target. This currently 468 means either STABS, ECOFF or DWARF2. When the debug format is 469 DWARF then a '.debug_info' and '.debug_line' section is only 470 emitted when the assembly file doesn't generate one itself. 471 472'--gstabs' 473 Generate stabs debugging information for each assembler line. This 474 may help debugging assembler code, if the debugger can handle it. 475 476'--gstabs+' 477 Generate stabs debugging information for each assembler line, with 478 GNU extensions that probably only gdb can handle, and that could 479 make other debuggers crash or refuse to read your program. This 480 may help debugging assembler code. Currently the only GNU 481 extension is the location of the current working directory at 482 assembling time. 483 484'--gdwarf-2' 485 Generate DWARF2 debugging information for each assembler line. 486 This may help debugging assembler code, if the debugger can handle 487 it. Note--this option is only supported by some targets, not all 488 of them. 489 490'--gdwarf-3' 491 This option is the same as the '--gdwarf-2' option, except that it 492 allows for the possibility of the generation of extra debug 493 information as per version 3 of the DWARF specification. Note - 494 enabling this option does not guarantee the generation of any extra 495 information, the choice to do so is on a per target basis. 496 497'--gdwarf-4' 498 This option is the same as the '--gdwarf-2' option, except that it 499 allows for the possibility of the generation of extra debug 500 information as per version 4 of the DWARF specification. Note - 501 enabling this option does not guarantee the generation of any extra 502 information, the choice to do so is on a per target basis. 503 504'--gdwarf-5' 505 This option is the same as the '--gdwarf-2' option, except that it 506 allows for the possibility of the generation of extra debug 507 information as per version 5 of the DWARF specification. Note - 508 enabling this option does not guarantee the generation of any extra 509 information, the choice to do so is on a per target basis. 510 511'--gdwarf-sections' 512 Instead of creating a .debug_line section, create a series of 513 .debug_line.FOO sections where FOO is the name of the corresponding 514 code section. For example a code section called .TEXT.FUNC will 515 have its dwarf line number information placed into a section called 516 .DEBUG_LINE.TEXT.FUNC. If the code section is just called .TEXT 517 then debug line section will still be called just .DEBUG_LINE 518 without any suffix. 519 520'--gdwarf-cie-version=VERSION' 521 Control which version of DWARF Common Information Entries (CIEs) 522 are produced. When this flag is not specificed the default is 523 version 1, though some targets can modify this default. Other 524 possible values for VERSION are 3 or 4. 525 526'--size-check=error' 527'--size-check=warning' 528 Issue an error or warning for invalid ELF .size directive. 529 530'--elf-stt-common=no' 531'--elf-stt-common=yes' 532 These options control whether the ELF assembler should generate 533 common symbols with the 'STT_COMMON' type. The default can be 534 controlled by a configure option '--enable-elf-stt-common'. 535 536'--generate-missing-build-notes=yes' 537'--generate-missing-build-notes=no' 538 These options control whether the ELF assembler should generate GNU 539 Build attribute notes if none are present in the input sources. 540 The default can be controlled by the 541 '--enable-generate-build-notes' configure option. 542 543'--help' 544 Print a summary of the command-line options and exit. 545 546'--target-help' 547 Print a summary of all target specific options and exit. 548 549'-I DIR' 550 Add directory DIR to the search list for '.include' directives. 551 552'-J' 553 Don't warn about signed overflow. 554 555'-K' 556 Issue warnings when difference tables altered for long 557 displacements. 558 559'-L' 560'--keep-locals' 561 Keep (in the symbol table) local symbols. These symbols start with 562 system-specific local label prefixes, typically '.L' for ELF 563 systems or 'L' for traditional a.out systems. *Note Symbol 564 Names::. 565 566'--listing-lhs-width=NUMBER' 567 Set the maximum width, in words, of the output data column for an 568 assembler listing to NUMBER. 569 570'--listing-lhs-width2=NUMBER' 571 Set the maximum width, in words, of the output data column for 572 continuation lines in an assembler listing to NUMBER. 573 574'--listing-rhs-width=NUMBER' 575 Set the maximum width of an input source line, as displayed in a 576 listing, to NUMBER bytes. 577 578'--listing-cont-lines=NUMBER' 579 Set the maximum number of lines printed in a listing for a single 580 line of input to NUMBER + 1. 581 582'--no-pad-sections' 583 Stop the assembler for padding the ends of output sections to the 584 alignment of that section. The default is to pad the sections, but 585 this can waste space which might be needed on targets which have 586 tight memory constraints. 587 588'-o OBJFILE' 589 Name the object-file output from 'as' OBJFILE. 590 591'-R' 592 Fold the data section into the text section. 593 594'--sectname-subst' 595 Honor substitution sequences in section names. *Note '.section 596 NAME': Section Name Substitutions. 597 598'--statistics' 599 Print the maximum space (in bytes) and total time (in seconds) used 600 by assembly. 601 602'--strip-local-absolute' 603 Remove local absolute symbols from the outgoing symbol table. 604 605'-v' 606'-version' 607 Print the 'as' version. 608 609'--version' 610 Print the 'as' version and exit. 611 612'-W' 613'--no-warn' 614 Suppress warning messages. 615 616'--fatal-warnings' 617 Treat warnings as errors. 618 619'--warn' 620 Don't suppress warning messages or treat them as errors. 621 622'-w' 623 Ignored. 624 625'-x' 626 Ignored. 627 628'-Z' 629 Generate an object file even after errors. 630 631'-- | FILES ...' 632 Standard input, or source files to assemble. 633 634 *Note AArch64 Options::, for the options available when as is 635configured for the 64-bit mode of the ARM Architecture (AArch64). 636 637 *Note Alpha Options::, for the options available when as is 638configured for an Alpha processor. 639 640 The following options are available when as is configured for an ARC 641processor. 642 643'-mcpu=CPU' 644 This option selects the core processor variant. 645'-EB | -EL' 646 Select either big-endian (-EB) or little-endian (-EL) output. 647'-mcode-density' 648 Enable Code Density extension instructions. 649 650 The following options are available when as is configured for the ARM 651processor family. 652 653'-mcpu=PROCESSOR[+EXTENSION...]' 654 Specify which ARM processor variant is the target. 655'-march=ARCHITECTURE[+EXTENSION...]' 656 Specify which ARM architecture variant is used by the target. 657'-mfpu=FLOATING-POINT-FORMAT' 658 Select which Floating Point architecture is the target. 659'-mfloat-abi=ABI' 660 Select which floating point ABI is in use. 661'-mthumb' 662 Enable Thumb only instruction decoding. 663'-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' 664 Select which procedure calling convention is in use. 665'-EB | -EL' 666 Select either big-endian (-EB) or little-endian (-EL) output. 667'-mthumb-interwork' 668 Specify that the code has been generated with interworking between 669 Thumb and ARM code in mind. 670'-mccs' 671 Turns on CodeComposer Studio assembly syntax compatibility mode. 672'-k' 673 Specify that PIC code has been generated. 674 675 *Note Blackfin Options::, for the options available when as is 676configured for the Blackfin processor family. 677 678 *Note BPF Options::, for the options available when as is configured 679for the Linux kernel BPF processor family. 680 681 See the info pages for documentation of the CRIS-specific options. 682 683 *Note C-SKY Options::, for the options available when as is 684configured for the C-SKY processor family. 685 686 The following options are available when as is configured for a D10V 687processor. 688'-O' 689 Optimize output by parallelizing instructions. 690 691 The following options are available when as is configured for a D30V 692processor. 693'-O' 694 Optimize output by parallelizing instructions. 695 696'-n' 697 Warn when nops are generated. 698 699'-N' 700 Warn when a nop after a 32-bit multiply instruction is generated. 701 702 The following options are available when as is configured for the 703Adapteva EPIPHANY series. 704 705 *Note Epiphany Options::, for the options available when as is 706configured for an Epiphany processor. 707 708 *Note i386-Options::, for the options available when as is configured 709for an i386 processor. 710 711 The following options are available when as is configured for the 712Ubicom IP2K series. 713 714'-mip2022ext' 715 Specifies that the extended IP2022 instructions are allowed. 716 717'-mip2022' 718 Restores the default behaviour, which restricts the permitted 719 instructions to just the basic IP2022 ones. 720 721 The following options are available when as is configured for the 722Renesas M32C and M16C processors. 723 724'-m32c' 725 Assemble M32C instructions. 726 727'-m16c' 728 Assemble M16C instructions (the default). 729 730'-relax' 731 Enable support for link-time relaxations. 732 733'-h-tick-hex' 734 Support H'00 style hex constants in addition to 0x00 style. 735 736 The following options are available when as is configured for the 737Renesas M32R (formerly Mitsubishi M32R) series. 738 739'--m32rx' 740 Specify which processor in the M32R family is the target. The 741 default is normally the M32R, but this option changes it to the 742 M32RX. 743 744'--warn-explicit-parallel-conflicts or --Wp' 745 Produce warning messages when questionable parallel constructs are 746 encountered. 747 748'--no-warn-explicit-parallel-conflicts or --Wnp' 749 Do not produce warning messages when questionable parallel 750 constructs are encountered. 751 752 The following options are available when as is configured for the 753Motorola 68000 series. 754 755'-l' 756 Shorten references to undefined symbols, to one word instead of 757 two. 758 759'-m68000 | -m68008 | -m68010 | -m68020 | -m68030' 760'| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' 761'| -m68333 | -m68340 | -mcpu32 | -m5200' 762 Specify what processor in the 68000 family is the target. The 763 default is normally the 68020, but this can be changed at 764 configuration time. 765 766'-m68881 | -m68882 | -mno-68881 | -mno-68882' 767 The target machine does (or does not) have a floating-point 768 coprocessor. The default is to assume a coprocessor for 68020, 769 68030, and cpu32. Although the basic 68000 is not compatible with 770 the 68881, a combination of the two can be specified, since it's 771 possible to do emulation of the coprocessor instructions with the 772 main processor. 773 774'-m68851 | -mno-68851' 775 The target machine does (or does not) have a memory-management unit 776 coprocessor. The default is to assume an MMU for 68020 and up. 777 778 *Note Nios II Options::, for the options available when as is 779configured for an Altera Nios II processor. 780 781 For details about the PDP-11 machine dependent features options, see 782*note PDP-11-Options::. 783 784'-mpic | -mno-pic' 785 Generate position-independent (or position-dependent) code. The 786 default is '-mpic'. 787 788'-mall' 789'-mall-extensions' 790 Enable all instruction set extensions. This is the default. 791 792'-mno-extensions' 793 Disable all instruction set extensions. 794 795'-mEXTENSION | -mno-EXTENSION' 796 Enable (or disable) a particular instruction set extension. 797 798'-mCPU' 799 Enable the instruction set extensions supported by a particular 800 CPU, and disable all other extensions. 801 802'-mMACHINE' 803 Enable the instruction set extensions supported by a particular 804 machine model, and disable all other extensions. 805 806 The following options are available when as is configured for a 807picoJava processor. 808 809'-mb' 810 Generate "big endian" format output. 811 812'-ml' 813 Generate "little endian" format output. 814 815 *Note PRU Options::, for the options available when as is configured 816for a PRU processor. 817 818 The following options are available when as is configured for the 819Motorola 68HC11 or 68HC12 series. 820 821'-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg' 822 Specify what processor is the target. The default is defined by 823 the configuration option when building the assembler. 824 825'--xgate-ramoffset' 826 Instruct the linker to offset RAM addresses from S12X address space 827 into XGATE address space. 828 829'-mshort' 830 Specify to use the 16-bit integer ABI. 831 832'-mlong' 833 Specify to use the 32-bit integer ABI. 834 835'-mshort-double' 836 Specify to use the 32-bit double ABI. 837 838'-mlong-double' 839 Specify to use the 64-bit double ABI. 840 841'--force-long-branches' 842 Relative branches are turned into absolute ones. This concerns 843 conditional branches, unconditional branches and branches to a sub 844 routine. 845 846'-S | --short-branches' 847 Do not turn relative branches into absolute ones when the offset is 848 out of range. 849 850'--strict-direct-mode' 851 Do not turn the direct addressing mode into extended addressing 852 mode when the instruction does not support direct addressing mode. 853 854'--print-insn-syntax' 855 Print the syntax of instruction in case of error. 856 857'--print-opcodes' 858 Print the list of instructions with syntax and then exit. 859 860'--generate-example' 861 Print an example of instruction for each possible instruction and 862 then exit. This option is only useful for testing 'as'. 863 864 The following options are available when 'as' is configured for the 865SPARC architecture: 866 867'-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 868'-Av8plus | -Av8plusa | -Av9 | -Av9a' 869 Explicitly select a variant of the SPARC architecture. 870 871 '-Av8plus' and '-Av8plusa' select a 32 bit environment. '-Av9' and 872 '-Av9a' select a 64 bit environment. 873 874 '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with 875 UltraSPARC extensions. 876 877'-xarch=v8plus | -xarch=v8plusa' 878 For compatibility with the Solaris v9 assembler. These options are 879 equivalent to -Av8plus and -Av8plusa, respectively. 880 881'-bump' 882 Warn when the assembler switches to another architecture. 883 884 The following options are available when as is configured for the 885'c54x architecture. 886 887'-mfar-mode' 888 Enable extended addressing mode. All addresses and relocations 889 will assume extended addressing (usually 23 bits). 890'-mcpu=CPU_VERSION' 891 Sets the CPU version being compiled for. 892'-merrors-to-file FILENAME' 893 Redirect error output to a file, for broken systems which don't 894 support such behaviour in the shell. 895 896 The following options are available when as is configured for a MIPS 897processor. 898 899'-G NUM' 900 This option sets the largest size of an object that can be 901 referenced implicitly with the 'gp' register. It is only accepted 902 for targets that use ECOFF format, such as a DECstation running 903 Ultrix. The default value is 8. 904 905'-EB' 906 Generate "big endian" format output. 907 908'-EL' 909 Generate "little endian" format output. 910 911'-mips1' 912'-mips2' 913'-mips3' 914'-mips4' 915'-mips5' 916'-mips32' 917'-mips32r2' 918'-mips32r3' 919'-mips32r5' 920'-mips32r6' 921'-mips64' 922'-mips64r2' 923'-mips64r3' 924'-mips64r5' 925'-mips64r6' 926 Generate code for a particular MIPS Instruction Set Architecture 927 level. '-mips1' is an alias for '-march=r3000', '-mips2' is an 928 alias for '-march=r6000', '-mips3' is an alias for '-march=r4000' 929 and '-mips4' is an alias for '-march=r8000'. '-mips5', '-mips32', 930 '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6', '-mips64', 931 '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6' correspond 932 to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, 933 MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, 934 MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA 935 processors, respectively. 936 937'-march=CPU' 938 Generate code for a particular MIPS CPU. 939 940'-mtune=CPU' 941 Schedule and tune for a particular MIPS CPU. 942 943'-mfix7000' 944'-mno-fix7000' 945 Cause nops to be inserted if the read of the destination register 946 of an mfhi or mflo instruction occurs in the following two 947 instructions. 948 949'-mfix-rm7000' 950'-mno-fix-rm7000' 951 Cause nops to be inserted if a dmult or dmultu instruction is 952 followed by a load instruction. 953 954'-mfix-r5900' 955'-mno-fix-r5900' 956 Do not attempt to schedule the preceding instruction into the delay 957 slot of a branch instruction placed at the end of a short loop of 958 six instructions or fewer and always schedule a 'nop' instruction 959 there instead. The short loop bug under certain conditions causes 960 loops to execute only once or twice, due to a hardware bug in the 961 R5900 chip. 962 963'-mdebug' 964'-no-mdebug' 965 Cause stabs-style debugging output to go into an ECOFF-style 966 .mdebug section instead of the standard ELF .stabs sections. 967 968'-mpdr' 969'-mno-pdr' 970 Control generation of '.pdr' sections. 971 972'-mgp32' 973'-mfp32' 974 The register sizes are normally inferred from the ISA and ABI, but 975 these flags force a certain group of registers to be treated as 32 976 bits wide at all times. '-mgp32' controls the size of 977 general-purpose registers and '-mfp32' controls the size of 978 floating-point registers. 979 980'-mgp64' 981'-mfp64' 982 The register sizes are normally inferred from the ISA and ABI, but 983 these flags force a certain group of registers to be treated as 64 984 bits wide at all times. '-mgp64' controls the size of 985 general-purpose registers and '-mfp64' controls the size of 986 floating-point registers. 987 988'-mfpxx' 989 The register sizes are normally inferred from the ISA and ABI, but 990 using this flag in combination with '-mabi=32' enables an ABI 991 variant which will operate correctly with floating-point registers 992 which are 32 or 64 bits wide. 993 994'-modd-spreg' 995'-mno-odd-spreg' 996 Enable use of floating-point operations on odd-numbered 997 single-precision registers when supported by the ISA. '-mfpxx' 998 implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'. 999 1000'-mips16' 1001'-no-mips16' 1002 Generate code for the MIPS 16 processor. This is equivalent to 1003 putting '.module mips16' at the start of the assembly file. 1004 '-no-mips16' turns off this option. 1005 1006'-mmips16e2' 1007'-mno-mips16e2' 1008 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is 1009 equivalent to putting '.module mips16e2' at the start of the 1010 assembly file. '-mno-mips16e2' turns off this option. 1011 1012'-mmicromips' 1013'-mno-micromips' 1014 Generate code for the microMIPS processor. This is equivalent to 1015 putting '.module micromips' at the start of the assembly file. 1016 '-mno-micromips' turns off this option. This is equivalent to 1017 putting '.module nomicromips' at the start of the assembly file. 1018 1019'-msmartmips' 1020'-mno-smartmips' 1021 Enables the SmartMIPS extension to the MIPS32 instruction set. 1022 This is equivalent to putting '.module smartmips' at the start of 1023 the assembly file. '-mno-smartmips' turns off this option. 1024 1025'-mips3d' 1026'-no-mips3d' 1027 Generate code for the MIPS-3D Application Specific Extension. This 1028 tells the assembler to accept MIPS-3D instructions. '-no-mips3d' 1029 turns off this option. 1030 1031'-mdmx' 1032'-no-mdmx' 1033 Generate code for the MDMX Application Specific Extension. This 1034 tells the assembler to accept MDMX instructions. '-no-mdmx' turns 1035 off this option. 1036 1037'-mdsp' 1038'-mno-dsp' 1039 Generate code for the DSP Release 1 Application Specific Extension. 1040 This tells the assembler to accept DSP Release 1 instructions. 1041 '-mno-dsp' turns off this option. 1042 1043'-mdspr2' 1044'-mno-dspr2' 1045 Generate code for the DSP Release 2 Application Specific Extension. 1046 This option implies '-mdsp'. This tells the assembler to accept 1047 DSP Release 2 instructions. '-mno-dspr2' turns off this option. 1048 1049'-mdspr3' 1050'-mno-dspr3' 1051 Generate code for the DSP Release 3 Application Specific Extension. 1052 This option implies '-mdsp' and '-mdspr2'. This tells the 1053 assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns 1054 off this option. 1055 1056'-mmsa' 1057'-mno-msa' 1058 Generate code for the MIPS SIMD Architecture Extension. This tells 1059 the assembler to accept MSA instructions. '-mno-msa' turns off 1060 this option. 1061 1062'-mxpa' 1063'-mno-xpa' 1064 Generate code for the MIPS eXtended Physical Address (XPA) 1065 Extension. This tells the assembler to accept XPA instructions. 1066 '-mno-xpa' turns off this option. 1067 1068'-mmt' 1069'-mno-mt' 1070 Generate code for the MT Application Specific Extension. This 1071 tells the assembler to accept MT instructions. '-mno-mt' turns off 1072 this option. 1073 1074'-mmcu' 1075'-mno-mcu' 1076 Generate code for the MCU Application Specific Extension. This 1077 tells the assembler to accept MCU instructions. '-mno-mcu' turns 1078 off this option. 1079 1080'-mcrc' 1081'-mno-crc' 1082 Generate code for the MIPS cyclic redundancy check (CRC) 1083 Application Specific Extension. This tells the assembler to accept 1084 CRC instructions. '-mno-crc' turns off this option. 1085 1086'-mginv' 1087'-mno-ginv' 1088 Generate code for the Global INValidate (GINV) Application Specific 1089 Extension. This tells the assembler to accept GINV instructions. 1090 '-mno-ginv' turns off this option. 1091 1092'-mloongson-mmi' 1093'-mno-loongson-mmi' 1094 Generate code for the Loongson MultiMedia extensions Instructions 1095 (MMI) Application Specific Extension. This tells the assembler to 1096 accept MMI instructions. '-mno-loongson-mmi' turns off this 1097 option. 1098 1099'-mloongson-cam' 1100'-mno-loongson-cam' 1101 Generate code for the Loongson Content Address Memory (CAM) 1102 instructions. This tells the assembler to accept Loongson CAM 1103 instructions. '-mno-loongson-cam' turns off this option. 1104 1105'-mloongson-ext' 1106'-mno-loongson-ext' 1107 Generate code for the Loongson EXTensions (EXT) instructions. This 1108 tells the assembler to accept Loongson EXT instructions. 1109 '-mno-loongson-ext' turns off this option. 1110 1111'-mloongson-ext2' 1112'-mno-loongson-ext2' 1113 Generate code for the Loongson EXTensions R2 (EXT2) instructions. 1114 This option implies '-mloongson-ext'. This tells the assembler to 1115 accept Loongson EXT2 instructions. '-mno-loongson-ext2' turns off 1116 this option. 1117 1118'-minsn32' 1119'-mno-insn32' 1120 Only use 32-bit instruction encodings when generating code for the 1121 microMIPS processor. This option inhibits the use of any 16-bit 1122 instructions. This is equivalent to putting '.set insn32' at the 1123 start of the assembly file. '-mno-insn32' turns off this option. 1124 This is equivalent to putting '.set noinsn32' at the start of the 1125 assembly file. By default '-mno-insn32' is selected, allowing all 1126 instructions to be used. 1127 1128'--construct-floats' 1129'--no-construct-floats' 1130 The '--no-construct-floats' option disables the construction of 1131 double width floating point constants by loading the two halves of 1132 the value into the two single width floating point registers that 1133 make up the double width register. By default '--construct-floats' 1134 is selected, allowing construction of these floating point 1135 constants. 1136 1137'--relax-branch' 1138'--no-relax-branch' 1139 The '--relax-branch' option enables the relaxation of out-of-range 1140 branches. By default '--no-relax-branch' is selected, causing any 1141 out-of-range branches to produce an error. 1142 1143'-mignore-branch-isa' 1144'-mno-ignore-branch-isa' 1145 Ignore branch checks for invalid transitions between ISA modes. 1146 The semantics of branches does not provide for an ISA mode switch, 1147 so in most cases the ISA mode a branch has been encoded for has to 1148 be the same as the ISA mode of the branch's target label. 1149 Therefore GAS has checks implemented that verify in branch assembly 1150 that the two ISA modes match. '-mignore-branch-isa' disables these 1151 checks. By default '-mno-ignore-branch-isa' is selected, causing 1152 any invalid branch requiring a transition between ISA modes to 1153 produce an error. 1154 1155'-mnan=ENCODING' 1156 Select between the IEEE 754-2008 ('-mnan=2008') or the legacy 1157 ('-mnan=legacy') NaN encoding format. The latter is the default. 1158 1159'--emulation=NAME' 1160 This option was formerly used to switch between ELF and ECOFF 1161 output on targets like IRIX 5 that supported both. MIPS ECOFF 1162 support was removed in GAS 2.24, so the option now serves little 1163 purpose. It is retained for backwards compatibility. 1164 1165 The available configuration names are: 'mipself', 'mipslelf' and 1166 'mipsbelf'. Choosing 'mipself' now has no effect, since the output 1167 is always ELF. 'mipslelf' and 'mipsbelf' select little- and 1168 big-endian output respectively, but '-EL' and '-EB' are now the 1169 preferred options instead. 1170 1171'-nocpp' 1172 'as' ignores this option. It is accepted for compatibility with 1173 the native tools. 1174 1175'--trap' 1176'--no-trap' 1177'--break' 1178'--no-break' 1179 Control how to deal with multiplication overflow and division by 1180 zero. '--trap' or '--no-break' (which are synonyms) take a trap 1181 exception (and only work for Instruction Set Architecture level 2 1182 and higher); '--break' or '--no-trap' (also synonyms, and the 1183 default) take a break exception. 1184 1185'-n' 1186 When this option is used, 'as' will issue a warning every time it 1187 generates a nop instruction from a macro. 1188 1189 The following options are available when as is configured for an 1190MCore processor. 1191 1192'-jsri2bsr' 1193'-nojsri2bsr' 1194 Enable or disable the JSRI to BSR transformation. By default this 1195 is enabled. The command-line option '-nojsri2bsr' can be used to 1196 disable it. 1197 1198'-sifilter' 1199'-nosifilter' 1200 Enable or disable the silicon filter behaviour. By default this is 1201 disabled. The default can be overridden by the '-sifilter' 1202 command-line option. 1203 1204'-relax' 1205 Alter jump instructions for long displacements. 1206 1207'-mcpu=[210|340]' 1208 Select the cpu type on the target hardware. This controls which 1209 instructions can be assembled. 1210 1211'-EB' 1212 Assemble for a big endian target. 1213 1214'-EL' 1215 Assemble for a little endian target. 1216 1217 *Note Meta Options::, for the options available when as is configured 1218for a Meta processor. 1219 1220 See the info pages for documentation of the MMIX-specific options. 1221 1222 *Note NDS32 Options::, for the options available when as is 1223configured for a NDS32 processor. 1224 1225 *Note PowerPC-Opts::, for the options available when as is configured 1226for a PowerPC processor. 1227 1228 *Note RISC-V-Options::, for the options available when as is 1229configured for a RISC-V processor. 1230 1231 See the info pages for documentation of the RX-specific options. 1232 1233 The following options are available when as is configured for the 1234s390 processor family. 1235 1236'-m31' 1237'-m64' 1238 Select the word size, either 31/32 bits or 64 bits. 1239'-mesa' 1240'-mzarch' 1241 Select the architecture mode, either the Enterprise System 1242 Architecture (esa) or the z/Architecture mode (zarch). 1243'-march=PROCESSOR' 1244 Specify which s390 processor variant is the target, 'g5' (or 1245 'arch3'), 'g6', 'z900' (or 'arch5'), 'z990' (or 'arch6'), 'z9-109', 1246 'z9-ec' (or 'arch7'), 'z10' (or 'arch8'), 'z196' (or 'arch9'), 1247 'zEC12' (or 'arch10'), 'z13' (or 'arch11'), 'z14' (or 'arch12'), or 1248 'z15' (or 'arch13'). 1249'-mregnames' 1250'-mno-regnames' 1251 Allow or disallow symbolic names for registers. 1252'-mwarn-areg-zero' 1253 Warn whenever the operand for a base or index register has been 1254 specified but evaluates to zero. 1255 1256 *Note TIC6X Options::, for the options available when as is 1257configured for a TMS320C6000 processor. 1258 1259 *Note TILE-Gx Options::, for the options available when as is 1260configured for a TILE-Gx processor. 1261 1262 *Note Visium Options::, for the options available when as is 1263configured for a Visium processor. 1264 1265 *Note Xtensa Options::, for the options available when as is 1266configured for an Xtensa processor. 1267 1268 *Note Z80 Options::, for the options available when as is configured 1269for an Z80 processor. 1270 1271* Menu: 1272 1273* Manual:: Structure of this Manual 1274* GNU Assembler:: The GNU Assembler 1275* Object Formats:: Object File Formats 1276* Command Line:: Command Line 1277* Input Files:: Input Files 1278* Object:: Output (Object) File 1279* Errors:: Error and Warning Messages 1280 1281 1282File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview 1283 12841.1 Structure of this Manual 1285============================ 1286 1287This manual is intended to describe what you need to know to use GNU 1288'as'. We cover the syntax expected in source files, including notation 1289for symbols, constants, and expressions; the directives that 'as' 1290understands; and of course how to invoke 'as'. 1291 1292 This manual also describes some of the machine-dependent features of 1293various flavors of the assembler. 1294 1295 On the other hand, this manual is _not_ intended as an introduction 1296to programming in assembly language--let alone programming in general! 1297In a similar vein, we make no attempt to introduce the machine 1298architecture; we do _not_ describe the instruction set, standard 1299mnemonics, registers or addressing modes that are standard to a 1300particular architecture. You may want to consult the manufacturer's 1301machine architecture manual for this information. 1302 1303 1304File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview 1305 13061.2 The GNU Assembler 1307===================== 1308 1309GNU 'as' is really a family of assemblers. If you use (or have used) 1310the GNU assembler on one architecture, you should find a fairly similar 1311environment when you use it on another architecture. Each version has 1312much in common with the others, including object file formats, most 1313assembler directives (often called "pseudo-ops") and assembler syntax. 1314 1315 'as' is primarily intended to assemble the output of the GNU C 1316compiler 'gcc' for use by the linker 'ld'. Nevertheless, we've tried to 1317make 'as' assemble correctly everything that other assemblers for the 1318same machine would assemble. Any exceptions are documented explicitly 1319(*note Machine Dependencies::). This doesn't mean 'as' always uses the 1320same syntax as another assembler for the same architecture; for example, 1321we know of several incompatible versions of 680x0 assembly language 1322syntax. 1323 1324 Unlike older assemblers, 'as' is designed to assemble a source 1325program in one pass of the source file. This has a subtle impact on the 1326'.org' directive (*note '.org': Org.). 1327 1328 1329File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview 1330 13311.3 Object File Formats 1332======================= 1333 1334The GNU assembler can be configured to produce several alternative 1335object file formats. For the most part, this does not affect how you 1336write assembly language programs; but directives for debugging symbols 1337are typically different in different file formats. *Note Symbol 1338Attributes: Symbol Attributes. 1339 1340 1341File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview 1342 13431.4 Command Line 1344================ 1345 1346After the program name 'as', the command line may contain options and 1347file names. Options may appear in any order, and may be before, after, 1348or between file names. The order of file names is significant. 1349 1350 '--' (two hyphens) by itself names the standard input file 1351explicitly, as one of the files for 'as' to assemble. 1352 1353 Except for '--' any command-line argument that begins with a hyphen 1354('-') is an option. Each option changes the behavior of 'as'. No 1355option changes the way another option works. An option is a '-' 1356followed by one or more letters; the case of the letter is important. 1357All options are optional. 1358 1359 Some options expect exactly one file name to follow them. The file 1360name may either immediately follow the option's letter (compatible with 1361older assemblers) or it may be the next command argument (GNU standard). 1362These two command lines are equivalent: 1363 1364 as -o my-object-file.o mumble.s 1365 as -omy-object-file.o mumble.s 1366 1367 1368File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview 1369 13701.5 Input Files 1371=============== 1372 1373We use the phrase "source program", abbreviated "source", to describe 1374the program input to one run of 'as'. The program may be in one or more 1375files; how the source is partitioned into files doesn't change the 1376meaning of the source. 1377 1378 The source program is a concatenation of the text in all the files, 1379in the order specified. 1380 1381 Each time you run 'as' it assembles exactly one source program. The 1382source program is made up of one or more files. (The standard input is 1383also a file.) 1384 1385 You give 'as' a command line that has zero or more input file names. 1386The input files are read (from left file name to right). A command-line 1387argument (in any position) that has no special meaning is taken to be an 1388input file name. 1389 1390 If you give 'as' no file names it attempts to read one input file 1391from the 'as' standard input, which is normally your terminal. You may 1392have to type <ctl-D> to tell 'as' there is no more program to assemble. 1393 1394 Use '--' if you need to explicitly name the standard input file in 1395your command line. 1396 1397 If the source is empty, 'as' produces a small, empty object file. 1398 1399Filenames and Line-numbers 1400-------------------------- 1401 1402There are two ways of locating a line in the input file (or files) and 1403either may be used in reporting error messages. One way refers to a 1404line number in a physical file; the other refers to a line number in a 1405"logical" file. *Note Error and Warning Messages: Errors. 1406 1407 "Physical files" are those files named in the command line given to 1408'as'. 1409 1410 "Logical files" are simply names declared explicitly by assembler 1411directives; they bear no relation to physical files. Logical file names 1412help error messages reflect the original source file, when 'as' source 1413is itself synthesized from other files. 'as' understands the '#' 1414directives emitted by the 'gcc' preprocessor. See also *note '.file': 1415File. 1416 1417 1418File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1419 14201.6 Output (Object) File 1421======================== 1422 1423Every time you run 'as' it produces an output file, which is your 1424assembly language program translated into numbers. This file is the 1425object file. Its default name is 'a.out'. You can give it another name 1426by using the '-o' option. Conventionally, object file names end with 1427'.o'. The default name is used for historical reasons: older assemblers 1428were capable of assembling self-contained programs directly into a 1429runnable program. (For some formats, this isn't currently possible, but 1430it can be done for the 'a.out' format.) 1431 1432 The object file is meant for input to the linker 'ld'. It contains 1433assembled program code, information to help 'ld' integrate the assembled 1434program into a runnable file, and (optionally) symbolic information for 1435the debugger. 1436 1437 1438File: as.info, Node: Errors, Prev: Object, Up: Overview 1439 14401.7 Error and Warning Messages 1441============================== 1442 1443'as' may write warnings and error messages to the standard error file 1444(usually your terminal). This should not happen when a compiler runs 1445'as' automatically. Warnings report an assumption made so that 'as' 1446could keep assembling a flawed program; errors report a grave problem 1447that stops the assembly. 1448 1449 Warning messages have the format 1450 1451 file_name:NNN:Warning Message Text 1452 1453(where NNN is a line number). If both a logical file name (*note 1454'.file': File.) and a logical line number (*note '.line': Line.) have 1455been given then they will be used, otherwise the file name and line 1456number in the current assembler source file will be used. The message 1457text is intended to be self explanatory (in the grand Unix tradition). 1458 1459 Note the file name must be set via the logical version of the '.file' 1460directive, not the DWARF2 version of the '.file' directive. For 1461example: 1462 1463 .file 2 "bar.c" 1464 error_assembler_source 1465 .file "foo.c" 1466 .line 30 1467 error_c_source 1468 1469 produces this output: 1470 1471 Assembler messages: 1472 asm.s:2: Error: no such instruction: `error_assembler_source' 1473 foo.c:31: Error: no such instruction: `error_c_source' 1474 1475 Error messages have the format 1476 1477 file_name:NNN:FATAL:Error Message Text 1478 1479 The file name and line number are derived as for warning messages. 1480The actual message text may be rather less explanatory because many of 1481them aren't supposed to happen. 1482 1483 1484File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top 1485 14862 Command-Line Options 1487********************** 1488 1489This chapter describes command-line options available in _all_ versions 1490of the GNU assembler; see *note Machine Dependencies::, for options 1491specific to particular machine architectures. 1492 1493 If you are invoking 'as' via the GNU C compiler, you can use the 1494'-Wa' option to pass arguments through to the assembler. The assembler 1495arguments must be separated from each other (and the '-Wa') by commas. 1496For example: 1497 1498 gcc -c -g -O -Wa,-alh,-L file.c 1499 1500This passes two options to the assembler: '-alh' (emit a listing to 1501standard output with high-level and assembly source) and '-L' (retain 1502local symbols in the symbol table). 1503 1504 Usually you do not need to use this '-Wa' mechanism, since many 1505compiler command-line options are automatically passed to the assembler 1506by the compiler. (You can call the GNU compiler driver with the '-v' 1507option to see precisely what options it passes to each compilation pass, 1508including the assembler.) 1509 1510* Menu: 1511 1512* a:: -a[cdghlns] enable listings 1513* alternate:: -alternate enable alternate macro syntax 1514* D:: -D for compatibility 1515* f:: -f to work faster 1516* I:: -I for .include search path 1517* K:: -K for difference tables 1518 1519* L:: -L to retain local symbols 1520* listing:: -listing-XXX to configure listing output 1521* M:: -M or -mri to assemble in MRI compatibility mode 1522* MD:: -MD for dependency tracking 1523* no-pad-sections:: -no-pad-sections to stop section padding 1524* o:: -o to name the object file 1525* R:: -R to join data and text sections 1526* statistics:: -statistics to see statistics about assembly 1527* traditional-format:: -traditional-format for compatible output 1528* v:: -v to announce version 1529* W:: -W, -no-warn, -warn, -fatal-warnings to control warnings 1530* Z:: -Z to make object file even after errors 1531 1532 1533File: as.info, Node: a, Next: alternate, Up: Invoking 1534 15352.1 Enable Listings: '-a[cdghlns]' 1536================================== 1537 1538These options enable listing output from the assembler. By itself, '-a' 1539requests high-level, assembly, and symbols listing. You can use other 1540letters to select specific options for the list: '-ah' requests a 1541high-level language listing, '-al' requests an output-program assembly 1542listing, and '-as' requests a symbol table listing. High-level listings 1543require that a compiler debugging option like '-g' be used, and that 1544assembly listings ('-al') be requested also. 1545 1546 Use the '-ag' option to print a first section with general assembly 1547information, like as version, switches passed, or time stamp. 1548 1549 Use the '-ac' option to omit false conditionals from a listing. Any 1550lines which are not assembled because of a false '.if' (or '.ifdef', or 1551any other conditional), or a true '.if' followed by an '.else', will be 1552omitted from the listing. 1553 1554 Use the '-ad' option to omit debugging directives from the listing. 1555 1556 Once you have specified one of these options, you can further control 1557listing output and its appearance using the directives '.list', 1558'.nolist', '.psize', '.eject', '.title', and '.sbttl'. The '-an' option 1559turns off all forms processing. If you do not request listing output 1560with one of the '-a' options, the listing-control directives have no 1561effect. 1562 1563 The letters after '-a' may be combined into one option, _e.g._, 1564'-aln'. 1565 1566 Note if the assembler source is coming from the standard input (e.g., 1567because it is being created by 'gcc' and the '-pipe' command-line switch 1568is being used) then the listing will not contain any comments or 1569preprocessor directives. This is because the listing code buffers input 1570source lines from stdin only after they have been preprocessed by the 1571assembler. This reduces memory usage and makes the code more efficient. 1572 1573 1574File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking 1575 15762.2 '--alternate' 1577================= 1578 1579Begin in alternate macro mode, see *note '.altmacro': Altmacro. 1580 1581 1582File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking 1583 15842.3 '-D' 1585======== 1586 1587This option has no effect whatsoever, but it is accepted to make it more 1588likely that scripts written for other assemblers also work with 'as'. 1589 1590 1591File: as.info, Node: f, Next: I, Prev: D, Up: Invoking 1592 15932.4 Work Faster: '-f' 1594===================== 1595 1596'-f' should only be used when assembling programs written by a (trusted) 1597compiler. '-f' stops the assembler from doing whitespace and comment 1598preprocessing on the input file(s) before assembling them. *Note 1599Preprocessing: Preprocessing. 1600 1601 _Warning:_ if you use '-f' when the files actually need to be 1602 preprocessed (if they contain comments, for example), 'as' does not 1603 work correctly. 1604 1605 1606File: as.info, Node: I, Next: K, Prev: f, Up: Invoking 1607 16082.5 '.include' Search Path: '-I' PATH 1609===================================== 1610 1611Use this option to add a PATH to the list of directories 'as' searches 1612for files specified in '.include' directives (*note '.include': 1613Include.). You may use '-I' as many times as necessary to include a 1614variety of paths. The current working directory is always searched 1615first; after that, 'as' searches any '-I' directories in the same order 1616as they were specified (left to right) on the command line. 1617 1618 1619File: as.info, Node: K, Next: L, Prev: I, Up: Invoking 1620 16212.6 Difference Tables: '-K' 1622=========================== 1623 1624'as' sometimes alters the code emitted for directives of the form '.word 1625SYM1-SYM2'. *Note '.word': Word. You can use the '-K' option if you 1626want a warning issued when this is done. 1627 1628 1629File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking 1630 16312.7 Include Local Symbols: '-L' 1632=============================== 1633 1634Symbols beginning with system-specific local label prefixes, typically 1635'.L' for ELF systems or 'L' for traditional a.out systems, are called 1636"local symbols". *Note Symbol Names::. Normally you do not see such 1637symbols when debugging, because they are intended for the use of 1638programs (like compilers) that compose assembler programs, not for your 1639notice. Normally both 'as' and 'ld' discard such symbols, so you do not 1640normally debug with them. 1641 1642 This option tells 'as' to retain those local symbols in the object 1643file. Usually if you do this you also tell the linker 'ld' to preserve 1644those symbols. 1645 1646 1647File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking 1648 16492.8 Configuring listing output: '--listing' 1650=========================================== 1651 1652The listing feature of the assembler can be enabled via the command-line 1653switch '-a' (*note a::). This feature combines the input source file(s) 1654with a hex dump of the corresponding locations in the output object 1655file, and displays them as a listing file. The format of this listing 1656can be controlled by directives inside the assembler source (i.e., 1657'.list' (*note List::), '.title' (*note Title::), '.sbttl' (*note 1658Sbttl::), '.psize' (*note Psize::), and '.eject' (*note Eject::) and 1659also by the following switches: 1660 1661'--listing-lhs-width='number'' 1662 Sets the maximum width, in words, of the first line of the hex byte 1663 dump. This dump appears on the left hand side of the listing 1664 output. 1665 1666'--listing-lhs-width2='number'' 1667 Sets the maximum width, in words, of any further lines of the hex 1668 byte dump for a given input source line. If this value is not 1669 specified, it defaults to being the same as the value specified for 1670 '--listing-lhs-width'. If neither switch is used the default is to 1671 one. 1672 1673'--listing-rhs-width='number'' 1674 Sets the maximum width, in characters, of the source line that is 1675 displayed alongside the hex dump. The default value for this 1676 parameter is 100. The source line is displayed on the right hand 1677 side of the listing output. 1678 1679'--listing-cont-lines='number'' 1680 Sets the maximum number of continuation lines of hex dump that will 1681 be displayed for a given single line of source input. The default 1682 value is 4. 1683 1684 1685File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking 1686 16872.9 Assemble in MRI Compatibility Mode: '-M' 1688============================================ 1689 1690The '-M' or '--mri' option selects MRI compatibility mode. This changes 1691the syntax and pseudo-op handling of 'as' to make it compatible with the 1692'ASM68K' assembler from Microtec Research. The exact nature of the MRI 1693syntax will not be documented here; see the MRI manuals for more 1694information. Note in particular that the handling of macros and macro 1695arguments is somewhat different. The purpose of this option is to 1696permit assembling existing MRI assembler code using 'as'. 1697 1698 The MRI compatibility is not complete. Certain operations of the MRI 1699assembler depend upon its object file format, and can not be supported 1700using other object file formats. Supporting these would require 1701enhancing each object file format individually. These are: 1702 1703 * global symbols in common section 1704 1705 The m68k MRI assembler supports common sections which are merged by 1706 the linker. Other object file formats do not support this. 'as' 1707 handles common sections by treating them as a single common symbol. 1708 It permits local symbols to be defined within a common section, but 1709 it can not support global symbols, since it has no way to describe 1710 them. 1711 1712 * complex relocations 1713 1714 The MRI assemblers support relocations against a negated section 1715 address, and relocations which combine the start addresses of two 1716 or more sections. These are not support by other object file 1717 formats. 1718 1719 * 'END' pseudo-op specifying start address 1720 1721 The MRI 'END' pseudo-op permits the specification of a start 1722 address. This is not supported by other object file formats. The 1723 start address may instead be specified using the '-e' option to the 1724 linker, or in a linker script. 1725 1726 * 'IDNT', '.ident' and 'NAME' pseudo-ops 1727 1728 The MRI 'IDNT', '.ident' and 'NAME' pseudo-ops assign a module name 1729 to the output file. This is not supported by other object file 1730 formats. 1731 1732 * 'ORG' pseudo-op 1733 1734 The m68k MRI 'ORG' pseudo-op begins an absolute section at a given 1735 address. This differs from the usual 'as' '.org' pseudo-op, which 1736 changes the location within the current section. Absolute sections 1737 are not supported by other object file formats. The address of a 1738 section may be assigned within a linker script. 1739 1740 There are some other features of the MRI assembler which are not 1741supported by 'as', typically either because they are difficult or 1742because they seem of little consequence. Some of these may be supported 1743in future releases. 1744 1745 * EBCDIC strings 1746 1747 EBCDIC strings are not supported. 1748 1749 * packed binary coded decimal 1750 1751 Packed binary coded decimal is not supported. This means that the 1752 'DC.P' and 'DCB.P' pseudo-ops are not supported. 1753 1754 * 'FEQU' pseudo-op 1755 1756 The m68k 'FEQU' pseudo-op is not supported. 1757 1758 * 'NOOBJ' pseudo-op 1759 1760 The m68k 'NOOBJ' pseudo-op is not supported. 1761 1762 * 'OPT' branch control options 1763 1764 The m68k 'OPT' branch control options--'B', 'BRS', 'BRB', 'BRL', 1765 and 'BRW'--are ignored. 'as' automatically relaxes all branches, 1766 whether forward or backward, to an appropriate size, so these 1767 options serve no purpose. 1768 1769 * 'OPT' list control options 1770 1771 The following m68k 'OPT' list control options are ignored: 'C', 1772 'CEX', 'CL', 'CRE', 'E', 'G', 'I', 'M', 'MEX', 'MC', 'MD', 'X'. 1773 1774 * other 'OPT' options 1775 1776 The following m68k 'OPT' options are ignored: 'NEST', 'O', 'OLD', 1777 'OP', 'P', 'PCO', 'PCR', 'PCS', 'R'. 1778 1779 * 'OPT' 'D' option is default 1780 1781 The m68k 'OPT' 'D' option is the default, unlike the MRI assembler. 1782 'OPT NOD' may be used to turn it off. 1783 1784 * 'XREF' pseudo-op. 1785 1786 The m68k 'XREF' pseudo-op is ignored. 1787 1788 1789File: as.info, Node: MD, Next: no-pad-sections, Prev: M, Up: Invoking 1790 17912.10 Dependency Tracking: '--MD' 1792================================ 1793 1794'as' can generate a dependency file for the file it creates. This file 1795consists of a single rule suitable for 'make' describing the 1796dependencies of the main source file. 1797 1798 The rule is written to the file named in its argument. 1799 1800 This feature is used in the automatic updating of makefiles. 1801 1802 1803File: as.info, Node: no-pad-sections, Next: o, Prev: MD, Up: Invoking 1804 18052.11 Output Section Padding 1806=========================== 1807 1808Normally the assembler will pad the end of each output section up to its 1809alignment boundary. But this can waste space, which can be significant 1810on memory constrained targets. So the '--no-pad-sections' option will 1811disable this behaviour. 1812 1813 1814File: as.info, Node: o, Next: R, Prev: no-pad-sections, Up: Invoking 1815 18162.12 Name the Object File: '-o' 1817=============================== 1818 1819There is always one object file output when you run 'as'. By default it 1820has the name 'a.out'. You use this option (which takes exactly one 1821filename) to give the object file a different name. 1822 1823 Whatever the object file is called, 'as' overwrites any existing file 1824of the same name. 1825 1826 1827File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking 1828 18292.13 Join Data and Text Sections: '-R' 1830====================================== 1831 1832'-R' tells 'as' to write the object file as if all data-section data 1833lives in the text section. This is only done at the very last moment: 1834your binary data are the same, but data section parts are relocated 1835differently. The data section part of your object file is zero bytes 1836long because all its bytes are appended to the text section. (*Note 1837Sections and Relocation: Sections.) 1838 1839 When you specify '-R' it would be possible to generate shorter 1840address displacements (because we do not have to cross between text and 1841data section). We refrain from doing this simply for compatibility with 1842older versions of 'as'. In future, '-R' may work this way. 1843 1844 When 'as' is configured for COFF or ELF output, this option is only 1845useful if you use sections named '.text' and '.data'. 1846 1847 '-R' is not supported for any of the HPPA targets. Using '-R' 1848generates a warning from 'as'. 1849 1850 1851File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking 1852 18532.14 Display Assembly Statistics: '--statistics' 1854================================================ 1855 1856Use '--statistics' to display two statistics about the resources used by 1857'as': the maximum amount of space allocated during the assembly (in 1858bytes), and the total execution time taken for the assembly (in CPU 1859seconds). 1860 1861 1862File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking 1863 18642.15 Compatible Output: '--traditional-format' 1865============================================== 1866 1867For some targets, the output of 'as' is different in some ways from the 1868output of some existing assembler. This switch requests 'as' to use the 1869traditional format instead. 1870 1871 For example, it disables the exception frame optimizations which 'as' 1872normally does by default on 'gcc' output. 1873 1874 1875File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking 1876 18772.16 Announce Version: '-v' 1878=========================== 1879 1880You can find out what version of as is running by including the option 1881'-v' (which you can also spell as '-version') on the command line. 1882 1883 1884File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking 1885 18862.17 Control Warnings: '-W', '--warn', '--no-warn', '--fatal-warnings' 1887====================================================================== 1888 1889'as' should never give a warning or error message when assembling 1890compiler output. But programs written by people often cause 'as' to 1891give a warning that a particular assumption was made. All such warnings 1892are directed to the standard error file. 1893 1894 If you use the '-W' and '--no-warn' options, no warnings are issued. 1895This only affects the warning messages: it does not change any 1896particular of how 'as' assembles your file. Errors, which stop the 1897assembly, are still reported. 1898 1899 If you use the '--fatal-warnings' option, 'as' considers files that 1900generate warnings to be in error. 1901 1902 You can switch these options off again by specifying '--warn', which 1903causes warnings to be output as usual. 1904 1905 1906File: as.info, Node: Z, Prev: W, Up: Invoking 1907 19082.18 Generate Object File in Spite of Errors: '-Z' 1909================================================== 1910 1911After an error message, 'as' normally produces no output. If for some 1912reason you are interested in object file output even after 'as' gives an 1913error message on your program, use the '-Z' option. If there are any 1914errors, 'as' continues anyways, and writes an object file after a final 1915warning message of the form 'N errors, M warnings, generating bad object 1916file.' 1917 1918 1919File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top 1920 19213 Syntax 1922******** 1923 1924This chapter describes the machine-independent syntax allowed in a 1925source file. 'as' syntax is similar to what many other assemblers use; 1926it is inspired by the BSD 4.2 assembler, except that 'as' does not 1927assemble Vax bit-fields. 1928 1929* Menu: 1930 1931* Preprocessing:: Preprocessing 1932* Whitespace:: Whitespace 1933* Comments:: Comments 1934* Symbol Intro:: Symbols 1935* Statements:: Statements 1936* Constants:: Constants 1937 1938 1939File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 1940 19413.1 Preprocessing 1942================= 1943 1944The 'as' internal preprocessor: 1945 * adjusts and removes extra whitespace. It leaves one space or tab 1946 before the keywords on a line, and turns any other whitespace on 1947 the line into a single space. 1948 1949 * removes all comments, replacing them with a single space, or an 1950 appropriate number of newlines. 1951 1952 * converts character constants into the appropriate numeric values. 1953 1954 It does not do macro processing, include file handling, or anything 1955else you may get from your C compiler's preprocessor. You can do 1956include file processing with the '.include' directive (*note '.include': 1957Include.). You can use the GNU C compiler driver to get other "CPP" 1958style preprocessing by giving the input file a '.S' suffix. See the 1959'Options Controlling the Kind of Output' section of the GCC manual for 1960more details 1961(https://gcc.gnu.org/onlinedocs/gcc/Overall-Options.html#Overall-Options) 1962 1963 Excess whitespace, comments, and character constants cannot be used 1964in the portions of the input text that are not preprocessed. 1965 1966 If the first line of an input file is '#NO_APP' or if you use the 1967'-f' option, whitespace and comments are not removed from the input 1968file. Within an input file, you can ask for whitespace and comment 1969removal in specific portions of the by putting a line that says '#APP' 1970before the text that may contain whitespace or comments, and putting a 1971line that says '#NO_APP' after this text. This feature is mainly intend 1972to support 'asm' statements in compilers whose output is otherwise free 1973of comments and whitespace. 1974 1975 1976File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax 1977 19783.2 Whitespace 1979============== 1980 1981"Whitespace" is one or more blanks or tabs, in any order. Whitespace is 1982used to separate symbols, and to make programs neater for people to 1983read. Unless within character constants (*note Character Constants: 1984Characters.), any whitespace means the same as exactly one space. 1985 1986 1987File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax 1988 19893.3 Comments 1990============ 1991 1992There are two ways of rendering comments to 'as'. In both cases the 1993comment is equivalent to one space. 1994 1995 Anything from '/*' through the next '*/' is a comment. This means 1996you may not nest these comments. 1997 1998 /* 1999 The only way to include a newline ('\n') in a comment 2000 is to use this sort of comment. 2001 */ 2002 2003 /* This sort of comment does not nest. */ 2004 2005 Anything from a "line comment" character up to the next newline is 2006considered a comment and is ignored. The line comment character is 2007target specific, and some targets multiple comment characters. Some 2008targets also have line comment characters that only work if they are the 2009first character on a line. Some targets use a sequence of two 2010characters to introduce a line comment. Some targets can also change 2011their line comment characters depending upon command-line options that 2012have been used. For more details see the _Syntax_ section in the 2013documentation for individual targets. 2014 2015 If the line comment character is the hash sign ('#') then it still 2016has the special ability to enable and disable preprocessing (*note 2017Preprocessing::) and to specify logical line numbers: 2018 2019 To be compatible with past assemblers, lines that begin with '#' have 2020a special interpretation. Following the '#' should be an absolute 2021expression (*note Expressions::): the logical line number of the _next_ 2022line. Then a string (*note Strings: Strings.) is allowed: if present it 2023is a new logical file name. The rest of the line, if any, should be 2024whitespace. 2025 2026 If the first non-whitespace characters on the line are not numeric, 2027the line is ignored. (Just like a comment.) 2028 2029 # This is an ordinary comment. 2030 # 42-6 "new_file_name" # New logical file name 2031 # This is logical line # 36. 2032 This feature is deprecated, and may disappear from future versions of 2033'as'. 2034 2035 2036File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax 2037 20383.4 Symbols 2039=========== 2040 2041A "symbol" is one or more characters chosen from the set of all letters 2042(both upper and lower case), digits and the three characters '_.$'. On 2043most machines, you can also use '$' in symbol names; exceptions are 2044noted in *note Machine Dependencies::. No symbol may begin with a 2045digit. Case is significant. There is no length limit; all characters 2046are significant. Multibyte characters are supported. Symbols are 2047delimited by characters not in that set, or by the beginning of a file 2048(since the source program must end with a newline, the end of a file is 2049not a possible symbol delimiter). *Note Symbols::. 2050 2051 Symbol names may also be enclosed in double quote '"' characters. In 2052such cases any characters are allowed, except for the NUL character. If 2053a double quote character is to be included in the symbol name it must be 2054preceded by a backslash '\' character. 2055 2056 2057File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax 2058 20593.5 Statements 2060============== 2061 2062A "statement" ends at a newline character ('\n') or a "line separator 2063character". The line separator character is target specific and 2064described in the _Syntax_ section of each target's documentation. Not 2065all targets support a line separator character. The newline or line 2066separator character is considered to be part of the preceding statement. 2067Newlines and separators within character constants are an exception: 2068they do not end statements. 2069 2070 It is an error to end any statement with end-of-file: the last 2071character of any input file should be a newline. 2072 2073 An empty statement is allowed, and may include whitespace. It is 2074ignored. 2075 2076 A statement begins with zero or more labels, optionally followed by a 2077key symbol which determines what kind of statement it is. The key 2078symbol determines the syntax of the rest of the statement. If the 2079symbol begins with a dot '.' then the statement is an assembler 2080directive: typically valid for any computer. If the symbol begins with 2081a letter the statement is an assembly language "instruction": it 2082assembles into a machine language instruction. Different versions of 2083'as' for different computers recognize different instructions. In fact, 2084the same symbol may represent a different instruction in a different 2085computer's assembly language. 2086 2087 A label is a symbol immediately followed by a colon (':'). 2088Whitespace before a label or after a colon is permitted, but you may not 2089have whitespace between a label's symbol and its colon. *Note Labels::. 2090 2091 For HPPA targets, labels need not be immediately followed by a colon, 2092but the definition of a label must begin in column zero. This also 2093implies that only one label may be defined on each line. 2094 2095 label: .directive followed by something 2096 another_label: # This is an empty statement. 2097 instruction operand_1, operand_2, ... 2098 2099 2100File: as.info, Node: Constants, Prev: Statements, Up: Syntax 2101 21023.6 Constants 2103============= 2104 2105A constant is a number, written so that its value is known by 2106inspection, without knowing any context. Like this: 2107 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. 2108 .ascii "Ring the bell\7" # A string constant. 2109 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. 2110 .float 0f-314159265358979323846264338327\ 2111 95028841971.693993751E-40 # - pi, a flonum. 2112 2113* Menu: 2114 2115* Characters:: Character Constants 2116* Numbers:: Number Constants 2117 2118 2119File: as.info, Node: Characters, Next: Numbers, Up: Constants 2120 21213.6.1 Character Constants 2122------------------------- 2123 2124There are two kinds of character constants. A "character" stands for 2125one character in one byte and its value may be used in numeric 2126expressions. String constants (properly called string _literals_) are 2127potentially many bytes and their values may not be used in arithmetic 2128expressions. 2129 2130* Menu: 2131 2132* Strings:: Strings 2133* Chars:: Characters 2134 2135 2136File: as.info, Node: Strings, Next: Chars, Up: Characters 2137 21383.6.1.1 Strings 2139............... 2140 2141A "string" is written between double-quotes. It may contain 2142double-quotes or null characters. The way to get special characters 2143into a string is to "escape" these characters: precede them with a 2144backslash '\' character. For example '\\' represents one backslash: the 2145first '\' is an escape which tells 'as' to interpret the second 2146character literally as a backslash (which prevents 'as' from recognizing 2147the second '\' as an escape character). The complete list of escapes 2148follows. 2149 2150'\b' 2151 Mnemonic for backspace; for ASCII this is octal code 010. 2152 2153'backslash-f' 2154 Mnemonic for FormFeed; for ASCII this is octal code 014. 2155 2156'\n' 2157 Mnemonic for newline; for ASCII this is octal code 012. 2158 2159'\r' 2160 Mnemonic for carriage-Return; for ASCII this is octal code 015. 2161 2162'\t' 2163 Mnemonic for horizontal Tab; for ASCII this is octal code 011. 2164 2165'\ DIGIT DIGIT DIGIT' 2166 An octal character code. The numeric code is 3 octal digits. For 2167 compatibility with other Unix systems, 8 and 9 are accepted as 2168 digits: for example, '\008' has the value 010, and '\009' the value 2169 011. 2170 2171'\x HEX-DIGITS...' 2172 A hex character code. All trailing hex digits are combined. 2173 Either upper or lower case 'x' works. 2174 2175'\\' 2176 Represents one '\' character. 2177 2178'\"' 2179 Represents one '"' character. Needed in strings to represent this 2180 character, because an unescaped '"' would end the string. 2181 2182'\ ANYTHING-ELSE' 2183 Any other character when escaped by '\' gives a warning, but 2184 assembles as if the '\' was not present. The idea is that if you 2185 used an escape sequence you clearly didn't want the literal 2186 interpretation of the following character. However 'as' has no 2187 other interpretation, so 'as' knows it is giving you the wrong code 2188 and warns you of the fact. 2189 2190 Which characters are escapable, and what those escapes represent, 2191varies widely among assemblers. The current set is what we think the 2192BSD 4.2 assembler recognizes, and is a subset of what most C compilers 2193recognize. If you are in doubt, do not use an escape sequence. 2194 2195 2196File: as.info, Node: Chars, Prev: Strings, Up: Characters 2197 21983.6.1.2 Characters 2199.................. 2200 2201A single character may be written as a single quote immediately followed 2202by that character. Some backslash escapes apply to characters, '\b', 2203'\f', '\n', '\r', '\t', and '\"' with the same meaning as for strings, 2204plus '\'' for a single quote. So if you want to write the character 2205backslash, you must write ''\\' where the first '\' escapes the second 2206'\'. As you can see, the quote is an acute accent, not a grave accent. 2207A newline immediately following an acute accent is taken as a literal 2208character and does not count as the end of a statement. The value of a 2209character constant in a numeric expression is the machine's byte-wide 2210code for that character. 'as' assumes your character code is ASCII: 2211''A' means 65, ''B' means 66, and so on. 2212 2213 2214File: as.info, Node: Numbers, Prev: Characters, Up: Constants 2215 22163.6.2 Number Constants 2217---------------------- 2218 2219'as' distinguishes three kinds of numbers according to how they are 2220stored in the target machine. _Integers_ are numbers that would fit 2221into an 'int' in the C language. _Bignums_ are integers, but they are 2222stored in more than 32 bits. _Flonums_ are floating point numbers, 2223described below. 2224 2225* Menu: 2226 2227* Integers:: Integers 2228* Bignums:: Bignums 2229* Flonums:: Flonums 2230 2231 2232File: as.info, Node: Integers, Next: Bignums, Up: Numbers 2233 22343.6.2.1 Integers 2235................ 2236 2237A binary integer is '0b' or '0B' followed by zero or more of the binary 2238digits '01'. 2239 2240 An octal integer is '0' followed by zero or more of the octal digits 2241('01234567'). 2242 2243 A decimal integer starts with a non-zero digit followed by zero or 2244more digits ('0123456789'). 2245 2246 A hexadecimal integer is '0x' or '0X' followed by one or more 2247hexadecimal digits chosen from '0123456789abcdefABCDEF'. 2248 2249 Integers have the usual values. To denote a negative integer, use 2250the prefix operator '-' discussed under expressions (*note Prefix 2251Operators: Prefix Ops.). 2252 2253 2254File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers 2255 22563.6.2.2 Bignums 2257............... 2258 2259A "bignum" has the same syntax and semantics as an integer except that 2260the number (or its negative) takes more than 32 bits to represent in 2261binary. The distinction is made because in some places integers are 2262permitted while bignums are not. 2263 2264 2265File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers 2266 22673.6.2.3 Flonums 2268............... 2269 2270A "flonum" represents a floating point number. The translation is 2271indirect: a decimal floating point number from the text is converted by 2272'as' to a generic binary floating point number of more than sufficient 2273precision. This generic floating point number is converted to a 2274particular computer's floating point format (or formats) by a portion of 2275'as' specialized to that computer. 2276 2277 A flonum is written by writing (in order) 2278 * The digit '0'. ('0' is optional on the HPPA.) 2279 2280 * A letter, to tell 'as' the rest of the number is a flonum. 'e' is 2281 recommended. Case is not important. 2282 2283 On the H8/300 and Renesas / SuperH SH architectures, the letter 2284 must be one of the letters 'DFPRSX' (in upper or lower case). 2285 2286 On the ARC, the letter must be one of the letters 'DFRS' (in upper 2287 or lower case). 2288 2289 On the HPPA architecture, the letter must be 'E' (upper case only). 2290 2291 * An optional sign: either '+' or '-'. 2292 2293 * An optional "integer part": zero or more decimal digits. 2294 2295 * An optional "fractional part": '.' followed by zero or more decimal 2296 digits. 2297 2298 * An optional exponent, consisting of: 2299 2300 * An 'E' or 'e'. 2301 * Optional sign: either '+' or '-'. 2302 * One or more decimal digits. 2303 2304 At least one of the integer part or the fractional part must be 2305present. The floating point number has the usual base-10 value. 2306 2307 'as' does all processing using integers. Flonums are computed 2308independently of any floating point hardware in the computer running 2309'as'. 2310 2311 2312File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top 2313 23144 Sections and Relocation 2315************************* 2316 2317* Menu: 2318 2319* Secs Background:: Background 2320* Ld Sections:: Linker Sections 2321* As Sections:: Assembler Internal Sections 2322* Sub-Sections:: Sub-Sections 2323* bss:: bss Section 2324 2325 2326File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections 2327 23284.1 Background 2329============== 2330 2331Roughly, a section is a range of addresses, with no gaps; all data "in" 2332those addresses is treated the same for some particular purpose. For 2333example there may be a "read only" section. 2334 2335 The linker 'ld' reads many object files (partial programs) and 2336combines their contents to form a runnable program. When 'as' emits an 2337object file, the partial program is assumed to start at address 0. 'ld' 2338assigns the final addresses for the partial program, so that different 2339partial programs do not overlap. This is actually an 2340oversimplification, but it suffices to explain how 'as' uses sections. 2341 2342 'ld' moves blocks of bytes of your program to their run-time 2343addresses. These blocks slide to their run-time addresses as rigid 2344units; their length does not change and neither does the order of bytes 2345within them. Such a rigid unit is called a _section_. Assigning 2346run-time addresses to sections is called "relocation". It includes the 2347task of adjusting mentions of object-file addresses so they refer to the 2348proper run-time addresses. For the H8/300, and for the Renesas / SuperH 2349SH, 'as' pads sections if needed to ensure they end on a word (sixteen 2350bit) boundary. 2351 2352 An object file written by 'as' has at least three sections, any of 2353which may be empty. These are named "text", "data" and "bss" sections. 2354 2355 When it generates COFF or ELF output, 'as' can also generate whatever 2356other named sections you specify using the '.section' directive (*note 2357'.section': Section.). If you do not use any directives that place 2358output in the '.text' or '.data' sections, these sections still exist, 2359but are empty. 2360 2361 When 'as' generates SOM or ELF output for the HPPA, 'as' can also 2362generate whatever other named sections you specify using the '.space' 2363and '.subspace' directives. See 'HP9000 Series 800 Assembly Language 2364Reference Manual' (HP 92432-90001) for details on the '.space' and 2365'.subspace' assembler directives. 2366 2367 Additionally, 'as' uses different names for the standard text, data, 2368and bss sections when generating SOM output. Program text is placed 2369into the '$CODE$' section, data into '$DATA$', and BSS into '$BSS$'. 2370 2371 Within the object file, the text section starts at address '0', the 2372data section follows, and the bss section follows the data section. 2373 2374 When generating either SOM or ELF output files on the HPPA, the text 2375section starts at address '0', the data section at address '0x4000000', 2376and the bss section follows the data section. 2377 2378 To let 'ld' know which data changes when the sections are relocated, 2379and how to change that data, 'as' also writes to the object file details 2380of the relocation needed. To perform relocation 'ld' must know, each 2381time an address in the object file is mentioned: 2382 * Where in the object file is the beginning of this reference to an 2383 address? 2384 * How long (in bytes) is this reference? 2385 * Which section does the address refer to? What is the numeric value 2386 of 2387 (ADDRESS) - (START-ADDRESS OF SECTION)? 2388 * Is the reference to an address "Program-Counter relative"? 2389 2390 In fact, every address 'as' ever uses is expressed as 2391 (SECTION) + (OFFSET INTO SECTION) 2392Further, most expressions 'as' computes have this section-relative 2393nature. (For some object formats, such as SOM for the HPPA, some 2394expressions are symbol-relative instead.) 2395 2396 In this manual we use the notation {SECNAME N} to mean "offset N into 2397section SECNAME." 2398 2399 Apart from text, data and bss sections you need to know about the 2400"absolute" section. When 'ld' mixes partial programs, addresses in the 2401absolute section remain unchanged. For example, address '{absolute 0}' 2402is "relocated" to run-time address 0 by 'ld'. Although the linker never 2403arranges two partial programs' data sections with overlapping addresses 2404after linking, _by definition_ their absolute sections must overlap. 2405Address '{absolute 239}' in one part of a program is always the same 2406address when the program is running as address '{absolute 239}' in any 2407other part of the program. 2408 2409 The idea of sections is extended to the "undefined" section. Any 2410address whose section is unknown at assembly time is by definition 2411rendered {undefined U}--where U is filled in later. Since numbers are 2412always defined, the only way to generate an undefined address is to 2413mention an undefined symbol. A reference to a named common block would 2414be such a symbol: its value is unknown at assembly time so it has 2415section _undefined_. 2416 2417 By analogy the word _section_ is used to describe groups of sections 2418in the linked program. 'ld' puts all partial programs' text sections in 2419contiguous addresses in the linked program. It is customary to refer to 2420the _text section_ of a program, meaning all the addresses of all 2421partial programs' text sections. Likewise for data and bss sections. 2422 2423 Some sections are manipulated by 'ld'; others are invented for use of 2424'as' and have no meaning except during assembly. 2425 2426 2427File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections 2428 24294.2 Linker Sections 2430=================== 2431 2432'ld' deals with just four kinds of sections, summarized below. 2433 2434*named sections* 2435*text section* 2436*data section* 2437 These sections hold your program. 'as' and 'ld' treat them as 2438 separate but equal sections. Anything you can say of one section 2439 is true of another. When the program is running, however, it is 2440 customary for the text section to be unalterable. The text section 2441 is often shared among processes: it contains instructions, 2442 constants and the like. The data section of a running program is 2443 usually alterable: for example, C variables would be stored in the 2444 data section. 2445 2446*bss section* 2447 This section contains zeroed bytes when your program begins 2448 running. It is used to hold uninitialized variables or common 2449 storage. The length of each partial program's bss section is 2450 important, but because it starts out containing zeroed bytes there 2451 is no need to store explicit zero bytes in the object file. The 2452 bss section was invented to eliminate those explicit zeros from 2453 object files. 2454 2455*absolute section* 2456 Address 0 of this section is always "relocated" to runtime address 2457 0. This is useful if you want to refer to an address that 'ld' 2458 must not change when relocating. In this sense we speak of 2459 absolute addresses being "unrelocatable": they do not change during 2460 relocation. 2461 2462*undefined section* 2463 This "section" is a catch-all for address references to objects not 2464 in the preceding sections. 2465 2466 An idealized example of three relocatable sections follows. The 2467example uses the traditional section names '.text' and '.data'. Memory 2468addresses are on the horizontal axis. 2469 2470 +-----+----+--+ 2471 partial program # 1: |ttttt|dddd|00| 2472 +-----+----+--+ 2473 2474 text data bss 2475 seg. seg. seg. 2476 2477 +---+---+---+ 2478 partial program # 2: |TTT|DDD|000| 2479 +---+---+---+ 2480 2481 +--+---+-----+--+----+---+-----+~~ 2482 linked program: | |TTT|ttttt| |dddd|DDD|00000| 2483 +--+---+-----+--+----+---+-----+~~ 2484 2485 addresses: 0 ... 2486 2487 2488File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections 2489 24904.3 Assembler Internal Sections 2491=============================== 2492 2493These sections are meant only for the internal use of 'as'. They have 2494no meaning at run-time. You do not really need to know about these 2495sections for most purposes; but they can be mentioned in 'as' warning 2496messages, so it might be helpful to have an idea of their meanings to 2497'as'. These sections are used to permit the value of every expression 2498in your assembly language program to be a section-relative address. 2499 2500ASSEMBLER-INTERNAL-LOGIC-ERROR! 2501 An internal assembler logic error has been found. This means there 2502 is a bug in the assembler. 2503 2504expr section 2505 The assembler stores complex expression internally as combinations 2506 of symbols. When it needs to represent an expression as a symbol, 2507 it puts it in the expr section. 2508 2509 2510File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections 2511 25124.4 Sub-Sections 2513================ 2514 2515Assembled bytes conventionally fall into two sections: text and data. 2516You may have separate groups of data in named sections that you want to 2517end up near to each other in the object file, even though they are not 2518contiguous in the assembler source. 'as' allows you to use 2519"subsections" for this purpose. Within each section, there can be 2520numbered subsections with values from 0 to 8192. Objects assembled into 2521the same subsection go into the object file together with other objects 2522in the same subsection. For example, a compiler might want to store 2523constants in the text section, but might not want to have them 2524interspersed with the program being assembled. In this case, the 2525compiler could issue a '.text 0' before each section of code being 2526output, and a '.text 1' before each group of constants being output. 2527 2528 Subsections are optional. If you do not use subsections, everything 2529goes in subsection number zero. 2530 2531 Each subsection is zero-padded up to a multiple of four bytes. 2532(Subsections may be padded a different amount on different flavors of 2533'as'.) 2534 2535 Subsections appear in your object file in numeric order, lowest 2536numbered to highest. (All this to be compatible with other people's 2537assemblers.) The object file contains no representation of subsections; 2538'ld' and other programs that manipulate object files see no trace of 2539them. They just see all your text subsections as a text section, and 2540all your data subsections as a data section. 2541 2542 To specify which subsection you want subsequent statements assembled 2543into, use a numeric argument to specify it, in a '.text EXPRESSION' or a 2544'.data EXPRESSION' statement. When generating COFF output, you can also 2545use an extra subsection argument with arbitrary named sections: 2546'.section NAME, EXPRESSION'. When generating ELF output, you can also 2547use the '.subsection' directive (*note SubSection::) to specify a 2548subsection: '.subsection EXPRESSION'. EXPRESSION should be an absolute 2549expression (*note Expressions::). If you just say '.text' then '.text 25500' is assumed. Likewise '.data' means '.data 0'. Assembly begins in 2551'text 0'. For instance: 2552 .text 0 # The default subsection is text 0 anyway. 2553 .ascii "This lives in the first text subsection. *" 2554 .text 1 2555 .ascii "But this lives in the second text subsection." 2556 .data 0 2557 .ascii "This lives in the data section," 2558 .ascii "in the first data subsection." 2559 .text 0 2560 .ascii "This lives in the first text section," 2561 .ascii "immediately following the asterisk (*)." 2562 2563 Each section has a "location counter" incremented by one for every 2564byte assembled into that section. Because subsections are merely a 2565convenience restricted to 'as' there is no concept of a subsection 2566location counter. There is no way to directly manipulate a location 2567counter--but the '.align' directive changes it, and any label definition 2568captures its current value. The location counter of the section where 2569statements are being assembled is said to be the "active" location 2570counter. 2571 2572 2573File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections 2574 25754.5 bss Section 2576=============== 2577 2578The bss section is used for local common variable storage. You may 2579allocate address space in the bss section, but you may not dictate data 2580to load into it before your program executes. When your program starts 2581running, all the contents of the bss section are zeroed bytes. 2582 2583 The '.lcomm' pseudo-op defines a symbol in the bss section; see *note 2584'.lcomm': Lcomm. 2585 2586 The '.comm' pseudo-op may be used to declare a common symbol, which 2587is another form of uninitialized symbol; see *note '.comm': Comm. 2588 2589 When assembling for a target which supports multiple sections, such 2590as ELF or COFF, you may switch into the '.bss' section and define 2591symbols as usual; see *note '.section': Section. You may only assemble 2592zero values into the section. Typically the section will only contain 2593symbol definitions and '.skip' directives (*note '.skip': Skip.). 2594 2595 2596File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top 2597 25985 Symbols 2599********* 2600 2601Symbols are a central concept: the programmer uses symbols to name 2602things, the linker uses symbols to link, and the debugger uses symbols 2603to debug. 2604 2605 _Warning:_ 'as' does not place symbols in the object file in the 2606 same order they were declared. This may break some debuggers. 2607 2608* Menu: 2609 2610* Labels:: Labels 2611* Setting Symbols:: Giving Symbols Other Values 2612* Symbol Names:: Symbol Names 2613* Dot:: The Special Dot Symbol 2614* Symbol Attributes:: Symbol Attributes 2615 2616 2617File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 2618 26195.1 Labels 2620========== 2621 2622A "label" is written as a symbol immediately followed by a colon ':'. 2623The symbol then represents the current value of the active location 2624counter, and is, for example, a suitable instruction operand. You are 2625warned if you use the same symbol to represent two different locations: 2626the first definition overrides any other definitions. 2627 2628 On the HPPA, the usual form for a label need not be immediately 2629followed by a colon, but instead must start in column zero. Only one 2630label may be defined on a single line. To work around this, the HPPA 2631version of 'as' also provides a special directive '.label' for defining 2632labels more flexibly. 2633 2634 2635File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols 2636 26375.2 Giving Symbols Other Values 2638=============================== 2639 2640A symbol can be given an arbitrary value by writing a symbol, followed 2641by an equals sign '=', followed by an expression (*note Expressions::). 2642This is equivalent to using the '.set' directive. *Note '.set': Set. 2643In the same way, using a double equals sign '=''=' here represents an 2644equivalent of the '.eqv' directive. *Note '.eqv': Eqv. 2645 2646 Blackfin does not support symbol assignment with '='. 2647 2648 2649File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols 2650 26515.3 Symbol Names 2652================ 2653 2654Symbol names begin with a letter or with one of '._'. On most machines, 2655you can also use '$' in symbol names; exceptions are noted in *note 2656Machine Dependencies::. That character may be followed by any string of 2657digits, letters, dollar signs (unless otherwise noted for a particular 2658target machine), and underscores. 2659 2660 Case of letters is significant: 'foo' is a different symbol name than 2661'Foo'. 2662 2663 Symbol names do not start with a digit. An exception to this rule is 2664made for Local Labels. See below. 2665 2666 Multibyte characters are supported. To generate a symbol name 2667containing multibyte characters enclose it within double quotes and use 2668escape codes. cf *Note Strings::. Generating a multibyte symbol name 2669from a label is not currently supported. 2670 2671 Each symbol has exactly one name. Each name in an assembly language 2672program refers to exactly one symbol. You may use that symbol name any 2673number of times in a program. 2674 2675Local Symbol Names 2676------------------ 2677 2678A local symbol is any symbol beginning with certain local label 2679prefixes. By default, the local label prefix is '.L' for ELF systems or 2680'L' for traditional a.out systems, but each target may have its own set 2681of local label prefixes. On the HPPA local symbols begin with 'L$'. 2682 2683 Local symbols are defined and used within the assembler, but they are 2684normally not saved in object files. Thus, they are not visible when 2685debugging. You may use the '-L' option (*note Include Local Symbols: 2686L.) to retain the local symbols in the object files. 2687 2688Local Labels 2689------------ 2690 2691Local labels are different from local symbols. Local labels help 2692compilers and programmers use names temporarily. They create symbols 2693which are guaranteed to be unique over the entire scope of the input 2694source code and which can be referred to by a simple notation. To 2695define a local label, write a label of the form 'N:' (where N represents 2696any non-negative integer). To refer to the most recent previous 2697definition of that label write 'Nb', using the same number as when you 2698defined the label. To refer to the next definition of a local label, 2699write 'Nf'. The 'b' stands for "backwards" and the 'f' stands for 2700"forwards". 2701 2702 There is no restriction on how you can use these labels, and you can 2703reuse them too. So that it is possible to repeatedly define the same 2704local label (using the same number 'N'), although you can only refer to 2705the most recently defined local label of that number (for a backwards 2706reference) or the next definition of a specific local label for a 2707forward reference. It is also worth noting that the first 10 local 2708labels ('0:'...'9:') are implemented in a slightly more efficient manner 2709than the others. 2710 2711 Here is an example: 2712 2713 1: branch 1f 2714 2: branch 1b 2715 1: branch 2f 2716 2: branch 1b 2717 2718 Which is the equivalent of: 2719 2720 label_1: branch label_3 2721 label_2: branch label_1 2722 label_3: branch label_4 2723 label_4: branch label_3 2724 2725 Local label names are only a notational device. They are immediately 2726transformed into more conventional symbol names before the assembler 2727uses them. The symbol names are stored in the symbol table, appear in 2728error messages, and are optionally emitted to the object file. The 2729names are constructed using these parts: 2730 2731'_local label prefix_' 2732 All local symbols begin with the system-specific local label 2733 prefix. Normally both 'as' and 'ld' forget symbols that start with 2734 the local label prefix. These labels are used for symbols you are 2735 never intended to see. If you use the '-L' option then 'as' 2736 retains these symbols in the object file. If you also instruct 2737 'ld' to retain these symbols, you may use them in debugging. 2738 2739'NUMBER' 2740 This is the number that was used in the local label definition. So 2741 if the label is written '55:' then the number is '55'. 2742 2743'C-B' 2744 This unusual character is included so you do not accidentally 2745 invent a symbol of the same name. The character has ASCII value of 2746 '\002' (control-B). 2747 2748'_ordinal number_' 2749 This is a serial number to keep the labels distinct. The first 2750 definition of '0:' gets the number '1'. The 15th definition of 2751 '0:' gets the number '15', and so on. Likewise the first 2752 definition of '1:' gets the number '1' and its 15th definition gets 2753 '15' as well. 2754 2755 So for example, the first '1:' may be named '.L1C-B1', and the 44th 2756'3:' may be named '.L3C-B44'. 2757 2758Dollar Local Labels 2759------------------- 2760 2761On some targets 'as' also supports an even more local form of local 2762labels called dollar labels. These labels go out of scope (i.e., they 2763become undefined) as soon as a non-local label is defined. Thus they 2764remain valid for only a small region of the input source code. Normal 2765local labels, by contrast, remain in scope for the entire file, or until 2766they are redefined by another occurrence of the same local label. 2767 2768 Dollar labels are defined in exactly the same way as ordinary local 2769labels, except that they have a dollar sign suffix to their numeric 2770value, e.g., '55$:'. 2771 2772 They can also be distinguished from ordinary local labels by their 2773transformed names which use ASCII character '\001' (control-A) as the 2774magic character to distinguish them from ordinary labels. For example, 2775the fifth definition of '6$' may be named '.L6'C-A'5'. 2776 2777 2778File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols 2779 27805.4 The Special Dot Symbol 2781========================== 2782 2783The special symbol '.' refers to the current address that 'as' is 2784assembling into. Thus, the expression 'melvin: .long .' defines 2785'melvin' to contain its own address. Assigning a value to '.' is 2786treated the same as a '.org' directive. Thus, the expression '.=.+4' is 2787the same as saying '.space 4'. 2788 2789 2790File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols 2791 27925.5 Symbol Attributes 2793===================== 2794 2795Every symbol has, as well as its name, the attributes "Value" and 2796"Type". Depending on output format, symbols can also have auxiliary 2797attributes. 2798 2799 If you use a symbol without defining it, 'as' assumes zero for all 2800these attributes, and probably won't warn you. This makes the symbol an 2801externally defined symbol, which is generally what you would want. 2802 2803* Menu: 2804 2805* Symbol Value:: Value 2806* Symbol Type:: Type 2807* a.out Symbols:: Symbol Attributes: 'a.out' 2808* COFF Symbols:: Symbol Attributes for COFF 2809* SOM Symbols:: Symbol Attributes for SOM 2810 2811 2812File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes 2813 28145.5.1 Value 2815----------- 2816 2817The value of a symbol is (usually) 32 bits. For a symbol which labels a 2818location in the text, data, bss or absolute sections the value is the 2819number of addresses from the start of that section to the label. 2820Naturally for text, data and bss sections the value of a symbol changes 2821as 'ld' changes section base addresses during linking. Absolute 2822symbols' values do not change during linking: that is why they are 2823called absolute. 2824 2825 The value of an undefined symbol is treated in a special way. If it 2826is 0 then the symbol is not defined in this assembler source file, and 2827'ld' tries to determine its value from other files linked into the same 2828program. You make this kind of symbol simply by mentioning a symbol 2829name without defining it. A non-zero value represents a '.comm' common 2830declaration. The value is how much common storage to reserve, in bytes 2831(addresses). The symbol refers to the first address of the allocated 2832storage. 2833 2834 2835File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes 2836 28375.5.2 Type 2838---------- 2839 2840The type attribute of a symbol contains relocation (section) 2841information, any flag settings indicating that a symbol is external, and 2842(optionally), other information for linkers and debuggers. The exact 2843format depends on the object-code output format in use. 2844 2845 2846File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes 2847 28485.5.3 Symbol Attributes: 'a.out' 2849-------------------------------- 2850 2851* Menu: 2852 2853* Symbol Desc:: Descriptor 2854* Symbol Other:: Other 2855 2856 2857File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols 2858 28595.5.3.1 Descriptor 2860.................. 2861 2862This is an arbitrary 16-bit value. You may establish a symbol's 2863descriptor value by using a '.desc' statement (*note '.desc': Desc.). A 2864descriptor value means nothing to 'as'. 2865 2866 2867File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 2868 28695.5.3.2 Other 2870............. 2871 2872This is an arbitrary 8-bit value. It means nothing to 'as'. 2873 2874 2875File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes 2876 28775.5.4 Symbol Attributes for COFF 2878-------------------------------- 2879 2880The COFF format supports a multitude of auxiliary symbol attributes; 2881like the primary symbol attributes, they are set between '.def' and 2882'.endef' directives. 2883 28845.5.4.1 Primary Attributes 2885.......................... 2886 2887The symbol name is set with '.def'; the value and type, respectively, 2888with '.val' and '.type'. 2889 28905.5.4.2 Auxiliary Attributes 2891............................ 2892 2893The 'as' directives '.dim', '.line', '.scl', '.size', '.tag', and 2894'.weak' can generate auxiliary symbol table information for COFF. 2895 2896 2897File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes 2898 28995.5.5 Symbol Attributes for SOM 2900------------------------------- 2901 2902The SOM format for the HPPA supports a multitude of symbol attributes 2903set with the '.EXPORT' and '.IMPORT' directives. 2904 2905 The attributes are described in 'HP9000 Series 800 Assembly Language 2906Reference Manual' (HP 92432-90001) under the 'IMPORT' and 'EXPORT' 2907assembler directive documentation. 2908 2909 2910File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top 2911 29126 Expressions 2913************* 2914 2915An "expression" specifies an address or numeric value. Whitespace may 2916precede and/or follow an expression. 2917 2918 The result of an expression must be an absolute number, or else an 2919offset into a particular section. If an expression is not absolute, and 2920there is not enough information when 'as' sees the expression to know 2921its section, a second pass over the source program might be necessary to 2922interpret the expression--but the second pass is currently not 2923implemented. 'as' aborts with an error message in this situation. 2924 2925* Menu: 2926 2927* Empty Exprs:: Empty Expressions 2928* Integer Exprs:: Integer Expressions 2929 2930 2931File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions 2932 29336.1 Empty Expressions 2934===================== 2935 2936An empty expression has no value: it is just whitespace or null. 2937Wherever an absolute expression is required, you may omit the 2938expression, and 'as' assumes a value of (absolute) 0. This is 2939compatible with other assemblers. 2940 2941 2942File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions 2943 29446.2 Integer Expressions 2945======================= 2946 2947An "integer expression" is one or more _arguments_ delimited by 2948_operators_. 2949 2950* Menu: 2951 2952* Arguments:: Arguments 2953* Operators:: Operators 2954* Prefix Ops:: Prefix Operators 2955* Infix Ops:: Infix Operators 2956 2957 2958File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs 2959 29606.2.1 Arguments 2961--------------- 2962 2963"Arguments" are symbols, numbers or subexpressions. In other contexts 2964arguments are sometimes called "arithmetic operands". In this manual, 2965to avoid confusing them with the "instruction operands" of the machine 2966language, we use the term "argument" to refer to parts of expressions 2967only, reserving the word "operand" to refer only to machine instruction 2968operands. 2969 2970 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of 2971text, data, bss, absolute, or undefined. NNN is a signed, 2's 2972complement 32 bit integer. 2973 2974 Numbers are usually integers. 2975 2976 A number can be a flonum or bignum. In this case, you are warned 2977that only the low order 32 bits are used, and 'as' pretends these 32 2978bits are an integer. You may write integer-manipulating instructions 2979that act on exotic constants, compatible with other assemblers. 2980 2981 Subexpressions are a left parenthesis '(' followed by an integer 2982expression, followed by a right parenthesis ')'; or a prefix operator 2983followed by an argument. 2984 2985 2986File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs 2987 29886.2.2 Operators 2989--------------- 2990 2991"Operators" are arithmetic functions, like '+' or '%'. Prefix operators 2992are followed by an argument. Infix operators appear between their 2993arguments. Operators may be preceded and/or followed by whitespace. 2994 2995 2996File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs 2997 29986.2.3 Prefix Operator 2999--------------------- 3000 3001'as' has the following "prefix operators". They each take one argument, 3002which must be absolute. 3003 3004'-' 3005 "Negation". Two's complement negation. 3006'~' 3007 "Complementation". Bitwise not. 3008 3009 3010File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs 3011 30126.2.4 Infix Operators 3013--------------------- 3014 3015"Infix operators" take two arguments, one on either side. Operators 3016have precedence, but operations with equal precedence are performed left 3017to right. Apart from '+' or '-', both arguments must be absolute, and 3018the result is absolute. 3019 3020 1. Highest Precedence 3021 3022 '*' 3023 "Multiplication". 3024 3025 '/' 3026 "Division". Truncation is the same as the C operator '/' 3027 3028 '%' 3029 "Remainder". 3030 3031 '<<' 3032 "Shift Left". Same as the C operator '<<'. 3033 3034 '>>' 3035 "Shift Right". Same as the C operator '>>'. 3036 3037 2. Intermediate precedence 3038 3039 '|' 3040 3041 "Bitwise Inclusive Or". 3042 3043 '&' 3044 "Bitwise And". 3045 3046 '^' 3047 "Bitwise Exclusive Or". 3048 3049 '!' 3050 "Bitwise Or Not". 3051 3052 3. Low Precedence 3053 3054 '+' 3055 "Addition". If either argument is absolute, the result has 3056 the section of the other argument. You may not add together 3057 arguments from different sections. 3058 3059 '-' 3060 "Subtraction". If the right argument is absolute, the result 3061 has the section of the left argument. If both arguments are 3062 in the same section, the result is absolute. You may not 3063 subtract arguments from different sections. 3064 3065 '==' 3066 "Is Equal To" 3067 '<>' 3068 '!=' 3069 "Is Not Equal To" 3070 '<' 3071 "Is Less Than" 3072 '>' 3073 "Is Greater Than" 3074 '>=' 3075 "Is Greater Than Or Equal To" 3076 '<=' 3077 "Is Less Than Or Equal To" 3078 3079 The comparison operators can be used as infix operators. A 3080 true results has a value of -1 whereas a false result has a 3081 value of 0. Note, these operators perform signed comparisons. 3082 3083 4. Lowest Precedence 3084 3085 '&&' 3086 "Logical And". 3087 3088 '||' 3089 "Logical Or". 3090 3091 These two logical operations can be used to combine the 3092 results of sub expressions. Note, unlike the comparison 3093 operators a true result returns a value of 1 but a false 3094 results does still return 0. Also note that the logical or 3095 operator has a slightly lower precedence than logical and. 3096 3097 In short, it's only meaningful to add or subtract the _offsets_ in an 3098address; you can only have a defined section in one of the two 3099arguments. 3100 3101 3102File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top 3103 31047 Assembler Directives 3105********************** 3106 3107All assembler directives have names that begin with a period ('.'). The 3108names are case insensitive for most targets, and usually written in 3109lower case. 3110 3111 This chapter discusses directives that are available regardless of 3112the target machine configuration for the GNU assembler. Some machine 3113configurations provide additional directives. *Note Machine 3114Dependencies::. 3115 3116* Menu: 3117 3118* Abort:: '.abort' 3119* ABORT (COFF):: '.ABORT' 3120 3121* Align:: '.align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 3122* Altmacro:: '.altmacro' 3123* Ascii:: '.ascii "STRING"'... 3124* Asciz:: '.asciz "STRING"'... 3125* Attach_to_group:: '.attach_to_group NAME' 3126* Balign:: '.balign [ABS-EXPR[, ABS-EXPR]]' 3127* Bss:: '.bss SUBSECTION' 3128* Bundle directives:: '.bundle_align_mode ABS-EXPR', etc 3129* Byte:: '.byte EXPRESSIONS' 3130* CFI directives:: '.cfi_startproc [simple]', '.cfi_endproc', etc. 3131* Comm:: '.comm SYMBOL , LENGTH ' 3132* Data:: '.data SUBSECTION' 3133* Dc:: '.dc[SIZE] EXPRESSIONS' 3134* Dcb:: '.dcb[SIZE] NUMBER [,FILL]' 3135* Ds:: '.ds[SIZE] NUMBER [,FILL]' 3136* Def:: '.def NAME' 3137* Desc:: '.desc SYMBOL, ABS-EXPRESSION' 3138* Dim:: '.dim' 3139 3140* Double:: '.double FLONUMS' 3141* Eject:: '.eject' 3142* Else:: '.else' 3143* Elseif:: '.elseif' 3144* End:: '.end' 3145* Endef:: '.endef' 3146 3147* Endfunc:: '.endfunc' 3148* Endif:: '.endif' 3149* Equ:: '.equ SYMBOL, EXPRESSION' 3150* Equiv:: '.equiv SYMBOL, EXPRESSION' 3151* Eqv:: '.eqv SYMBOL, EXPRESSION' 3152* Err:: '.err' 3153* Error:: '.error STRING' 3154* Exitm:: '.exitm' 3155* Extern:: '.extern' 3156* Fail:: '.fail' 3157* File:: '.file' 3158* Fill:: '.fill REPEAT , SIZE , VALUE' 3159* Float:: '.float FLONUMS' 3160* Func:: '.func' 3161* Global:: '.global SYMBOL', '.globl SYMBOL' 3162* Gnu_attribute:: '.gnu_attribute TAG,VALUE' 3163* Hidden:: '.hidden NAMES' 3164 3165* hword:: '.hword EXPRESSIONS' 3166* Ident:: '.ident' 3167* If:: '.if ABSOLUTE EXPRESSION' 3168* Incbin:: '.incbin "FILE"[,SKIP[,COUNT]]' 3169* Include:: '.include "FILE"' 3170* Int:: '.int EXPRESSIONS' 3171* Internal:: '.internal NAMES' 3172 3173* Irp:: '.irp SYMBOL,VALUES'... 3174* Irpc:: '.irpc SYMBOL,VALUES'... 3175* Lcomm:: '.lcomm SYMBOL , LENGTH' 3176* Lflags:: '.lflags' 3177* Line:: '.line LINE-NUMBER' 3178 3179* Linkonce:: '.linkonce [TYPE]' 3180* List:: '.list' 3181* Ln:: '.ln LINE-NUMBER' 3182* Loc:: '.loc FILENO LINENO' 3183* Loc_mark_labels:: '.loc_mark_labels ENABLE' 3184* Local:: '.local NAMES' 3185 3186* Long:: '.long EXPRESSIONS' 3187 3188* Macro:: '.macro NAME ARGS'... 3189* MRI:: '.mri VAL' 3190* Noaltmacro:: '.noaltmacro' 3191* Nolist:: '.nolist' 3192* Nop:: '.nop' 3193* Nops:: '.nops SIZE[, CONTROL]' 3194* Octa:: '.octa BIGNUMS' 3195* Offset:: '.offset LOC' 3196* Org:: '.org NEW-LC, FILL' 3197* P2align:: '.p2align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 3198* PopSection:: '.popsection' 3199* Previous:: '.previous' 3200 3201* Print:: '.print STRING' 3202* Protected:: '.protected NAMES' 3203 3204* Psize:: '.psize LINES, COLUMNS' 3205* Purgem:: '.purgem NAME' 3206* PushSection:: '.pushsection NAME' 3207 3208* Quad:: '.quad BIGNUMS' 3209* Reloc:: '.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 3210* Rept:: '.rept COUNT' 3211* Sbttl:: '.sbttl "SUBHEADING"' 3212* Scl:: '.scl CLASS' 3213* Section:: '.section NAME[, FLAGS]' 3214 3215* Set:: '.set SYMBOL, EXPRESSION' 3216* Short:: '.short EXPRESSIONS' 3217* Single:: '.single FLONUMS' 3218* Size:: '.size [NAME , EXPRESSION]' 3219* Skip:: '.skip SIZE [,FILL]' 3220 3221* Sleb128:: '.sleb128 EXPRESSIONS' 3222* Space:: '.space SIZE [,FILL]' 3223* Stab:: '.stabd, .stabn, .stabs' 3224 3225* String:: '.string "STR"', '.string8 "STR"', '.string16 "STR"', '.string32 "STR"', '.string64 "STR"' 3226* Struct:: '.struct EXPRESSION' 3227* SubSection:: '.subsection' 3228* Symver:: '.symver NAME,NAME2@NODENAME[,VISIBILITY]' 3229 3230* Tag:: '.tag STRUCTNAME' 3231 3232* Text:: '.text SUBSECTION' 3233* Title:: '.title "HEADING"' 3234* Tls_common:: '.tls_common SYMBOL, LENGTH[, ALIGNMENT]' 3235* Type:: '.type <INT | NAME , TYPE DESCRIPTION>' 3236 3237* Uleb128:: '.uleb128 EXPRESSIONS' 3238* Val:: '.val ADDR' 3239 3240* Version:: '.version "STRING"' 3241* VTableEntry:: '.vtable_entry TABLE, OFFSET' 3242* VTableInherit:: '.vtable_inherit CHILD, PARENT' 3243 3244* Warning:: '.warning STRING' 3245* Weak:: '.weak NAMES' 3246* Weakref:: '.weakref ALIAS, SYMBOL' 3247* Word:: '.word EXPRESSIONS' 3248* Zero:: '.zero SIZE' 3249* 2byte:: '.2byte EXPRESSIONS' 3250* 4byte:: '.4byte EXPRESSIONS' 3251* 8byte:: '.8byte BIGNUMS' 3252* Deprecated:: Deprecated Directives 3253 3254 3255File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops 3256 32577.1 '.abort' 3258============ 3259 3260This directive stops the assembly immediately. It is for compatibility 3261with other assemblers. The original idea was that the assembly language 3262source would be piped into the assembler. If the sender of the source 3263quit, it could use this directive tells 'as' to quit also. One day 3264'.abort' will not be supported. 3265 3266 3267File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops 3268 32697.2 '.ABORT' (COFF) 3270=================== 3271 3272When producing COFF output, 'as' accepts this directive as a synonym for 3273'.abort'. 3274 3275 3276File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops 3277 32787.3 '.align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 3279=============================================== 3280 3281Pad the location counter (in the current subsection) to a particular 3282storage boundary. The first expression (which must be absolute) is the 3283alignment required, as described below. If this expression is omitted 3284then a default value of 0 is used, effectively disabling alignment 3285requirements. 3286 3287 The second expression (also absolute) gives the fill value to be 3288stored in the padding bytes. It (and the comma) may be omitted. If it 3289is omitted, the padding bytes are normally zero. However, on most 3290systems, if the section is marked as containing code and the fill value 3291is omitted, the space is filled with no-op instructions. 3292 3293 The third expression is also absolute, and is also optional. If it 3294is present, it is the maximum number of bytes that should be skipped by 3295this alignment directive. If doing the alignment would require skipping 3296more bytes than the specified maximum, then the alignment is not done at 3297all. You can omit the fill value (the second argument) entirely by 3298simply using two commas after the required alignment; this can be useful 3299if you want the alignment to be filled with no-op instructions when 3300appropriate. 3301 3302 The way the required alignment is specified varies from system to 3303system. For the arc, hppa, i386 using ELF, iq2000, m68k, or1k, s390, 3304sparc, tic4x and xtensa, the first expression is the alignment request 3305in bytes. For example '.align 8' advances the location counter until it 3306is a multiple of 8. If the location counter is already a multiple of 8, 3307no change is needed. For the tic54x, the first expression is the 3308alignment request in words. 3309 3310 For other systems, including ppc, i386 using a.out format, arm and 3311strongarm, it is the number of low-order zero bits the location counter 3312must have after advancement. For example '.align 3' advances the 3313location counter until it is a multiple of 8. If the location counter 3314is already a multiple of 8, no change is needed. 3315 3316 This inconsistency is due to the different behaviors of the various 3317native assemblers for these systems which GAS must emulate. GAS also 3318provides '.balign' and '.p2align' directives, described later, which 3319have a consistent behavior across all architectures (but are specific to 3320GAS). 3321 3322 3323File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops 3324 33257.4 '.altmacro' 3326=============== 3327 3328Enable alternate macro mode, enabling: 3329 3330'LOCAL NAME [ , ... ]' 3331 One additional directive, 'LOCAL', is available. It is used to 3332 generate a string replacement for each of the NAME arguments, and 3333 replace any instances of NAME in each macro expansion. The 3334 replacement string is unique in the assembly, and different for 3335 each separate macro expansion. 'LOCAL' allows you to write macros 3336 that define symbols, without fear of conflict between separate 3337 macro expansions. 3338 3339'String delimiters' 3340 You can write strings delimited in these other ways besides 3341 '"STRING"': 3342 3343 ''STRING'' 3344 You can delimit strings with single-quote characters. 3345 3346 '<STRING>' 3347 You can delimit strings with matching angle brackets. 3348 3349'single-character string escape' 3350 To include any single character literally in a string (even if the 3351 character would otherwise have some special meaning), you can 3352 prefix the character with '!' (an exclamation mark). For example, 3353 you can write '<4.3 !> 5.4!!>' to get the literal text '4.3 > 3354 5.4!'. 3355 3356'Expression results as strings' 3357 You can write '%EXPR' to evaluate the expression EXPR and use the 3358 result as a string. 3359 3360 3361File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops 3362 33637.5 '.ascii "STRING"'... 3364======================== 3365 3366'.ascii' expects zero or more string literals (*note Strings::) 3367separated by commas. It assembles each string (with no automatic 3368trailing zero byte) into consecutive addresses. 3369 3370 3371File: as.info, Node: Asciz, Next: Attach_to_group, Prev: Ascii, Up: Pseudo Ops 3372 33737.6 '.asciz "STRING"'... 3374======================== 3375 3376'.asciz' is just like '.ascii', but each string is followed by a zero 3377byte. The "z" in '.asciz' stands for "zero". Note that multiple string 3378arguments not separated by commas will be concatenated together and only 3379one final zero byte will be stored. 3380 3381 3382File: as.info, Node: Attach_to_group, Next: Balign, Prev: Asciz, Up: Pseudo Ops 3383 33847.7 '.attach_to_group NAME' 3385=========================== 3386 3387Attaches the current section to the named group. This is like declaring 3388the section with the 'G' attribute, but can be done after the section 3389has been created. Note if the group section does not exist at the point 3390that this directive is used then it will be created. 3391 3392 3393File: as.info, Node: Balign, Next: Bss, Prev: Attach_to_group, Up: Pseudo Ops 3394 33957.8 '.balign[wl] [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 3396==================================================== 3397 3398Pad the location counter (in the current subsection) to a particular 3399storage boundary. The first expression (which must be absolute) is the 3400alignment request in bytes. For example '.balign 8' advances the 3401location counter until it is a multiple of 8. If the location counter 3402is already a multiple of 8, no change is needed. If the expression is 3403omitted then a default value of 0 is used, effectively disabling 3404alignment requirements. 3405 3406 The second expression (also absolute) gives the fill value to be 3407stored in the padding bytes. It (and the comma) may be omitted. If it 3408is omitted, the padding bytes are normally zero. However, on most 3409systems, if the section is marked as containing code and the fill value 3410is omitted, the space is filled with no-op instructions. 3411 3412 The third expression is also absolute, and is also optional. If it 3413is present, it is the maximum number of bytes that should be skipped by 3414this alignment directive. If doing the alignment would require skipping 3415more bytes than the specified maximum, then the alignment is not done at 3416all. You can omit the fill value (the second argument) entirely by 3417simply using two commas after the required alignment; this can be useful 3418if you want the alignment to be filled with no-op instructions when 3419appropriate. 3420 3421 The '.balignw' and '.balignl' directives are variants of the 3422'.balign' directive. The '.balignw' directive treats the fill pattern 3423as a two byte word value. The '.balignl' directives treats the fill 3424pattern as a four byte longword value. For example, '.balignw 4,0x368d' 3425will align to a multiple of 4. If it skips two bytes, they will be 3426filled in with the value 0x368d (the exact placement of the bytes 3427depends upon the endianness of the processor). If it skips 1 or 3 3428bytes, the fill value is undefined. 3429 3430 3431File: as.info, Node: Bss, Next: Bundle directives, Prev: Balign, Up: Pseudo Ops 3432 34337.9 '.bss SUBSECTION' 3434===================== 3435 3436'.bss' tells 'as' to assemble the following statements onto the end of 3437the bss section. For ELF based targets an optional SUBSECTION 3438expression (which must evaluate to a positive integer) can be provided. 3439In this case the statements are appended to the end of the indicated bss 3440subsection. 3441 3442 3443File: as.info, Node: Bundle directives, Next: Byte, Prev: Bss, Up: Pseudo Ops 3444 34457.10 Bundle directives 3446====================== 3447 34487.10.1 '.bundle_align_mode ABS-EXPR' 3449------------------------------------ 3450 3451'.bundle_align_mode' enables or disables "aligned instruction bundle" 3452mode. In this mode, sequences of adjacent instructions are grouped into 3453fixed-sized "bundles". If the argument is zero, this mode is disabled 3454(which is the default state). If the argument it not zero, it gives the 3455size of an instruction bundle as a power of two (as for the '.p2align' 3456directive, *note P2align::). 3457 3458 For some targets, it's an ABI requirement that no instruction may 3459span a certain aligned boundary. A "bundle" is simply a sequence of 3460instructions that starts on an aligned boundary. For example, if 3461ABS-EXPR is '5' then the bundle size is 32, so each aligned chunk of 32 3462bytes is a bundle. When aligned instruction bundle mode is in effect, 3463no single instruction may span a boundary between bundles. If an 3464instruction would start too close to the end of a bundle for the length 3465of that particular instruction to fit within the bundle, then the space 3466at the end of that bundle is filled with no-op instructions so the 3467instruction starts in the next bundle. As a corollary, it's an error if 3468any single instruction's encoding is longer than the bundle size. 3469 34707.10.2 '.bundle_lock' and '.bundle_unlock' 3471------------------------------------------ 3472 3473The '.bundle_lock' and directive '.bundle_unlock' directives allow 3474explicit control over instruction bundle padding. These directives are 3475only valid when '.bundle_align_mode' has been used to enable aligned 3476instruction bundle mode. It's an error if they appear when 3477'.bundle_align_mode' has not been used at all, or when the last 3478directive was '.bundle_align_mode 0'. 3479 3480 For some targets, it's an ABI requirement that certain instructions 3481may appear only as part of specified permissible sequences of multiple 3482instructions, all within the same bundle. A pair of '.bundle_lock' and 3483'.bundle_unlock' directives define a "bundle-locked" instruction 3484sequence. For purposes of aligned instruction bundle mode, a sequence 3485starting with '.bundle_lock' and ending with '.bundle_unlock' is treated 3486as a single instruction. That is, the entire sequence must fit into a 3487single bundle and may not span a bundle boundary. If necessary, no-op 3488instructions will be inserted before the first instruction of the 3489sequence so that the whole sequence starts on an aligned bundle 3490boundary. It's an error if the sequence is longer than the bundle size. 3491 3492 For convenience when using '.bundle_lock' and '.bundle_unlock' inside 3493assembler macros (*note Macro::), bundle-locked sequences may be nested. 3494That is, a second '.bundle_lock' directive before the next 3495'.bundle_unlock' directive has no effect except that it must be matched 3496by another closing '.bundle_unlock' so that there is the same number of 3497'.bundle_lock' and '.bundle_unlock' directives. 3498 3499 3500File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops 3501 35027.11 '.byte EXPRESSIONS' 3503======================== 3504 3505'.byte' expects zero or more expressions, separated by commas. Each 3506expression is assembled into the next byte. 3507 3508 3509File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops 3510 35117.12 CFI directives 3512=================== 3513 35147.12.1 '.cfi_sections SECTION_LIST' 3515----------------------------------- 3516 3517'.cfi_sections' may be used to specify whether CFI directives should 3518emit '.eh_frame' section and/or '.debug_frame' section. If SECTION_LIST 3519is '.eh_frame', '.eh_frame' is emitted, if SECTION_LIST is 3520'.debug_frame', '.debug_frame' is emitted. To emit both use '.eh_frame, 3521.debug_frame'. The default if this directive is not used is 3522'.cfi_sections .eh_frame'. 3523 3524 On targets that support compact unwinding tables these can be 3525generated by specifying '.eh_frame_entry' instead of '.eh_frame'. 3526 3527 Some targets may support an additional name, such as '.c6xabi.exidx' 3528which is used by the target. 3529 3530 The '.cfi_sections' directive can be repeated, with the same or 3531different arguments, provided that CFI generation has not yet started. 3532Once CFI generation has started however the section list is fixed and 3533any attempts to redefine it will result in an error. 3534 35357.12.2 '.cfi_startproc [simple]' 3536-------------------------------- 3537 3538'.cfi_startproc' is used at the beginning of each function that should 3539have an entry in '.eh_frame'. It initializes some internal data 3540structures. Don't forget to close the function by '.cfi_endproc'. 3541 3542 Unless '.cfi_startproc' is used along with parameter 'simple' it also 3543emits some architecture dependent initial CFI instructions. 3544 35457.12.3 '.cfi_endproc' 3546--------------------- 3547 3548'.cfi_endproc' is used at the end of a function where it closes its 3549unwind entry previously opened by '.cfi_startproc', and emits it to 3550'.eh_frame'. 3551 35527.12.4 '.cfi_personality ENCODING [, EXP]' 3553------------------------------------------ 3554 3555'.cfi_personality' defines personality routine and its encoding. 3556ENCODING must be a constant determining how the personality should be 3557encoded. If it is 255 ('DW_EH_PE_omit'), second argument is not 3558present, otherwise second argument should be a constant or a symbol 3559name. When using indirect encodings, the symbol provided should be the 3560location where personality can be loaded from, not the personality 3561routine itself. The default after '.cfi_startproc' is '.cfi_personality 35620xff', no personality routine. 3563 35647.12.5 '.cfi_personality_id ID' 3565------------------------------- 3566 3567'cfi_personality_id' defines a personality routine by its index as 3568defined in a compact unwinding format. Only valid when generating 3569compact EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3570 35717.12.6 '.cfi_fde_data [OPCODE1 [, ...]]' 3572---------------------------------------- 3573 3574'cfi_fde_data' is used to describe the compact unwind opcodes to be used 3575for the current function. These are emitted inline in the 3576'.eh_frame_entry' section if small enough and there is no LSDA, or in 3577the '.gnu.extab' section otherwise. Only valid when generating compact 3578EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3579 35807.12.7 '.cfi_lsda ENCODING [, EXP]' 3581----------------------------------- 3582 3583'.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant 3584determining how the LSDA should be encoded. If it is 255 3585('DW_EH_PE_omit'), the second argument is not present, otherwise the 3586second argument should be a constant or a symbol name. The default 3587after '.cfi_startproc' is '.cfi_lsda 0xff', meaning that no LSDA is 3588present. 3589 35907.12.8 '.cfi_inline_lsda' [ALIGN] 3591--------------------------------- 3592 3593'.cfi_inline_lsda' marks the start of a LSDA data section and switches 3594to the corresponding '.gnu.extab' section. Must be preceded by a CFI 3595block containing a '.cfi_lsda' directive. Only valid when generating 3596compact EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3597 3598 The table header and unwinding opcodes will be generated at this 3599point, so that they are immediately followed by the LSDA data. The 3600symbol referenced by the '.cfi_lsda' directive should still be defined 3601in case a fallback FDE based encoding is used. The LSDA data is 3602terminated by a section directive. 3603 3604 The optional ALIGN argument specifies the alignment required. The 3605alignment is specified as a power of two, as with the '.p2align' 3606directive. 3607 36087.12.9 '.cfi_def_cfa REGISTER, OFFSET' 3609-------------------------------------- 3610 3611'.cfi_def_cfa' defines a rule for computing CFA as: take address from 3612REGISTER and add OFFSET to it. 3613 36147.12.10 '.cfi_def_cfa_register REGISTER' 3615---------------------------------------- 3616 3617'.cfi_def_cfa_register' modifies a rule for computing CFA. From now on 3618REGISTER will be used instead of the old one. Offset remains the same. 3619 36207.12.11 '.cfi_def_cfa_offset OFFSET' 3621------------------------------------ 3622 3623'.cfi_def_cfa_offset' modifies a rule for computing CFA. Register 3624remains the same, but OFFSET is new. Note that it is the absolute 3625offset that will be added to a defined register to compute CFA address. 3626 36277.12.12 '.cfi_adjust_cfa_offset OFFSET' 3628--------------------------------------- 3629 3630Same as '.cfi_def_cfa_offset' but OFFSET is a relative value that is 3631added/subtracted from the previous offset. 3632 36337.12.13 '.cfi_offset REGISTER, OFFSET' 3634-------------------------------------- 3635 3636Previous value of REGISTER is saved at offset OFFSET from CFA. 3637 36387.12.14 '.cfi_val_offset REGISTER, OFFSET' 3639------------------------------------------ 3640 3641Previous value of REGISTER is CFA + OFFSET. 3642 36437.12.15 '.cfi_rel_offset REGISTER, OFFSET' 3644------------------------------------------ 3645 3646Previous value of REGISTER is saved at offset OFFSET from the current 3647CFA register. This is transformed to '.cfi_offset' using the known 3648displacement of the CFA register from the CFA. This is often easier to 3649use, because the number will match the code it's annotating. 3650 36517.12.16 '.cfi_register REGISTER1, REGISTER2' 3652-------------------------------------------- 3653 3654Previous value of REGISTER1 is saved in register REGISTER2. 3655 36567.12.17 '.cfi_restore REGISTER' 3657------------------------------- 3658 3659'.cfi_restore' says that the rule for REGISTER is now the same as it was 3660at the beginning of the function, after all initial instruction added by 3661'.cfi_startproc' were executed. 3662 36637.12.18 '.cfi_undefined REGISTER' 3664--------------------------------- 3665 3666From now on the previous value of REGISTER can't be restored anymore. 3667 36687.12.19 '.cfi_same_value REGISTER' 3669---------------------------------- 3670 3671Current value of REGISTER is the same like in the previous frame, i.e. 3672no restoration needed. 3673 36747.12.20 '.cfi_remember_state' and '.cfi_restore_state' 3675------------------------------------------------------ 3676 3677'.cfi_remember_state' pushes the set of rules for every register onto an 3678implicit stack, while '.cfi_restore_state' pops them off the stack and 3679places them in the current row. This is useful for situations where you 3680have multiple '.cfi_*' directives that need to be undone due to the 3681control flow of the program. For example, we could have something like 3682this (assuming the CFA is the value of 'rbp'): 3683 3684 je label 3685 popq %rbx 3686 .cfi_restore %rbx 3687 popq %r12 3688 .cfi_restore %r12 3689 popq %rbp 3690 .cfi_restore %rbp 3691 .cfi_def_cfa %rsp, 8 3692 ret 3693 label: 3694 /* Do something else */ 3695 3696 Here, we want the '.cfi' directives to affect only the rows 3697corresponding to the instructions before 'label'. This means we'd have 3698to add multiple '.cfi' directives after 'label' to recreate the original 3699save locations of the registers, as well as setting the CFA back to the 3700value of 'rbp'. This would be clumsy, and result in a larger binary 3701size. Instead, we can write: 3702 3703 je label 3704 popq %rbx 3705 .cfi_remember_state 3706 .cfi_restore %rbx 3707 popq %r12 3708 .cfi_restore %r12 3709 popq %rbp 3710 .cfi_restore %rbp 3711 .cfi_def_cfa %rsp, 8 3712 ret 3713 label: 3714 .cfi_restore_state 3715 /* Do something else */ 3716 3717 That way, the rules for the instructions after 'label' will be the 3718same as before the first '.cfi_restore' without having to use multiple 3719'.cfi' directives. 3720 37217.12.21 '.cfi_return_column REGISTER' 3722------------------------------------- 3723 3724Change return column REGISTER, i.e. the return address is either 3725directly in REGISTER or can be accessed by rules for REGISTER. 3726 37277.12.22 '.cfi_signal_frame' 3728--------------------------- 3729 3730Mark current function as signal trampoline. 3731 37327.12.23 '.cfi_window_save' 3733-------------------------- 3734 3735SPARC register window has been saved. 3736 37377.12.24 '.cfi_escape' EXPRESSION[, ...] 3738--------------------------------------- 3739 3740Allows the user to add arbitrary bytes to the unwind info. One might 3741use this to add OS-specific CFI opcodes, or generic CFI opcodes that GAS 3742does not yet support. 3743 37447.12.25 '.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' 3745--------------------------------------------------------- 3746 3747The current value of REGISTER is LABEL. The value of LABEL will be 3748encoded in the output file according to ENCODING; see the description of 3749'.cfi_personality' for details on this encoding. 3750 3751 The usefulness of equating a register to a fixed label is probably 3752limited to the return address register. Here, it can be useful to mark 3753a code segment that has only one return address which is reached by a 3754direct branch and no copy of the return address exists in memory or 3755another register. 3756 3757 3758File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops 3759 37607.13 '.comm SYMBOL , LENGTH ' 3761============================= 3762 3763'.comm' declares a common symbol named SYMBOL. When linking, a common 3764symbol in one object file may be merged with a defined or common symbol 3765of the same name in another object file. If 'ld' does not see a 3766definition for the symbol-just one or more common symbols-then it will 3767allocate LENGTH bytes of uninitialized memory. LENGTH must be an 3768absolute expression. If 'ld' sees multiple common symbols with the same 3769name, and they do not all have the same size, it will allocate space 3770using the largest size. 3771 3772 When using ELF or (as a GNU extension) PE, the '.comm' directive 3773takes an optional third argument. This is the desired alignment of the 3774symbol, specified for ELF as a byte boundary (for example, an alignment 3775of 16 means that the least significant 4 bits of the address should be 3776zero), and for PE as a power of two (for example, an alignment of 5 3777means aligned to a 32-byte boundary). The alignment must be an absolute 3778expression, and it must be a power of two. If 'ld' allocates 3779uninitialized memory for the common symbol, it will use the alignment 3780when placing the symbol. If no alignment is specified, 'as' will set 3781the alignment to the largest power of two less than or equal to the size 3782of the symbol, up to a maximum of 16 on ELF, or the default section 3783alignment of 4 on PE(1). 3784 3785 The syntax for '.comm' differs slightly on the HPPA. The syntax is 3786'SYMBOL .comm, LENGTH'; SYMBOL is optional. 3787 3788 ---------- Footnotes ---------- 3789 3790 (1) This is not the same as the executable image file alignment 3791controlled by 'ld''s '--section-alignment' option; image file sections 3792in PE are aligned to multiples of 4096, which is far too large an 3793alignment for ordinary variables. It is rather the default alignment 3794for (non-debug) sections within object ('*.o') files, which are less 3795strictly aligned. 3796 3797 3798File: as.info, Node: Data, Next: Dc, Prev: Comm, Up: Pseudo Ops 3799 38007.14 '.data SUBSECTION' 3801======================= 3802 3803'.data' tells 'as' to assemble the following statements onto the end of 3804the data subsection numbered SUBSECTION (which is an absolute 3805expression). If SUBSECTION is omitted, it defaults to zero. 3806 3807 3808File: as.info, Node: Dc, Next: Dcb, Prev: Data, Up: Pseudo Ops 3809 38107.15 '.dc[SIZE] EXPRESSIONS' 3811============================ 3812 3813The '.dc' directive expects zero or more EXPRESSIONS separated by 3814commas. These expressions are evaluated and their values inserted into 3815the current section. The size of the emitted value depends upon the 3816suffix to the '.dc' directive: 3817 3818''.a'' 3819 Emits N-bit values, where N is the size of an address on the target 3820 system. 3821''.b'' 3822 Emits 8-bit values. 3823''.d'' 3824 Emits double precision floating-point values. 3825''.l'' 3826 Emits 32-bit values. 3827''.s'' 3828 Emits single precision floating-point values. 3829''.w'' 3830 Emits 16-bit values. Note - this is true even on targets where the 3831 '.word' directive would emit 32-bit values. 3832''.x'' 3833 Emits long double precision floating-point values. 3834 3835 If no suffix is used then '.w' is assumed. 3836 3837 The byte ordering is target dependent, as is the size and format of 3838floating point values. 3839 3840 3841File: as.info, Node: Dcb, Next: Ds, Prev: Dc, Up: Pseudo Ops 3842 38437.16 '.dcb[SIZE] NUMBER [,FILL]' 3844================================ 3845 3846This directive emits NUMBER copies of FILL, each of SIZE bytes. Both 3847NUMBER and FILL are absolute expressions. If the comma and FILL are 3848omitted, FILL is assumed to be zero. The SIZE suffix, if present, must 3849be one of: 3850 3851''.b'' 3852 Emits single byte values. 3853''.d'' 3854 Emits double-precision floating point values. 3855''.l'' 3856 Emits 4-byte values. 3857''.s'' 3858 Emits single-precision floating point values. 3859''.w'' 3860 Emits 2-byte values. 3861''.x'' 3862 Emits long double-precision floating point values. 3863 3864 If the SIZE suffix is omitted then '.w' is assumed. 3865 3866 The byte ordering is target dependent, as is the size and format of 3867floating point values. 3868 3869 3870File: as.info, Node: Ds, Next: Def, Prev: Dcb, Up: Pseudo Ops 3871 38727.17 '.ds[SIZE] NUMBER [,FILL]' 3873=============================== 3874 3875This directive emits NUMBER copies of FILL, each of SIZE bytes. Both 3876NUMBER and FILL are absolute expressions. If the comma and FILL are 3877omitted, FILL is assumed to be zero. The SIZE suffix, if present, must 3878be one of: 3879 3880''.b'' 3881 Emits single byte values. 3882''.d'' 3883 Emits 8-byte values. 3884''.l'' 3885 Emits 4-byte values. 3886''.p'' 3887 Emits 12-byte values. 3888''.s'' 3889 Emits 4-byte values. 3890''.w'' 3891 Emits 2-byte values. 3892''.x'' 3893 Emits 12-byte values. 3894 3895 Note - unlike the '.dcb' directive the '.d', '.s' and '.x' suffixes 3896do not indicate that floating-point values are to be inserted. 3897 3898 If the SIZE suffix is omitted then '.w' is assumed. 3899 3900 The byte ordering is target dependent. 3901 3902 3903File: as.info, Node: Def, Next: Desc, Prev: Ds, Up: Pseudo Ops 3904 39057.18 '.def NAME' 3906================ 3907 3908Begin defining debugging information for a symbol NAME; the definition 3909extends until the '.endef' directive is encountered. 3910 3911 3912File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops 3913 39147.19 '.desc SYMBOL, ABS-EXPRESSION' 3915=================================== 3916 3917This directive sets the descriptor of the symbol (*note Symbol 3918Attributes::) to the low 16 bits of an absolute expression. 3919 3920 The '.desc' directive is not available when 'as' is configured for 3921COFF output; it is only for 'a.out' or 'b.out' object format. For the 3922sake of compatibility, 'as' accepts it, but produces no output, when 3923configured for COFF. 3924 3925 3926File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops 3927 39287.20 '.dim' 3929=========== 3930 3931This directive is generated by compilers to include auxiliary debugging 3932information in the symbol table. It is only permitted inside 3933'.def'/'.endef' pairs. 3934 3935 3936File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops 3937 39387.21 '.double FLONUMS' 3939====================== 3940 3941'.double' expects zero or more flonums, separated by commas. It 3942assembles floating point numbers. The exact kind of floating point 3943numbers emitted depends on how 'as' is configured. *Note Machine 3944Dependencies::. 3945 3946 3947File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops 3948 39497.22 '.eject' 3950============= 3951 3952Force a page break at this point, when generating assembly listings. 3953 3954 3955File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops 3956 39577.23 '.else' 3958============ 3959 3960'.else' is part of the 'as' support for conditional assembly; see *note 3961'.if': If. It marks the beginning of a section of code to be assembled 3962if the condition for the preceding '.if' was false. 3963 3964 3965File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops 3966 39677.24 '.elseif' 3968============== 3969 3970'.elseif' is part of the 'as' support for conditional assembly; see 3971*note '.if': If. It is shorthand for beginning a new '.if' block that 3972would otherwise fill the entire '.else' section. 3973 3974 3975File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops 3976 39777.25 '.end' 3978=========== 3979 3980'.end' marks the end of the assembly file. 'as' does not process 3981anything in the file past the '.end' directive. 3982 3983 3984File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops 3985 39867.26 '.endef' 3987============= 3988 3989This directive flags the end of a symbol definition begun with '.def'. 3990 3991 3992File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops 3993 39947.27 '.endfunc' 3995=============== 3996 3997'.endfunc' marks the end of a function specified with '.func'. 3998 3999 4000File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops 4001 40027.28 '.endif' 4003============= 4004 4005'.endif' is part of the 'as' support for conditional assembly; it marks 4006the end of a block of code that is only assembled conditionally. *Note 4007'.if': If. 4008 4009 4010File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops 4011 40127.29 '.equ SYMBOL, EXPRESSION' 4013============================== 4014 4015This directive sets the value of SYMBOL to EXPRESSION. It is synonymous 4016with '.set'; see *note '.set': Set. 4017 4018 The syntax for 'equ' on the HPPA is 'SYMBOL .equ EXPRESSION'. 4019 4020 The syntax for 'equ' on the Z80 is 'SYMBOL equ EXPRESSION'. On the 4021Z80 it is an error if SYMBOL is already defined, but the symbol is not 4022protected from later redefinition. Compare *note Equiv::. 4023 4024 4025File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops 4026 40277.30 '.equiv SYMBOL, EXPRESSION' 4028================================ 4029 4030The '.equiv' directive is like '.equ' and '.set', except that the 4031assembler will signal an error if SYMBOL is already defined. Note a 4032symbol which has been referenced but not actually defined is considered 4033to be undefined. 4034 4035 Except for the contents of the error message, this is roughly 4036equivalent to 4037 .ifdef SYM 4038 .err 4039 .endif 4040 .equ SYM,VAL 4041 plus it protects the symbol from later redefinition. 4042 4043 4044File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops 4045 40467.31 '.eqv SYMBOL, EXPRESSION' 4047============================== 4048 4049The '.eqv' directive is like '.equiv', but no attempt is made to 4050evaluate the expression or any part of it immediately. Instead each 4051time the resulting symbol is used in an expression, a snapshot of its 4052current value is taken. 4053 4054 4055File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops 4056 40577.32 '.err' 4058=========== 4059 4060If 'as' assembles a '.err' directive, it will print an error message 4061and, unless the '-Z' option was used, it will not generate an object 4062file. This can be used to signal an error in conditionally compiled 4063code. 4064 4065 4066File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops 4067 40687.33 '.error "STRING"' 4069====================== 4070 4071Similarly to '.err', this directive emits an error, but you can specify 4072a string that will be emitted as the error message. If you don't 4073specify the message, it defaults to '".error directive invoked in source 4074file"'. *Note Error and Warning Messages: Errors. 4075 4076 .error "This code has not been assembled and tested." 4077 4078 4079File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops 4080 40817.34 '.exitm' 4082============= 4083 4084Exit early from the current macro definition. *Note Macro::. 4085 4086 4087File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops 4088 40897.35 '.extern' 4090============== 4091 4092'.extern' is accepted in the source program--for compatibility with 4093other assemblers--but it is ignored. 'as' treats all undefined symbols 4094as external. 4095 4096 4097File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops 4098 40997.36 '.fail EXPRESSION' 4100======================= 4101 4102Generates an error or a warning. If the value of the EXPRESSION is 500 4103or more, 'as' will print a warning message. If the value is less than 4104500, 'as' will print an error message. The message will include the 4105value of EXPRESSION. This can occasionally be useful inside complex 4106nested macros or conditional assembly. 4107 4108 4109File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops 4110 41117.37 '.file' 4112============ 4113 4114There are two different versions of the '.file' directive. Targets that 4115support DWARF2 line number information use the DWARF2 version of 4116'.file'. Other targets use the default version. 4117 4118Default Version 4119--------------- 4120 4121This version of the '.file' directive tells 'as' that we are about to 4122start a new logical file. The syntax is: 4123 4124 .file STRING 4125 4126 STRING is the new file name. In general, the filename is recognized 4127whether or not it is surrounded by quotes '"'; but if you wish to 4128specify an empty file name, you must give the quotes-'""'. This 4129statement may go away in future: it is only recognized to be compatible 4130with old 'as' programs. 4131 4132DWARF2 Version 4133-------------- 4134 4135When emitting DWARF2 line number information, '.file' assigns filenames 4136to the '.debug_line' file name table. The syntax is: 4137 4138 .file FILENO FILENAME 4139 4140 The FILENO operand should be a unique positive integer to use as the 4141index of the entry in the table. The FILENAME operand is a C string 4142literal enclosed in double quotes. The FILENAME can include directory 4143elements. If it does, then the directory will be added to the directory 4144table and the basename will be added to the file table. 4145 4146 The detail of filename indices is exposed to the user because the 4147filename table is shared with the '.debug_info' section of the DWARF2 4148debugging information, and thus the user must know the exact indices 4149that table entries will have. 4150 4151 If DWARF-5 support has been enabled via the '-gdwarf-5' option then 4152an extended version of the 'file' is also allowed: 4153 4154 .file FILENO [DIRNAME] FILENAME [md5 VALUE] 4155 4156 With this version a separate directory name is allowed, although if 4157this is used then FILENAME should not contain any directory components. 4158In addtion an md5 hash value of the contents of FILENAME can be 4159provided. This will be stored in the the file table as well, and can be 4160used by tools reading the debug information to verify that the contents 4161of the source file match the contents of the compiled file. 4162 4163 4164File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops 4165 41667.38 '.fill REPEAT , SIZE , VALUE' 4167================================== 4168 4169REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT 4170copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or 4171more, but if it is more than 8, then it is deemed to have the value 8, 4172compatible with other people's assemblers. The contents of each REPEAT 4173bytes is taken from an 8-byte number. The highest order 4 bytes are 4174zero. The lowest order 4 bytes are VALUE rendered in the byte-order of 4175an integer on the computer 'as' is assembling for. Each SIZE bytes in a 4176repetition is taken from the lowest order SIZE bytes of this number. 4177Again, this bizarre behavior is compatible with other people's 4178assemblers. 4179 4180 SIZE and VALUE are optional. If the second comma and VALUE are 4181absent, VALUE is assumed zero. If the first comma and following tokens 4182are absent, SIZE is assumed to be 1. 4183 4184 4185File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops 4186 41877.39 '.float FLONUMS' 4188===================== 4189 4190This directive assembles zero or more flonums, separated by commas. It 4191has the same effect as '.single'. The exact kind of floating point 4192numbers emitted depends on how 'as' is configured. *Note Machine 4193Dependencies::. 4194 4195 4196File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops 4197 41987.40 '.func NAME[,LABEL]' 4199========================= 4200 4201'.func' emits debugging information to denote function NAME, and is 4202ignored unless the file is assembled with debugging enabled. Only 4203'--gstabs[+]' is currently supported. LABEL is the entry point of the 4204function and if omitted NAME prepended with the 'leading char' is used. 4205'leading char' is usually '_' or nothing, depending on the target. All 4206functions are currently defined to have 'void' return type. The 4207function must be terminated with '.endfunc'. 4208 4209 4210File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops 4211 42127.41 '.global SYMBOL', '.globl SYMBOL' 4213====================================== 4214 4215'.global' makes the symbol visible to 'ld'. If you define SYMBOL in 4216your partial program, its value is made available to other partial 4217programs that are linked with it. Otherwise, SYMBOL takes its 4218attributes from a symbol of the same name from another file linked into 4219the same program. 4220 4221 Both spellings ('.globl' and '.global') are accepted, for 4222compatibility with other assemblers. 4223 4224 On the HPPA, '.global' is not always enough to make it accessible to 4225other partial programs. You may need the HPPA-only '.EXPORT' directive 4226as well. *Note HPPA Assembler Directives: HPPA Directives. 4227 4228 4229File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops 4230 42317.42 '.gnu_attribute TAG,VALUE' 4232=============================== 4233 4234Record a GNU object attribute for this file. *Note Object Attributes::. 4235 4236 4237File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops 4238 42397.43 '.hidden NAMES' 4240==================== 4241 4242This is one of the ELF visibility directives. The other two are 4243'.internal' (*note '.internal': Internal.) and '.protected' (*note 4244'.protected': Protected.). 4245 4246 This directive overrides the named symbols default visibility (which 4247is set by their binding: local, global or weak). The directive sets the 4248visibility to 'hidden' which means that the symbols are not visible to 4249other components. Such symbols are always considered to be 'protected' 4250as well. 4251 4252 4253File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops 4254 42557.44 '.hword EXPRESSIONS' 4256========================= 4257 4258This expects zero or more EXPRESSIONS, and emits a 16 bit number for 4259each. 4260 4261 This directive is a synonym for '.short'; depending on the target 4262architecture, it may also be a synonym for '.word'. 4263 4264 4265File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops 4266 42677.45 '.ident' 4268============= 4269 4270This directive is used by some assemblers to place tags in object files. 4271The behavior of this directive varies depending on the target. When 4272using the a.out object file format, 'as' simply accepts the directive 4273for source-file compatibility with existing assemblers, but does not 4274emit anything for it. When using COFF, comments are emitted to the 4275'.comment' or '.rdata' section, depending on the target. When using 4276ELF, comments are emitted to the '.comment' section. 4277 4278 4279File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops 4280 42817.46 '.if ABSOLUTE EXPRESSION' 4282============================== 4283 4284'.if' marks the beginning of a section of code which is only considered 4285part of the source program being assembled if the argument (which must 4286be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional 4287section of code must be marked by '.endif' (*note '.endif': Endif.); 4288optionally, you may include code for the alternative condition, flagged 4289by '.else' (*note '.else': Else.). If you have several conditions to 4290check, '.elseif' may be used to avoid nesting blocks if/else within each 4291subsequent '.else' block. 4292 4293 The following variants of '.if' are also supported: 4294'.ifdef SYMBOL' 4295 Assembles the following section of code if the specified SYMBOL has 4296 been defined. Note a symbol which has been referenced but not yet 4297 defined is considered to be undefined. 4298 4299'.ifb TEXT' 4300 Assembles the following section of code if the operand is blank 4301 (empty). 4302 4303'.ifc STRING1,STRING2' 4304 Assembles the following section of code if the two strings are the 4305 same. The strings may be optionally quoted with single quotes. If 4306 they are not quoted, the first string stops at the first comma, and 4307 the second string stops at the end of the line. Strings which 4308 contain whitespace should be quoted. The string comparison is case 4309 sensitive. 4310 4311'.ifeq ABSOLUTE EXPRESSION' 4312 Assembles the following section of code if the argument is zero. 4313 4314'.ifeqs STRING1,STRING2' 4315 Another form of '.ifc'. The strings must be quoted using double 4316 quotes. 4317 4318'.ifge ABSOLUTE EXPRESSION' 4319 Assembles the following section of code if the argument is greater 4320 than or equal to zero. 4321 4322'.ifgt ABSOLUTE EXPRESSION' 4323 Assembles the following section of code if the argument is greater 4324 than zero. 4325 4326'.ifle ABSOLUTE EXPRESSION' 4327 Assembles the following section of code if the argument is less 4328 than or equal to zero. 4329 4330'.iflt ABSOLUTE EXPRESSION' 4331 Assembles the following section of code if the argument is less 4332 than zero. 4333 4334'.ifnb TEXT' 4335 Like '.ifb', but the sense of the test is reversed: this assembles 4336 the following section of code if the operand is non-blank 4337 (non-empty). 4338 4339'.ifnc STRING1,STRING2.' 4340 Like '.ifc', but the sense of the test is reversed: this assembles 4341 the following section of code if the two strings are not the same. 4342 4343'.ifndef SYMBOL' 4344'.ifnotdef SYMBOL' 4345 Assembles the following section of code if the specified SYMBOL has 4346 not been defined. Both spelling variants are equivalent. Note a 4347 symbol which has been referenced but not yet defined is considered 4348 to be undefined. 4349 4350'.ifne ABSOLUTE EXPRESSION' 4351 Assembles the following section of code if the argument is not 4352 equal to zero (in other words, this is equivalent to '.if'). 4353 4354'.ifnes STRING1,STRING2' 4355 Like '.ifeqs', but the sense of the test is reversed: this 4356 assembles the following section of code if the two strings are not 4357 the same. 4358 4359 4360File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops 4361 43627.47 '.incbin "FILE"[,SKIP[,COUNT]]' 4363==================================== 4364 4365The 'incbin' directive includes FILE verbatim at the current location. 4366You can control the search paths used with the '-I' command-line option 4367(*note Command-Line Options: Invoking.). Quotation marks are required 4368around FILE. 4369 4370 The SKIP argument skips a number of bytes from the start of the FILE. 4371The COUNT argument indicates the maximum number of bytes to read. Note 4372that the data is not aligned in any way, so it is the user's 4373responsibility to make sure that proper alignment is provided both 4374before and after the 'incbin' directive. 4375 4376 4377File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops 4378 43797.48 '.include "FILE"' 4380====================== 4381 4382This directive provides a way to include supporting files at specified 4383points in your source program. The code from FILE is assembled as if it 4384followed the point of the '.include'; when the end of the included file 4385is reached, assembly of the original file continues. You can control 4386the search paths used with the '-I' command-line option (*note 4387Command-Line Options: Invoking.). Quotation marks are required around 4388FILE. 4389 4390 4391File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops 4392 43937.49 '.int EXPRESSIONS' 4394======================= 4395 4396Expect zero or more EXPRESSIONS, of any section, separated by commas. 4397For each expression, emit a number that, at run time, is the value of 4398that expression. The byte order and bit size of the number depends on 4399what kind of target the assembly is for. 4400 4401 4402File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops 4403 44047.50 '.internal NAMES' 4405====================== 4406 4407This is one of the ELF visibility directives. The other two are 4408'.hidden' (*note '.hidden': Hidden.) and '.protected' (*note 4409'.protected': Protected.). 4410 4411 This directive overrides the named symbols default visibility (which 4412is set by their binding: local, global or weak). The directive sets the 4413visibility to 'internal' which means that the symbols are considered to 4414be 'hidden' (i.e., not visible to other components), and that some 4415extra, processor specific processing must also be performed upon the 4416symbols as well. 4417 4418 4419File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops 4420 44217.51 '.irp SYMBOL,VALUES'... 4422============================ 4423 4424Evaluate a sequence of statements assigning different values to SYMBOL. 4425The sequence of statements starts at the '.irp' directive, and is 4426terminated by an '.endr' directive. For each VALUE, SYMBOL is set to 4427VALUE, and the sequence of statements is assembled. If no VALUE is 4428listed, the sequence of statements is assembled once, with SYMBOL set to 4429the null string. To refer to SYMBOL within the sequence of statements, 4430use \SYMBOL. 4431 4432 For example, assembling 4433 4434 .irp param,1,2,3 4435 move d\param,sp@- 4436 .endr 4437 4438 is equivalent to assembling 4439 4440 move d1,sp@- 4441 move d2,sp@- 4442 move d3,sp@- 4443 4444 For some caveats with the spelling of SYMBOL, see also *note Macro::. 4445 4446 4447File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops 4448 44497.52 '.irpc SYMBOL,VALUES'... 4450============================= 4451 4452Evaluate a sequence of statements assigning different values to SYMBOL. 4453The sequence of statements starts at the '.irpc' directive, and is 4454terminated by an '.endr' directive. For each character in VALUE, SYMBOL 4455is set to the character, and the sequence of statements is assembled. 4456If no VALUE is listed, the sequence of statements is assembled once, 4457with SYMBOL set to the null string. To refer to SYMBOL within the 4458sequence of statements, use \SYMBOL. 4459 4460 For example, assembling 4461 4462 .irpc param,123 4463 move d\param,sp@- 4464 .endr 4465 4466 is equivalent to assembling 4467 4468 move d1,sp@- 4469 move d2,sp@- 4470 move d3,sp@- 4471 4472 For some caveats with the spelling of SYMBOL, see also the discussion 4473at *Note Macro::. 4474 4475 4476File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops 4477 44787.53 '.lcomm SYMBOL , LENGTH' 4479============================= 4480 4481Reserve LENGTH (an absolute expression) bytes for a local common denoted 4482by SYMBOL. The section and value of SYMBOL are those of the new local 4483common. The addresses are allocated in the bss section, so that at 4484run-time the bytes start off zeroed. SYMBOL is not declared global 4485(*note '.global': Global.), so is normally not visible to 'ld'. 4486 4487 Some targets permit a third argument to be used with '.lcomm'. This 4488argument specifies the desired alignment of the symbol in the bss 4489section. 4490 4491 The syntax for '.lcomm' differs slightly on the HPPA. The syntax is 4492'SYMBOL .lcomm, LENGTH'; SYMBOL is optional. 4493 4494 4495File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops 4496 44977.54 '.lflags' 4498============== 4499 4500'as' accepts this directive, for compatibility with other assemblers, 4501but ignores it. 4502 4503 4504File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops 4505 45067.55 '.line LINE-NUMBER' 4507======================== 4508 4509Change the logical line number. LINE-NUMBER must be an absolute 4510expression. The next line has that logical line number. Therefore any 4511other statements on the current line (after a statement separator 4512character) are reported as on logical line number LINE-NUMBER - 1. One 4513day 'as' will no longer support this directive: it is recognized only 4514for compatibility with existing assembler programs. 4515 4516 Even though this is a directive associated with the 'a.out' or 4517'b.out' object-code formats, 'as' still recognizes it when producing 4518COFF output, and treats '.line' as though it were the COFF '.ln' _if_ it 4519is found outside a '.def'/'.endef' pair. 4520 4521 Inside a '.def', '.line' is, instead, one of the directives used by 4522compilers to generate auxiliary symbol information for debugging. 4523 4524 4525File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops 4526 45277.56 '.linkonce [TYPE]' 4528======================= 4529 4530Mark the current section so that the linker only includes a single copy 4531of it. This may be used to include the same section in several 4532different object files, but ensure that the linker will only include it 4533once in the final output file. The '.linkonce' pseudo-op must be used 4534for each instance of the section. Duplicate sections are detected based 4535on the section name, so it should be unique. 4536 4537 This directive is only supported by a few object file formats; as of 4538this writing, the only object file format which supports it is the 4539Portable Executable format used on Windows NT. 4540 4541 The TYPE argument is optional. If specified, it must be one of the 4542following strings. For example: 4543 .linkonce same_size 4544 Not all types may be supported on all object file formats. 4545 4546'discard' 4547 Silently discard duplicate sections. This is the default. 4548 4549'one_only' 4550 Warn if there are duplicate sections, but still keep only one copy. 4551 4552'same_size' 4553 Warn if any of the duplicates have different sizes. 4554 4555'same_contents' 4556 Warn if any of the duplicates do not have exactly the same 4557 contents. 4558 4559 4560File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops 4561 45627.57 '.list' 4563============ 4564 4565Control (in conjunction with the '.nolist' directive) whether or not 4566assembly listings are generated. These two directives maintain an 4567internal counter (which is zero initially). '.list' increments the 4568counter, and '.nolist' decrements it. Assembly listings are generated 4569whenever the counter is greater than zero. 4570 4571 By default, listings are disabled. When you enable them (with the 4572'-a' command-line option; *note Command-Line Options: Invoking.), the 4573initial value of the listing counter is one. 4574 4575 4576File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops 4577 45787.58 '.ln LINE-NUMBER' 4579====================== 4580 4581'.ln' is a synonym for '.line'. 4582 4583 4584File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops 4585 45867.59 '.loc FILENO LINENO [COLUMN] [OPTIONS]' 4587============================================ 4588 4589When emitting DWARF2 line number information, the '.loc' directive will 4590add a row to the '.debug_line' line number matrix corresponding to the 4591immediately following assembly instruction. The FILENO, LINENO, and 4592optional COLUMN arguments will be applied to the '.debug_line' state 4593machine before the row is added. It is an error for the input assembly 4594file to generate a non-empty '.debug_line' and also use 'loc' 4595directives. 4596 4597 The OPTIONS are a sequence of the following tokens in any order: 4598 4599'basic_block' 4600 This option will set the 'basic_block' register in the 4601 '.debug_line' state machine to 'true'. 4602 4603'prologue_end' 4604 This option will set the 'prologue_end' register in the 4605 '.debug_line' state machine to 'true'. 4606 4607'epilogue_begin' 4608 This option will set the 'epilogue_begin' register in the 4609 '.debug_line' state machine to 'true'. 4610 4611'is_stmt VALUE' 4612 This option will set the 'is_stmt' register in the '.debug_line' 4613 state machine to 'value', which must be either 0 or 1. 4614 4615'isa VALUE' 4616 This directive will set the 'isa' register in the '.debug_line' 4617 state machine to VALUE, which must be an unsigned integer. 4618 4619'discriminator VALUE' 4620 This directive will set the 'discriminator' register in the 4621 '.debug_line' state machine to VALUE, which must be an unsigned 4622 integer. 4623 4624'view VALUE' 4625 This option causes a row to be added to '.debug_line' in reference 4626 to the current address (which might not be the same as that of the 4627 following assembly instruction), and to associate VALUE with the 4628 'view' register in the '.debug_line' state machine. If VALUE is a 4629 label, both the 'view' register and the label are set to the number 4630 of prior '.loc' directives at the same program location. If VALUE 4631 is the literal '0', the 'view' register is set to zero, and the 4632 assembler asserts that there aren't any prior '.loc' directives at 4633 the same program location. If VALUE is the literal '-0', the 4634 assembler arrange for the 'view' register to be reset in this row, 4635 even if there are prior '.loc' directives at the same program 4636 location. 4637 4638 4639File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops 4640 46417.60 '.loc_mark_labels ENABLE' 4642============================== 4643 4644When emitting DWARF2 line number information, the '.loc_mark_labels' 4645directive makes the assembler emit an entry to the '.debug_line' line 4646number matrix with the 'basic_block' register in the state machine set 4647whenever a code label is seen. The ENABLE argument should be either 1 4648or 0, to enable or disable this function respectively. 4649 4650 4651File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops 4652 46537.61 '.local NAMES' 4654=================== 4655 4656This directive, which is available for ELF targets, marks each symbol in 4657the comma-separated list of 'names' as a local symbol so that it will 4658not be externally visible. If the symbols do not already exist, they 4659will be created. 4660 4661 For targets where the '.lcomm' directive (*note Lcomm::) does not 4662accept an alignment argument, which is the case for most ELF targets, 4663the '.local' directive can be used in combination with '.comm' (*note 4664Comm::) to define aligned local common data. 4665 4666 4667File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops 4668 46697.62 '.long EXPRESSIONS' 4670======================== 4671 4672'.long' is the same as '.int'. *Note '.int': Int. 4673 4674 4675File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops 4676 46777.63 '.macro' 4678============= 4679 4680The commands '.macro' and '.endm' allow you to define macros that 4681generate assembly output. For example, this definition specifies a 4682macro 'sum' that puts a sequence of numbers into memory: 4683 4684 .macro sum from=0, to=5 4685 .long \from 4686 .if \to-\from 4687 sum "(\from+1)",\to 4688 .endif 4689 .endm 4690 4691With that definition, 'SUM 0,5' is equivalent to this assembly input: 4692 4693 .long 0 4694 .long 1 4695 .long 2 4696 .long 3 4697 .long 4 4698 .long 5 4699 4700'.macro MACNAME' 4701'.macro MACNAME MACARGS ...' 4702 Begin the definition of a macro called MACNAME. If your macro 4703 definition requires arguments, specify their names after the macro 4704 name, separated by commas or spaces. You can qualify the macro 4705 argument to indicate whether all invocations must specify a 4706 non-blank value (through ':'req''), or whether it takes all of the 4707 remaining arguments (through ':'vararg''). You can supply a 4708 default value for any macro argument by following the name with 4709 '=DEFLT'. You cannot define two macros with the same MACNAME 4710 unless it has been subject to the '.purgem' directive (*note 4711 Purgem::) between the two definitions. For example, these are all 4712 valid '.macro' statements: 4713 4714 '.macro comm' 4715 Begin the definition of a macro called 'comm', which takes no 4716 arguments. 4717 4718 '.macro plus1 p, p1' 4719 '.macro plus1 p p1' 4720 Either statement begins the definition of a macro called 4721 'plus1', which takes two arguments; within the macro 4722 definition, write '\p' or '\p1' to evaluate the arguments. 4723 4724 '.macro reserve_str p1=0 p2' 4725 Begin the definition of a macro called 'reserve_str', with two 4726 arguments. The first argument has a default value, but not 4727 the second. After the definition is complete, you can call 4728 the macro either as 'reserve_str A,B' (with '\p1' evaluating 4729 to A and '\p2' evaluating to B), or as 'reserve_str ,B' (with 4730 '\p1' evaluating as the default, in this case '0', and '\p2' 4731 evaluating to B). 4732 4733 '.macro m p1:req, p2=0, p3:vararg' 4734 Begin the definition of a macro called 'm', with at least 4735 three arguments. The first argument must always have a value 4736 specified, but not the second, which instead has a default 4737 value. The third formal will get assigned all remaining 4738 arguments specified at invocation time. 4739 4740 When you call a macro, you can specify the argument values 4741 either by position, or by keyword. For example, 'sum 9,17' is 4742 equivalent to 'sum to=17, from=9'. 4743 4744 Note that since each of the MACARGS can be an identifier exactly as 4745 any other one permitted by the target architecture, there may be 4746 occasional problems if the target hand-crafts special meanings to 4747 certain characters when they occur in a special position. For 4748 example, if the colon (':') is generally permitted to be part of a 4749 symbol name, but the architecture specific code special-cases it 4750 when occurring as the final character of a symbol (to denote a 4751 label), then the macro parameter replacement code will have no way 4752 of knowing that and consider the whole construct (including the 4753 colon) an identifier, and check only this identifier for being the 4754 subject to parameter substitution. So for example this macro 4755 definition: 4756 4757 .macro label l 4758 \l: 4759 .endm 4760 4761 might not work as expected. Invoking 'label foo' might not create 4762 a label called 'foo' but instead just insert the text '\l:' into 4763 the assembler source, probably generating an error about an 4764 unrecognised identifier. 4765 4766 Similarly problems might occur with the period character ('.') 4767 which is often allowed inside opcode names (and hence identifier 4768 names). So for example constructing a macro to build an opcode 4769 from a base name and a length specifier like this: 4770 4771 .macro opcode base length 4772 \base.\length 4773 .endm 4774 4775 and invoking it as 'opcode store l' will not create a 'store.l' 4776 instruction but instead generate some kind of error as the 4777 assembler tries to interpret the text '\base.\length'. 4778 4779 There are several possible ways around this problem: 4780 4781 'Insert white space' 4782 If it is possible to use white space characters then this is 4783 the simplest solution. eg: 4784 4785 .macro label l 4786 \l : 4787 .endm 4788 4789 'Use '\()'' 4790 The string '\()' can be used to separate the end of a macro 4791 argument from the following text. eg: 4792 4793 .macro opcode base length 4794 \base\().\length 4795 .endm 4796 4797 'Use the alternate macro syntax mode' 4798 In the alternative macro syntax mode the ampersand character 4799 ('&') can be used as a separator. eg: 4800 4801 .altmacro 4802 .macro label l 4803 l&: 4804 .endm 4805 4806 Note: this problem of correctly identifying string parameters to 4807 pseudo ops also applies to the identifiers used in '.irp' (*note 4808 Irp::) and '.irpc' (*note Irpc::) as well. 4809 4810'.endm' 4811 Mark the end of a macro definition. 4812 4813'.exitm' 4814 Exit early from the current macro definition. 4815 4816'\@' 4817 'as' maintains a counter of how many macros it has executed in this 4818 pseudo-variable; you can copy that number to your output with '\@', 4819 but _only within a macro definition_. 4820 4821'LOCAL NAME [ , ... ]' 4822 _Warning: 'LOCAL' is only available if you select "alternate macro 4823 syntax" with '--alternate' or '.altmacro'._ *Note '.altmacro': 4824 Altmacro. 4825 4826 4827File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops 4828 48297.64 '.mri VAL' 4830=============== 4831 4832If VAL is non-zero, this tells 'as' to enter MRI mode. If VAL is zero, 4833this tells 'as' to exit MRI mode. This change affects code assembled 4834until the next '.mri' directive, or until the end of the file. *Note 4835MRI mode: M. 4836 4837 4838File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops 4839 48407.65 '.noaltmacro' 4841================== 4842 4843Disable alternate macro mode. *Note Altmacro::. 4844 4845 4846File: as.info, Node: Nolist, Next: Nop, Prev: Noaltmacro, Up: Pseudo Ops 4847 48487.66 '.nolist' 4849============== 4850 4851Control (in conjunction with the '.list' directive) whether or not 4852assembly listings are generated. These two directives maintain an 4853internal counter (which is zero initially). '.list' increments the 4854counter, and '.nolist' decrements it. Assembly listings are generated 4855whenever the counter is greater than zero. 4856 4857 4858File: as.info, Node: Nop, Next: Nops, Prev: Nolist, Up: Pseudo Ops 4859 48607.67 '.nop [SIZE]' 4861================== 4862 4863This directive emits no-op instructions. It is provided on all 4864architectures, allowing the creation of architecture neutral tests 4865involving actual code. The size of the generated instruction is target 4866specific, but if the optional SIZE argument is given and resolves to an 4867absolute positive value at that point in assembly (no forward 4868expressions allowed) then the fewest no-op instructions are emitted that 4869equal or exceed a total SIZE in bytes. '.nop' does affect the 4870generation of DWARF debug line information. Some targets do not support 4871using '.nop' with SIZE. 4872 4873 4874File: as.info, Node: Nops, Next: Octa, Prev: Nop, Up: Pseudo Ops 4875 48767.68 '.nops SIZE[, CONTROL]' 4877============================ 4878 4879This directive emits no-op instructions. It is specific to the Intel 488080386 and AMD x86-64 targets. It takes a SIZE argument and generates 4881SIZE bytes of no-op instructions. SIZE must be absolute and positive. 4882These bytes do not affect the generation of DWARF debug line 4883information. 4884 4885 The optional CONTROL argument specifies a size limit for a single 4886no-op instruction. If not provided then a value of 0 is assumed. The 4887valid values of CONTROL are between 0 and 4 in 16-bit mode, between 0 4888and 7 when tuning for older processors in 32-bit mode, between 0 and 11 4889in 64-bit mode or when tuning for newer processors in 32-bit mode. When 48900 is used, the no-op instruction size limit is set to the maximum 4891supported size. 4892 4893 4894File: as.info, Node: Octa, Next: Offset, Prev: Nops, Up: Pseudo Ops 4895 48967.69 '.octa BIGNUMS' 4897==================== 4898 4899This directive expects zero or more bignums, separated by commas. For 4900each bignum, it emits a 16-byte integer. 4901 4902 The term "octa" comes from contexts in which a "word" is two bytes; 4903hence _octa_-word for 16 bytes. 4904 4905 4906File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops 4907 49087.70 '.offset LOC' 4909================== 4910 4911Set the location counter to LOC in the absolute section. LOC must be an 4912absolute expression. This directive may be useful for defining symbols 4913with absolute values. Do not confuse it with the '.org' directive. 4914 4915 4916File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops 4917 49187.71 '.org NEW-LC , FILL' 4919========================= 4920 4921Advance the location counter of the current section to NEW-LC. NEW-LC 4922is either an absolute expression or an expression with the same section 4923as the current subsection. That is, you can't use '.org' to cross 4924sections: if NEW-LC has the wrong section, the '.org' directive is 4925ignored. To be compatible with former assemblers, if the section of 4926NEW-LC is absolute, 'as' issues a warning, then pretends the section of 4927NEW-LC is the same as the current subsection. 4928 4929 '.org' may only increase the location counter, or leave it unchanged; 4930you cannot use '.org' to move the location counter backwards. 4931 4932 Because 'as' tries to assemble programs in one pass, NEW-LC may not 4933be undefined. If you really detest this restriction we eagerly await a 4934chance to share your improved assembler. 4935 4936 Beware that the origin is relative to the start of the section, not 4937to the start of the subsection. This is compatible with other people's 4938assemblers. 4939 4940 When the location counter (of the current subsection) is advanced, 4941the intervening bytes are filled with FILL which should be an absolute 4942expression. If the comma and FILL are omitted, FILL defaults to zero. 4943 4944 4945File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops 4946 49477.72 '.p2align[wl] [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 4948====================================================== 4949 4950Pad the location counter (in the current subsection) to a particular 4951storage boundary. The first expression (which must be absolute) is the 4952number of low-order zero bits the location counter must have after 4953advancement. For example '.p2align 3' advances the location counter 4954until it is a multiple of 8. If the location counter is already a 4955multiple of 8, no change is needed. If the expression is omitted then a 4956default value of 0 is used, effectively disabling alignment 4957requirements. 4958 4959 The second expression (also absolute) gives the fill value to be 4960stored in the padding bytes. It (and the comma) may be omitted. If it 4961is omitted, the padding bytes are normally zero. However, on most 4962systems, if the section is marked as containing code and the fill value 4963is omitted, the space is filled with no-op instructions. 4964 4965 The third expression is also absolute, and is also optional. If it 4966is present, it is the maximum number of bytes that should be skipped by 4967this alignment directive. If doing the alignment would require skipping 4968more bytes than the specified maximum, then the alignment is not done at 4969all. You can omit the fill value (the second argument) entirely by 4970simply using two commas after the required alignment; this can be useful 4971if you want the alignment to be filled with no-op instructions when 4972appropriate. 4973 4974 The '.p2alignw' and '.p2alignl' directives are variants of the 4975'.p2align' directive. The '.p2alignw' directive treats the fill pattern 4976as a two byte word value. The '.p2alignl' directives treats the fill 4977pattern as a four byte longword value. For example, '.p2alignw 49782,0x368d' will align to a multiple of 4. If it skips two bytes, they 4979will be filled in with the value 0x368d (the exact placement of the 4980bytes depends upon the endianness of the processor). If it skips 1 or 3 4981bytes, the fill value is undefined. 4982 4983 4984File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops 4985 49867.73 '.popsection' 4987================== 4988 4989This is one of the ELF section stack manipulation directives. The 4990others are '.section' (*note Section::), '.subsection' (*note 4991SubSection::), '.pushsection' (*note PushSection::), and '.previous' 4992(*note Previous::). 4993 4994 This directive replaces the current section (and subsection) with the 4995top section (and subsection) on the section stack. This section is 4996popped off the stack. 4997 4998 4999File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops 5000 50017.74 '.previous' 5002================ 5003 5004This is one of the ELF section stack manipulation directives. The 5005others are '.section' (*note Section::), '.subsection' (*note 5006SubSection::), '.pushsection' (*note PushSection::), and '.popsection' 5007(*note PopSection::). 5008 5009 This directive swaps the current section (and subsection) with most 5010recently referenced section/subsection pair prior to this one. Multiple 5011'.previous' directives in a row will flip between two sections (and 5012their subsections). For example: 5013 5014 .section A 5015 .subsection 1 5016 .word 0x1234 5017 .subsection 2 5018 .word 0x5678 5019 .previous 5020 .word 0x9abc 5021 5022 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into 5023subsection 2 of section A. Whilst: 5024 5025 .section A 5026 .subsection 1 5027 # Now in section A subsection 1 5028 .word 0x1234 5029 .section B 5030 .subsection 0 5031 # Now in section B subsection 0 5032 .word 0x5678 5033 .subsection 1 5034 # Now in section B subsection 1 5035 .word 0x9abc 5036 .previous 5037 # Now in section B subsection 0 5038 .word 0xdef0 5039 5040 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0 5041of section B and 0x9abc into subsection 1 of section B. 5042 5043 In terms of the section stack, this directive swaps the current 5044section with the top section on the section stack. 5045 5046 5047File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops 5048 50497.75 '.print STRING' 5050==================== 5051 5052'as' will print STRING on the standard output during assembly. You must 5053put STRING in double quotes. 5054 5055 5056File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops 5057 50587.76 '.protected NAMES' 5059======================= 5060 5061This is one of the ELF visibility directives. The other two are 5062'.hidden' (*note Hidden::) and '.internal' (*note Internal::). 5063 5064 This directive overrides the named symbols default visibility (which 5065is set by their binding: local, global or weak). The directive sets the 5066visibility to 'protected' which means that any references to the symbols 5067from within the components that defines them must be resolved to the 5068definition in that component, even if a definition in another component 5069would normally preempt this. 5070 5071 5072File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops 5073 50747.77 '.psize LINES , COLUMNS' 5075============================= 5076 5077Use this directive to declare the number of lines--and, optionally, the 5078number of columns--to use for each page, when generating listings. 5079 5080 If you do not use '.psize', listings use a default line-count of 60. 5081You may omit the comma and COLUMNS specification; the default width is 5082200 columns. 5083 5084 'as' generates formfeeds whenever the specified number of lines is 5085exceeded (or whenever you explicitly request one, using '.eject'). 5086 5087 If you specify LINES as '0', no formfeeds are generated save those 5088explicitly specified with '.eject'. 5089 5090 5091File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops 5092 50937.78 '.purgem NAME' 5094=================== 5095 5096Undefine the macro NAME, so that later uses of the string will not be 5097expanded. *Note Macro::. 5098 5099 5100File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops 5101 51027.79 '.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' 5103======================================================================== 5104 5105This is one of the ELF section stack manipulation directives. The 5106others are '.section' (*note Section::), '.subsection' (*note 5107SubSection::), '.popsection' (*note PopSection::), and '.previous' 5108(*note Previous::). 5109 5110 This directive pushes the current section (and subsection) onto the 5111top of the section stack, and then replaces the current section and 5112subsection with 'name' and 'subsection'. The optional 'flags', 'type' 5113and 'arguments' are treated the same as in the '.section' (*note 5114Section::) directive. 5115 5116 5117File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops 5118 51197.80 '.quad BIGNUMS' 5120==================== 5121 5122'.quad' expects zero or more bignums, separated by commas. For each 5123bignum, it emits an 8-byte integer. If the bignum won't fit in 8 bytes, 5124it prints a warning message; and just takes the lowest order 8 bytes of 5125the bignum. 5126 5127 The term "quad" comes from contexts in which a "word" is two bytes; 5128hence _quad_-word for 8 bytes. 5129 5130 5131File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops 5132 51337.81 '.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 5134============================================== 5135 5136Generate a relocation at OFFSET of type RELOC_NAME with value 5137EXPRESSION. If OFFSET is a number, the relocation is generated in the 5138current section. If OFFSET is an expression that resolves to a symbol 5139plus offset, the relocation is generated in the given symbol's section. 5140EXPRESSION, if present, must resolve to a symbol plus addend or to an 5141absolute value, but note that not all targets support an addend. e.g. 5142ELF REL targets such as i386 store an addend in the section contents 5143rather than in the relocation. This low level interface does not 5144support addends stored in the section. 5145 5146 5147File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops 5148 51497.82 '.rept COUNT' 5150================== 5151 5152Repeat the sequence of lines between the '.rept' directive and the next 5153'.endr' directive COUNT times. 5154 5155 For example, assembling 5156 5157 .rept 3 5158 .long 0 5159 .endr 5160 5161 is equivalent to assembling 5162 5163 .long 0 5164 .long 0 5165 .long 0 5166 5167 A count of zero is allowed, but nothing is generated. Negative 5168counts are not allowed and if encountered will be treated as if they 5169were zero. 5170 5171 5172File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops 5173 51747.83 '.sbttl "SUBHEADING"' 5175========================== 5176 5177Use SUBHEADING as the title (third line, immediately after the title 5178line) when generating assembly listings. 5179 5180 This directive affects subsequent pages, as well as the current page 5181if it appears within ten lines of the top of a page. 5182 5183 5184File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops 5185 51867.84 '.scl CLASS' 5187================= 5188 5189Set the storage-class value for a symbol. This directive may only be 5190used inside a '.def'/'.endef' pair. Storage class may flag whether a 5191symbol is static or external, or it may record further symbolic 5192debugging information. 5193 5194 5195File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops 5196 51977.85 '.section NAME' 5198==================== 5199 5200Use the '.section' directive to assemble the following code into a 5201section named NAME. 5202 5203 This directive is only supported for targets that actually support 5204arbitrarily named sections; on 'a.out' targets, for example, it is not 5205accepted, even with a standard 'a.out' section name. 5206 5207COFF Version 5208------------ 5209 5210For COFF targets, the '.section' directive is used in one of the 5211following ways: 5212 5213 .section NAME[, "FLAGS"] 5214 .section NAME[, SUBSECTION] 5215 5216 If the optional argument is quoted, it is taken as flags to use for 5217the section. Each flag is a single character. The following flags are 5218recognized: 5219 5220'b' 5221 bss section (uninitialized data) 5222'n' 5223 section is not loaded 5224'w' 5225 writable section 5226'd' 5227 data section 5228'e' 5229 exclude section from linking 5230'r' 5231 read-only section 5232'x' 5233 executable section 5234's' 5235 shared section (meaningful for PE targets) 5236'a' 5237 ignored. (For compatibility with the ELF version) 5238'y' 5239 section is not readable (meaningful for PE targets) 5240'0-9' 5241 single-digit power-of-two section alignment (GNU extension) 5242 5243 If no flags are specified, the default flags depend upon the section 5244name. If the section name is not recognized, the default will be for 5245the section to be loaded and writable. Note the 'n' and 'w' flags 5246remove attributes from the section, rather than adding them, so if they 5247are used on their own it will be as if no flags had been specified at 5248all. 5249 5250 If the optional argument to the '.section' directive is not quoted, 5251it is taken as a subsection number (*note Sub-Sections::). 5252 5253ELF Version 5254----------- 5255 5256This is one of the ELF section stack manipulation directives. The 5257others are '.subsection' (*note SubSection::), '.pushsection' (*note 5258PushSection::), '.popsection' (*note PopSection::), and '.previous' 5259(*note Previous::). 5260 5261 For ELF targets, the '.section' directive is used like this: 5262 5263 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] 5264 5265 If the '--sectname-subst' command-line option is provided, the NAME 5266argument may contain a substitution sequence. Only '%S' is supported at 5267the moment, and substitutes the current section name. For example: 5268 5269 .macro exception_code 5270 .section %S.exception 5271 [exception code here] 5272 .previous 5273 .endm 5274 5275 .text 5276 [code] 5277 exception_code 5278 [...] 5279 5280 .section .init 5281 [init code] 5282 exception_code 5283 [...] 5284 5285 The two 'exception_code' invocations above would create the 5286'.text.exception' and '.init.exception' sections respectively. This is 5287useful e.g. to discriminate between ancillary sections that are tied to 5288setup code to be discarded after use from ancillary sections that need 5289to stay resident without having to define multiple 'exception_code' 5290macros just for that purpose. 5291 5292 The optional FLAGS argument is a quoted string which may contain any 5293combination of the following characters: 5294 5295'a' 5296 section is allocatable 5297'd' 5298 section is a GNU_MBIND section 5299'e' 5300 section is excluded from executable and shared library. 5301'o' 5302 section references a symbol defined in another section (the 5303 linked-to section) in the same file. 5304'w' 5305 section is writable 5306'x' 5307 section is executable 5308'M' 5309 section is mergeable 5310'S' 5311 section contains zero terminated strings 5312'G' 5313 section is a member of a section group 5314'T' 5315 section is used for thread-local-storage 5316'?' 5317 section is a member of the previously-current section's group, if 5318 any 5319'R' 5320 retained section (apply SHF_GNU_RETAIN to prevent linker garbage 5321 collection, GNU ELF extension) 5322'<number>' 5323 a numeric value indicating the bits to be set in the ELF section 5324 header's flags field. Note - if one or more of the alphabetic 5325 characters described above is also included in the flags field, 5326 their bit values will be ORed into the resulting value. 5327'<target specific>' 5328 some targets extend this list with their own flag characters 5329 5330 Note - once a section's flags have been set they cannot be changed. 5331There are a few exceptions to this rule however. Processor and 5332application specific flags can be added to an already defined section. 5333The '.interp', '.strtab' and '.symtab' sections can have the allocate 5334flag ('a') set after they are initially defined, and the 5335'.note-GNU-stack' section may have the executable ('x') flag added. 5336Also note that the '.attach_to_group' directive can be used to add a 5337section to a group even if the section was not originally declared to be 5338part of that group. 5339 5340 The optional TYPE argument may contain one of the following 5341constants: 5342 5343'@progbits' 5344 section contains data 5345'@nobits' 5346 section does not contain data (i.e., section only occupies space) 5347'@note' 5348 section contains data which is used by things other than the 5349 program 5350'@init_array' 5351 section contains an array of pointers to init functions 5352'@fini_array' 5353 section contains an array of pointers to finish functions 5354'@preinit_array' 5355 section contains an array of pointers to pre-init functions 5356'@<number>' 5357 a numeric value to be set as the ELF section header's type field. 5358'@<target specific>' 5359 some targets extend this list with their own types 5360 5361 Many targets only support the first three section types. The type 5362may be enclosed in double quotes if necessary. 5363 5364 Note on targets where the '@' character is the start of a comment (eg 5365ARM) then another character is used instead. For example the ARM port 5366uses the '%' character. 5367 5368 Note - some sections, eg '.text' and '.data' are considered to be 5369special and have fixed types. Any attempt to declare them with a 5370different type will generate an error from the assembler. 5371 5372 If FLAGS contains the 'M' symbol then the TYPE argument must be 5373specified as well as an extra argument--ENTSIZE--like this: 5374 5375 .section NAME , "FLAGS"M, @TYPE, ENTSIZE 5376 5377 Sections with the 'M' flag but not 'S' flag must contain fixed size 5378constants, each ENTSIZE octets long. Sections with both 'M' and 'S' 5379must contain zero terminated strings where each character is ENTSIZE 5380bytes long. The linker may remove duplicates within sections with the 5381same name, same entity size and same flags. ENTSIZE must be an absolute 5382expression. For sections with both 'M' and 'S', a string which is a 5383suffix of a larger string is considered a duplicate. Thus '"def"' will 5384be merged with '"abcdef"'; A reference to the first '"def"' will be 5385changed to a reference to '"abcdef"+3'. 5386 5387 If FLAGS contains the 'o' flag, then the TYPE argument must be 5388present along with an additional field like this: 5389 5390 .section NAME,"FLAGS"o,@TYPE,SYMBOLNAME|SECTIONINDEX 5391 5392 The SYMBOLNAME field specifies the symbol name which the section 5393references. Alternatively a numeric SECTIONINDEX can be provided. This 5394is not generally a good idea as section indicies are rarely known at 5395assembly time, but the facility is provided for testing purposes. An 5396index of zero is allowed. It indicates that the linked-to section has 5397already been discarded. 5398 5399 Note: If both the M and O flags are present, then the fields for the 5400Merge flag should come first, like this: 5401 5402 .section NAME,"FLAGS"Mo,@TYPE,ENTSIZE,SYMBOLNAME 5403 5404 If FLAGS contains the 'G' symbol then the TYPE argument must be 5405present along with an additional field like this: 5406 5407 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] 5408 5409 The GROUPNAME field specifies the name of the section group to which 5410this particular section belongs. The optional linkage field can 5411contain: 5412 5413'comdat' 5414 indicates that only one copy of this section should be retained 5415'.gnu.linkonce' 5416 an alias for comdat 5417 5418 Note: if both the M and G flags are present then the fields for the 5419Merge flag should come first, like this: 5420 5421 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] 5422 5423 If both 'o' flag and 'G' flag are present, then the SYMBOLNAME field 5424for 'o' comes first, like this: 5425 5426 .section NAME,"FLAGS"oG,@TYPE,SYMBOLNAME,GROUPNAME[,LINKAGE] 5427 5428 If FLAGS contains the '?' symbol then it may not also contain the 'G' 5429symbol and the GROUPNAME or LINKAGE fields should not be present. 5430Instead, '?' says to consider the section that's current before this 5431directive. If that section used 'G', then the new section will use 'G' 5432with those same GROUPNAME and LINKAGE fields implicitly. If not, then 5433the '?' symbol has no effect. 5434 5435 The optional UNIQUE,'<NUMBER>' argument must come last. It assigns 5436'<NUMBER>' as a unique section ID to distinguish different sections with 5437the same section name like these: 5438 5439 .section NAME,"FLAGS",@TYPE,UNIQUE,<NUMBER> 5440 .section NAME,"FLAGS"G,@TYPE,GROUPNAME,[LINKAGE],UNIQUE,<NUMBER> 5441 .section NAME,"FLAGS"MG,@TYPE,ENTSIZE,GROUPNAME[,LINKAGE],UNIQUE,<NUMBER> 5442 5443 The valid values of '<NUMBER>' are between 0 and 4294967295. 5444 5445 If no flags are specified, the default flags depend upon the section 5446name. If the section name is not recognized, the default will be for 5447the section to have none of the above flags: it will not be allocated in 5448memory, nor writable, nor executable. The section will contain data. 5449 5450 For ELF targets, the assembler supports another type of '.section' 5451directive for compatibility with the Solaris assembler: 5452 5453 .section "NAME"[, FLAGS...] 5454 5455 Note that the section name is quoted. There may be a sequence of 5456comma separated flags: 5457 5458'#alloc' 5459 section is allocatable 5460'#write' 5461 section is writable 5462'#execinstr' 5463 section is executable 5464'#exclude' 5465 section is excluded from executable and shared library. 5466'#tls' 5467 section is used for thread local storage 5468 5469 This directive replaces the current section and subsection. See the 5470contents of the gas testsuite directory 'gas/testsuite/gas/elf' for some 5471examples of how this directive and the other section stack directives 5472work. 5473 5474 5475File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops 5476 54777.86 '.set SYMBOL, EXPRESSION' 5478============================== 5479 5480Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and 5481type to conform to EXPRESSION. If SYMBOL was flagged as external, it 5482remains flagged (*note Symbol Attributes::). 5483 5484 You may '.set' a symbol many times in the same assembly provided that 5485the values given to the symbol are constants. Values that are based on 5486expressions involving other symbols are allowed, but some targets may 5487restrict this to only being done once per assembly. This is because 5488those targets do not set the addresses of symbols at assembly time, but 5489rather delay the assignment until a final link is performed. This 5490allows the linker a chance to change the code in the files, changing the 5491location of, and the relative distance between, various different 5492symbols. 5493 5494 If you '.set' a global symbol, the value stored in the object file is 5495the last value stored into it. 5496 5497 On Z80 'set' is a real instruction, use '.set' or 'SYMBOL defl 5498EXPRESSION' instead. 5499 5500 5501File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops 5502 55037.87 '.short EXPRESSIONS' 5504========================= 5505 5506'.short' is normally the same as '.word'. *Note '.word': Word. 5507 5508 In some configurations, however, '.short' and '.word' generate 5509numbers of different lengths. *Note Machine Dependencies::. 5510 5511 5512File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops 5513 55147.88 '.single FLONUMS' 5515====================== 5516 5517This directive assembles zero or more flonums, separated by commas. It 5518has the same effect as '.float'. The exact kind of floating point 5519numbers emitted depends on how 'as' is configured. *Note Machine 5520Dependencies::. 5521 5522 5523File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops 5524 55257.89 '.size' 5526============ 5527 5528This directive is used to set the size associated with a symbol. 5529 5530COFF Version 5531------------ 5532 5533For COFF targets, the '.size' directive is only permitted inside 5534'.def'/'.endef' pairs. It is used like this: 5535 5536 .size EXPRESSION 5537 5538ELF Version 5539----------- 5540 5541For ELF targets, the '.size' directive is used like this: 5542 5543 .size NAME , EXPRESSION 5544 5545 This directive sets the size associated with a symbol NAME. The size 5546in bytes is computed from EXPRESSION which can make use of label 5547arithmetic. This directive is typically used to set the size of 5548function symbols. 5549 5550 5551File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops 5552 55537.90 '.skip SIZE [,FILL]' 5554========================= 5555 5556This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL 5557are absolute expressions. If the comma and FILL are omitted, FILL is 5558assumed to be zero. This is the same as '.space'. 5559 5560 5561File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops 5562 55637.91 '.sleb128 EXPRESSIONS' 5564=========================== 5565 5566SLEB128 stands for "signed little endian base 128." This is a compact, 5567variable length representation of numbers used by the DWARF symbolic 5568debugging format. *Note '.uleb128': Uleb128. 5569 5570 5571File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops 5572 55737.92 '.space SIZE [,FILL]' 5574========================== 5575 5576This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL 5577are absolute expressions. If the comma and FILL are omitted, FILL is 5578assumed to be zero. This is the same as '.skip'. 5579 5580 _Warning:_ '.space' has a completely different meaning for HPPA 5581 targets; use '.block' as a substitute. See 'HP9000 Series 800 5582 Assembly Language Reference Manual' (HP 92432-90001) for the 5583 meaning of the '.space' directive. *Note HPPA Assembler 5584 Directives: HPPA Directives, for a summary. 5585 5586 5587File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops 5588 55897.93 '.stabd, .stabn, .stabs' 5590============================= 5591 5592There are three directives that begin '.stab'. All emit symbols (*note 5593Symbols::), for use by symbolic debuggers. The symbols are not entered 5594in the 'as' hash table: they cannot be referenced elsewhere in the 5595source file. Up to five fields are required: 5596 5597STRING 5598 This is the symbol's name. It may contain any character except 5599 '\000', so is more general than ordinary symbol names. Some 5600 debuggers used to code arbitrarily complex structures into symbol 5601 names using this field. 5602 5603TYPE 5604 An absolute expression. The symbol's type is set to the low 8 bits 5605 of this expression. Any bit pattern is permitted, but 'ld' and 5606 debuggers choke on silly bit patterns. 5607 5608OTHER 5609 An absolute expression. The symbol's "other" attribute is set to 5610 the low 8 bits of this expression. 5611 5612DESC 5613 An absolute expression. The symbol's descriptor is set to the low 5614 16 bits of this expression. 5615 5616VALUE 5617 An absolute expression which becomes the symbol's value. 5618 5619 If a warning is detected while reading a '.stabd', '.stabn', or 5620'.stabs' statement, the symbol has probably already been created; you 5621get a half-formed symbol in your object file. This is compatible with 5622earlier assemblers! 5623 5624'.stabd TYPE , OTHER , DESC' 5625 5626 The "name" of the symbol generated is not even an empty string. It 5627 is a null pointer, for compatibility. Older assemblers used a null 5628 pointer so they didn't waste space in object files with empty 5629 strings. 5630 5631 The symbol's value is set to the location counter, relocatably. 5632 When your program is linked, the value of this symbol is the 5633 address of the location counter when the '.stabd' was assembled. 5634 5635'.stabn TYPE , OTHER , DESC , VALUE' 5636 The name of the symbol is set to the empty string '""'. 5637 5638'.stabs STRING , TYPE , OTHER , DESC , VALUE' 5639 All five fields are specified. 5640 5641 5642File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops 5643 56447.94 '.string' "STR", '.string8' "STR", '.string16' 5645=================================================== 5646 5647"STR", '.string32' "STR", '.string64' "STR" 5648 5649 Copy the characters in STR to the object file. You may specify more 5650than one string to copy, separated by commas. Unless otherwise 5651specified for a particular machine, the assembler marks the end of each 5652string with a 0 byte. You can use any of the escape sequences described 5653in *note Strings: Strings. 5654 5655 The variants 'string16', 'string32' and 'string64' differ from the 5656'string' pseudo opcode in that each 8-bit character from STR is copied 5657and expanded to 16, 32 or 64 bits respectively. The expanded characters 5658are stored in target endianness byte order. 5659 5660 Example: 5661 .string32 "BYE" 5662 expands to: 5663 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ 5664 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ 5665 5666 5667File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops 5668 56697.95 '.struct EXPRESSION' 5670========================= 5671 5672Switch to the absolute section, and set the section offset to 5673EXPRESSION, which must be an absolute expression. You might use this as 5674follows: 5675 .struct 0 5676 field1: 5677 .struct field1 + 4 5678 field2: 5679 .struct field2 + 4 5680 field3: 5681 This would define the symbol 'field1' to have the value 0, the symbol 5682'field2' to have the value 4, and the symbol 'field3' to have the value 56838. Assembly would be left in the absolute section, and you would need 5684to use a '.section' directive of some sort to change to some other 5685section before further assembly. 5686 5687 5688File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops 5689 56907.96 '.subsection NAME' 5691======================= 5692 5693This is one of the ELF section stack manipulation directives. The 5694others are '.section' (*note Section::), '.pushsection' (*note 5695PushSection::), '.popsection' (*note PopSection::), and '.previous' 5696(*note Previous::). 5697 5698 This directive replaces the current subsection with 'name'. The 5699current section is not changed. The replaced subsection is put onto the 5700section stack in place of the then current top of stack subsection. 5701 5702 5703File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops 5704 57057.97 '.symver' 5706============== 5707 5708Use the '.symver' directive to bind symbols to specific version nodes 5709within a source file. This is only supported on ELF platforms, and is 5710typically used when assembling files to be linked into a shared library. 5711There are cases where it may make sense to use this in objects to be 5712bound into an application itself so as to override a versioned symbol 5713from a shared library. 5714 5715 For ELF targets, the '.symver' directive can be used like this: 5716 .symver NAME, NAME2@NODENAME[ ,VISIBILITY] 5717 If the original symbol NAME is defined within the file being 5718assembled, the '.symver' directive effectively creates a symbol alias 5719with the name NAME2@NODENAME, and in fact the main reason that we just 5720don't try and create a regular alias is that the @ character isn't 5721permitted in symbol names. The NAME2 part of the name is the actual 5722name of the symbol by which it will be externally referenced. The name 5723NAME itself is merely a name of convenience that is used so that it is 5724possible to have definitions for multiple versions of a function within 5725a single source file, and so that the compiler can unambiguously know 5726which version of a function is being mentioned. The NODENAME portion of 5727the alias should be the name of a node specified in the version script 5728supplied to the linker when building a shared library. If you are 5729attempting to override a versioned symbol from a shared library, then 5730NODENAME should correspond to the nodename of the symbol you are trying 5731to override. The optional argument VISIBILITY updates the visibility of 5732the original symbol. The valid visibilities are 'local', 'hidden', and 5733'remove'. The 'local' visibility makes the original symbol a local 5734symbol (*note Local::). The 'hidden' visibility sets the visibility of 5735the original symbol to 'hidden' (*note Hidden::). The 'remove' 5736visibility removes the original symbol from the symbol table. If 5737visibility isn't specified, the original symbol is unchanged. 5738 5739 If the symbol NAME is not defined within the file being assembled, 5740all references to NAME will be changed to NAME2@NODENAME. If no 5741reference to NAME is made, NAME2@NODENAME will be removed from the 5742symbol table. 5743 5744 Another usage of the '.symver' directive is: 5745 .symver NAME, NAME2@@NODENAME 5746 In this case, the symbol NAME must exist and be defined within the 5747file being assembled. It is similar to NAME2@NODENAME. The difference 5748is NAME2@@NODENAME will also be used to resolve references to NAME2 by 5749the linker. 5750 5751 The third usage of the '.symver' directive is: 5752 .symver NAME, NAME2@@@NODENAME 5753 When NAME is not defined within the file being assembled, it is 5754treated as NAME2@NODENAME. When NAME is defined within the file being 5755assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. 5756 5757 5758File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops 5759 57607.98 '.tag STRUCTNAME' 5761====================== 5762 5763This directive is generated by compilers to include auxiliary debugging 5764information in the symbol table. It is only permitted inside 5765'.def'/'.endef' pairs. Tags are used to link structure definitions in 5766the symbol table with instances of those structures. 5767 5768 5769File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops 5770 57717.99 '.text SUBSECTION' 5772======================= 5773 5774Tells 'as' to assemble the following statements onto the end of the text 5775subsection numbered SUBSECTION, which is an absolute expression. If 5776SUBSECTION is omitted, subsection number zero is used. 5777 5778 5779File: as.info, Node: Title, Next: Tls_common, Prev: Text, Up: Pseudo Ops 5780 57817.100 '.title "HEADING"' 5782======================== 5783 5784Use HEADING as the title (second line, immediately after the source file 5785name and pagenumber) when generating assembly listings. 5786 5787 This directive affects subsequent pages, as well as the current page 5788if it appears within ten lines of the top of a page. 5789 5790 5791File: as.info, Node: Tls_common, Next: Type, Prev: Title, Up: Pseudo Ops 5792 57937.101 '.tls_common SYMBOL, LENGTH[, ALIGNMENT]' 5794=============================================== 5795 5796This directive behaves in the same way as the '.comm' directive (*note 5797Comm::) except that SYMBOL has type of STT_TLS instead of STT_OBJECT. 5798 5799 5800File: as.info, Node: Type, Next: Uleb128, Prev: Tls_common, Up: Pseudo Ops 5801 58027.102 '.type' 5803============= 5804 5805This directive is used to set the type of a symbol. 5806 5807COFF Version 5808------------ 5809 5810For COFF targets, this directive is permitted only within 5811'.def'/'.endef' pairs. It is used like this: 5812 5813 .type INT 5814 5815 This records the integer INT as the type attribute of a symbol table 5816entry. 5817 5818ELF Version 5819----------- 5820 5821For ELF targets, the '.type' directive is used like this: 5822 5823 .type NAME , TYPE DESCRIPTION 5824 5825 This sets the type of symbol NAME to be either a function symbol or 5826an object symbol. There are five different syntaxes supported for the 5827TYPE DESCRIPTION field, in order to provide compatibility with various 5828other assemblers. 5829 5830 Because some of the characters used in these syntaxes (such as '@' 5831and '#') are comment characters for some architectures, some of the 5832syntaxes below do not work on all architectures. The first variant will 5833be accepted by the GNU assembler on all architectures so that variant 5834should be used for maximum portability, if you do not need to assemble 5835your code with other assemblers. 5836 5837 The syntaxes supported are: 5838 5839 .type <name> STT_<TYPE_IN_UPPER_CASE> 5840 .type <name>,#<type> 5841 .type <name>,@<type> 5842 .type <name>,%<type> 5843 .type <name>,"<type>" 5844 5845 The types supported are: 5846 5847'STT_FUNC' 5848'function' 5849 Mark the symbol as being a function name. 5850 5851'STT_GNU_IFUNC' 5852'gnu_indirect_function' 5853 Mark the symbol as an indirect function when evaluated during reloc 5854 processing. (This is only supported on assemblers targeting GNU 5855 systems). 5856 5857'STT_OBJECT' 5858'object' 5859 Mark the symbol as being a data object. 5860 5861'STT_TLS' 5862'tls_object' 5863 Mark the symbol as being a thread-local data object. 5864 5865'STT_COMMON' 5866'common' 5867 Mark the symbol as being a common data object. 5868 5869'STT_NOTYPE' 5870'notype' 5871 Does not mark the symbol in any way. It is supported just for 5872 completeness. 5873 5874'gnu_unique_object' 5875 Marks the symbol as being a globally unique data object. The 5876 dynamic linker will make sure that in the entire process there is 5877 just one symbol with this name and type in use. (This is only 5878 supported on assemblers targeting GNU systems). 5879 5880 Changing between incompatible types other than from/to STT_NOTYPE 5881will result in a diagnostic. An intermediate change to STT_NOTYPE will 5882silence this. 5883 5884 Note: Some targets support extra types in addition to those listed 5885above. 5886 5887 5888File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops 5889 58907.103 '.uleb128 EXPRESSIONS' 5891============================ 5892 5893ULEB128 stands for "unsigned little endian base 128." This is a 5894compact, variable length representation of numbers used by the DWARF 5895symbolic debugging format. *Note '.sleb128': Sleb128. 5896 5897 5898File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops 5899 59007.104 '.val ADDR' 5901================= 5902 5903This directive, permitted only within '.def'/'.endef' pairs, records the 5904address ADDR as the value attribute of a symbol table entry. 5905 5906 5907File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops 5908 59097.105 '.version "STRING"' 5910========================= 5911 5912This directive creates a '.note' section and places into it an ELF 5913formatted note of type NT_VERSION. The note's name is set to 'string'. 5914 5915 5916File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops 5917 59187.106 '.vtable_entry TABLE, OFFSET' 5919=================================== 5920 5921This directive finds or creates a symbol 'table' and creates a 5922'VTABLE_ENTRY' relocation for it with an addend of 'offset'. 5923 5924 5925File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops 5926 59277.107 '.vtable_inherit CHILD, PARENT' 5928===================================== 5929 5930This directive finds the symbol 'child' and finds or creates the symbol 5931'parent' and then creates a 'VTABLE_INHERIT' relocation for the parent 5932whose addend is the value of the child symbol. As a special case the 5933parent name of '0' is treated as referring to the '*ABS*' section. 5934 5935 5936File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops 5937 59387.108 '.warning "STRING"' 5939========================= 5940 5941Similar to the directive '.error' (*note '.error "STRING"': Error.), but 5942just emits a warning. 5943 5944 5945File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops 5946 59477.109 '.weak NAMES' 5948=================== 5949 5950This directive sets the weak attribute on the comma separated list of 5951symbol 'names'. If the symbols do not already exist, they will be 5952created. 5953 5954 On COFF targets other than PE, weak symbols are a GNU extension. 5955This directive sets the weak attribute on the comma separated list of 5956symbol 'names'. If the symbols do not already exist, they will be 5957created. 5958 5959 On the PE target, weak symbols are supported natively as weak 5960aliases. When a weak symbol is created that is not an alias, GAS 5961creates an alternate symbol to hold the default value. 5962 5963 5964File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops 5965 59667.110 '.weakref ALIAS, TARGET' 5967============================== 5968 5969This directive creates an alias to the target symbol that enables the 5970symbol to be referenced with weak-symbol semantics, but without actually 5971making it weak. If direct references or definitions of the symbol are 5972present, then the symbol will not be weak, but if all references to it 5973are through weak references, the symbol will be marked as weak in the 5974symbol table. 5975 5976 The effect is equivalent to moving all references to the alias to a 5977separate assembly source file, renaming the alias to the symbol in it, 5978declaring the symbol as weak there, and running a reloadable link to 5979merge the object files resulting from the assembly of the new source 5980file and the old source file that had the references to the alias 5981removed. 5982 5983 The alias itself never makes to the symbol table, and is entirely 5984handled within the assembler. 5985 5986 5987File: as.info, Node: Word, Next: Zero, Prev: Weakref, Up: Pseudo Ops 5988 59897.111 '.word EXPRESSIONS' 5990========================= 5991 5992This directive expects zero or more EXPRESSIONS, of any section, 5993separated by commas. 5994 5995 The size of the number emitted, and its byte order, depend on what 5996target computer the assembly is for. 5997 5998 _Warning: Special Treatment to support Compilers_ 5999 6000 Machines with a 32-bit address space, but that do less than 32-bit 6001addressing, require the following special treatment. If the machine of 6002interest to you does 32-bit addressing (or doesn't require it; *note 6003Machine Dependencies::), you can ignore this issue. 6004 6005 In order to assemble compiler output into something that works, 'as' 6006occasionally does strange things to '.word' directives. Directives of 6007the form '.word sym1-sym2' are often emitted by compilers as part of 6008jump tables. Therefore, when 'as' assembles a directive of the form 6009'.word sym1-sym2', and the difference between 'sym1' and 'sym2' does not 6010fit in 16 bits, 'as' creates a "secondary jump table", immediately 6011before the next label. This secondary jump table is preceded by a 6012short-jump to the first byte after the secondary table. This short-jump 6013prevents the flow of control from accidentally falling into the new 6014table. Inside the table is a long-jump to 'sym2'. The original '.word' 6015contains 'sym1' minus the address of the long-jump to 'sym2'. 6016 6017 If there were several occurrences of '.word sym1-sym2' before the 6018secondary jump table, all of them are adjusted. If there was a '.word 6019sym3-sym4', that also did not fit in sixteen bits, a long-jump to 'sym4' 6020is included in the secondary jump table, and the '.word' directives are 6021adjusted to contain 'sym3' minus the address of the long-jump to 'sym4'; 6022and so on, for as many entries in the original jump table as necessary. 6023 6024 6025File: as.info, Node: Zero, Next: 2byte, Prev: Word, Up: Pseudo Ops 6026 60277.112 '.zero SIZE' 6028================== 6029 6030This directive emits SIZE 0-valued bytes. SIZE must be an absolute 6031expression. This directive is actually an alias for the '.skip' 6032directive so it can take an optional second argument of the value to 6033store in the bytes instead of zero. Using '.zero' in this way would be 6034confusing however. 6035 6036 6037File: as.info, Node: 2byte, Next: 4byte, Prev: Zero, Up: Pseudo Ops 6038 60397.113 '.2byte EXPRESSION [, EXPRESSION]*' 6040========================================= 6041 6042This directive expects zero or more expressions, separated by commas. 6043If there are no expressions then the directive does nothing. Otherwise 6044each expression is evaluated in turn and placed in the next two bytes of 6045the current output section, using the endian model of the target. If an 6046expression will not fit in two bytes, a warning message is displayed and 6047the least significant two bytes of the expression's value are used. If 6048an expression cannot be evaluated at assembly time then relocations will 6049be generated in order to compute the value at link time. 6050 6051 This directive does not apply any alignment before or after inserting 6052the values. As a result of this, if relocations are generated, they may 6053be different from those used for inserting values with a guaranteed 6054alignment. 6055 6056 6057File: as.info, Node: 4byte, Next: 8byte, Prev: 2byte, Up: Pseudo Ops 6058 60597.114 '.4byte EXPRESSION [, EXPRESSION]*' 6060========================================= 6061 6062Like the '.2byte' directive, except that it inserts unaligned, four byte 6063long values into the output. 6064 6065 6066File: as.info, Node: 8byte, Next: Deprecated, Prev: 4byte, Up: Pseudo Ops 6067 60687.115 '.8byte EXPRESSION [, EXPRESSION]*' 6069========================================= 6070 6071Like the '.2byte' directive, except that it inserts unaligned, eight 6072byte long bignum values into the output. 6073 6074 6075File: as.info, Node: Deprecated, Prev: 8byte, Up: Pseudo Ops 6076 60777.116 Deprecated Directives 6078=========================== 6079 6080One day these directives won't work. They are included for 6081compatibility with older assemblers. 6082.abort 6083.line 6084 6085 6086File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top 6087 60888 Object Attributes 6089******************* 6090 6091'as' assembles source files written for a specific architecture into 6092object files for that architecture. But not all object files are alike. 6093Many architectures support incompatible variations. For instance, 6094floating point arguments might be passed in floating point registers if 6095the object file requires hardware floating point support--or floating 6096point arguments might be passed in integer registers if the object file 6097supports processors with no hardware floating point unit. Or, if two 6098objects are built for different generations of the same architecture, 6099the combination may require the newer generation at run-time. 6100 6101 This information is useful during and after linking. At link time, 6102'ld' can warn about incompatible object files. After link time, tools 6103like 'gdb' can use it to process the linked file correctly. 6104 6105 Compatibility information is recorded as a series of object 6106attributes. Each attribute has a "vendor", "tag", and "value". The 6107vendor is a string, and indicates who sets the meaning of the tag. The 6108tag is an integer, and indicates what property the attribute describes. 6109The value may be a string or an integer, and indicates how the property 6110affects this object. Missing attributes are the same as attributes with 6111a zero value or empty string value. 6112 6113 Object attributes were developed as part of the ABI for the ARM 6114Architecture. The file format is documented in 'ELF for the ARM 6115Architecture'. 6116 6117* Menu: 6118 6119* GNU Object Attributes:: GNU Object Attributes 6120* Defining New Object Attributes:: Defining New Object Attributes 6121 6122 6123File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes 6124 61258.1 GNU Object Attributes 6126========================= 6127 6128The '.gnu_attribute' directive records an object attribute with vendor 6129'gnu'. 6130 6131 Except for 'Tag_compatibility', which has both an integer and a 6132string for its value, GNU attributes have a string value if the tag 6133number is odd and an integer value if the tag number is even. The 6134second bit ('TAG & 2' is set for architecture-independent attributes and 6135clear for architecture-dependent ones. 6136 61378.1.1 Common GNU attributes 6138--------------------------- 6139 6140These attributes are valid on all architectures. 6141 6142Tag_compatibility (32) 6143 The compatibility attribute takes an integer flag value and a 6144 vendor name. If the flag value is 0, the file is compatible with 6145 other toolchains. If it is 1, then the file is only compatible 6146 with the named toolchain. If it is greater than 1, the file can 6147 only be processed by other toolchains under some private 6148 arrangement indicated by the flag value and the vendor name. 6149 61508.1.2 M680x0 Attributes 6151----------------------- 6152 6153Tag_GNU_M68K_ABI_FP (4) 6154 The floating-point ABI used by this object file. The value will 6155 be: 6156 6157 * 0 for files not affected by the floating-point ABI. 6158 * 1 for files using double-precision hardware floating-point 6159 ABI. 6160 * 2 for files using the software floating-point ABI. 6161 61628.1.3 MIPS Attributes 6163--------------------- 6164 6165Tag_GNU_MIPS_ABI_FP (4) 6166 The floating-point ABI used by this object file. The value will 6167 be: 6168 6169 * 0 for files not affected by the floating-point ABI. 6170 * 1 for files using the hardware floating-point ABI with a 6171 standard double-precision FPU. 6172 * 2 for files using the hardware floating-point ABI with a 6173 single-precision FPU. 6174 * 3 for files using the software floating-point ABI. 6175 * 4 for files using the deprecated hardware floating-point ABI 6176 which used 64-bit floating-point registers, 32-bit 6177 general-purpose registers and increased the number of 6178 callee-saved floating-point registers. 6179 * 5 for files using the hardware floating-point ABI with a 6180 double-precision FPU with either 32-bit or 64-bit 6181 floating-point registers and 32-bit general-purpose registers. 6182 * 6 for files using the hardware floating-point ABI with 64-bit 6183 floating-point registers and 32-bit general-purpose registers. 6184 * 7 for files using the hardware floating-point ABI with 64-bit 6185 floating-point registers, 32-bit general-purpose registers and 6186 a rule that forbids the direct use of odd-numbered 6187 single-precision floating-point registers. 6188 61898.1.4 PowerPC Attributes 6190------------------------ 6191 6192Tag_GNU_Power_ABI_FP (4) 6193 The floating-point ABI used by this object file. The value will 6194 be: 6195 6196 * 0 for files not affected by the floating-point ABI. 6197 * 1 for files using double-precision hardware floating-point 6198 ABI. 6199 * 2 for files using the software floating-point ABI. 6200 * 3 for files using single-precision hardware floating-point 6201 ABI. 6202 6203Tag_GNU_Power_ABI_Vector (8) 6204 The vector ABI used by this object file. The value will be: 6205 6206 * 0 for files not affected by the vector ABI. 6207 * 1 for files using general purpose registers to pass vectors. 6208 * 2 for files using AltiVec registers to pass vectors. 6209 * 3 for files using SPE registers to pass vectors. 6210 62118.1.5 IBM z Systems Attributes 6212------------------------------ 6213 6214Tag_GNU_S390_ABI_Vector (8) 6215 The vector ABI used by this object file. The value will be: 6216 6217 * 0 for files not affected by the vector ABI. 6218 * 1 for files using software vector ABI. 6219 * 2 for files using hardware vector ABI. 6220 62218.1.6 MSP430 Attributes 6222----------------------- 6223 6224Tag_GNU_MSP430_Data_Region (4) 6225 The data region used by this object file. The value will be: 6226 6227 * 0 for files not using the large memory model. 6228 * 1 for files which have been compiled with the condition that 6229 all data is in the lower memory region, i.e. below address 6230 0x10000. 6231 * 2 for files which allow data to be placed in the full 20-bit 6232 memory range. 6233 6234 6235File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes 6236 62378.2 Defining New Object Attributes 6238================================== 6239 6240If you want to define a new GNU object attribute, here are the places 6241you will need to modify. New attributes should be discussed on the 6242'binutils' mailing list. 6243 6244 * This manual, which is the official register of attributes. 6245 * The header for your architecture 'include/elf', to define the tag. 6246 * The 'bfd' support file for your architecture, to merge the 6247 attribute and issue any appropriate link warnings. 6248 * Test cases in 'ld/testsuite' for merging and link warnings. 6249 * 'binutils/readelf.c' to display your attribute. 6250 * GCC, if you want the compiler to mark the attribute automatically. 6251 6252 6253File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top 6254 62559 Machine Dependent Features 6256**************************** 6257 6258The machine instruction sets are (almost by definition) different on 6259each machine where 'as' runs. Floating point representations vary as 6260well, and 'as' often supports a few additional directives or 6261command-line options for compatibility with other assemblers on a 6262particular platform. Finally, some versions of 'as' support special 6263pseudo-instructions for branch optimization. 6264 6265 This chapter discusses most of these differences, though it does not 6266include details on any machine's instruction set. For details on that 6267subject, see the hardware manufacturer's manual. 6268 6269* Menu: 6270 6271* AArch64-Dependent:: AArch64 Dependent Features 6272* Alpha-Dependent:: Alpha Dependent Features 6273* ARC-Dependent:: ARC Dependent Features 6274* ARM-Dependent:: ARM Dependent Features 6275* AVR-Dependent:: AVR Dependent Features 6276* Blackfin-Dependent:: Blackfin Dependent Features 6277* BPF-Dependent:: BPF Dependent Features 6278* CR16-Dependent:: CR16 Dependent Features 6279* CRIS-Dependent:: CRIS Dependent Features 6280* C-SKY-Dependent:: C-SKY Dependent Features 6281* D10V-Dependent:: D10V Dependent Features 6282* D30V-Dependent:: D30V Dependent Features 6283* Epiphany-Dependent:: EPIPHANY Dependent Features 6284* H8/300-Dependent:: Renesas H8/300 Dependent Features 6285* HPPA-Dependent:: HPPA Dependent Features 6286* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features 6287* IA-64-Dependent:: Intel IA-64 Dependent Features 6288* IP2K-Dependent:: IP2K Dependent Features 6289* LM32-Dependent:: LM32 Dependent Features 6290* M32C-Dependent:: M32C Dependent Features 6291* M32R-Dependent:: M32R Dependent Features 6292* M68K-Dependent:: M680x0 Dependent Features 6293* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features 6294* S12Z-Dependent:: S12Z Dependent Features 6295* Meta-Dependent :: Meta Dependent Features 6296* MicroBlaze-Dependent:: MICROBLAZE Dependent Features 6297* MIPS-Dependent:: MIPS Dependent Features 6298* MMIX-Dependent:: MMIX Dependent Features 6299* MSP430-Dependent:: MSP430 Dependent Features 6300* NDS32-Dependent:: Andes NDS32 Dependent Features 6301* NiosII-Dependent:: Altera Nios II Dependent Features 6302* NS32K-Dependent:: NS32K Dependent Features 6303* OpenRISC-Dependent:: OpenRISC 1000 Features 6304* PDP-11-Dependent:: PDP-11 Dependent Features 6305* PJ-Dependent:: picoJava Dependent Features 6306* PPC-Dependent:: PowerPC Dependent Features 6307* PRU-Dependent:: PRU Dependent Features 6308* RISC-V-Dependent:: RISC-V Dependent Features 6309* RL78-Dependent:: RL78 Dependent Features 6310* RX-Dependent:: RX Dependent Features 6311* S/390-Dependent:: IBM S/390 Dependent Features 6312* SCORE-Dependent:: SCORE Dependent Features 6313* SH-Dependent:: Renesas / SuperH SH Dependent Features 6314* Sparc-Dependent:: SPARC Dependent Features 6315* TIC54X-Dependent:: TI TMS320C54x Dependent Features 6316* TIC6X-Dependent :: TI TMS320C6x Dependent Features 6317* TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features 6318* TILEPro-Dependent :: Tilera TILEPro Dependent Features 6319* V850-Dependent:: V850 Dependent Features 6320* Vax-Dependent:: VAX Dependent Features 6321* Visium-Dependent:: Visium Dependent Features 6322* WebAssembly-Dependent:: WebAssembly Dependent Features 6323* XGATE-Dependent:: XGATE Dependent Features 6324* XSTORMY16-Dependent:: XStormy16 Dependent Features 6325* Xtensa-Dependent:: Xtensa Dependent Features 6326* Z80-Dependent:: Z80 Dependent Features 6327* Z8000-Dependent:: Z8000 Dependent Features 6328 6329 6330File: as.info, Node: AArch64-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies 6331 63329.1 AArch64 Dependent Features 6333============================== 6334 6335* Menu: 6336 6337* AArch64 Options:: Options 6338* AArch64 Extensions:: Extensions 6339* AArch64 Syntax:: Syntax 6340* AArch64 Floating Point:: Floating Point 6341* AArch64 Directives:: AArch64 Machine Directives 6342* AArch64 Opcodes:: Opcodes 6343* AArch64 Mapping Symbols:: Mapping Symbols 6344 6345 6346File: as.info, Node: AArch64 Options, Next: AArch64 Extensions, Up: AArch64-Dependent 6347 63489.1.1 Options 6349------------- 6350 6351'-EB' 6352 This option specifies that the output generated by the assembler 6353 should be marked as being encoded for a big-endian processor. 6354 6355'-EL' 6356 This option specifies that the output generated by the assembler 6357 should be marked as being encoded for a little-endian processor. 6358 6359'-mabi=ABI' 6360 Specify which ABI the source code uses. The recognized arguments 6361 are: 'ilp32' and 'lp64', which decides the generated object file in 6362 ELF32 and ELF64 format respectively. The default is 'lp64'. 6363 6364'-mcpu=PROCESSOR[+EXTENSION...]' 6365 This option specifies the target processor. The assembler will 6366 issue an error message if an attempt is made to assemble an 6367 instruction which will not execute on the target processor. The 6368 following processor names are recognized: 'cortex-a34', 6369 'cortex-a35', 'cortex-a53', 'cortex-a55', 'cortex-a57', 6370 'cortex-a65', 'cortex-a65ae', 'cortex-a72', 'cortex-a73', 6371 'cortex-a75', 'cortex-a76', 'cortex-a76ae', 'cortex-a77', 6372 'cortex-a78', 'cortex-a78ae', 'cortex-a78c', 'ares', 'exynos-m1', 6373 'falkor', 'neoverse-n1', 'neoverse-n2', 'neoverse-e1', 6374 'neoverse-v1', 'qdf24xx', 'saphira', 'thunderx', 'vulcan', 'xgene1' 6375 'xgene2', 'cortex-r82', and 'cortex-x1'. The special name 'all' 6376 may be used to allow the assembler to accept instructions valid for 6377 any supported processor, including all optional extensions. 6378 6379 In addition to the basic instruction set, the assembler can be told 6380 to accept, or restrict, various extension mnemonics that extend the 6381 processor. *Note AArch64 Extensions::. 6382 6383 If some implementations of a particular processor can have an 6384 extension, then then those extensions are automatically enabled. 6385 Consequently, you will not normally have to specify any additional 6386 extensions. 6387 6388'-march=ARCHITECTURE[+EXTENSION...]' 6389 This option specifies the target architecture. The assembler will 6390 issue an error message if an attempt is made to assemble an 6391 instruction which will not execute on the target architecture. The 6392 following architecture names are recognized: 'armv8-a', 6393 'armv8.1-a', 'armv8.2-a', 'armv8.3-a', 'armv8.4-a' 'armv8.5-a', 6394 'armv8.6-a', 'armv8.7-a', and 'armv8-r'. 6395 6396 If both '-mcpu' and '-march' are specified, the assembler will use 6397 the setting for '-mcpu'. If neither are specified, the assembler 6398 will default to '-mcpu=all'. 6399 6400 The architecture option can be extended with the same instruction 6401 set extension options as the '-mcpu' option. Unlike '-mcpu', 6402 extensions are not always enabled by default, *Note AArch64 6403 Extensions::. 6404 6405'-mverbose-error' 6406 This option enables verbose error messages for AArch64 gas. This 6407 option is enabled by default. 6408 6409'-mno-verbose-error' 6410 This option disables verbose error messages in AArch64 gas. 6411 6412 6413File: as.info, Node: AArch64 Extensions, Next: AArch64 Syntax, Prev: AArch64 Options, Up: AArch64-Dependent 6414 64159.1.2 Architecture Extensions 6416----------------------------- 6417 6418The table below lists the permitted architecture extensions that are 6419supported by the assembler and the conditions under which they are 6420automatically enabled. 6421 6422 Multiple extensions may be specified, separated by a '+'. Extension 6423mnemonics may also be removed from those the assembler accepts. This is 6424done by prepending 'no' to the option that adds the extension. 6425Extensions that are removed must be listed after all extensions that 6426have been added. 6427 6428 Enabling an extension that requires other extensions will 6429automatically cause those extensions to be enabled. Similarly, 6430disabling an extension that is required by other extensions will 6431automatically cause those extensions to be disabled. 6432 6433Extension Minimum Enabled by Description 6434 Architecture default 6435---------------------------------------------------------------------------- 6436'i8mm' ARMv8.2-A ARMv8.6-A Enable Int8 Matrix Multiply 6437 or later extension. 6438'f32mm' ARMv8.2-A No Enable F32 Matrix Multiply extension. 6439'f64mm' ARMv8.2-A No Enable F64 Matrix Multiply extension. 6440'bf16' ARMv8.2-A ARMv8.6-A Enable BFloat16 extension. 6441 or later 6442'compnum' ARMv8.2-A ARMv8.3-A Enable the complex number SIMD 6443 or later extensions. This implies 'fp16' and 6444 'simd'. 6445'crc' ARMv8-A ARMv8.1-A Enable CRC instructions. 6446 or later 6447'crypto' ARMv8-A No Enable cryptographic extensions. 6448 This implies 'fp', 'simd', 'aes' and 6449 'sha2'. 6450'aes' ARMv8-A No Enable the AES cryptographic 6451 extensions. This implies 'fp' and 6452 'simd'. 6453'sha2' ARMv8-A No Enable the SHA2 cryptographic 6454 extensions. This implies 'fp' and 6455 'simd'. 6456'sha3' ARMv8.2-A No Enable the ARMv8.2-A SHA2 and SHA3 6457 cryptographic extensions. This 6458 implies 'fp', 'simd' and 'sha2'. 6459'sm4' ARMv8.2-A No Enable the ARMv8.2-A SM3 and SM4 6460 cryptographic extensions. This 6461 implies 'fp' and 'simd'. 6462'fp' ARMv8-A ARMv8-A or Enable floating-point extensions. 6463 later 6464'fp16' ARMv8.2-A ARMv8.2-A Enable ARMv8.2 16-bit floating-point 6465 or later support. This implies 'fp'. 6466'lor' ARMv8-A ARMv8.1-A Enable Limited Ordering Regions 6467 or later extensions. 6468'lse' ARMv8-A ARMv8.1-A Enable Large System extensions. 6469 or later 6470'pan' ARMv8-A ARMv8.1-A Enable Privileged Access Never 6471 or later support. 6472'profile' ARMv8.2-A No Enable statistical profiling 6473 extensions. 6474'ras' ARMv8-A ARMv8.2-A Enable the Reliability, Availability 6475 or later and Serviceability extension. 6476'rcpc' ARMv8.2-A ARMv8.3-A Enable the weak release consistency 6477 or later extension. 6478'rdma' ARMv8-A ARMv8.1-A Enable ARMv8.1 Advanced SIMD 6479 or later extensions. This implies 'simd'. 6480'simd' ARMv8-A ARMv8-A or Enable Advanced SIMD extensions. 6481 later This implies 'fp'. 6482'sve' ARMv8.2-A No Enable the Scalable Vector 6483 Extensions. This implies 'fp16', 6484 'simd' and 'compnum'. 6485'dotprod' ARMv8.2-A ARMv8.4-A Enable the Dot Product extension. 6486 or later This implies 'simd'. 6487'fp16fml' ARMv8.2-A ARMv8.4-A Enable ARMv8.2 16-bit floating-point 6488 or later multiplication variant support. This 6489 implies 'fp16'. 6490'sb' ARMv8-A ARMv8.5-A Enable the speculation barrier 6491 or later instruction sb. 6492'predres' ARMv8-A ARMv8.5-A Enable the Execution and Data and 6493 or later Prediction instructions. 6494'rng' ARMv8.5-A No Enable ARMv8.5-A random number 6495 instructions. 6496'ssbs' ARMv8-A ARMv8.5-A Enable Speculative Store Bypassing 6497 or later Safe state read and write. 6498'memtag' ARMv8.5-A No Enable ARMv8.5-A Memory Tagging 6499 Extensions. 6500'tme' ARMv8-A No Enable Transactional Memory 6501 Extensions. 6502'sve2' ARMv8-A No Enable the SVE2 Extension. 6503'sve2-bitperm'ARMv8-A No Enable SVE2 BITPERM Extension. 6504'sve2-sm4'ARMv8-A No Enable SVE2 SM4 Extension. 6505'sve2-aes'ARMv8-A No Enable SVE2 AES Extension. This also 6506 enables the .Q->.B form of the 6507 'pmullt' and 'pmullb' instructions. 6508'sve2-sha3'ARMv8-A No Enable SVE2 SHA3 Extension. 6509'flagm' ARMv8-A ARMv8.4-A Enable Flag Manipulation 6510 or later instructions. 6511'ls64' ARMv8.6-A ARMv8.7-A Enable 64 Byte Loads/Stores. 6512 or later 6513'pauth' ARMv8-A No Enable Pointer Authentication. 6514 6515 6516File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Extensions, Up: AArch64-Dependent 6517 65189.1.3 Syntax 6519------------ 6520 6521* Menu: 6522 6523* AArch64-Chars:: Special Characters 6524* AArch64-Regs:: Register Names 6525* AArch64-Relocations:: Relocations 6526 6527 6528File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax 6529 65309.1.3.1 Special Characters 6531.......................... 6532 6533The presence of a '//' on a line indicates the start of a comment that 6534extends to the end of the current line. If a '#' appears as the first 6535character of a line, the whole line is treated as a comment. 6536 6537 The ';' character can be used instead of a newline to separate 6538statements. 6539 6540 The '#' can be optionally used to indicate immediate operands. 6541 6542 6543File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax 6544 65459.1.3.2 Register Names 6546...................... 6547 6548Please refer to the section '4.4 Register Names' of 'ARMv8 Instruction 6549Set Overview', which is available at <http://infocenter.arm.com>. 6550 6551 6552File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax 6553 65549.1.3.3 Relocations 6555................... 6556 6557Relocations for 'MOVZ' and 'MOVK' instructions can be generated by 6558prefixing the label with '#:abs_g2:' etc. For example to load the 655948-bit absolute address of FOO into x0: 6560 6561 movz x0, #:abs_g2:foo // bits 32-47, overflow check 6562 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 6563 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 6564 6565 Relocations for 'ADRP', and 'ADD', 'LDR' or 'STR' instructions can be 6566generated by prefixing the label with ':pg_hi21:' and '#:lo12:' 6567respectively. 6568 6569 For example to use 33-bit (+/-4GB) pc-relative addressing to load the 6570address of FOO into x0: 6571 6572 adrp x0, :pg_hi21:foo 6573 add x0, x0, #:lo12:foo 6574 6575 Or to load the value of FOO into x0: 6576 6577 adrp x0, :pg_hi21:foo 6578 ldr x0, [x0, #:lo12:foo] 6579 6580 Note that ':pg_hi21:' is optional. 6581 6582 adrp x0, foo 6583 6584 is equivalent to 6585 6586 adrp x0, :pg_hi21:foo 6587 6588 6589File: as.info, Node: AArch64 Floating Point, Next: AArch64 Directives, Prev: AArch64 Syntax, Up: AArch64-Dependent 6590 65919.1.4 Floating Point 6592-------------------- 6593 6594The AArch64 architecture uses IEEE floating-point numbers. 6595 6596 6597File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 Floating Point, Up: AArch64-Dependent 6598 65999.1.5 AArch64 Machine Directives 6600-------------------------------- 6601 6602'.arch NAME' 6603 Select the target architecture. Valid values for NAME are the same 6604 as for the '-march' command-line option. 6605 6606 Specifying '.arch' clears any previously selected architecture 6607 extensions. 6608 6609'.arch_extension NAME' 6610 Add or remove an architecture extension to the target architecture. 6611 Valid values for NAME are the same as those accepted as 6612 architectural extensions by the '-mcpu' command-line option. 6613 6614 '.arch_extension' may be used multiple times to add or remove 6615 extensions incrementally to the architecture being compiled for. 6616 6617'.bss' 6618 This directive switches to the '.bss' section. 6619 6620'.cpu NAME' 6621 Set the target processor. Valid values for NAME are the same as 6622 those accepted by the '-mcpu=' command-line option. 6623 6624'.dword EXPRESSIONS' 6625 The '.dword' directive produces 64 bit values. 6626 6627'.even' 6628 The '.even' directive aligns the output on the next even byte 6629 boundary. 6630 6631'.float16 VALUE [,...,VALUE_N]' 6632 Place the half precision floating point representation of one or 6633 more floating-point values into the current section. The format 6634 used to encode the floating point values is always the IEEE 6635 754-2008 half precision floating point format. 6636 6637'.inst EXPRESSIONS' 6638 Inserts the expressions into the output as if they were 6639 instructions, rather than data. 6640 6641'.ltorg' 6642 This directive causes the current contents of the literal pool to 6643 be dumped into the current section (which is assumed to be the 6644 .text section) at the current location (aligned to a word 6645 boundary). GAS maintains a separate literal pool for each section 6646 and each sub-section. The '.ltorg' directive will only affect the 6647 literal pool of the current section and sub-section. At the end of 6648 assembly all remaining, un-empty literal pools will automatically 6649 be dumped. 6650 6651 Note - older versions of GAS would dump the current literal pool 6652 any time a section change occurred. This is no longer done, since 6653 it prevents accurate control of the placement of literal pools. 6654 6655'.pool' 6656 This is a synonym for .ltorg. 6657 6658'NAME .req REGISTER NAME' 6659 This creates an alias for REGISTER NAME called NAME. For example: 6660 6661 foo .req w0 6662 6663 ip0, ip1, lr and fp are automatically defined to alias to X16, X17, 6664 X30 and X29 respectively. 6665 6666'.tlsdescadd' 6667 Emits a TLSDESC_ADD reloc on the next instruction. 6668 6669'.tlsdesccall' 6670 Emits a TLSDESC_CALL reloc on the next instruction. 6671 6672'.tlsdescldr' 6673 Emits a TLSDESC_LDR reloc on the next instruction. 6674 6675'.unreq ALIAS-NAME' 6676 This undefines a register alias which was previously defined using 6677 the 'req' directive. For example: 6678 6679 foo .req w0 6680 .unreq foo 6681 6682 An error occurs if the name is undefined. Note - this pseudo op 6683 can be used to delete builtin in register name aliases (eg 'w0'). 6684 This should only be done if it is really necessary. 6685 6686'.variant_pcs SYMBOL' 6687 This directive marks SYMBOL referencing a function that may follow 6688 a variant procedure call standard with different register usage 6689 convention from the base procedure call standard. 6690 6691'.xword EXPRESSIONS' 6692 The '.xword' directive produces 64 bit values. This is the same as 6693 the '.dword' directive. 6694 6695'.cfi_b_key_frame' 6696 The '.cfi_b_key_frame' directive inserts a 'B' character into the 6697 CIE corresponding to the current frame's FDE, meaning that its 6698 return address has been signed with the B-key. If two frames are 6699 signed with differing keys then they will not share the same CIE. 6700 This information is intended to be used by the stack unwinder in 6701 order to properly authenticate return addresses. 6702 6703 6704File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent 6705 67069.1.6 Opcodes 6707------------- 6708 6709GAS implements all the standard AArch64 opcodes. It also implements 6710several pseudo opcodes, including several synthetic load instructions. 6711 6712'LDR =' 6713 ldr <register> , =<expression> 6714 6715 The constant expression will be placed into the nearest literal 6716 pool (if it not already there) and a PC-relative LDR instruction 6717 will be generated. 6718 6719 For more information on the AArch64 instruction set and assembly 6720language notation, see 'ARMv8 Instruction Set Overview' available at 6721<http://infocenter.arm.com>. 6722 6723 6724File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent 6725 67269.1.7 Mapping Symbols 6727--------------------- 6728 6729The AArch64 ELF specification requires that special symbols be inserted 6730into object files to mark certain features: 6731 6732'$x' 6733 At the start of a region of code containing AArch64 instructions. 6734 6735'$d' 6736 At the start of a region of data. 6737 6738 6739File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies 6740 67419.2 Alpha Dependent Features 6742============================ 6743 6744* Menu: 6745 6746* Alpha Notes:: Notes 6747* Alpha Options:: Options 6748* Alpha Syntax:: Syntax 6749* Alpha Floating Point:: Floating Point 6750* Alpha Directives:: Alpha Machine Directives 6751* Alpha Opcodes:: Opcodes 6752 6753 6754File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 6755 67569.2.1 Notes 6757----------- 6758 6759The documentation here is primarily for the ELF object format. 'as' 6760also supports the ECOFF and EVAX formats, but features specific to these 6761formats are not yet documented. 6762 6763 6764File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent 6765 67669.2.2 Options 6767------------- 6768 6769'-mCPU' 6770 This option specifies the target processor. If an attempt is made 6771 to assemble an instruction which will not execute on the target 6772 processor, the assembler may either expand the instruction as a 6773 macro or issue an error message. This option is equivalent to the 6774 '.arch' directive. 6775 6776 The following processor names are recognized: '21064', '21064a', 6777 '21066', '21068', '21164', '21164a', '21164pc', '21264', '21264a', 6778 '21264b', 'ev4', 'ev5', 'lca45', 'ev5', 'ev56', 'pca56', 'ev6', 6779 'ev67', 'ev68'. The special name 'all' may be used to allow the 6780 assembler to accept instructions valid for any Alpha processor. 6781 6782 In order to support existing practice in OSF/1 with respect to 6783 '.arch', and existing practice within 'MILO' (the Linux ARC 6784 bootloader), the numbered processor names (e.g. 21064) enable the 6785 processor-specific PALcode instructions, while the "electro-vlasic" 6786 names (e.g. 'ev4') do not. 6787 6788'-mdebug' 6789'-no-mdebug' 6790 Enables or disables the generation of '.mdebug' encapsulation for 6791 stabs directives and procedure descriptors. The default is to 6792 automatically enable '.mdebug' when the first stabs directive is 6793 seen. 6794 6795'-relax' 6796 This option forces all relocations to be put into the object file, 6797 instead of saving space and resolving some relocations at assembly 6798 time. Note that this option does not propagate all symbol 6799 arithmetic into the object file, because not all symbol arithmetic 6800 can be represented. However, the option can still be useful in 6801 specific applications. 6802 6803'-replace' 6804'-noreplace' 6805 Enables or disables the optimization of procedure calls, both at 6806 assemblage and at link time. These options are only available for 6807 VMS targets and '-replace' is the default. See section 1.4.1 of 6808 the OpenVMS Linker Utility Manual. 6809 6810'-g' 6811 This option is used when the compiler generates debug information. 6812 When 'gcc' is using 'mips-tfile' to generate debug information for 6813 ECOFF, local labels must be passed through to the object file. 6814 Otherwise this option has no effect. 6815 6816'-GSIZE' 6817 A local common symbol larger than SIZE is placed in '.bss', while 6818 smaller symbols are placed in '.sbss'. 6819 6820'-F' 6821'-32addr' 6822 These options are ignored for backward compatibility. 6823 6824 6825File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent 6826 68279.2.3 Syntax 6828------------ 6829 6830The assembler syntax closely follow the Alpha Reference Manual; 6831assembler directives and general syntax closely follow the OSF/1 and 6832OpenVMS syntax, with a few differences for ELF. 6833 6834* Menu: 6835 6836* Alpha-Chars:: Special Characters 6837* Alpha-Regs:: Register Names 6838* Alpha-Relocs:: Relocations 6839 6840 6841File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 6842 68439.2.3.1 Special Characters 6844.......................... 6845 6846'#' is the line comment character. Note that if '#' is the first 6847character on a line then it can also be a logical line number directive 6848(*note Comments::) or a preprocessor control command (*note 6849Preprocessing::). 6850 6851 ';' can be used instead of a newline to separate statements. 6852 6853 6854File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax 6855 68569.2.3.2 Register Names 6857...................... 6858 6859The 32 integer registers are referred to as '$N' or '$rN'. In addition, 6860registers 15, 28, 29, and 30 may be referred to by the symbols '$fp', 6861'$at', '$gp', and '$sp' respectively. 6862 6863 The 32 floating-point registers are referred to as '$fN'. 6864 6865 6866File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax 6867 68689.2.3.3 Relocations 6869................... 6870 6871Some of these relocations are available for ECOFF, but mostly only for 6872ELF. They are modeled after the relocation format introduced in Digital 6873Unix 4.0, but there are additions. 6874 6875 The format is '!TAG' or '!TAG!NUMBER' where TAG is the name of the 6876relocation. In some cases NUMBER is used to relate specific 6877instructions. 6878 6879 The relocation is placed at the end of the instruction like so: 6880 6881 ldah $0,a($29) !gprelhigh 6882 lda $0,a($0) !gprellow 6883 ldq $1,b($29) !literal!100 6884 ldl $2,0($1) !lituse_base!100 6885 6886'!literal' 6887'!literal!N' 6888 Used with an 'ldq' instruction to load the address of a symbol from 6889 the GOT. 6890 6891 A sequence number N is optional, and if present is used to pair 6892 'lituse' relocations with this 'literal' relocation. The 'lituse' 6893 relocations are used by the linker to optimize the code based on 6894 the final location of the symbol. 6895 6896 Note that these optimizations are dependent on the data flow of the 6897 program. Therefore, if _any_ 'lituse' is paired with a 'literal' 6898 relocation, then _all_ uses of the register set by the 'literal' 6899 instruction must also be marked with 'lituse' relocations. This is 6900 because the original 'literal' instruction may be deleted or 6901 transformed into another instruction. 6902 6903 Also note that there may be a one-to-many relationship between 6904 'literal' and 'lituse', but not a many-to-one. That is, if there 6905 are two code paths that load up the same address and feed the value 6906 to a single use, then the use may not use a 'lituse' relocation. 6907 6908'!lituse_base!N' 6909 Used with any memory format instruction (e.g. 'ldl') to indicate 6910 that the literal is used for an address load. The offset field of 6911 the instruction must be zero. During relaxation, the code may be 6912 altered to use a gp-relative load. 6913 6914'!lituse_jsr!N' 6915 Used with a register branch format instruction (e.g. 'jsr') to 6916 indicate that the literal is used for a call. During relaxation, 6917 the code may be altered to use a direct branch (e.g. 'bsr'). 6918 6919'!lituse_jsrdirect!N' 6920 Similar to 'lituse_jsr', but also that this call cannot be vectored 6921 through a PLT entry. This is useful for functions with special 6922 calling conventions which do not allow the normal call-clobbered 6923 registers to be clobbered. 6924 6925'!lituse_bytoff!N' 6926 Used with a byte mask instruction (e.g. 'extbl') to indicate that 6927 only the low 3 bits of the address are relevant. During 6928 relaxation, the code may be altered to use an immediate instead of 6929 a register shift. 6930 6931'!lituse_addr!N' 6932 Used with any other instruction to indicate that the original 6933 address is in fact used, and the original 'ldq' instruction may not 6934 be altered or deleted. This is useful in conjunction with 6935 'lituse_jsr' to test whether a weak symbol is defined. 6936 6937 ldq $27,foo($29) !literal!1 6938 beq $27,is_undef !lituse_addr!1 6939 jsr $26,($27),foo !lituse_jsr!1 6940 6941'!lituse_tlsgd!N' 6942 Used with a register branch format instruction to indicate that the 6943 literal is the call to '__tls_get_addr' used to compute the address 6944 of the thread-local storage variable whose descriptor was loaded 6945 with '!tlsgd!N'. 6946 6947'!lituse_tlsldm!N' 6948 Used with a register branch format instruction to indicate that the 6949 literal is the call to '__tls_get_addr' used to compute the address 6950 of the base of the thread-local storage block for the current 6951 module. The descriptor for the module must have been loaded with 6952 '!tlsldm!N'. 6953 6954'!gpdisp!N' 6955 Used with 'ldah' and 'lda' to load the GP from the current address, 6956 a-la the 'ldgp' macro. The source register for the 'ldah' 6957 instruction must contain the address of the 'ldah' instruction. 6958 There must be exactly one 'lda' instruction paired with the 'ldah' 6959 instruction, though it may appear anywhere in the instruction 6960 stream. The immediate operands must be zero. 6961 6962 bsr $26,foo 6963 ldah $29,0($26) !gpdisp!1 6964 lda $29,0($29) !gpdisp!1 6965 6966'!gprelhigh' 6967 Used with an 'ldah' instruction to add the high 16 bits of a 32-bit 6968 displacement from the GP. 6969 6970'!gprellow' 6971 Used with any memory format instruction to add the low 16 bits of a 6972 32-bit displacement from the GP. 6973 6974'!gprel' 6975 Used with any memory format instruction to add a 16-bit 6976 displacement from the GP. 6977 6978'!samegp' 6979 Used with any branch format instruction to skip the GP load at the 6980 target address. The referenced symbol must have the same GP as the 6981 source object file, and it must be declared to either not use '$27' 6982 or perform a standard GP load in the first two instructions via the 6983 '.prologue' directive. 6984 6985'!tlsgd' 6986'!tlsgd!N' 6987 Used with an 'lda' instruction to load the address of a TLS 6988 descriptor for a symbol in the GOT. 6989 6990 The sequence number N is optional, and if present it used to pair 6991 the descriptor load with both the 'literal' loading the address of 6992 the '__tls_get_addr' function and the 'lituse_tlsgd' marking the 6993 call to that function. 6994 6995 For proper relaxation, both the 'tlsgd', 'literal' and 'lituse' 6996 relocations must be in the same extended basic block. That is, the 6997 relocation with the lowest address must be executed first at 6998 runtime. 6999 7000'!tlsldm' 7001'!tlsldm!N' 7002 Used with an 'lda' instruction to load the address of a TLS 7003 descriptor for the current module in the GOT. 7004 7005 Similar in other respects to 'tlsgd'. 7006 7007'!gotdtprel' 7008 Used with an 'ldq' instruction to load the offset of the TLS symbol 7009 within its module's thread-local storage block. Also known as the 7010 dynamic thread pointer offset or dtp-relative offset. 7011 7012'!dtprelhi' 7013'!dtprello' 7014'!dtprel' 7015 Like 'gprel' relocations except they compute dtp-relative offsets. 7016 7017'!gottprel' 7018 Used with an 'ldq' instruction to load the offset of the TLS symbol 7019 from the thread pointer. Also known as the tp-relative offset. 7020 7021'!tprelhi' 7022'!tprello' 7023'!tprel' 7024 Like 'gprel' relocations except they compute tp-relative offsets. 7025 7026 7027File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent 7028 70299.2.4 Floating Point 7030-------------------- 7031 7032The Alpha family uses both IEEE and VAX floating-point numbers. 7033 7034 7035File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent 7036 70379.2.5 Alpha Assembler Directives 7038-------------------------------- 7039 7040'as' for the Alpha supports many additional directives for compatibility 7041with the native assembler. This section describes them only briefly. 7042 7043 These are the additional directives in 'as' for the Alpha: 7044 7045'.arch CPU' 7046 Specifies the target processor. This is equivalent to the '-mCPU' 7047 command-line option. *Note Options: Alpha Options, for a list of 7048 values for CPU. 7049 7050'.ent FUNCTION[, N]' 7051 Mark the beginning of FUNCTION. An optional number may follow for 7052 compatibility with the OSF/1 assembler, but is ignored. When 7053 generating '.mdebug' information, this will create a procedure 7054 descriptor for the function. In ELF, it will mark the symbol as a 7055 function a-la the generic '.type' directive. 7056 7057'.end FUNCTION' 7058 Mark the end of FUNCTION. In ELF, it will set the size of the 7059 symbol a-la the generic '.size' directive. 7060 7061'.mask MASK, OFFSET' 7062 Indicate which of the integer registers are saved in the current 7063 function's stack frame. MASK is interpreted a bit mask in which 7064 bit N set indicates that register N is saved. The registers are 7065 saved in a block located OFFSET bytes from the "canonical frame 7066 address" (CFA) which is the value of the stack pointer on entry to 7067 the function. The registers are saved sequentially, except that 7068 the return address register (normally '$26') is saved first. 7069 7070 This and the other directives that describe the stack frame are 7071 currently only used when generating '.mdebug' information. They 7072 may in the future be used to generate DWARF2 '.debug_frame' unwind 7073 information for hand written assembly. 7074 7075'.fmask MASK, OFFSET' 7076 Indicate which of the floating-point registers are saved in the 7077 current stack frame. The MASK and OFFSET parameters are 7078 interpreted as with '.mask'. 7079 7080'.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' 7081 Describes the shape of the stack frame. The frame pointer in use 7082 is FRAMEREG; normally this is either '$fp' or '$sp'. The frame 7083 pointer is FRAMEOFFSET bytes below the CFA. The return address is 7084 initially located in RETREG until it is saved as indicated in 7085 '.mask'. For compatibility with OSF/1 an optional ARGOFFSET 7086 parameter is accepted and ignored. It is believed to indicate the 7087 offset from the CFA to the saved argument registers. 7088 7089'.prologue N' 7090 Indicate that the stack frame is set up and all registers have been 7091 spilled. The argument N indicates whether and how the function 7092 uses the incoming "procedure vector" (the address of the called 7093 function) in '$27'. 0 indicates that '$27' is not used; 1 7094 indicates that the first two instructions of the function use '$27' 7095 to perform a load of the GP register; 2 indicates that '$27' is 7096 used in some non-standard way and so the linker cannot elide the 7097 load of the procedure vector during relaxation. 7098 7099'.usepv FUNCTION, WHICH' 7100 Used to indicate the use of the '$27' register, similar to 7101 '.prologue', but without the other semantics of needing to be 7102 inside an open '.ent'/'.end' block. 7103 7104 The WHICH argument should be either 'no', indicating that '$27' is 7105 not used, or 'std', indicating that the first two instructions of 7106 the function perform a GP load. 7107 7108 One might use this directive instead of '.prologue' if you are also 7109 using dwarf2 CFI directives. 7110 7111'.gprel32 EXPRESSION' 7112 Computes the difference between the address in EXPRESSION and the 7113 GP for the current object file, and stores it in 4 bytes. In 7114 addition to being smaller than a full 8 byte address, this also 7115 does not require a dynamic relocation when used in a shared 7116 library. 7117 7118'.t_floating EXPRESSION' 7119 Stores EXPRESSION as an IEEE double precision value. 7120 7121'.s_floating EXPRESSION' 7122 Stores EXPRESSION as an IEEE single precision value. 7123 7124'.f_floating EXPRESSION' 7125 Stores EXPRESSION as a VAX F format value. 7126 7127'.g_floating EXPRESSION' 7128 Stores EXPRESSION as a VAX G format value. 7129 7130'.d_floating EXPRESSION' 7131 Stores EXPRESSION as a VAX D format value. 7132 7133'.set FEATURE' 7134 Enables or disables various assembler features. Using the positive 7135 name of the feature enables while using 'noFEATURE' disables. 7136 7137 'at' 7138 Indicates that macro expansions may clobber the "assembler 7139 temporary" ('$at' or '$28') register. Some macros may not be 7140 expanded without this and will generate an error message if 7141 'noat' is in effect. When 'at' is in effect, a warning will 7142 be generated if '$at' is used by the programmer. 7143 7144 'macro' 7145 Enables the expansion of macro instructions. Note that 7146 variants of real instructions, such as 'br label' vs 'br 7147 $31,label' are considered alternate forms and not macros. 7148 7149 'move' 7150 'reorder' 7151 'volatile' 7152 These control whether and how the assembler may re-order 7153 instructions. Accepted for compatibility with the OSF/1 7154 assembler, but 'as' does not do instruction scheduling, so 7155 these features are ignored. 7156 7157 The following directives are recognized for compatibility with the 7158OSF/1 assembler but are ignored. 7159 7160 .proc .aproc 7161 .reguse .livereg 7162 .option .aent 7163 .ugen .eflag 7164 .alias .noalias 7165 7166 7167File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent 7168 71699.2.6 Opcodes 7170------------- 7171 7172For detailed information on the Alpha machine instruction set, see the 7173Alpha Architecture Handbook 7174(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf). 7175 7176 7177File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies 7178 71799.3 ARC Dependent Features 7180========================== 7181 7182* Menu: 7183 7184* ARC Options:: Options 7185* ARC Syntax:: Syntax 7186* ARC Directives:: ARC Machine Directives 7187* ARC Modifiers:: ARC Assembler Modifiers 7188* ARC Symbols:: ARC Pre-defined Symbols 7189* ARC Opcodes:: Opcodes 7190 7191 7192File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 7193 71949.3.1 Options 7195------------- 7196 7197The following options control the type of CPU for which code is 7198assembled, and generic constraints on the code generated: 7199 7200'-mcpu=CPU' 7201 Set architecture type and register usage for CPU. There are also 7202 shortcut alias options available for backward compatibility and 7203 convenience. Supported values for CPU are 7204 7205 'arc600' 7206 Assemble for ARC 600. Aliases: '-mA6', '-mARC600'. 7207 7208 'arc600_norm' 7209 Assemble for ARC 600 with norm instructions. 7210 7211 'arc600_mul64' 7212 Assemble for ARC 600 with mul64 instructions. 7213 7214 'arc600_mul32x16' 7215 Assemble for ARC 600 with mul32x16 instructions. 7216 7217 'arc601' 7218 Assemble for ARC 601. Alias: '-mARC601'. 7219 7220 'arc601_norm' 7221 Assemble for ARC 601 with norm instructions. 7222 7223 'arc601_mul64' 7224 Assemble for ARC 601 with mul64 instructions. 7225 7226 'arc601_mul32x16' 7227 Assemble for ARC 601 with mul32x16 instructions. 7228 7229 'arc700' 7230 Assemble for ARC 700. Aliases: '-mA7', '-mARC700'. 7231 7232 'arcem' 7233 Assemble for ARC EM. Aliases: '-mEM' 7234 7235 'em' 7236 Assemble for ARC EM, identical as arcem variant. 7237 7238 'em4' 7239 Assemble for ARC EM with code-density instructions. 7240 7241 'em4_dmips' 7242 Assemble for ARC EM with code-density instructions. 7243 7244 'em4_fpus' 7245 Assemble for ARC EM with code-density instructions. 7246 7247 'em4_fpuda' 7248 Assemble for ARC EM with code-density, and double-precision 7249 assist instructions. 7250 7251 'quarkse_em' 7252 Assemble for QuarkSE-EM cpu. 7253 7254 'archs' 7255 Assemble for ARC HS. Aliases: '-mHS', '-mav2hs'. 7256 7257 'hs' 7258 Assemble for ARC HS. 7259 7260 'hs34' 7261 Assemble for ARC HS34. 7262 7263 'hs38' 7264 Assemble for ARC HS38. 7265 7266 'hs38_linux' 7267 Assemble for ARC HS38 with floating point support on. 7268 7269 'nps400' 7270 Assemble for ARC 700 with NPS-400 extended instructions. 7271 7272 Note: the '.cpu' directive (*note ARC Directives::) can to be used 7273 to select a core variant from within assembly code. 7274 7275'-EB' 7276 This option specifies that the output generated by the assembler 7277 should be marked as being encoded for a big-endian processor. 7278 7279'-EL' 7280 This option specifies that the output generated by the assembler 7281 should be marked as being encoded for a little-endian processor - 7282 this is the default. 7283 7284'-mcode-density' 7285 This option turns on Code Density instructions. Only valid for ARC 7286 EM processors. 7287 7288'-mrelax' 7289 Enable support for assembly-time relaxation. The assembler will 7290 replace a longer version of an instruction with a shorter one, 7291 whenever it is possible. 7292 7293'-mnps400' 7294 Enable support for NPS-400 extended instructions. 7295 7296'-mspfp' 7297 Enable support for single-precision floating point instructions. 7298 7299'-mdpfp' 7300 Enable support for double-precision floating point instructions. 7301 7302'-mfpuda' 7303 Enable support for double-precision assist floating point 7304 instructions. Only valid for ARC EM processors. 7305 7306 7307File: as.info, Node: ARC Syntax, Next: ARC Directives, Prev: ARC Options, Up: ARC-Dependent 7308 73099.3.2 Syntax 7310------------ 7311 7312* Menu: 7313 7314* ARC-Chars:: Special Characters 7315* ARC-Regs:: Register Names 7316 7317 7318File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 7319 73209.3.2.1 Special Characters 7321.......................... 7322 7323'%' 7324 A register name can optionally be prefixed by a '%' character. So 7325 register '%r0' is equivalent to 'r0' in the assembly code. 7326 7327'#' 7328 The presence of a '#' character within a line (but not at the start 7329 of a line) indicates the start of a comment that extends to the end 7330 of the current line. 7331 7332 _Note:_ if a line starts with a '#' character then it can also be a 7333 logical line number directive (*note Comments::) or a preprocessor 7334 control command (*note Preprocessing::). 7335 7336'@' 7337 Prefixing an operand with an '@' specifies that the operand is a 7338 symbol and not a register. This is how the assembler disambiguates 7339 the use of an ARC register name as a symbol. So the instruction 7340 mov r0, @r0 7341 moves the address of symbol 'r0' into register 'r0'. 7342 7343'`' 7344 The '`' (backtick) character is used to separate statements on a 7345 single line. 7346 7347'-' 7348 Used as a separator to obtain a sequence of commands from a C 7349 preprocessor macro. 7350 7351 7352File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax 7353 73549.3.2.2 Register Names 7355...................... 7356 7357The ARC assembler uses the following register names for its core 7358registers: 7359 7360'r0-r31' 7361 The core general registers. Registers 'r26' through 'r31' have 7362 special functions, and are usually referred to by those synonyms. 7363 7364'gp' 7365 The global pointer and a synonym for 'r26'. 7366 7367'fp' 7368 The frame pointer and a synonym for 'r27'. 7369 7370'sp' 7371 The stack pointer and a synonym for 'r28'. 7372 7373'ilink1' 7374 For ARC 600 and ARC 700, the level 1 interrupt link register and a 7375 synonym for 'r29'. Not supported for ARCv2. 7376 7377'ilink' 7378 For ARCv2, the interrupt link register and a synonym for 'r29'. 7379 Not supported for ARC 600 and ARC 700. 7380 7381'ilink2' 7382 For ARC 600 and ARC 700, the level 2 interrupt link register and a 7383 synonym for 'r30'. Not supported for ARC v2. 7384 7385'blink' 7386 The link register and a synonym for 'r31'. 7387 7388'r32-r59' 7389 The extension core registers. 7390 7391'lp_count' 7392 The loop count register. 7393 7394'pcl' 7395 The word aligned program counter. 7396 7397 In addition the ARC processor has a large number of _auxiliary 7398registers_. The precise set depends on the extensions being supported, 7399but the following baseline set are always defined: 7400 7401'identity' 7402 Processor Identification register. Auxiliary register address 0x4. 7403 7404'pc' 7405 Program Counter. Auxiliary register address 0x6. 7406 7407'status32' 7408 Status register. Auxiliary register address 0x0a. 7409 7410'bta' 7411 Branch Target Address. Auxiliary register address 0x412. 7412 7413'ecr' 7414 Exception Cause Register. Auxiliary register address 0x403. 7415 7416'int_vector_base' 7417 Interrupt Vector Base address. Auxiliary register address 0x25. 7418 7419'status32_p0' 7420 Stored STATUS32 register on entry to level P0 interrupts. 7421 Auxiliary register address 0xb. 7422 7423'aux_user_sp' 7424 Saved User Stack Pointer. Auxiliary register address 0xd. 7425 7426'eret' 7427 Exception Return Address. Auxiliary register address 0x400. 7428 7429'erbta' 7430 BTA saved on exception entry. Auxiliary register address 0x401. 7431 7432'erstatus' 7433 STATUS32 saved on exception. Auxiliary register address 0x402. 7434 7435'bcr_ver' 7436 Build Configuration Registers Version. Auxiliary register address 7437 0x60. 7438 7439'bta_link_build' 7440 Build configuration for: BTA Registers. Auxiliary register address 7441 0x63. 7442 7443'vecbase_ac_build' 7444 Build configuration for: Interrupts. Auxiliary register address 7445 0x68. 7446 7447'rf_build' 7448 Build configuration for: Core Registers. Auxiliary register 7449 address 0x6e. 7450 7451'dccm_build' 7452 DCCM RAM Configuration Register. Auxiliary register address 0xc1. 7453 7454 Additional auxiliary register names are defined according to the 7455processor architecture version and extensions selected by the options. 7456 7457 7458File: as.info, Node: ARC Directives, Next: ARC Modifiers, Prev: ARC Syntax, Up: ARC-Dependent 7459 74609.3.3 ARC Machine Directives 7461---------------------------- 7462 7463The ARC version of 'as' supports the following additional machine 7464directives: 7465 7466'.lcomm SYMBOL, LENGTH[, ALIGNMENT]' 7467 Reserve LENGTH (an absolute expression) bytes for a local common 7468 denoted by SYMBOL. The section and value of SYMBOL are those of 7469 the new local common. The addresses are allocated in the bss 7470 section, so that at run-time the bytes start off zeroed. Since 7471 SYMBOL is not declared global, it is normally not visible to 'ld'. 7472 The optional third parameter, ALIGNMENT, specifies the desired 7473 alignment of the symbol in the bss section, specified as a byte 7474 boundary (for example, an alignment of 16 means that the least 7475 significant 4 bits of the address should be zero). The alignment 7476 must be an absolute expression, and it must be a power of two. If 7477 no alignment is specified, as will set the alignment to the largest 7478 power of two less than or equal to the size of the symbol, up to a 7479 maximum of 16. 7480 7481'.lcommon SYMBOL, LENGTH[, ALIGNMENT]' 7482 The same as 'lcomm' directive. 7483 7484'.cpu CPU' 7485 The '.cpu' directive must be followed by the desired core version. 7486 Permitted values for CPU are: 7487 'ARC600' 7488 Assemble for the ARC600 instruction set. 7489 7490 'arc600_norm' 7491 Assemble for ARC 600 with norm instructions. 7492 7493 'arc600_mul64' 7494 Assemble for ARC 600 with mul64 instructions. 7495 7496 'arc600_mul32x16' 7497 Assemble for ARC 600 with mul32x16 instructions. 7498 7499 'arc601' 7500 Assemble for ARC 601 instruction set. 7501 7502 'arc601_norm' 7503 Assemble for ARC 601 with norm instructions. 7504 7505 'arc601_mul64' 7506 Assemble for ARC 601 with mul64 instructions. 7507 7508 'arc601_mul32x16' 7509 Assemble for ARC 601 with mul32x16 instructions. 7510 7511 'ARC700' 7512 Assemble for the ARC700 instruction set. 7513 7514 'NPS400' 7515 Assemble for the NPS400 instruction set. 7516 7517 'EM' 7518 Assemble for the ARC EM instruction set. 7519 7520 'arcem' 7521 Assemble for ARC EM instruction set 7522 7523 'em4' 7524 Assemble for ARC EM with code-density instructions. 7525 7526 'em4_dmips' 7527 Assemble for ARC EM with code-density instructions. 7528 7529 'em4_fpus' 7530 Assemble for ARC EM with code-density instructions. 7531 7532 'em4_fpuda' 7533 Assemble for ARC EM with code-density, and double-precision 7534 assist instructions. 7535 7536 'quarkse_em' 7537 Assemble for QuarkSE-EM instruction set. 7538 7539 'HS' 7540 Assemble for the ARC HS instruction set. 7541 7542 'archs' 7543 Assemble for ARC HS instruction set. 7544 7545 'hs' 7546 Assemble for ARC HS instruction set. 7547 7548 'hs34' 7549 Assemble for ARC HS34 instruction set. 7550 7551 'hs38' 7552 Assemble for ARC HS38 instruction set. 7553 7554 'hs38_linux' 7555 Assemble for ARC HS38 with floating point support on. 7556 7557 Note: the '.cpu' directive overrides the command-line option 7558 '-mcpu=CPU'; a warning is emitted when the version is not 7559 consistent between the two. 7560 7561'.extAuxRegister NAME, ADDR, MODE' 7562 Auxiliary registers can be defined in the assembler source code by 7563 using this directive. The first parameter, NAME, is the name of 7564 the new auxiliary register. The second parameter, ADDR, is address 7565 the of the auxiliary register. The third parameter, MODE, 7566 specifies whether the register is readable and/or writable and is 7567 one of: 7568 'r' 7569 Read only; 7570 7571 'w' 7572 Write only; 7573 7574 'r|w' 7575 Read and write. 7576 7577 For example: 7578 .extAuxRegister mulhi, 0x12, w 7579 specifies a write only extension auxiliary register, MULHI at 7580 address 0x12. 7581 7582'.extCondCode SUFFIX, VAL' 7583 ARC supports extensible condition codes. This directive defines a 7584 new condition code, to be known by the suffix, SUFFIX and will 7585 depend on the value, VAL in the condition code. 7586 7587 For example: 7588 .extCondCode is_busy,0x14 7589 add.is_busy r1,r2,r3 7590 will only execute the 'add' instruction if the condition code value 7591 is 0x14. 7592 7593'.extCoreRegister NAME, REGNUM, MODE, SHORTCUT' 7594 Specifies an extension core register named NAME as a synonym for 7595 the register numbered REGNUM. The register number must be between 7596 32 and 59. The third argument, MODE, indicates whether the 7597 register is readable and/or writable and is one of: 7598 'r' 7599 Read only; 7600 7601 'w' 7602 Write only; 7603 7604 'r|w' 7605 Read and write. 7606 7607 The final parameter, SHORTCUT indicates whether the register has a 7608 short cut in the pipeline. The valid values are: 7609 'can_shortcut' 7610 The register has a short cut in the pipeline; 7611 7612 'cannot_shortcut' 7613 The register does not have a short cut in the pipeline. 7614 7615 For example: 7616 .extCoreRegister mlo, 57, r , can_shortcut 7617 defines a read only extension core register, 'mlo', which is 7618 register 57, and can short cut the pipeline. 7619 7620'.extInstruction NAME, OPCODE, SUBOPCODE, SUFFIXCLASS, SYNTAXCLASS' 7621 ARC allows the user to specify extension instructions. These 7622 extension instructions are not macros; the assembler creates 7623 encodings for use of these instructions according to the 7624 specification by the user. 7625 7626 The first argument, NAME, gives the name of the instruction. 7627 7628 The second argument, OPCODE, is the opcode to be used (bits 31:27 7629 in the encoding). 7630 7631 The third argument, SUBOPCODE, is the sub-opcode to be used, but 7632 the correct value also depends on the fifth argument, SYNTAXCLASS 7633 7634 The fourth argument, SUFFIXCLASS, determines the kinds of suffixes 7635 to be allowed. Valid values are: 7636 'SUFFIX_NONE' 7637 No suffixes are permitted; 7638 7639 'SUFFIX_COND' 7640 Conditional suffixes are permitted; 7641 7642 'SUFFIX_FLAG' 7643 Flag setting suffixes are permitted. 7644 7645 'SUFFIX_COND|SUFFIX_FLAG' 7646 Both conditional and flag setting suffices are permitted. 7647 7648 The fifth and final argument, SYNTAXCLASS, determines the syntax 7649 class for the instruction. It can have the following values: 7650 'SYNTAX_2OP' 7651 Two Operand Instruction; 7652 7653 'SYNTAX_3OP' 7654 Three Operand Instruction. 7655 7656 'SYNTAX_1OP' 7657 One Operand Instruction. 7658 7659 'SYNTAX_NOP' 7660 No Operand Instruction. 7661 7662 The syntax class may be followed by '|' and one of the following 7663 modifiers. 7664 7665 'OP1_MUST_BE_IMM' 7666 Modifies syntax class 'SYNTAX_3OP', specifying that the first 7667 operand of a three-operand instruction must be an immediate 7668 (i.e., the result is discarded). This is usually used to set 7669 the flags using specific instructions and not retain results. 7670 7671 'OP1_IMM_IMPLIED' 7672 Modifies syntax class 'SYNTAX_20P', specifying that there is 7673 an implied immediate destination operand which does not appear 7674 in the syntax. 7675 7676 For example, if the source code contains an instruction like: 7677 inst r1,r2 7678 the first argument is an implied immediate (that is, the 7679 result is discarded). This is the same as though the source 7680 code were: inst 0,r1,r2. 7681 7682 For example, defining a 64-bit multiplier with immediate operands: 7683 .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, 7684 SYNTAX_3OP|OP1_MUST_BE_IMM 7685 which specifies an extension instruction named 'mp64' with 3 7686 operands. It sets the flags and can be used with a condition code, 7687 for which the first operand is an immediate, i.e. equivalent to 7688 discarding the result of the operation. 7689 7690 A two operands instruction variant would be: 7691 .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, 7692 SYNTAX_2OP|OP1_IMM_IMPLIED 7693 which describes a two operand instruction with an implicit first 7694 immediate operand. The result of this operation would be 7695 discarded. 7696 7697'.arc_attribute TAG, VALUE' 7698 Set the ARC object attribute TAG to VALUE. 7699 7700 The TAG is either an attribute number, or one of the following: 7701 'Tag_ARC_PCS_config', 'Tag_ARC_CPU_base', 'Tag_ARC_CPU_variation', 7702 'Tag_ARC_CPU_name', 'Tag_ARC_ABI_rf16', 'Tag_ARC_ABI_osver', 7703 'Tag_ARC_ABI_sda', 'Tag_ARC_ABI_pic', 'Tag_ARC_ABI_tls', 7704 'Tag_ARC_ABI_enumsize', 'Tag_ARC_ABI_exceptions', 7705 'Tag_ARC_ABI_double_size', 'Tag_ARC_ISA_config', 7706 'Tag_ARC_ISA_apex', 'Tag_ARC_ISA_mpy_option' 7707 7708 The VALUE is either a 'number', '"string"', or 'number, "string"' 7709 depending on the tag. 7710 7711 7712File: as.info, Node: ARC Modifiers, Next: ARC Symbols, Prev: ARC Directives, Up: ARC-Dependent 7713 77149.3.4 ARC Assembler Modifiers 7715----------------------------- 7716 7717The following additional assembler modifiers have been added for 7718position-independent code. These modifiers are available only with the 7719ARC 700 and above processors and generate relocation entries, which are 7720interpreted by the linker as follows: 7721 7722'@pcl(SYMBOL)' 7723 Relative distance of SYMBOL's from the current program counter 7724 location. 7725 7726'@gotpc(SYMBOL)' 7727 Relative distance of SYMBOL's Global Offset Table entry from the 7728 current program counter location. 7729 7730'@gotoff(SYMBOL)' 7731 Distance of SYMBOL from the base of the Global Offset Table. 7732 7733'@plt(SYMBOL)' 7734 Distance of SYMBOL's Procedure Linkage Table entry from the current 7735 program counter. This is valid only with branch and link 7736 instructions and PC-relative calls. 7737 7738'@sda(SYMBOL)' 7739 Relative distance of SYMBOL from the base of the Small Data 7740 Pointer. 7741 7742 7743File: as.info, Node: ARC Symbols, Next: ARC Opcodes, Prev: ARC Modifiers, Up: ARC-Dependent 7744 77459.3.5 ARC Pre-defined Symbols 7746----------------------------- 7747 7748The following assembler symbols will prove useful when developing 7749position-independent code. These symbols are available only with the 7750ARC 700 and above processors. 7751 7752'__GLOBAL_OFFSET_TABLE__' 7753 Symbol referring to the base of the Global Offset Table. 7754 7755'__DYNAMIC__' 7756 An alias for the Global Offset Table 'Base__GLOBAL_OFFSET_TABLE__'. 7757 It can be used only with '@gotpc' modifiers. 7758 7759 7760File: as.info, Node: ARC Opcodes, Prev: ARC Symbols, Up: ARC-Dependent 7761 77629.3.6 Opcodes 7763------------- 7764 7765For information on the ARC instruction set, see 'ARC Programmers 7766Reference Manual', available where you download the processor IP 7767library. 7768 7769 7770File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies 7771 77729.4 ARM Dependent Features 7773========================== 7774 7775* Menu: 7776 7777* ARM Options:: Options 7778* ARM Syntax:: Syntax 7779* ARM Floating Point:: Floating Point 7780* ARM Directives:: ARM Machine Directives 7781* ARM Opcodes:: Opcodes 7782* ARM Mapping Symbols:: Mapping Symbols 7783* ARM Unwinding Tutorial:: Unwinding 7784 7785 7786File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 7787 77889.4.1 Options 7789------------- 7790 7791'-mcpu=PROCESSOR[+EXTENSION...]' 7792 This option specifies the target processor. The assembler will 7793 issue an error message if an attempt is made to assemble an 7794 instruction which will not execute on the target processor. The 7795 following processor names are recognized: 'arm1', 'arm2', 'arm250', 7796 'arm3', 'arm6', 'arm60', 'arm600', 'arm610', 'arm620', 'arm7', 7797 'arm7m', 'arm7d', 'arm7dm', 'arm7di', 'arm7dmi', 'arm70', 'arm700', 7798 'arm700i', 'arm710', 'arm710t', 'arm720', 'arm720t', 'arm740t', 7799 'arm710c', 'arm7100', 'arm7500', 'arm7500fe', 'arm7t', 'arm7tdmi', 7800 'arm7tdmi-s', 'arm8', 'arm810', 'strongarm', 'strongarm1', 7801 'strongarm110', 'strongarm1100', 'strongarm1110', 'arm9', 'arm920', 7802 'arm920t', 'arm922t', 'arm940t', 'arm9tdmi', 'fa526' (Faraday FA526 7803 processor), 'fa626' (Faraday FA626 processor), 'arm9e', 'arm926e', 7804 'arm926ej-s', 'arm946e-r0', 'arm946e', 'arm946e-s', 'arm966e-r0', 7805 'arm966e', 'arm966e-s', 'arm968e-s', 'arm10t', 'arm10tdmi', 7806 'arm10e', 'arm1020', 'arm1020t', 'arm1020e', 'arm1022e', 7807 'arm1026ej-s', 'fa606te' (Faraday FA606TE processor), 'fa616te' 7808 (Faraday FA616TE processor), 'fa626te' (Faraday FA626TE processor), 7809 'fmp626' (Faraday FMP626 processor), 'fa726te' (Faraday FA726TE 7810 processor), 'arm1136j-s', 'arm1136jf-s', 'arm1156t2-s', 7811 'arm1156t2f-s', 'arm1176jz-s', 'arm1176jzf-s', 'mpcore', 7812 'mpcorenovfp', 'cortex-a5', 'cortex-a7', 'cortex-a8', 'cortex-a9', 7813 'cortex-a15', 'cortex-a17', 'cortex-a32', 'cortex-a35', 7814 'cortex-a53', 'cortex-a55', 'cortex-a57', 'cortex-a72', 7815 'cortex-a73', 'cortex-a75', 'cortex-a76', 'cortex-a76ae', 7816 'cortex-a77', 'cortex-a78', 'cortex-a78ae', 'cortex-a78c', 'ares', 7817 'cortex-r4', 'cortex-r4f', 'cortex-r5', 'cortex-r7', 'cortex-r8', 7818 'cortex-r52', 'cortex-m35p', 'cortex-m33', 'cortex-m23', 7819 'cortex-m7', 'cortex-m4', 'cortex-m3', 'cortex-m1', 'cortex-m0', 7820 'cortex-m0plus', 'cortex-x1', 'exynos-m1', 'marvell-pj4', 7821 'marvell-whitney', 'neoverse-n1', 'neoverse-n2', 'neoverse-v1', 7822 'xgene1', 'xgene2', 'ep9312' (ARM920 with Cirrus Maverick 7823 coprocessor), 'i80200' (Intel XScale processor) 'iwmmxt' (Intel 7824 XScale processor with Wireless MMX technology coprocessor) and 7825 'xscale'. The special name 'all' may be used to allow the 7826 assembler to accept instructions valid for any ARM processor. 7827 7828 In addition to the basic instruction set, the assembler can be told 7829 to accept various extension mnemonics that extend the processor 7830 using the co-processor instruction space. For example, 7831 '-mcpu=arm920+maverick' is equivalent to specifying '-mcpu=ep9312'. 7832 7833 Multiple extensions may be specified, separated by a '+'. The 7834 extensions should be specified in ascending alphabetical order. 7835 7836 Some extensions may be restricted to particular architectures; this 7837 is documented in the list of extensions below. 7838 7839 Extension mnemonics may also be removed from those the assembler 7840 accepts. This is done be prepending 'no' to the option that adds 7841 the extension. Extensions that are removed should be listed after 7842 all extensions which have been added, again in ascending 7843 alphabetical order. For example, '-mcpu=ep9312+nomaverick' is 7844 equivalent to specifying '-mcpu=arm920'. 7845 7846 The following extensions are currently supported: 'bf16' (BFloat16 7847 extensions for v8.6-A architecture), 'i8mm' (Int8 Matrix Multiply 7848 extensions for v8.6-A architecture), 'crc' 'crypto' (Cryptography 7849 Extensions for v8-A architecture, implies 'fp+simd'), 'dotprod' 7850 (Dot Product Extensions for v8.2-A architecture, implies 7851 'fp+simd'), 'fp' (Floating Point Extensions for v8-A architecture), 7852 'fp16' (FP16 Extensions for v8.2-A architecture, implies 'fp'), 7853 'fp16fml' (FP16 Floating Point Multiplication Variant Extensions 7854 for v8.2-A architecture, implies 'fp16'), 'idiv' (Integer Divide 7855 Extensions for v7-A and v7-R architectures), 'iwmmxt', 'iwmmxt2', 7856 'xscale', 'maverick', 'mp' (Multiprocessing Extensions for v7-A and 7857 v7-R architectures), 'os' (Operating System for v6M architecture), 7858 'predres' (Execution and Data Prediction Restriction Instruction 7859 for v8-A architectures, added by default from v8.5-A), 'sb' 7860 (Speculation Barrier Instruction for v8-A architectures, added by 7861 default from v8.5-A), 'sec' (Security Extensions for v6K and v7-A 7862 architectures), 'simd' (Advanced SIMD Extensions for v8-A 7863 architecture, implies 'fp'), 'virt' (Virtualization Extensions for 7864 v7-A architecture, implies 'idiv'), 'pan' (Privileged Access Never 7865 Extensions for v8-A architecture), 'ras' (Reliability, Availability 7866 and Serviceability extensions for v8-A architecture), 'rdma' 7867 (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies 7868 'simd') and 'xscale'. 7869 7870'-march=ARCHITECTURE[+EXTENSION...]' 7871 This option specifies the target architecture. The assembler will 7872 issue an error message if an attempt is made to assemble an 7873 instruction which will not execute on the target architecture. The 7874 following architecture names are recognized: 'armv1', 'armv2', 7875 'armv2a', 'armv2s', 'armv3', 'armv3m', 'armv4', 'armv4xm', 7876 'armv4t', 'armv4txm', 'armv5', 'armv5t', 'armv5txm', 'armv5te', 7877 'armv5texp', 'armv6', 'armv6j', 'armv6k', 'armv6z', 'armv6kz', 7878 'armv6-m', 'armv6s-m', 'armv7', 'armv7-a', 'armv7ve', 'armv7-r', 7879 'armv7-m', 'armv7e-m', 'armv8-a', 'armv8.1-a', 'armv8.2-a', 7880 'armv8.3-a', 'armv8-r', 'armv8.4-a', 'armv8.5-a', 'armv8-m.base', 7881 'armv8-m.main', 'armv8.1-m.main', 'armv8.6-a', 'iwmmxt', 'iwmmxt2' 7882 and 'xscale'. If both '-mcpu' and '-march' are specified, the 7883 assembler will use the setting for '-mcpu'. 7884 7885 The architecture option can be extended with a set extension 7886 options. These extensions are context sensitive, i.e. the same 7887 extension may mean different things when used with different 7888 architectures. When used together with a '-mfpu' option, the union 7889 of both feature enablement is taken. See their availability and 7890 meaning below: 7891 7892 For 'armv5te', 'armv5texp', 'armv5tej', 'armv6', 'armv6j', 7893 'armv6k', 'armv6z', 'armv6kz', 'armv6zk', 'armv6t2', 'armv6kt2' and 7894 'armv6zt2': 7895 7896 '+fp': Enables VFPv2 instructions. '+nofp': Disables all FPU 7897 instrunctions. 7898 7899 For 'armv7': 7900 7901 '+fp': Enables VFPv3 instructions with 16 double-word registers. 7902 '+nofp': Disables all FPU instructions. 7903 7904 For 'armv7-a': 7905 7906 '+fp': Enables VFPv3 instructions with 16 double-word registers. 7907 '+vfpv3-d16': Alias for '+fp'. '+vfpv3': Enables VFPv3 7908 instructions with 32 double-word registers. '+vfpv3-d16-fp16': 7909 Enables VFPv3 with half precision floating-point conversion 7910 instructions and 16 double-word registers. '+vfpv3-fp16': Enables 7911 VFPv3 with half precision floating-point conversion instructions 7912 and 32 double-word registers. '+vfpv4-d16': Enables VFPv4 7913 instructions with 16 double-word registers. '+vfpv4': Enables 7914 VFPv4 instructions with 32 double-word registers. '+simd': Enables 7915 VFPv3 and NEONv1 instructions with 32 double-word registers. 7916 '+neon': Alias for '+simd'. '+neon-vfpv3': Alias for '+simd'. 7917 '+neon-fp16': Enables VFPv3, half precision floating-point 7918 conversion and NEONv1 instructions with 32 double-word registers. 7919 '+neon-vfpv4': Enables VFPv4 and NEONv1 with Fused-MAC instructions 7920 and 32 double-word registers. '+mp': Enables Multiprocessing 7921 Extensions. '+sec': Enables Security Extensions. '+nofp': 7922 Disables all FPU and NEON instructions. '+nosimd': Disables all 7923 NEON instructions. 7924 7925 For 'armv7ve': 7926 7927 '+fp': Enables VFPv4 instructions with 16 double-word registers. 7928 '+vfpv4-d16': Alias for '+fp'. '+vfpv3-d16': Enables VFPv3 7929 instructions with 16 double-word registers. '+vfpv3': Enables 7930 VFPv3 instructions with 32 double-word registers. 7931 '+vfpv3-d16-fp16': Enables VFPv3 with half precision floating-point 7932 conversion instructions and 16 double-word registers. 7933 '+vfpv3-fp16': Enables VFPv3 with half precision floating-point 7934 conversion instructions and 32 double-word registers. '+vfpv4': 7935 Enables VFPv4 instructions with 32 double-word registers. '+simd': 7936 Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 7937 double-word registers. '+neon-vfpv4': Alias for '+simd'. '+neon': 7938 Enables VFPv3 and NEONv1 instructions with 32 double-word 7939 registers. '+neon-vfpv3': Alias for '+neon'. '+neon-fp16': 7940 Enables VFPv3, half precision floating-point conversion and NEONv1 7941 instructions with 32 double-word registers. double-word registers. 7942 '+nofp': Disables all FPU and NEON instructions. '+nosimd': 7943 Disables all NEON instructions. 7944 7945 For 'armv7-r': 7946 7947 '+fp.sp': Enables single-precision only VFPv3 instructions with 16 7948 double-word registers. '+vfpv3xd': Alias for '+fp.sp'. '+fp': 7949 Enables VFPv3 instructions with 16 double-word registers. 7950 '+vfpv3-d16': Alias for '+fp'. '+vfpv3xd-fp16': Enables 7951 single-precision only VFPv3 and half floating-point conversion 7952 instructions with 16 double-word registers. '+vfpv3-d16-fp16': 7953 Enables VFPv3 and half precision floating-point conversion 7954 instructions with 16 double-word registers. '+idiv': Enables 7955 integer division instructions in ARM mode. '+nofp': Disables all 7956 FPU instructions. 7957 7958 For 'armv7e-m': 7959 7960 '+fp': Enables single-precision only VFPv4 instructions with 16 7961 double-word registers. '+vfpvf4-sp-d16': Alias for '+fp'. 7962 '+fpv5': Enables single-precision only VFPv5 instructions with 16 7963 double-word registers. '+fp.dp': Enables VFPv5 instructions with 7964 16 double-word registers. '+fpv5-d16"': Alias for '+fp.dp'. 7965 '+nofp': Disables all FPU instructions. 7966 7967 For 'armv8-m.main': 7968 7969 '+dsp': Enables DSP Extension. '+fp': Enables single-precision 7970 only VFPv5 instructions with 16 double-word registers. '+fp.dp': 7971 Enables VFPv5 instructions with 16 double-word registers. 7972 '+cdecp0' (CDE extensions for v8-m architecture with coprocessor 7973 0), '+cdecp1' (CDE extensions for v8-m architecture with 7974 coprocessor 1), '+cdecp2' (CDE extensions for v8-m architecture 7975 with coprocessor 2), '+cdecp3' (CDE extensions for v8-m 7976 architecture with coprocessor 3), '+cdecp4' (CDE extensions for 7977 v8-m architecture with coprocessor 4), '+cdecp5' (CDE extensions 7978 for v8-m architecture with coprocessor 5), '+cdecp6' (CDE 7979 extensions for v8-m architecture with coprocessor 6), '+cdecp7' 7980 (CDE extensions for v8-m architecture with coprocessor 7), '+nofp': 7981 Disables all FPU instructions. '+nodsp': Disables DSP Extension. 7982 7983 For 'armv8.1-m.main': 7984 7985 '+dsp': Enables DSP Extension. '+fp': Enables single and half 7986 precision scalar Floating Point Extensions for Armv8.1-M Mainline 7987 with 16 double-word registers. '+fp.dp': Enables double precision 7988 scalar Floating Point Extensions for Armv8.1-M Mainline, implies 7989 '+fp'. '+mve': Enables integer only M-profile Vector Extension for 7990 Armv8.1-M Mainline, implies '+dsp'. '+mve.fp': Enables Floating 7991 Point M-profile Vector Extension for Armv8.1-M Mainline, implies 7992 '+mve' and '+fp'. '+nofp': Disables all FPU instructions. 7993 '+nodsp': Disables DSP Extension. '+nomve': Disables all M-profile 7994 Vector Extensions. 7995 7996 For 'armv8-a': 7997 7998 '+crc': Enables CRC32 Extension. '+simd': Enables VFP and NEON for 7999 Armv8-A. '+crypto': Enables Cryptography Extensions for Armv8-A, 8000 implies '+simd'. '+sb': Enables Speculation Barrier Instruction 8001 for Armv8-A. '+predres': Enables Execution and Data Prediction 8002 Restriction Instruction for Armv8-A. '+nofp': Disables all FPU, 8003 NEON and Cryptography Extensions. '+nocrypto': Disables 8004 Cryptography Extensions. 8005 8006 For 'armv8.1-a': 8007 8008 '+simd': Enables VFP and NEON for Armv8.1-A. '+crypto': Enables 8009 Cryptography Extensions for Armv8-A, implies '+simd'. '+sb': 8010 Enables Speculation Barrier Instruction for Armv8-A. '+predres': 8011 Enables Execution and Data Prediction Restriction Instruction for 8012 Armv8-A. '+nofp': Disables all FPU, NEON and Cryptography 8013 Extensions. '+nocrypto': Disables Cryptography Extensions. 8014 8015 For 'armv8.2-a' and 'armv8.3-a': 8016 8017 '+simd': Enables VFP and NEON for Armv8.1-A. '+fp16': Enables FP16 8018 Extension for Armv8.2-A, implies '+simd'. '+fp16fml': Enables FP16 8019 Floating Point Multiplication Variant Extensions for Armv8.2-A, 8020 implies '+fp16'. '+crypto': Enables Cryptography Extensions for 8021 Armv8-A, implies '+simd'. '+dotprod': Enables Dot Product 8022 Extensions for Armv8.2-A, implies '+simd'. '+sb': Enables 8023 Speculation Barrier Instruction for Armv8-A. '+predres': Enables 8024 Execution and Data Prediction Restriction Instruction for Armv8-A. 8025 '+nofp': Disables all FPU, NEON, Cryptography and Dot Product 8026 Extensions. '+nocrypto': Disables Cryptography Extensions. 8027 8028 For 'armv8.4-a': 8029 8030 '+simd': Enables VFP and NEON for Armv8.1-A and Dot Product 8031 Extensions for Armv8.2-A. '+fp16': Enables FP16 Floating Point and 8032 Floating Point Multiplication Variant Extensions for Armv8.2-A, 8033 implies '+simd'. '+crypto': Enables Cryptography Extensions for 8034 Armv8-A, implies '+simd'. '+sb': Enables Speculation Barrier 8035 Instruction for Armv8-A. '+predres': Enables Execution and Data 8036 Prediction Restriction Instruction for Armv8-A. '+nofp': Disables 8037 all FPU, NEON, Cryptography and Dot Product Extensions. 8038 '+nocryptp': Disables Cryptography Extensions. 8039 8040 For 'armv8.5-a': 8041 8042 '+simd': Enables VFP and NEON for Armv8.1-A and Dot Product 8043 Extensions for Armv8.2-A. '+fp16': Enables FP16 Floating Point and 8044 Floating Point Multiplication Variant Extensions for Armv8.2-A, 8045 implies '+simd'. '+crypto': Enables Cryptography Extensions for 8046 Armv8-A, implies '+simd'. '+nofp': Disables all FPU, NEON, 8047 Cryptography and Dot Product Extensions. '+nocryptp': Disables 8048 Cryptography Extensions. 8049 8050'-mfpu=FLOATING-POINT-FORMAT' 8051 8052 This option specifies the floating point format to assemble for. 8053 The assembler will issue an error message if an attempt is made to 8054 assemble an instruction which will not execute on the target 8055 floating point unit. The following format options are recognized: 8056 'softfpa', 'fpe', 'fpe2', 'fpe3', 'fpa', 'fpa10', 'fpa11', 8057 'arm7500fe', 'softvfp', 'softvfp+vfp', 'vfp', 'vfp10', 'vfp10-r0', 8058 'vfp9', 'vfpxd', 'vfpv2', 'vfpv3', 'vfpv3-fp16', 'vfpv3-d16', 8059 'vfpv3-d16-fp16', 'vfpv3xd', 'vfpv3xd-d16', 'vfpv4', 'vfpv4-d16', 8060 'fpv4-sp-d16', 'fpv5-sp-d16', 'fpv5-d16', 'fp-armv8', 'arm1020t', 8061 'arm1020e', 'arm1136jf-s', 'maverick', 'neon', 'neon-vfpv3', 8062 'neon-fp16', 'neon-vfpv4', 'neon-fp-armv8', 'crypto-neon-fp-armv8', 8063 'neon-fp-armv8.1' and 'crypto-neon-fp-armv8.1'. 8064 8065 In addition to determining which instructions are assembled, this 8066 option also affects the way in which the '.double' assembler 8067 directive behaves when assembling little-endian code. 8068 8069 The default is dependent on the processor selected. For 8070 Architecture 5 or later, the default is to assemble for VFP 8071 instructions; for earlier architectures the default is to assemble 8072 for FPA instructions. 8073 8074'-mfp16-format=FORMAT' 8075 This option specifies the half-precision floating point format to 8076 use when assembling floating point numbers emitted by the 8077 '.float16' directive. The following format options are recognized: 8078 'ieee', 'alternative'. If 'ieee' is specified then the IEEE 8079 754-2008 half-precision floating point format is used, if 8080 'alternative' is specified then the Arm alternative half-precision 8081 format is used. If this option is set on the command line then the 8082 format is fixed and cannot be changed with the 'float16_format' 8083 directive. If this value is not set then the IEEE 754-2008 format 8084 is used until the format is explicitly set with the 8085 'float16_format' directive. 8086 8087'-mthumb' 8088 This option specifies that the assembler should start assembling 8089 Thumb instructions; that is, it should behave as though the file 8090 starts with a '.code 16' directive. 8091 8092'-mthumb-interwork' 8093 This option specifies that the output generated by the assembler 8094 should be marked as supporting interworking. It also affects the 8095 behaviour of the 'ADR' and 'ADRL' pseudo opcodes. 8096 8097'-mimplicit-it=never' 8098'-mimplicit-it=always' 8099'-mimplicit-it=arm' 8100'-mimplicit-it=thumb' 8101 The '-mimplicit-it' option controls the behavior of the assembler 8102 when conditional instructions are not enclosed in IT blocks. There 8103 are four possible behaviors. If 'never' is specified, such 8104 constructs cause a warning in ARM code and an error in Thumb-2 8105 code. If 'always' is specified, such constructs are accepted in 8106 both ARM and Thumb-2 code, where the IT instruction is added 8107 implicitly. If 'arm' is specified, such constructs are accepted in 8108 ARM code and cause an error in Thumb-2 code. If 'thumb' is 8109 specified, such constructs cause a warning in ARM code and are 8110 accepted in Thumb-2 code. If you omit this option, the behavior is 8111 equivalent to '-mimplicit-it=arm'. 8112 8113'-mapcs-26' 8114'-mapcs-32' 8115 These options specify that the output generated by the assembler 8116 should be marked as supporting the indicated version of the Arm 8117 Procedure. Calling Standard. 8118 8119'-matpcs' 8120 This option specifies that the output generated by the assembler 8121 should be marked as supporting the Arm/Thumb Procedure Calling 8122 Standard. If enabled this option will cause the assembler to 8123 create an empty debugging section in the object file called 8124 .arm.atpcs. Debuggers can use this to determine the ABI being used 8125 by. 8126 8127'-mapcs-float' 8128 This indicates the floating point variant of the APCS should be 8129 used. In this variant floating point arguments are passed in FP 8130 registers rather than integer registers. 8131 8132'-mapcs-reentrant' 8133 This indicates that the reentrant variant of the APCS should be 8134 used. This variant supports position independent code. 8135 8136'-mfloat-abi=ABI' 8137 This option specifies that the output generated by the assembler 8138 should be marked as using specified floating point ABI. The 8139 following values are recognized: 'soft', 'softfp' and 'hard'. 8140 8141'-meabi=VER' 8142 This option specifies which EABI version the produced object files 8143 should conform to. The following values are recognized: 'gnu', '4' 8144 and '5'. 8145 8146'-EB' 8147 This option specifies that the output generated by the assembler 8148 should be marked as being encoded for a big-endian processor. 8149 8150 Note: If a program is being built for a system with big-endian data 8151 and little-endian instructions then it should be assembled with the 8152 '-EB' option, (all of it, code and data) and then linked with the 8153 '--be8' option. This will reverse the endianness of the 8154 instructions back to little-endian, but leave the data as 8155 big-endian. 8156 8157'-EL' 8158 This option specifies that the output generated by the assembler 8159 should be marked as being encoded for a little-endian processor. 8160 8161'-k' 8162 This option specifies that the output of the assembler should be 8163 marked as position-independent code (PIC). 8164 8165'--fix-v4bx' 8166 Allow 'BX' instructions in ARMv4 code. This is intended for use 8167 with the linker option of the same name. 8168 8169'-mwarn-deprecated' 8170'-mno-warn-deprecated' 8171 Enable or disable warnings about using deprecated options or 8172 features. The default is to warn. 8173 8174'-mccs' 8175 Turns on CodeComposer Studio assembly syntax compatibility mode. 8176 8177'-mwarn-syms' 8178'-mno-warn-syms' 8179 Enable or disable warnings about symbols that match the names of 8180 ARM instructions. The default is to warn. 8181 8182 8183File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent 8184 81859.4.2 Syntax 8186------------ 8187 8188* Menu: 8189 8190* ARM-Instruction-Set:: Instruction Set 8191* ARM-Chars:: Special Characters 8192* ARM-Regs:: Register Names 8193* ARM-Relocations:: Relocations 8194* ARM-Neon-Alignment:: NEON Alignment Specifiers 8195 8196 8197File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax 8198 81999.4.2.1 Instruction Set Syntax 8200.............................. 8201 8202Two slightly different syntaxes are support for ARM and THUMB 8203instructions. The default, 'divided', uses the old style where ARM and 8204THUMB instructions had their own, separate syntaxes. The new, 'unified' 8205syntax, which can be selected via the '.syntax' directive, and has the 8206following main features: 8207 8208 * Immediate operands do not require a '#' prefix. 8209 8210 * The 'IT' instruction may appear, and if it does it is validated 8211 against subsequent conditional affixes. In ARM mode it does not 8212 generate machine code, in THUMB mode it does. 8213 8214 * For ARM instructions the conditional affixes always appear at the 8215 end of the instruction. For THUMB instructions conditional affixes 8216 can be used, but only inside the scope of an 'IT' instruction. 8217 8218 * All of the instructions new to the V6T2 architecture (and later) 8219 are available. (Only a few such instructions can be written in the 8220 'divided' syntax). 8221 8222 * The '.N' and '.W' suffixes are recognized and honored. 8223 8224 * All instructions set the flags if and only if they have an 's' 8225 affix. 8226 8227 8228File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax 8229 82309.4.2.2 Special Characters 8231.......................... 8232 8233The presence of a '@' anywhere on a line indicates the start of a 8234comment that extends to the end of that line. 8235 8236 If a '#' appears as the first character of a line then the whole line 8237is treated as a comment, but in this case the line could also be a 8238logical line number directive (*note Comments::) or a preprocessor 8239control command (*note Preprocessing::). 8240 8241 The ';' character can be used instead of a newline to separate 8242statements. 8243 8244 Either '#' or '$' can be used to indicate immediate operands. 8245 8246 *TODO* Explain about /data modifier on symbols. 8247 8248 8249File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax 8250 82519.4.2.3 Register Names 8252...................... 8253 8254*TODO* Explain about ARM register naming, and the predefined names. 8255 8256 8257File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax 8258 82599.4.2.4 ARM relocation generation 8260................................. 8261 8262Specific data relocations can be generated by putting the relocation 8263name in parentheses after the symbol name. For example: 8264 8265 .word foo(TARGET1) 8266 8267 This will generate an 'R_ARM_TARGET1' relocation against the symbol 8268FOO. The following relocations are supported: 'GOT', 'GOTOFF', 8269'TARGET1', 'TARGET2', 'SBREL', 'TLSGD', 'TLSLDM', 'TLSLDO', 'TLSDESC', 8270'TLSCALL', 'GOTTPOFF', 'GOT_PREL' and 'TPOFF'. 8271 8272 For compatibility with older toolchains the assembler also accepts 8273'(PLT)' after branch targets. On legacy targets this will generate the 8274deprecated 'R_ARM_PLT32' relocation. On EABI targets it will encode 8275either the 'R_ARM_CALL' or 'R_ARM_JUMP24' relocation, as appropriate. 8276 8277 Relocations for 'MOVW' and 'MOVT' instructions can be generated by 8278prefixing the value with '#:lower16:' and '#:upper16' respectively. For 8279example to load the 32-bit address of foo into r0: 8280 8281 MOVW r0, #:lower16:foo 8282 MOVT r0, #:upper16:foo 8283 8284 Relocations 'R_ARM_THM_ALU_ABS_G0_NC', 'R_ARM_THM_ALU_ABS_G1_NC', 8285'R_ARM_THM_ALU_ABS_G2_NC' and 'R_ARM_THM_ALU_ABS_G3_NC' can be generated 8286by prefixing the value with '#:lower0_7:#', '#:lower8_15:#', 8287'#:upper0_7:#' and '#:upper8_15:#' respectively. For example to load 8288the 32-bit address of foo into r0: 8289 8290 MOVS r0, #:upper8_15:#foo 8291 LSLS r0, r0, #8 8292 ADDS r0, #:upper0_7:#foo 8293 LSLS r0, r0, #8 8294 ADDS r0, #:lower8_15:#foo 8295 LSLS r0, r0, #8 8296 ADDS r0, #:lower0_7:#foo 8297 8298 8299File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax 8300 83019.4.2.5 NEON Alignment Specifiers 8302................................. 8303 8304Some NEON load/store instructions allow an optional address alignment 8305qualifier. The ARM documentation specifies that this is indicated by '@ 8306ALIGN'. However GAS already interprets the '@' character as a "line 8307comment" start, so ': ALIGN' is used instead. For example: 8308 8309 vld1.8 {q0}, [r0, :128] 8310 8311 8312File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent 8313 83149.4.3 Floating Point 8315-------------------- 8316 8317The ARM family uses IEEE floating-point numbers. 8318 8319 8320File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent 8321 83229.4.4 ARM Machine Directives 8323---------------------------- 8324 8325'.align EXPRESSION [, EXPRESSION]' 8326 This is the generic .ALIGN directive. For the ARM however if the 8327 first argument is zero (ie no alignment is needed) the assembler 8328 will behave as if the argument had been 2 (ie pad to the next four 8329 byte boundary). This is for compatibility with ARM's own 8330 assembler. 8331 8332'.arch NAME' 8333 Select the target architecture. Valid values for NAME are the same 8334 as for the '-march' command-line option without the instruction set 8335 extension. 8336 8337 Specifying '.arch' clears any previously selected architecture 8338 extensions. 8339 8340'.arch_extension NAME' 8341 Add or remove an architecture extension to the target architecture. 8342 Valid values for NAME are the same as those accepted as 8343 architectural extensions by the '-mcpu' and '-march' command-line 8344 options. 8345 8346 '.arch_extension' may be used multiple times to add or remove 8347 extensions incrementally to the architecture being compiled for. 8348 8349'.arm' 8350 This performs the same action as .CODE 32. 8351 8352'.bss' 8353 This directive switches to the '.bss' section. 8354 8355'.cantunwind' 8356 Prevents unwinding through the current function. No personality 8357 routine or exception table data is required or permitted. 8358 8359'.code [16|32]' 8360 This directive selects the instruction set being generated. The 8361 value 16 selects Thumb, with the value 32 selecting ARM. 8362 8363'.cpu NAME' 8364 Select the target processor. Valid values for NAME are the same as 8365 for the '-mcpu' command-line option without the instruction set 8366 extension. 8367 8368 Specifying '.cpu' clears any previously selected architecture 8369 extensions. 8370 8371'NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' 8372'NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' 8373 8374 The 'dn' and 'qn' directives are used to create typed and/or 8375 indexed register aliases for use in Advanced SIMD Extension (Neon) 8376 instructions. The former should be used to create aliases of 8377 double-precision registers, and the latter to create aliases of 8378 quad-precision registers. 8379 8380 If these directives are used to create typed aliases, those aliases 8381 can be used in Neon instructions instead of writing types after the 8382 mnemonic or after each operand. For example: 8383 8384 x .dn d2.f32 8385 y .dn d3.f32 8386 z .dn d4.f32[1] 8387 vmul x,y,z 8388 8389 This is equivalent to writing the following: 8390 8391 vmul.f32 d2,d3,d4[1] 8392 8393 Aliases created using 'dn' or 'qn' can be destroyed using 'unreq'. 8394 8395'.eabi_attribute TAG, VALUE' 8396 Set the EABI object attribute TAG to VALUE. 8397 8398 The TAG is either an attribute number, or one of the following: 8399 'Tag_CPU_raw_name', 'Tag_CPU_name', 'Tag_CPU_arch', 8400 'Tag_CPU_arch_profile', 'Tag_ARM_ISA_use', 'Tag_THUMB_ISA_use', 8401 'Tag_FP_arch', 'Tag_WMMX_arch', 'Tag_Advanced_SIMD_arch', 8402 'Tag_MVE_arch', 'Tag_PCS_config', 'Tag_ABI_PCS_R9_use', 8403 'Tag_ABI_PCS_RW_data', 'Tag_ABI_PCS_RO_data', 8404 'Tag_ABI_PCS_GOT_use', 'Tag_ABI_PCS_wchar_t', 8405 'Tag_ABI_FP_rounding', 'Tag_ABI_FP_denormal', 8406 'Tag_ABI_FP_exceptions', 'Tag_ABI_FP_user_exceptions', 8407 'Tag_ABI_FP_number_model', 'Tag_ABI_align_needed', 8408 'Tag_ABI_align_preserved', 'Tag_ABI_enum_size', 8409 'Tag_ABI_HardFP_use', 'Tag_ABI_VFP_args', 'Tag_ABI_WMMX_args', 8410 'Tag_ABI_optimization_goals', 'Tag_ABI_FP_optimization_goals', 8411 'Tag_compatibility', 'Tag_CPU_unaligned_access', 8412 'Tag_FP_HP_extension', 'Tag_ABI_FP_16bit_format', 8413 'Tag_MPextension_use', 'Tag_DIV_use', 'Tag_nodefaults', 8414 'Tag_also_compatible_with', 'Tag_conformance', 'Tag_T2EE_use', 8415 'Tag_Virtualization_use' 8416 8417 The VALUE is either a 'number', '"string"', or 'number, "string"' 8418 depending on the tag. 8419 8420 Note - the following legacy values are also accepted by TAG: 8421 'Tag_VFP_arch', 'Tag_ABI_align8_needed', 8422 'Tag_ABI_align8_preserved', 'Tag_VFP_HP_extension', 8423 8424'.even' 8425 This directive aligns to an even-numbered address. 8426 8427'.extend EXPRESSION [, EXPRESSION]*' 8428'.ldouble EXPRESSION [, EXPRESSION]*' 8429 These directives write 12byte long double floating-point values to 8430 the output section. These are not compatible with current ARM 8431 processors or ABIs. 8432 8433'.float16 VALUE [,...,VALUE_N]' 8434 Place the half precision floating point representation of one or 8435 more floating-point values into the current section. The exact 8436 format of the encoding is specified by '.float16_format'. If the 8437 format has not been explicitly set yet (either via the 8438 '.float16_format' directive or the command line option) then the 8439 IEEE 754-2008 format is used. 8440 8441'.float16_format FORMAT' 8442 Set the format to use when encoding float16 values emitted by the 8443 '.float16' directive. Once the format has been set it cannot be 8444 changed. 'format' should be one of the following: 'ieee' (encode 8445 in the IEEE 754-2008 half precision format) or 'alternative' 8446 (encode in the Arm alternative half precision format). 8447 8448'.fnend' 8449 Marks the end of a function with an unwind table entry. The unwind 8450 index table entry is created when this directive is processed. 8451 8452 If no personality routine has been specified then standard 8453 personality routine 0 or 1 will be used, depending on the number of 8454 unwind opcodes required. 8455 8456'.fnstart' 8457 Marks the start of a function with an unwind table entry. 8458 8459'.force_thumb' 8460 This directive forces the selection of Thumb instructions, even if 8461 the target processor does not support those instructions 8462 8463'.fpu NAME' 8464 Select the floating-point unit to assemble for. Valid values for 8465 NAME are the same as for the '-mfpu' command-line option. 8466 8467'.handlerdata' 8468 Marks the end of the current function, and the start of the 8469 exception table entry for that function. Anything between this 8470 directive and the '.fnend' directive will be added to the exception 8471 table entry. 8472 8473 Must be preceded by a '.personality' or '.personalityindex' 8474 directive. 8475 8476'.inst OPCODE [ , ... ]' 8477'.inst.n OPCODE [ , ... ]' 8478'.inst.w OPCODE [ , ... ]' 8479 Generates the instruction corresponding to the numerical value 8480 OPCODE. '.inst.n' and '.inst.w' allow the Thumb instruction size 8481 to be specified explicitly, overriding the normal encoding rules. 8482 8483'.ldouble EXPRESSION [, EXPRESSION]*' 8484 See '.extend'. 8485 8486'.ltorg' 8487 This directive causes the current contents of the literal pool to 8488 be dumped into the current section (which is assumed to be the 8489 .text section) at the current location (aligned to a word 8490 boundary). 'GAS' maintains a separate literal pool for each 8491 section and each sub-section. The '.ltorg' directive will only 8492 affect the literal pool of the current section and sub-section. At 8493 the end of assembly all remaining, un-empty literal pools will 8494 automatically be dumped. 8495 8496 Note - older versions of 'GAS' would dump the current literal pool 8497 any time a section change occurred. This is no longer done, since 8498 it prevents accurate control of the placement of literal pools. 8499 8500'.movsp REG [, #OFFSET]' 8501 Tell the unwinder that REG contains an offset from the current 8502 stack pointer. If OFFSET is not specified then it is assumed to be 8503 zero. 8504 8505'.object_arch NAME' 8506 Override the architecture recorded in the EABI object attribute 8507 section. Valid values for NAME are the same as for the '.arch' 8508 directive. Typically this is useful when code uses runtime 8509 detection of CPU features. 8510 8511'.packed EXPRESSION [, EXPRESSION]*' 8512 This directive writes 12-byte packed floating-point values to the 8513 output section. These are not compatible with current ARM 8514 processors or ABIs. 8515 8516'.pad #COUNT' 8517 Generate unwinder annotations for a stack adjustment of COUNT 8518 bytes. A positive value indicates the function prologue allocated 8519 stack space by decrementing the stack pointer. 8520 8521'.personality NAME' 8522 Sets the personality routine for the current function to NAME. 8523 8524'.personalityindex INDEX' 8525 Sets the personality routine for the current function to the EABI 8526 standard routine number INDEX 8527 8528'.pool' 8529 This is a synonym for .ltorg. 8530 8531'NAME .req REGISTER NAME' 8532 This creates an alias for REGISTER NAME called NAME. For example: 8533 8534 foo .req r0 8535 8536'.save REGLIST' 8537 Generate unwinder annotations to restore the registers in REGLIST. 8538 The format of REGLIST is the same as the corresponding 8539 store-multiple instruction. 8540 8541 _core registers_ 8542 .save {r4, r5, r6, lr} 8543 stmfd sp!, {r4, r5, r6, lr} 8544 _FPA registers_ 8545 .save f4, 2 8546 sfmfd f4, 2, [sp]! 8547 _VFP registers_ 8548 .save {d8, d9, d10} 8549 fstmdx sp!, {d8, d9, d10} 8550 _iWMMXt registers_ 8551 .save {wr10, wr11} 8552 wstrd wr11, [sp, #-8]! 8553 wstrd wr10, [sp, #-8]! 8554 or 8555 .save wr11 8556 wstrd wr11, [sp, #-8]! 8557 .save wr10 8558 wstrd wr10, [sp, #-8]! 8559 8560'.setfp FPREG, SPREG [, #OFFSET]' 8561 Make all unwinder annotations relative to a frame pointer. Without 8562 this the unwinder will use offsets from the stack pointer. 8563 8564 The syntax of this directive is the same as the 'add' or 'mov' 8565 instruction used to set the frame pointer. SPREG must be either 8566 'sp' or mentioned in a previous '.movsp' directive. 8567 8568 .movsp ip 8569 mov ip, sp 8570 ... 8571 .setfp fp, ip, #4 8572 add fp, ip, #4 8573 8574'.secrel32 EXPRESSION [, EXPRESSION]*' 8575 This directive emits relocations that evaluate to the 8576 section-relative offset of each expression's symbol. This 8577 directive is only supported for PE targets. 8578 8579'.syntax [unified | divided]' 8580 This directive sets the Instruction Set Syntax as described in the 8581 *note ARM-Instruction-Set:: section. 8582 8583'.thumb' 8584 This performs the same action as .CODE 16. 8585 8586'.thumb_func' 8587 This directive specifies that the following symbol is the name of a 8588 Thumb encoded function. This information is necessary in order to 8589 allow the assembler and linker to generate correct code for 8590 interworking between Arm and Thumb instructions and should be used 8591 even if interworking is not going to be performed. The presence of 8592 this directive also implies '.thumb' 8593 8594 This directive is not necessary when generating EABI objects. On 8595 these targets the encoding is implicit when generating Thumb code. 8596 8597'.thumb_set' 8598 This performs the equivalent of a '.set' directive in that it 8599 creates a symbol which is an alias for another symbol (possibly not 8600 yet defined). This directive also has the added property in that 8601 it marks the aliased symbol as being a thumb function entry point, 8602 in the same way that the '.thumb_func' directive does. 8603 8604'.tlsdescseq TLS-VARIABLE' 8605 This directive is used to annotate parts of an inlined TLS 8606 descriptor trampoline. Normally the trampoline is provided by the 8607 linker, and this directive is not needed. 8608 8609'.unreq ALIAS-NAME' 8610 This undefines a register alias which was previously defined using 8611 the 'req', 'dn' or 'qn' directives. For example: 8612 8613 foo .req r0 8614 .unreq foo 8615 8616 An error occurs if the name is undefined. Note - this pseudo op 8617 can be used to delete builtin in register name aliases (eg 'r0'). 8618 This should only be done if it is really necessary. 8619 8620'.unwind_raw OFFSET, BYTE1, ...' 8621 Insert one of more arbitrary unwind opcode bytes, which are known 8622 to adjust the stack pointer by OFFSET bytes. 8623 8624 For example '.unwind_raw 4, 0xb1, 0x01' is equivalent to '.save 8625 {r0}' 8626 8627'.vsave VFP-REGLIST' 8628 Generate unwinder annotations to restore the VFP registers in 8629 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are to 8630 be restored using VLDM. The format of VFP-REGLIST is the same as 8631 the corresponding store-multiple instruction. 8632 8633 _VFP registers_ 8634 .vsave {d8, d9, d10} 8635 fstmdd sp!, {d8, d9, d10} 8636 _VFPv3 registers_ 8637 .vsave {d15, d16, d17} 8638 vstm sp!, {d15, d16, d17} 8639 8640 Since FLDMX and FSTMX are now deprecated, this directive should be 8641 used in favour of '.save' for saving VFP registers for ARMv6 and 8642 above. 8643 8644 8645File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 8646 86479.4.5 Opcodes 8648------------- 8649 8650'as' implements all the standard ARM opcodes. It also implements 8651several pseudo opcodes, including several synthetic load instructions. 8652 8653'NOP' 8654 nop 8655 8656 This pseudo op will always evaluate to a legal ARM instruction that 8657 does nothing. Currently it will evaluate to MOV r0, r0. 8658 8659'LDR' 8660 ldr <register> , = <expression> 8661 8662 If expression evaluates to a numeric constant then a MOV or MVN 8663 instruction will be used in place of the LDR instruction, if the 8664 constant can be generated by either of these instructions. 8665 Otherwise the constant will be placed into the nearest literal pool 8666 (if it not already there) and a PC relative LDR instruction will be 8667 generated. 8668 8669'ADR' 8670 adr <register> <label> 8671 8672 This instruction will load the address of LABEL into the indicated 8673 register. The instruction will evaluate to a PC relative ADD or 8674 SUB instruction depending upon where the label is located. If the 8675 label is out of range, or if it is not defined in the same file 8676 (and section) as the ADR instruction, then an error will be 8677 generated. This instruction will not make use of the literal pool. 8678 8679 If LABEL is a thumb function symbol, and thumb interworking has 8680 been enabled via the '-mthumb-interwork' option then the bottom bit 8681 of the value stored into REGISTER will be set. This allows the 8682 following sequence to work as expected: 8683 8684 adr r0, thumb_function 8685 blx r0 8686 8687'ADRL' 8688 adrl <register> <label> 8689 8690 This instruction will load the address of LABEL into the indicated 8691 register. The instruction will evaluate to one or two PC relative 8692 ADD or SUB instructions depending upon where the label is located. 8693 If a second instruction is not needed a NOP instruction will be 8694 generated in its place, so that this instruction is always 8 bytes 8695 long. 8696 8697 If the label is out of range, or if it is not defined in the same 8698 file (and section) as the ADRL instruction, then an error will be 8699 generated. This instruction will not make use of the literal pool. 8700 8701 If LABEL is a thumb function symbol, and thumb interworking has 8702 been enabled via the '-mthumb-interwork' option then the bottom bit 8703 of the value stored into REGISTER will be set. 8704 8705 For information on the ARM or Thumb instruction sets, see 'ARM 8706Software Development Toolkit Reference Manual', Advanced RISC Machines 8707Ltd. 8708 8709 8710File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent 8711 87129.4.6 Mapping Symbols 8713--------------------- 8714 8715The ARM ELF specification requires that special symbols be inserted into 8716object files to mark certain features: 8717 8718'$a' 8719 At the start of a region of code containing ARM instructions. 8720 8721'$t' 8722 At the start of a region of code containing THUMB instructions. 8723 8724'$d' 8725 At the start of a region of data. 8726 8727 The assembler will automatically insert these symbols for you - there 8728is no need to code them yourself. Support for tagging symbols ($b, $f, 8729$p and $m) which is also mentioned in the current ARM ELF specification 8730is not implemented. This is because they have been dropped from the new 8731EABI and so tools cannot rely upon their presence. 8732 8733 8734File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent 8735 87369.4.7 Unwinding 8737--------------- 8738 8739The ABI for the ARM Architecture specifies a standard format for 8740exception unwind information. This information is used when an 8741exception is thrown to determine where control should be transferred. 8742In particular, the unwind information is used to determine which 8743function called the function that threw the exception, and which 8744function called that one, and so forth. This information is also used 8745to restore the values of callee-saved registers in the function catching 8746the exception. 8747 8748 If you are writing functions in assembly code, and those functions 8749call other functions that throw exceptions, you must use assembly pseudo 8750ops to ensure that appropriate exception unwind information is 8751generated. Otherwise, if one of the functions called by your assembly 8752code throws an exception, the run-time library will be unable to unwind 8753the stack through your assembly code and your program will not behave 8754correctly. 8755 8756 To illustrate the use of these pseudo ops, we will examine the code 8757that G++ generates for the following C++ input: 8758 8759void callee (int *); 8760 8761int 8762caller () 8763{ 8764 int i; 8765 callee (&i); 8766 return i; 8767} 8768 8769 This example does not show how to throw or catch an exception from 8770assembly code. That is a much more complex operation and should always 8771be done in a high-level language, such as C++, that directly supports 8772exceptions. 8773 8774 The code generated by one particular version of G++ when compiling 8775the example above is: 8776 8777_Z6callerv: 8778 .fnstart 8779.LFB2: 8780 @ Function supports interworking. 8781 @ args = 0, pretend = 0, frame = 8 8782 @ frame_needed = 1, uses_anonymous_args = 0 8783 stmfd sp!, {fp, lr} 8784 .save {fp, lr} 8785.LCFI0: 8786 .setfp fp, sp, #4 8787 add fp, sp, #4 8788.LCFI1: 8789 .pad #8 8790 sub sp, sp, #8 8791.LCFI2: 8792 sub r3, fp, #8 8793 mov r0, r3 8794 bl _Z6calleePi 8795 ldr r3, [fp, #-8] 8796 mov r0, r3 8797 sub sp, fp, #4 8798 ldmfd sp!, {fp, lr} 8799 bx lr 8800.LFE2: 8801 .fnend 8802 8803 Of course, the sequence of instructions varies based on the options 8804you pass to GCC and on the version of GCC in use. The exact 8805instructions are not important since we are focusing on the pseudo ops 8806that are used to generate unwind information. 8807 8808 An important assumption made by the unwinder is that the stack frame 8809does not change during the body of the function. In particular, since 8810we assume that the assembly code does not itself throw an exception, the 8811only point where an exception can be thrown is from a call, such as the 8812'bl' instruction above. At each call site, the same saved registers 8813(including 'lr', which indicates the return address) must be located in 8814the same locations relative to the frame pointer. 8815 8816 The '.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op 8817appears immediately before the first instruction of the function while 8818the '.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears 8819immediately after the last instruction of the function. These pseudo 8820ops specify the range of the function. 8821 8822 Only the order of the other pseudos ops (e.g., '.setfp' or '.pad') 8823matters; their exact locations are irrelevant. In the example above, 8824the compiler emits the pseudo ops with particular instructions. That 8825makes it easier to understand the code, but it is not required for 8826correctness. It would work just as well to emit all of the pseudo ops 8827other than '.fnend' in the same order, but immediately after '.fnstart'. 8828 8829 The '.save' (*note .save pseudo op: arm_save.) pseudo op indicates 8830registers that have been saved to the stack so that they can be restored 8831before the function returns. The argument to the '.save' pseudo op is a 8832list of registers to save. If a register is "callee-saved" (as 8833specified by the ABI) and is modified by the function you are writing, 8834then your code must save the value before it is modified and restore the 8835original value before the function returns. If an exception is thrown, 8836the run-time library restores the values of these registers from their 8837locations on the stack before returning control to the exception 8838handler. (Of course, if an exception is not thrown, the function that 8839contains the '.save' pseudo op restores these registers in the function 8840epilogue, as is done with the 'ldmfd' instruction above.) 8841 8842 You do not have to save callee-saved registers at the very beginning 8843of the function and you do not need to use the '.save' pseudo op 8844immediately following the point at which the registers are saved. 8845However, if you modify a callee-saved register, you must save it on the 8846stack before modifying it and before calling any functions which might 8847throw an exception. And, you must use the '.save' pseudo op to indicate 8848that you have done so. 8849 8850 The '.pad' (*note .pad: arm_pad.) pseudo op indicates a modification 8851of the stack pointer that does not save any registers. The argument is 8852the number of bytes (in decimal) that are subtracted from the stack 8853pointer. (On ARM CPUs, the stack grows downwards, so subtracting from 8854the stack pointer increases the size of the stack.) 8855 8856 The '.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op indicates 8857the register that contains the frame pointer. The first argument is the 8858register that is set, which is typically 'fp'. The second argument 8859indicates the register from which the frame pointer takes its value. 8860The third argument, if present, is the value (in decimal) added to the 8861register specified by the second argument to compute the value of the 8862frame pointer. You should not modify the frame pointer in the body of 8863the function. 8864 8865 If you do not use a frame pointer, then you should not use the 8866'.setfp' pseudo op. If you do not use a frame pointer, then you should 8867avoid modifying the stack pointer outside of the function prologue. 8868Otherwise, the run-time library will be unable to find saved registers 8869when it is unwinding the stack. 8870 8871 The pseudo ops described above are sufficient for writing assembly 8872code that calls functions which may throw exceptions. If you need to 8873know more about the object-file format used to represent unwind 8874information, you may consult the 'Exception Handling ABI for the ARM 8875Architecture' available from <http://infocenter.arm.com>. 8876 8877 8878File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies 8879 88809.5 AVR Dependent Features 8881========================== 8882 8883* Menu: 8884 8885* AVR Options:: Options 8886* AVR Syntax:: Syntax 8887* AVR Opcodes:: Opcodes 8888* AVR Pseudo Instructions:: Pseudo Instructions 8889 8890 8891File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 8892 88939.5.1 Options 8894------------- 8895 8896'-mmcu=MCU' 8897 Specify ATMEL AVR instruction set or MCU type. 8898 8899 Instruction set avr1 is for the minimal AVR core, not supported by 8900 the C compiler, only for assembler programs (MCU types: at90s1200, 8901 attiny11, attiny12, attiny15, attiny28). 8902 8903 Instruction set avr2 (default) is for the classic AVR core with up 8904 to 8K program memory space (MCU types: at90s2313, at90s2323, 8905 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, 8906 at90s4434, at90s8515, at90c8534, at90s8535). 8907 8908 Instruction set avr25 is for the classic AVR core with up to 8K 8909 program memory space plus the MOVW instruction (MCU types: 8910 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, 8911 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, 8912 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, 8913 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 8914 attiny828, at86rf401, ata6289, ata5272). 8915 8916 Instruction set avr3 is for the classic AVR core with up to 128K 8917 program memory space (MCU types: at43usb355, at76c711). 8918 8919 Instruction set avr31 is for the classic AVR core with exactly 128K 8920 program memory space (MCU types: atmega103, at43usb320). 8921 8922 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and 8923 JMP instructions (MCU types: attiny167, attiny1634, at90usb82, 8924 at90usb162, atmega8u2, atmega16u2, atmega32u2, ata5505). 8925 8926 Instruction set avr4 is for the enhanced AVR core with up to 8K 8927 program memory space (MCU types: atmega48, atmega48a, atmega48pa, 8928 atmega48p, atmega8, atmega8a, atmega88, atmega88a, atmega88p, 8929 atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, 8930 at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6285, ata6286). 8931 8932 Instruction set avr5 is for the enhanced AVR core with up to 128K 8933 program memory space (MCU types: at90pwm161, atmega16, atmega16a, 8934 atmega161, atmega162, atmega163, atmega164a, atmega164p, 8935 atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, 8936 atmega168, atmega168a, atmega168p, atmega168pa, atmega169, 8937 atmega169a, atmega169p, atmega169pa, atmega32, atmega323, 8938 atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, 8939 atmega32, atmega32a, atmega323, atmega324a, atmega324p, 8940 atmega324pa, atmega325, atmega325a, atmega325p, atmega325p, 8941 atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, 8942 atmega328, atmega328p, atmega329, atmega329a, atmega329p, 8943 atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406, 8944 atmega64, atmega64a, atmega64rfr2, atmega644rfr2, atmega640, 8945 atmega644, atmega644a, atmega644p, atmega644pa, atmega645, 8946 atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p, 8947 atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, 8948 atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, 8949 atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, 8950 at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, 8951 atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1, 8952 atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, 8953 at90scr100, ata5790, ata5795). 8954 8955 Instruction set avr51 is for the enhanced AVR core with exactly 8956 128K program memory space (MCU types: atmega128, atmega128a, 8957 atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1, 8958 atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 8959 at90usb1287, m3000). 8960 8961 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 8962 (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). 8963 8964 Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K 8965 program memory space and less than 64K data space (MCU types: 8966 atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, 8967 atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, 8968 atxmega8e5, atxmega32e5, atxmega32x1). 8969 8970 Instruction set avrxmega3 is for the XMEGA AVR core with up to 64K 8971 of combined program memory and RAM, and with program memory visible 8972 in the RAM address space (MCU types: attiny212, attiny214, 8973 attiny412, attiny414, attiny416, attiny417, attiny814, attiny816, 8974 attiny817, attiny1614, attiny1616, attiny1617, attiny3214, 8975 attiny3216, attiny3217). 8976 8977 Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K 8978 program memory space and less than 64K data space (MCU types: 8979 atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, 8980 atxmega64c3, atxmega64d3, atxmega64d4). 8981 8982 Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K 8983 program memory space and greater than 64K data space (MCU types: 8984 atxmega64a1, atxmega64a1u). 8985 8986 Instruction set avrxmega6 is for the XMEGA AVR core with larger 8987 than 64K program memory space and less than 64K data space (MCU 8988 types: atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, 8989 atxmega128d4, atxmega192a3, atxmega192a3u, atxmega128b1, 8990 atxmega128b3, atxmega192c3, atxmega192d3, atxmega256a3, 8991 atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3, 8992 atxmega256d3, atxmega384c3, atxmega256d3). 8993 8994 Instruction set avrxmega7 is for the XMEGA AVR core with larger 8995 than 64K program memory space and greater than 64K data space (MCU 8996 types: atxmega128a1, atxmega128a1u, atxmega128a4u). 8997 8998 Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 8999 microcontrollers. 9000 9001'-mall-opcodes' 9002 Accept all AVR opcodes, even if not supported by '-mmcu'. 9003 9004'-mno-skip-bug' 9005 This option disable warnings for skipping two-word instructions. 9006 9007'-mno-wrap' 9008 This option reject 'rjmp/rcall' instructions with 8K wrap-around. 9009 9010'-mrmw' 9011 Accept Read-Modify-Write ('XCH,LAC,LAS,LAT') instructions. 9012 9013'-mlink-relax' 9014 Enable support for link-time relaxation. This is now on by default 9015 and this flag no longer has any effect. 9016 9017'-mno-link-relax' 9018 Disable support for link-time relaxation. The assembler will 9019 resolve relocations when it can, and may be able to better compress 9020 some debug information. 9021 9022'-mgcc-isr' 9023 Enable the '__gcc_isr' pseudo instruction. 9024 9025 9026File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent 9027 90289.5.2 Syntax 9029------------ 9030 9031* Menu: 9032 9033* AVR-Chars:: Special Characters 9034* AVR-Regs:: Register Names 9035* AVR-Modifiers:: Relocatable Expression Modifiers 9036 9037 9038File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 9039 90409.5.2.1 Special Characters 9041.......................... 9042 9043The presence of a ';' anywhere on a line indicates the start of a 9044comment that extends to the end of that line. 9045 9046 If a '#' appears as the first character of a line, the whole line is 9047treated as a comment, but in this case the line can also be a logical 9048line number directive (*note Comments::) or a preprocessor control 9049command (*note Preprocessing::). 9050 9051 The '$' character can be used instead of a newline to separate 9052statements. 9053 9054 9055File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax 9056 90579.5.2.2 Register Names 9058...................... 9059 9060The AVR has 32 x 8-bit general purpose working registers 'r0', 'r1', ... 9061'r31'. Six of the 32 registers can be used as three 16-bit indirect 9062address register pointers for Data Space addressing. One of the these 9063address pointers can also be used as an address pointer for look up 9064tables in Flash program memory. These added function registers are the 906516-bit 'X', 'Y' and 'Z' - registers. 9066 9067 X = r26:r27 9068 Y = r28:r29 9069 Z = r30:r31 9070 9071 9072File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax 9073 90749.5.2.3 Relocatable Expression Modifiers 9075........................................ 9076 9077The assembler supports several modifiers when using relocatable 9078addresses in AVR instruction operands. The general syntax is the 9079following: 9080 9081 modifier(relocatable-expression) 9082 9083'lo8' 9084 9085 This modifier allows you to use bits 0 through 7 of an address 9086 expression as an 8 bit relocatable expression. 9087 9088'hi8' 9089 9090 This modifier allows you to use bits 7 through 15 of an address 9091 expression as an 8 bit relocatable expression. This is useful 9092 with, for example, the AVR 'ldi' instruction and 'lo8' modifier. 9093 9094 For example 9095 9096 ldi r26, lo8(sym+10) 9097 ldi r27, hi8(sym+10) 9098 9099'hh8' 9100 9101 This modifier allows you to use bits 16 through 23 of an address 9102 expression as an 8 bit relocatable expression. Also, can be useful 9103 for loading 32 bit constants. 9104 9105'hlo8' 9106 9107 Synonym of 'hh8'. 9108 9109'hhi8' 9110 9111 This modifier allows you to use bits 24 through 31 of an expression 9112 as an 8 bit expression. This is useful with, for example, the AVR 9113 'ldi' instruction and 'lo8', 'hi8', 'hlo8', 'hhi8', modifier. 9114 9115 For example 9116 9117 ldi r26, lo8(285774925) 9118 ldi r27, hi8(285774925) 9119 ldi r28, hlo8(285774925) 9120 ldi r29, hhi8(285774925) 9121 ; r29,r28,r27,r26 = 285774925 9122 9123'pm_lo8' 9124 9125 This modifier allows you to use bits 0 through 7 of an address 9126 expression as an 8 bit relocatable expression. This modifier is 9127 useful for addressing data or code from Flash/Program memory by 9128 two-byte words. The use of 'pm_lo8' is similar to 'lo8'. 9129 9130'pm_hi8' 9131 9132 This modifier allows you to use bits 8 through 15 of an address 9133 expression as an 8 bit relocatable expression. This modifier is 9134 useful for addressing data or code from Flash/Program memory by 9135 two-byte words. 9136 9137 For example, when setting the AVR 'Z' register with the 'ldi' 9138 instruction for subsequent use by the 'ijmp' instruction: 9139 9140 ldi r30, pm_lo8(sym) 9141 ldi r31, pm_hi8(sym) 9142 ijmp 9143 9144'pm_hh8' 9145 9146 This modifier allows you to use bits 15 through 23 of an address 9147 expression as an 8 bit relocatable expression. This modifier is 9148 useful for addressing data or code from Flash/Program memory by 9149 two-byte words. 9150 9151 9152File: as.info, Node: AVR Opcodes, Next: AVR Pseudo Instructions, Prev: AVR Syntax, Up: AVR-Dependent 9153 91549.5.3 Opcodes 9155------------- 9156 9157For detailed information on the AVR machine instruction set, see 9158<www.atmel.com/products/AVR>. 9159 9160 'as' implements all the standard AVR opcodes. The following table 9161summarizes the AVR opcodes, and their arguments. 9162 9163 Legend: 9164 r any register 9165 d 'ldi' register (r16-r31) 9166 v 'movw' even register (r0, r2, ..., r28, r30) 9167 a 'fmul' register (r16-r23) 9168 w 'adiw' register (r24,r26,r28,r30) 9169 e pointer registers (X,Y,Z) 9170 b base pointer register and displacement ([YZ]+disp) 9171 z Z pointer register (for [e]lpm Rd,Z[+]) 9172 M immediate value from 0 to 255 9173 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible 9174 s immediate value from 0 to 7 9175 P Port address value from 0 to 63. (in, out) 9176 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) 9177 K immediate value from 0 to 63 (used in 'adiw', 'sbiw') 9178 i immediate value 9179 l signed pc relative offset from -64 to 63 9180 L signed pc relative offset from -2048 to 2047 9181 h absolute code address (call, jmp) 9182 S immediate value from 0 to 7 (S = s << 4) 9183 ? use this opcode entry if no parameters, else use next opcode entry 9184 9185 1001010010001000 clc 9186 1001010011011000 clh 9187 1001010011111000 cli 9188 1001010010101000 cln 9189 1001010011001000 cls 9190 1001010011101000 clt 9191 1001010010111000 clv 9192 1001010010011000 clz 9193 1001010000001000 sec 9194 1001010001011000 seh 9195 1001010001111000 sei 9196 1001010000101000 sen 9197 1001010001001000 ses 9198 1001010001101000 set 9199 1001010000111000 sev 9200 1001010000011000 sez 9201 100101001SSS1000 bclr S 9202 100101000SSS1000 bset S 9203 1001010100001001 icall 9204 1001010000001001 ijmp 9205 1001010111001000 lpm ? 9206 1001000ddddd010+ lpm r,z 9207 1001010111011000 elpm ? 9208 1001000ddddd011+ elpm r,z 9209 0000000000000000 nop 9210 1001010100001000 ret 9211 1001010100011000 reti 9212 1001010110001000 sleep 9213 1001010110011000 break 9214 1001010110101000 wdr 9215 1001010111101000 spm 9216 000111rdddddrrrr adc r,r 9217 000011rdddddrrrr add r,r 9218 001000rdddddrrrr and r,r 9219 000101rdddddrrrr cp r,r 9220 000001rdddddrrrr cpc r,r 9221 000100rdddddrrrr cpse r,r 9222 001001rdddddrrrr eor r,r 9223 001011rdddddrrrr mov r,r 9224 100111rdddddrrrr mul r,r 9225 001010rdddddrrrr or r,r 9226 000010rdddddrrrr sbc r,r 9227 000110rdddddrrrr sub r,r 9228 001001rdddddrrrr clr r 9229 000011rdddddrrrr lsl r 9230 000111rdddddrrrr rol r 9231 001000rdddddrrrr tst r 9232 0111KKKKddddKKKK andi d,M 9233 0111KKKKddddKKKK cbr d,n 9234 1110KKKKddddKKKK ldi d,M 9235 11101111dddd1111 ser d 9236 0110KKKKddddKKKK ori d,M 9237 0110KKKKddddKKKK sbr d,M 9238 0011KKKKddddKKKK cpi d,M 9239 0100KKKKddddKKKK sbci d,M 9240 0101KKKKddddKKKK subi d,M 9241 1111110rrrrr0sss sbrc r,s 9242 1111111rrrrr0sss sbrs r,s 9243 1111100ddddd0sss bld r,s 9244 1111101ddddd0sss bst r,s 9245 10110PPdddddPPPP in r,P 9246 10111PPrrrrrPPPP out P,r 9247 10010110KKddKKKK adiw w,K 9248 10010111KKddKKKK sbiw w,K 9249 10011000pppppsss cbi p,s 9250 10011010pppppsss sbi p,s 9251 10011001pppppsss sbic p,s 9252 10011011pppppsss sbis p,s 9253 111101lllllll000 brcc l 9254 111100lllllll000 brcs l 9255 111100lllllll001 breq l 9256 111101lllllll100 brge l 9257 111101lllllll101 brhc l 9258 111100lllllll101 brhs l 9259 111101lllllll111 brid l 9260 111100lllllll111 brie l 9261 111100lllllll000 brlo l 9262 111100lllllll100 brlt l 9263 111100lllllll010 brmi l 9264 111101lllllll001 brne l 9265 111101lllllll010 brpl l 9266 111101lllllll000 brsh l 9267 111101lllllll110 brtc l 9268 111100lllllll110 brts l 9269 111101lllllll011 brvc l 9270 111100lllllll011 brvs l 9271 111101lllllllsss brbc s,l 9272 111100lllllllsss brbs s,l 9273 1101LLLLLLLLLLLL rcall L 9274 1100LLLLLLLLLLLL rjmp L 9275 1001010hhhhh111h call h 9276 1001010hhhhh110h jmp h 9277 1001010rrrrr0101 asr r 9278 1001010rrrrr0000 com r 9279 1001010rrrrr1010 dec r 9280 1001010rrrrr0011 inc r 9281 1001010rrrrr0110 lsr r 9282 1001010rrrrr0001 neg r 9283 1001000rrrrr1111 pop r 9284 1001001rrrrr1111 push r 9285 1001010rrrrr0111 ror r 9286 1001010rrrrr0010 swap r 9287 00000001ddddrrrr movw v,v 9288 00000010ddddrrrr muls d,d 9289 000000110ddd0rrr mulsu a,a 9290 000000110ddd1rrr fmul a,a 9291 000000111ddd0rrr fmuls a,a 9292 000000111ddd1rrr fmulsu a,a 9293 1001001ddddd0000 sts i,r 9294 1001000ddddd0000 lds r,i 9295 10o0oo0dddddbooo ldd r,b 9296 100!000dddddee-+ ld r,e 9297 10o0oo1rrrrrbooo std b,r 9298 100!001rrrrree-+ st e,r 9299 1001010100011001 eicall 9300 1001010000011001 eijmp 9301 9302 9303File: as.info, Node: AVR Pseudo Instructions, Prev: AVR Opcodes, Up: AVR-Dependent 9304 93059.5.4 Pseudo Instructions 9306------------------------- 9307 9308The only available pseudo-instruction '__gcc_isr' can be activated by 9309option '-mgcc-isr'. 9310 9311'__gcc_isr 1' 9312 Emit code chunk to be used in avr-gcc ISR prologue. It will expand 9313 to at most six 1-word instructions, all optional: push of 9314 'tmp_reg', push of 'SREG', push and clear of 'zero_reg', push of 9315 REG. 9316 9317'__gcc_isr 2' 9318 Emit code chunk to be used in an avr-gcc ISR epilogue. It will 9319 expand to at most five 1-word instructions, all optional: pop of 9320 REG, pop of 'zero_reg', pop of 'SREG', pop of 'tmp_reg'. 9321 9322'__gcc_isr 0, REG' 9323 Finish avr-gcc ISR function. Scan code since the last prologue for 9324 usage of: 'SREG', 'tmp_reg', 'zero_reg'. Prologue chunk and 9325 epilogue chunks will be replaced by appropriate code to save / 9326 restore 'SREG', 'tmp_reg', 'zero_reg' and REG. 9327 9328 Example input: 9329 9330 __vector1: 9331 __gcc_isr 1 9332 lds r24, var 9333 inc r24 9334 sts var, r24 9335 __gcc_isr 2 9336 reti 9337 __gcc_isr 0, r24 9338 9339 Example output: 9340 9341 00000000 <__vector1>: 9342 0: 8f 93 push r24 9343 2: 8f b7 in r24, 0x3f 9344 4: 8f 93 push r24 9345 6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var> 9346 a: 83 95 inc r24 9347 c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var> 9348 10: 8f 91 pop r24 9349 12: 8f bf out 0x3f, r24 9350 14: 8f 91 pop r24 9351 16: 18 95 reti 9352 9353 9354File: as.info, Node: Blackfin-Dependent, Next: BPF-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies 9355 93569.6 Blackfin Dependent Features 9357=============================== 9358 9359* Menu: 9360 9361* Blackfin Options:: Blackfin Options 9362* Blackfin Syntax:: Blackfin Syntax 9363* Blackfin Directives:: Blackfin Directives 9364 9365 9366File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent 9367 93689.6.1 Options 9369------------- 9370 9371'-mcpu=PROCESSOR[-SIREVISION]' 9372 This option specifies the target processor. The optional 9373 SIREVISION is not used in assembler. It's here such that GCC can 9374 easily pass down its '-mcpu=' option. The assembler will issue an 9375 error message if an attempt is made to assemble an instruction 9376 which will not execute on the target processor. The following 9377 processor names are recognized: 'bf504', 'bf506', 'bf512', 'bf514', 9378 'bf516', 'bf518', 'bf522', 'bf523', 'bf524', 'bf525', 'bf526', 9379 'bf527', 'bf531', 'bf532', 'bf533', 'bf534', 'bf535' (not 9380 implemented yet), 'bf536', 'bf537', 'bf538', 'bf539', 'bf542', 9381 'bf542m', 'bf544', 'bf544m', 'bf547', 'bf547m', 'bf548', 'bf548m', 9382 'bf549', 'bf549m', 'bf561', and 'bf592'. 9383 9384'-mfdpic' 9385 Assemble for the FDPIC ABI. 9386 9387'-mno-fdpic' 9388'-mnopic' 9389 Disable -mfdpic. 9390 9391 9392File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent 9393 93949.6.2 Syntax 9395------------ 9396 9397'Special Characters' 9398 Assembler input is free format and may appear anywhere on the line. 9399 One instruction may extend across multiple lines or more than one 9400 instruction may appear on the same line. White space (space, tab, 9401 comments or newline) may appear anywhere between tokens. A token 9402 must not have embedded spaces. Tokens include numbers, register 9403 names, keywords, user identifiers, and also some multicharacter 9404 special symbols like "+=", "/*" or "||". 9405 9406 Comments are introduced by the '#' character and extend to the end 9407 of the current line. If the '#' appears as the first character of 9408 a line, the whole line is treated as a comment, but in this case 9409 the line can also be a logical line number directive (*note 9410 Comments::) or a preprocessor control command (*note 9411 Preprocessing::). 9412 9413'Instruction Delimiting' 9414 A semicolon must terminate every instruction. Sometimes a complete 9415 instruction will consist of more than one operation. There are two 9416 cases where this occurs. The first is when two general operations 9417 are combined. Normally a comma separates the different parts, as 9418 in 9419 9420 a0= r3.h * r2.l, a1 = r3.l * r2.h ; 9421 9422 The second case occurs when a general instruction is combined with 9423 one or two memory references for joint issue. The latter portions 9424 are set off by a "||" token. 9425 9426 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 9427 9428 Multiple instructions can occur on the same line. Each must be 9429 terminated by a semicolon character. 9430 9431'Register Names' 9432 9433 The assembler treats register names and instruction keywords in a 9434 case insensitive manner. User identifiers are case sensitive. 9435 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the 9436 assembler. 9437 9438 Register names are reserved and may not be used as program 9439 identifiers. 9440 9441 Some operations (such as "Move Register") require a register pair. 9442 Register pairs are always data registers and are denoted using a 9443 colon, eg., R3:2. The larger number must be written firsts. Note 9444 that the hardware only supports odd-even pairs, eg., R7:6, R5:4, 9445 R3:2, and R1:0. 9446 9447 Some instructions (such as -SP (Push Multiple)) require a group of 9448 adjacent registers. Adjacent registers are denoted in the syntax 9449 by the range enclosed in parentheses and separated by a colon, eg., 9450 (R7:3). Again, the larger number appears first. 9451 9452 Portions of a particular register may be individually specified. 9453 This is written with a dot (".") following the register name and 9454 then a letter denoting the desired portion. For 32-bit registers, 9455 ".H" denotes the most significant ("High") portion. ".L" denotes 9456 the least-significant portion. The subdivisions of the 40-bit 9457 registers are described later. 9458 9459'Accumulators' 9460 The set of 40-bit registers A1 and A0 that normally contain data 9461 that is being manipulated. Each accumulator can be accessed in 9462 four ways. 9463 9464 'one 40-bit register' 9465 The register will be referred to as A1 or A0. 9466 'one 32-bit register' 9467 The registers are designated as A1.W or A0.W. 9468 'two 16-bit registers' 9469 The registers are designated as A1.H, A1.L, A0.H or A0.L. 9470 'one 8-bit register' 9471 The registers are designated as A1.X or A0.X for the bits that 9472 extend beyond bit 31. 9473 9474'Data Registers' 9475 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) 9476 that normally contain data for manipulation. These are abbreviated 9477 as D-register or Dreg. Data registers can be accessed as 32-bit 9478 registers or as two independent 16-bit registers. The least 9479 significant 16 bits of each register is called the "low" half and 9480 is designated with ".L" following the register name. The most 9481 significant 16 bits are called the "high" half and is designated 9482 with ".H" following the name. 9483 9484 R7.L, r2.h, r4.L, R0.H 9485 9486'Pointer Registers' 9487 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) 9488 that normally contain byte addresses of data structures. These are 9489 abbreviated as P-register or Preg. 9490 9491 p2, p5, fp, sp 9492 9493'Stack Pointer SP' 9494 The stack pointer contains the 32-bit address of the last occupied 9495 byte location in the stack. The stack grows by decrementing the 9496 stack pointer. 9497 9498'Frame Pointer FP' 9499 The frame pointer contains the 32-bit address of the previous frame 9500 pointer in the stack. It is located at the top of a frame. 9501 9502'Loop Top' 9503 LT0 and LT1. These registers contain the 32-bit address of the top 9504 of a zero overhead loop. 9505 9506'Loop Count' 9507 LC0 and LC1. These registers contain the 32-bit counter of the 9508 zero overhead loop executions. 9509 9510'Loop Bottom' 9511 LB0 and LB1. These registers contain the 32-bit address of the 9512 bottom of a zero overhead loop. 9513 9514'Index Registers' 9515 The set of 32-bit registers (I0, I1, I2, I3) that normally contain 9516 byte addresses of data structures. Abbreviated I-register or Ireg. 9517 9518'Modify Registers' 9519 The set of 32-bit registers (M0, M1, M2, M3) that normally contain 9520 offset values that are added and subtracted to one of the index 9521 registers. Abbreviated as Mreg. 9522 9523'Length Registers' 9524 The set of 32-bit registers (L0, L1, L2, L3) that normally contain 9525 the length in bytes of the circular buffer. Abbreviated as Lreg. 9526 Clear the Lreg to disable circular addressing for the corresponding 9527 Ireg. 9528 9529'Base Registers' 9530 The set of 32-bit registers (B0, B1, B2, B3) that normally contain 9531 the base address in bytes of the circular buffer. Abbreviated as 9532 Breg. 9533 9534'Floating Point' 9535 The Blackfin family has no hardware floating point but the .float 9536 directive generates ieee floating point numbers for use with 9537 software floating point libraries. 9538 9539'Blackfin Opcodes' 9540 For detailed information on the Blackfin machine instruction set, 9541 see the Blackfin Processor Instruction Set Reference. 9542 9543 9544File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent 9545 95469.6.3 Directives 9547---------------- 9548 9549The following directives are provided for compatibility with the VDSP 9550assembler. 9551 9552'.byte2' 9553 Initializes a two byte data object. 9554 9555 This maps to the '.short' directive. 9556'.byte4' 9557 Initializes a four byte data object. 9558 9559 This maps to the '.int' directive. 9560'.db' 9561 Initializes a single byte data object. 9562 9563 This directive is a synonym for '.byte'. 9564'.dw' 9565 Initializes a two byte data object. 9566 9567 This directive is a synonym for '.byte2'. 9568'.dd' 9569 Initializes a four byte data object. 9570 9571 This directive is a synonym for '.byte4'. 9572'.var' 9573 Define and initialize a 32 bit data object. 9574 9575 9576File: as.info, Node: BPF-Dependent, Next: CR16-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies 9577 95789.7 BPF Dependent Features 9579========================== 9580 9581* Menu: 9582 9583* BPF Options:: Options 9584* BPF Syntax:: Syntax 9585* BPF Directives:: Machine Directives 9586* BPF Opcodes:: Opcodes 9587 9588 9589File: as.info, Node: BPF Options, Next: BPF Syntax, Up: BPF-Dependent 9590 95919.7.1 Options 9592------------- 9593 9594'-EB' 9595 This option specifies that the assembler should emit big-endian 9596 eBPF. 9597 9598'-EL' 9599 This option specifies that the assembler should emit little-endian 9600 eBPF. 9601 9602 Note that if no endianness option is specified in the command line, 9603the host endianness is used. 9604 9605 9606File: as.info, Node: BPF Syntax, Next: BPF Directives, Prev: BPF Options, Up: BPF-Dependent 9607 96089.7.2 Syntax 9609------------ 9610 9611* Menu: 9612 9613* BPF-Chars:: Special Characters 9614* BPF-Regs:: Register Names 9615* BPF-Pseudo-Maps:: Pseudo map fds 9616 9617 9618File: as.info, Node: BPF-Chars, Next: BPF-Regs, Up: BPF Syntax 9619 96209.7.2.1 Special Characters 9621.......................... 9622 9623The presence of a ';' on a line indicates the start of a comment that 9624extends to the end of the current line. If a '#' appears as the first 9625character of a line, the whole line is treated as a comment. 9626 9627 Statements and assembly directives are separated by newlines. 9628 9629 9630File: as.info, Node: BPF-Regs, Next: BPF-Pseudo-Maps, Prev: BPF-Chars, Up: BPF Syntax 9631 96329.7.2.2 Register Names 9633...................... 9634 9635The eBPF processor provides ten general-purpose 64-bit registers, which 9636are read-write, and a read-only frame pointer register: 9637 9638'%r0 .. %r9' 9639 General-purpose registers. 9640'%r10' 9641 Frame pointer register. 9642 9643 Some registers have additional names, to reflect their role in the 9644eBPF ABI: 9645 9646'%a' 9647 This is '%r0'. 9648'%ctx' 9649 This is '%r6'. 9650'%fp' 9651 This is '%r10'. 9652 9653 9654File: as.info, Node: BPF-Pseudo-Maps, Prev: BPF-Regs, Up: BPF Syntax 9655 96569.7.2.3 Pseudo Maps 9657................... 9658 9659The 'LDDW' instruction can take a literal pseudo map file descriptor as 9660its second argument. This uses the syntax '%map_fd(N)' where 'N' is a 9661signed number. 9662 9663 For example, to load the address of the pseudo map with file 9664descriptor '2' in register 'r1' we would do: 9665 9666 lddw %r1, %map_fd(2) 9667 9668 9669File: as.info, Node: BPF Directives, Next: BPF Opcodes, Prev: BPF Syntax, Up: BPF-Dependent 9670 96719.7.3 Machine Directives 9672------------------------ 9673 9674The BPF version of 'as' supports the following additional machine 9675directives: 9676 9677'.word' 9678 The '.half' directive produces a 16 bit value. 9679 9680'.word' 9681 The '.word' directive produces a 32 bit value. 9682 9683'.dword' 9684 The '.dword' directive produces a 64 bit value. 9685 9686 9687File: as.info, Node: BPF Opcodes, Prev: BPF Directives, Up: BPF-Dependent 9688 96899.7.4 Opcodes 9690------------- 9691 9692In the instruction descriptions below the following field descriptors 9693are used: 9694 9695'%d' 9696 Destination general-purpose register whose role is to be 9697 destination of an operation. 9698'%s' 9699 Source general-purpose register whose role is to be the source of 9700 an operation. 9701'disp16' 9702 16-bit signed PC-relative offset, measured in number of 64-bit 9703 words, minus one. 9704'disp32' 9705 32-bit signed PC-relative offset, measured in number of 64-bit 9706 words, minus one. 9707'offset16' 9708 Signed 16-bit immediate. 9709'imm32' 9710 Signed 32-bit immediate. 9711'imm64' 9712 Signed 64-bit immediate. 9713 97149.7.4.1 Arithmetic instructions 9715............................... 9716 9717The destination register in these instructions act like an accumulator. 9718 9719'add %d, (%s|imm32)' 9720 64-bit arithmetic addition. 9721'sub %d, (%s|imm32)' 9722 64-bit arithmetic subtraction. 9723'mul %d, (%s|imm32)' 9724 64-bit arithmetic multiplication. 9725'div %d, (%s|imm32)' 9726 64-bit arithmetic integer division. 9727'mod %d, (%s|imm32)' 9728 64-bit integer remainder. 9729'and %d, (%s|imm32)' 9730 64-bit bit-wise "and" operation. 9731'or %d, (%s|imm32)' 9732 64-bit bit-wise "or" operation. 9733'xor %d, (%s|imm32)' 9734 64-bit bit-wise exclusive-or operation. 9735'lsh %d, (%s|imm32)' 9736 64-bit left shift, by '%s' or 'imm32' bits. 9737'rsh %d, (%s|imm32)' 9738 64-bit right logical shift, by '%s' or 'imm32' bits. 9739'arsh %d, (%s|imm32)' 9740 64-bit right arithmetic shift, by '%s' or 'imm32' bits. 9741'neg %d' 9742 64-bit arithmetic negation. 9743'mov %d, (%s|imm32)' 9744 Move the 64-bit value of '%s' in '%d', or load 'imm32' in '%d'. 9745 97469.7.4.2 32-bit arithmetic instructions 9747...................................... 9748 9749The destination register in these instructions act as an accumulator. 9750 9751'add32 %d, (%s|imm32)' 9752 32-bit arithmetic addition. 9753'sub32 %d, (%s|imm32)' 9754 32-bit arithmetic subtraction. 9755'mul32 %d, (%s|imm32)' 9756 32-bit arithmetic multiplication. 9757'div32 %d, (%s|imm32)' 9758 32-bit arithmetic integer division. 9759'mod32 %d, (%s|imm32)' 9760 32-bit integer remainder. 9761'and32 %d, (%s|imm32)' 9762 32-bit bit-wise "and" operation. 9763'or32 %d, (%s|imm32)' 9764 32-bit bit-wise "or" operation. 9765'xor32 %d, (%s|imm32)' 9766 32-bit bit-wise exclusive-or operation. 9767'lsh32 %d, (%s|imm32)' 9768 32-bit left shift, by '%s' or 'imm32' bits. 9769'rsh32 %d, (%s|imm32)' 9770 32-bit right logical shift, by '%s' or 'imm32' bits. 9771'arsh32 %d, (%s|imm32)' 9772 32-bit right arithmetic shift, by '%s' or 'imm32' bits. 9773'neg32 %d' 9774 32-bit arithmetic negation. 9775'mov32 %d, (%s|imm32)' 9776 Move the 32-bit value of '%s' in '%d', or load 'imm32' in '%d'. 9777 97789.7.4.3 Endianness conversion instructions 9779.......................................... 9780 9781'endle %d, (8|16|32)' 9782 Convert the 8-bit, 16-bit or 32-bit value in '%d' to little-endian. 9783'endbe %d, (8|16|32)' 9784 Convert the 8-bit, 16-bit or 32-bit value in '%d' to big-endian. 9785 97869.7.4.4 64-bit load and pseudo maps 9787................................... 9788 9789'lddw %d, imm64' 9790 Load the given signed 64-bit immediate, or pseudo map descriptor, 9791 to the destination register '%d'. 9792'lddw %d, %map_fd(N)' 9793 Load the address of the given pseudo map fd _N_ to the destination 9794 register '%d'. 9795 97969.7.4.5 Load instructions for socket filters 9797............................................ 9798 9799The following instructions are intended to be used in socket filters, 9800and are therefore not general-purpose: they make assumptions on the 9801contents of several registers. See the file 9802'Documentation/networking/filter.txt' in the Linux kernel source tree 9803for more information. 9804 9805 Absolute loads: 9806 9807'ldabsdw imm32' 9808 Absolute 64-bit load. 9809'ldabsw imm32' 9810 Absolute 32-bit load. 9811'ldabsh imm32' 9812 Absolute 16-bit load. 9813'ldabsb imm32' 9814 Absolute 8-bit load. 9815 9816 Indirect loads: 9817 9818'ldinddw %s, imm32' 9819 Indirect 64-bit load. 9820'ldindw %s, imm32' 9821 Indirect 32-bit load. 9822'ldindh %s, imm32' 9823 Indirect 16-bit load. 9824'ldindb %s, imm32' 9825 Indirect 8-bit load. 9826 98279.7.4.6 Generic load/store instructions 9828....................................... 9829 9830General-purpose load and store instructions are provided for several 9831word sizes. 9832 9833 Load to register instructions: 9834 9835'ldxdw %d, [%s+offset16]' 9836 Generic 64-bit load. 9837'ldxw %d, [%s+offset16]' 9838 Generic 32-bit load. 9839'ldxh %d, [%s+offset16]' 9840 Generic 16-bit load. 9841'ldxb %d, [%s+offset16]' 9842 Generic 8-bit load. 9843 9844 Store from register instructions: 9845 9846'stxdw [%d+offset16], %s' 9847 Generic 64-bit store. 9848'stxw [%d+offset16], %s' 9849 Generic 32-bit store. 9850'stxh [%d+offset16], %s' 9851 Generic 16-bit store. 9852'stxb [%d+offset16], %s' 9853 Generic 8-bit store. 9854 9855 Store from immediates instructions: 9856 9857'stddw [%d+offset16], imm32' 9858 Store immediate as 64-bit. 9859'stdw [%d+offset16], imm32' 9860 Store immediate as 32-bit. 9861'stdh [%d+offset16], imm32' 9862 Store immediate as 16-bit. 9863'stdb [%d+offset16], imm32' 9864 Store immediate as 8-bit. 9865 98669.7.4.7 Jump instructions 9867......................... 9868 9869eBPF provides the following compare-and-jump instructions, which compare 9870the values of the two given registers, or the values of a register and 9871an immediate, and perform a branch in case the comparison holds true. 9872 9873'ja %d,(%s|imm32),disp16' 9874 Jump-always. 9875'jeq %d,(%s|imm32),disp16' 9876 Jump if equal. 9877'jgt %d,(%s|imm32),disp16' 9878 Jump if greater. 9879'jge %d,(%s|imm32),disp16' 9880 Jump if greater or equal. 9881'jlt %d,(%s|imm32),disp16' 9882 Jump if lesser. 9883'jle %d,(%s|imm32),disp16' 9884 Jump if lesser or equal. 9885'jset %d,(%s|imm32),disp16' 9886 Jump if signed equal. 9887'jne %d,(%s|imm32),disp16' 9888 Jump if not equal. 9889'jsgt %d,(%s|imm32),disp16' 9890 Jump if signed greater. 9891'jsge %d,(%s|imm32),disp16' 9892 Jump if signed greater or equal. 9893'jslt %d,(%s|imm32),disp16' 9894 Jump if signed lesser. 9895'jsle %d,(%s|imm32),disp16' 9896 Jump if signed lesser or equal. 9897 9898 A call instruction is provided in order to perform calls to other 9899eBPF functions, or to external kernel helpers: 9900 9901'call (disp32|imm32)' 9902 Jump and link to the offset _disp32_, or to the kernel helper 9903 function identified by _imm32_. 9904 9905 Finally: 9906 9907'exit' 9908 Terminate the eBPF program. 9909 99109.7.4.8 Atomic instructions 9911........................... 9912 9913Atomic exchange-and-add instructions are provided in two flavors: one 9914for swapping 64-bit quantities and another for 32-bit quantities. 9915 9916'xadddw [%d+offset16],%s' 9917 Exchange-and-add a 64-bit value at the specified location. 9918'xaddw [%d+offset16],%s' 9919 Exchange-and-add a 32-bit value at the specified location. 9920 9921 9922File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: BPF-Dependent, Up: Machine Dependencies 9923 99249.8 CR16 Dependent Features 9925=========================== 9926 9927* Menu: 9928 9929* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers 9930* CR16 Syntax:: Syntax for the CR16 9931 9932 9933File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent 9934 99359.8.1 CR16 Operand Qualifiers 9936----------------------------- 9937 9938The National Semiconductor CR16 target of 'as' has a few machine 9939dependent operand qualifiers. 9940 9941 Operand expression type qualifier is an optional field in the 9942instruction operand, to determines the type of the expression field of 9943an operand. The '@' is required. CR16 architecture uses one of the 9944following expression qualifiers: 9945 9946's' 9947 - 'Specifies expression operand type as small' 9948'm' 9949 - 'Specifies expression operand type as medium' 9950'l' 9951 - 'Specifies expression operand type as large' 9952'c' 9953 - 'Specifies the CR16 Assembler generates a relocation entry for 9954 the operand, where pc has implied bit, the expression is adjusted 9955 accordingly. The linker uses the relocation entry to update the 9956 operand address at link time.' 9957'got/GOT' 9958 - 'Specifies the CR16 Assembler generates a relocation entry for 9959 the operand, offset from Global Offset Table. The linker uses this 9960 relocation entry to update the operand address at link time' 9961'cgot/cGOT' 9962 - 'Specifies the CompactRISC Assembler generates a relocation entry 9963 for the operand, where pc has implied bit, the expression is 9964 adjusted accordingly. The linker uses the relocation entry to 9965 update the operand address at link time.' 9966 9967 CR16 target operand qualifiers and its size (in bits): 9968 9969'Immediate Operand: s' 9970 4 bits. 9971 9972'Immediate Operand: m' 9973 16 bits, for movb and movw instructions. 9974 9975'Immediate Operand: m' 9976 20 bits, movd instructions. 9977 9978'Immediate Operand: l' 9979 32 bits. 9980 9981'Absolute Operand: s' 9982 Illegal specifier for this operand. 9983 9984'Absolute Operand: m' 9985 20 bits, movd instructions. 9986 9987'Displacement Operand: s' 9988 8 bits. 9989 9990'Displacement Operand: m' 9991 16 bits. 9992 9993'Displacement Operand: l' 9994 24 bits. 9995 9996 For example: 9997 1 movw $_myfun@c,r1 9998 9999 This loads the address of _myfun, shifted right by 1, into r1. 10000 10001 2 movd $_myfun@c,(r2,r1) 10002 10003 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 10004 10005 3 _myfun_ptr: 10006 .long _myfun@c 10007 loadd _myfun_ptr, (r1,r0) 10008 jal (r1,r0) 10009 10010 This .long directive, the address of _myfunc, shifted right by 1 at link time. 10011 10012 4 loadd _data1@GOT(r12), (r1,r0) 10013 10014 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 10015 10016 5 loadd _myfunc@cGOT(r12), (r1,r0) 10017 10018 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. 10019 10020 10021File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent 10022 100239.8.2 CR16 Syntax 10024----------------- 10025 10026* Menu: 10027 10028* CR16-Chars:: Special Characters 10029 10030 10031File: as.info, Node: CR16-Chars, Up: CR16 Syntax 10032 100339.8.2.1 Special Characters 10034.......................... 10035 10036The presence of a '#' on a line indicates the start of a comment that 10037extends to the end of the current line. If the '#' appears as the first 10038character of a line, the whole line is treated as a comment, but in this 10039case the line can also be a logical line number directive (*note 10040Comments::) or a preprocessor control command (*note Preprocessing::). 10041 10042 The ';' character can be used to separate statements on the same 10043line. 10044 10045 10046File: as.info, Node: CRIS-Dependent, Next: C-SKY-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies 10047 100489.9 CRIS Dependent Features 10049=========================== 10050 10051* Menu: 10052 10053* CRIS-Opts:: Command-line Options 10054* CRIS-Expand:: Instruction expansion 10055* CRIS-Symbols:: Symbols 10056* CRIS-Syntax:: Syntax 10057 10058 10059File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 10060 100619.9.1 Command-line Options 10062-------------------------- 10063 10064The CRIS version of 'as' has these machine-dependent command-line 10065options. 10066 10067 The format of the generated object files can be either ELF or a.out, 10068specified by the command-line options '--emulation=crisaout' and 10069'--emulation=criself'. The default is ELF (criself), unless 'as' has 10070been configured specifically for a.out by using the configuration name 10071'cris-axis-aout'. 10072 10073 There are two different link-incompatible ELF object file variants 10074for CRIS, for use in environments where symbols are expected to be 10075prefixed by a leading '_' character and for environments without such a 10076symbol prefix. The variant used for GNU/Linux port has no symbol 10077prefix. Which variant to produce is specified by either of the options 10078'--underscore' and '--no-underscore'. The default is '--underscore'. 10079Since symbols in CRIS a.out objects are expected to have a '_' prefix, 10080specifying '--no-underscore' when generating a.out objects is an error. 10081Besides the object format difference, the effect of this option is to 10082parse register names differently (*note crisnous::). The 10083'--no-underscore' option makes a '$' register prefix mandatory. 10084 10085 The option '--pic' must be passed to 'as' in order to recognize the 10086symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note 10087crispic::). This will also affect expansion of instructions. The 10088expansion with '--pic' will use PC-relative rather than (slightly 10089faster) absolute addresses in those expansions. This option is only 10090valid when generating ELF format object files. 10091 10092 The option '--march=ARCHITECTURE' specifies the recognized 10093instruction set and recognized register names. It also controls the 10094architecture type of the object file. Valid values for ARCHITECTURE 10095are: 10096 10097'v0_v10' 10098 All instructions and register names for any architecture variant in 10099 the set v0...v10 are recognized. This is the default if the target 10100 is configured as cris-*. 10101 10102'v10' 10103 Only instructions and register names for CRIS v10 (as found in 10104 ETRAX 100 LX) are recognized. This is the default if the target is 10105 configured as crisv10-*. 10106 10107'v32' 10108 Only instructions and register names for CRIS v32 (code name 10109 Guinness) are recognized. This is the default if the target is 10110 configured as crisv32-*. This value implies '--no-mul-bug-abort'. 10111 (A subsequent '--mul-bug-abort' will turn it back on.) 10112 10113'common_v10_v32' 10114 Only instructions with register names and addressing modes with 10115 opcodes common to the v10 and v32 are recognized. 10116 10117 When '-N' is specified, 'as' will emit a warning when a 16-bit branch 10118instruction is expanded into a 32-bit multiple-instruction construct 10119(*note CRIS-Expand::). 10120 10121 Some versions of the CRIS v10, for example in the Etrax 100 LX, 10122contain a bug that causes destabilizing memory accesses when a multiply 10123instruction is executed with certain values in the first operand just 10124before a cache-miss. When the '--mul-bug-abort' command-line option is 10125active (the default value), 'as' will refuse to assemble a file 10126containing a multiply instruction at a dangerous offset, one that could 10127be the last on a cache-line, or is in a section with insufficient 10128alignment. This placement checking does not catch any case where the 10129multiply instruction is dangerously placed because it is located in a 10130delay-slot. The '--mul-bug-abort' command-line option turns off the 10131checking. 10132 10133 10134File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent 10135 101369.9.2 Instruction expansion 10137--------------------------- 10138 10139'as' will silently choose an instruction that fits the operand size for 10140'[register+constant]' operands. For example, the offset '127' in 10141'move.d [r3+127],r4' fits in an instruction using a signed-byte offset. 10142Similarly, 'move.d [r2+32767],r1' will generate an instruction using a 1014316-bit offset. For symbolic expressions and constants that do not fit 10144in 16 bits including the sign bit, a 32-bit offset is generated. 10145 10146 For branches, 'as' will expand from a 16-bit branch instruction into 10147a sequence of instructions that can reach a full 32-bit address. Since 10148this does not correspond to a single instruction, such expansions can 10149optionally be warned about. *Note CRIS-Opts::. 10150 10151 If the operand is found to fit the range, a 'lapc' mnemonic will 10152translate to a 'lapcq' instruction. Use 'lapc.d' to force the 32-bit 10153'lapc' instruction. 10154 10155 Similarly, the 'addo' mnemonic will translate to the shortest fitting 10156instruction of 'addoq', 'addo.w' and 'addo.d', when used with a operand 10157that is a constant known at assembly time. 10158 10159 10160File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent 10161 101629.9.3 Symbols 10163------------- 10164 10165Some symbols are defined by the assembler. They're intended to be used 10166in conditional assembly, for example: 10167 .if ..asm.arch.cris.v32 10168 CODE FOR CRIS V32 10169 .elseif ..asm.arch.cris.common_v10_v32 10170 CODE COMMON TO CRIS V32 AND CRIS V10 10171 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 10172 CODE FOR V10 10173 .else 10174 .error "Code needs to be added here." 10175 .endif 10176 10177 These symbols are defined in the assembler, reflecting command-line 10178options, either when specified or the default. They are always defined, 10179to 0 or 1. 10180 10181'..asm.arch.cris.any_v0_v10' 10182 This symbol is non-zero when '--march=v0_v10' is specified or the 10183 default. 10184 10185'..asm.arch.cris.common_v10_v32' 10186 Set according to the option '--march=common_v10_v32'. 10187 10188'..asm.arch.cris.v10' 10189 Reflects the option '--march=v10'. 10190 10191'..asm.arch.cris.v32' 10192 Corresponds to '--march=v10'. 10193 10194 Speaking of symbols, when a symbol is used in code, it can have a 10195suffix modifying its value for use in position-independent code. *Note 10196CRIS-Pic::. 10197 10198 10199File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent 10200 102019.9.4 Syntax 10202------------ 10203 10204There are different aspects of the CRIS assembly syntax. 10205 10206* Menu: 10207 10208* CRIS-Chars:: Special Characters 10209* CRIS-Pic:: Position-Independent Code Symbols 10210* CRIS-Regs:: Register Names 10211* CRIS-Pseudos:: Assembler Directives 10212 10213 10214File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 10215 102169.9.4.1 Special Characters 10217.......................... 10218 10219The character '#' is a line comment character. It starts a comment if 10220and only if it is placed at the beginning of a line. 10221 10222 A ';' character starts a comment anywhere on the line, causing all 10223characters up to the end of the line to be ignored. 10224 10225 A '@' character is handled as a line separator equivalent to a 10226logical new-line character (except in a comment), so separate 10227instructions can be specified on a single line. 10228 10229 10230File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax 10231 102329.9.4.2 Symbols in position-independent code 10233............................................ 10234 10235When generating position-independent code (SVR4 PIC) for use in 10236cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol 10237suffixes are used to specify what kind of run-time symbol lookup will be 10238used, expressed in the object as different _relocation types_. Usually, 10239all absolute symbol values must be located in a table, the _global 10240offset table_, leaving the code position-independent; independent of 10241values of global symbols and independent of the address of the code. 10242The suffix modifies the value of the symbol, into for example an index 10243into the global offset table where the real symbol value is entered, or 10244a PC-relative value, or a value relative to the start of the global 10245offset table. All symbol suffixes start with the character ':' (omitted 10246in the list below). Every symbol use in code or a read-only section 10247must therefore have a PIC suffix to enable a useful shared library to be 10248created. Usually, these constructs must not be used with an additive 10249constant offset as is usually allowed, i.e. no 4 as in 'symbol + 4' is 10250allowed. This restriction is checked at link-time, not at 10251assembly-time. 10252 10253'GOT' 10254 10255 Attaching this suffix to a symbol in an instruction causes the 10256 symbol to be entered into the global offset table. The value is a 10257 32-bit index for that symbol into the global offset table. The 10258 name of the corresponding relocation is 'R_CRIS_32_GOT'. Example: 10259 'move.d [$r0+extsym:GOT],$r9' 10260 10261'GOT16' 10262 10263 Same as for 'GOT', but the value is a 16-bit index into the global 10264 offset table. The corresponding relocation is 'R_CRIS_16_GOT'. 10265 Example: 'move.d [$r0+asymbol:GOT16],$r10' 10266 10267'PLT' 10268 10269 This suffix is used for function symbols. It causes a _procedure 10270 linkage table_, an array of code stubs, to be created at the time 10271 the shared object is created or linked against, together with a 10272 global offset table entry. The value is a pc-relative offset to 10273 the corresponding stub code in the procedure linkage table. This 10274 arrangement causes the run-time symbol resolver to be called to 10275 look up and set the value of the symbol the first time the function 10276 is called (at latest; depending environment variables). It is only 10277 safe to leave the symbol unresolved this way if all references are 10278 function calls. The name of the relocation is 10279 'R_CRIS_32_PLT_PCREL'. Example: 'add.d fnname:PLT,$pc' 10280 10281'PLTG' 10282 10283 Like PLT, but the value is relative to the beginning of the global 10284 offset table. The relocation is 'R_CRIS_32_PLT_GOTREL'. Example: 10285 'move.d fnname:PLTG,$r3' 10286 10287'GOTPLT' 10288 10289 Similar to 'PLT', but the value of the symbol is a 32-bit index 10290 into the global offset table. This is somewhat of a mix between 10291 the effect of the 'GOT' and the 'PLT' suffix; the difference to 10292 'GOT' is that there will be a procedure linkage table entry 10293 created, and that the symbol is assumed to be a function entry and 10294 will be resolved by the run-time resolver as with 'PLT'. The 10295 relocation is 'R_CRIS_32_GOTPLT'. Example: 'jsr 10296 [$r0+fnname:GOTPLT]' 10297 10298'GOTPLT16' 10299 10300 A variant of 'GOTPLT' giving a 16-bit value. Its relocation name 10301 is 'R_CRIS_16_GOTPLT'. Example: 'jsr [$r0+fnname:GOTPLT16]' 10302 10303'GOTOFF' 10304 10305 This suffix must only be attached to a local symbol, but may be 10306 used in an expression adding an offset. The value is the address 10307 of the symbol relative to the start of the global offset table. 10308 The relocation name is 'R_CRIS_32_GOTREL'. Example: 'move.d 10309 [$r0+localsym:GOTOFF],r3' 10310 10311 10312File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax 10313 103149.9.4.3 Register names 10315...................... 10316 10317A '$' character may always prefix a general or special register name in 10318an instruction operand but is mandatory when the option 10319'--no-underscore' is specified or when the '.syntax register_prefix' 10320directive is in effect (*note crisnous::). Register names are 10321case-insensitive. 10322 10323 10324File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax 10325 103269.9.4.4 Assembler Directives 10327............................ 10328 10329There are a few CRIS-specific pseudo-directives in addition to the 10330generic ones. *Note Pseudo Ops::. Constants emitted by 10331pseudo-directives are in little-endian order for CRIS. There is no 10332support for floating-point-specific directives for CRIS. 10333 10334'.dword EXPRESSIONS' 10335 10336 The '.dword' directive is a synonym for '.int', expecting zero or 10337 more EXPRESSIONS, separated by commas. For each expression, a 10338 32-bit little-endian constant is emitted. 10339 10340'.syntax ARGUMENT' 10341 The '.syntax' directive takes as ARGUMENT one of the following 10342 case-sensitive choices. 10343 10344 'no_register_prefix' 10345 10346 The '.syntax no_register_prefix' directive makes a '$' 10347 character prefix on all registers optional. It overrides a 10348 previous setting, including the corresponding effect of the 10349 option '--no-underscore'. If this directive is used when 10350 ordinary symbols do not have a '_' character prefix, care must 10351 be taken to avoid ambiguities whether an operand is a register 10352 or a symbol; using symbols with names the same as general or 10353 special registers then invoke undefined behavior. 10354 10355 'register_prefix' 10356 10357 This directive makes a '$' character prefix on all registers 10358 mandatory. It overrides a previous setting, including the 10359 corresponding effect of the option '--underscore'. 10360 10361 'leading_underscore' 10362 10363 This is an assertion directive, emitting an error if the 10364 '--no-underscore' option is in effect. 10365 10366 'no_leading_underscore' 10367 10368 This is the opposite of the '.syntax leading_underscore' 10369 directive and emits an error if the option '--underscore' is 10370 in effect. 10371 10372'.arch ARGUMENT' 10373 This is an assertion directive, giving an error if the specified 10374 ARGUMENT is not the same as the specified or default value for the 10375 '--march=ARCHITECTURE' option (*note march-option::). 10376 10377 10378File: as.info, Node: C-SKY-Dependent, Next: D10V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies 10379 103809.10 C-SKY Dependent Features 10381============================= 10382 10383* Menu: 10384 10385* C-SKY Options:: Options 10386* C-SKY Syntax:: Syntax 10387 10388 10389File: as.info, Node: C-SKY Options, Next: C-SKY Syntax, Up: C-SKY-Dependent 10390 103919.10.1 Options 10392-------------- 10393 10394'-march=ARCHNAME' 10395 Assemble for architecture ARCHNAME. The '--help' option lists 10396 valid values for ARCHNAME. 10397 10398'-mcpu=CPUNAME' 10399 Assemble for architecture CPUNAME. The '--help' option lists valid 10400 values for CPUNAME. 10401 10402'-EL' 10403'-mlittle-endian' 10404 Generate little-endian output. 10405 10406'-EB' 10407'-mbig-endian' 10408 Generate big-endian output. 10409 10410'-fpic' 10411'-pic' 10412 Generate position-independent code. 10413 10414'-mljump' 10415'-mno-ljump' 10416 Enable/disable transformation of the short branch instructions 10417 'jbf', 'jbt', and 'jbr' to 'jmpi'. This option is for V2 10418 processors only. It is ignored on CK801 and CK802 targets, which 10419 do not support the 'jmpi' instruction, and is enabled by default 10420 for other processors. 10421 10422'-mbranch-stub' 10423'-mno-branch-stub' 10424 Pass through 'R_CKCORE_PCREL_IMM26BY2' relocations for 'bsr' 10425 instructions to the linker. 10426 10427 This option is only available for bare-metal C-SKY V2 ELF targets, 10428 where it is enabled by default. It cannot be used in code that 10429 will be dynamically linked against shared libraries. 10430 10431'-force2bsr' 10432'-mforce2bsr' 10433'-no-force2bsr' 10434'-mno-force2bsr' 10435 Enable/disable transformation of 'jbsr' instructions to 'bsr'. 10436 This option is always enabled (and '-mno-force2bsr' is ignored) for 10437 CK801/CK802 targets. It is also always enabled when 10438 '-mbranch-stub' is in effect. 10439 10440'-jsri2bsr' 10441'-mjsri2bsr' 10442'-no-jsri2bsr' 10443'-mno-jsri2bsr' 10444 Enable/disable transformation of 'jsri' instructions to 'bsr'. 10445 This option is enabled by default. 10446 10447'-mnolrw' 10448'-mno-lrw' 10449 Enable/disable transformation of 'lrw' instructions into a 10450 'movih'/'ori' pair. 10451 10452'-melrw' 10453'-mno-elrw' 10454 Enable/disable extended 'lrw' instructions. This option is enabled 10455 by default for CK800-series processors. 10456 10457'-mlaf' 10458'-mliterals-after-func' 10459'-mno-laf' 10460'-mno-literals-after-func' 10461 Enable/disable placement of literal pools after each function. 10462 10463'-mlabr' 10464'-mliterals-after-br' 10465'-mno-labr' 10466'-mnoliterals-after-br' 10467 Enable/disable placement of literal pools after unconditional 10468 branches. This option is enabled by default. 10469 10470'-mistack' 10471'-mno-istack' 10472 Enable/disable interrupt stack instructions. This option is 10473 enabled by default on CK801, CK802, and CK802 processors. 10474 10475 The following options explicitly enable certain optional 10476instructions. These features are also enabled implicitly by using 10477'-mcpu=' to specify a processor that supports it. 10478 10479'-mhard-float' 10480 Enable hard float instructions. 10481 10482'-mmp' 10483 Enable multiprocessor instructions. 10484 10485'-mcp' 10486 Enable coprocessor instructions. 10487 10488'-mcache' 10489 Enable cache prefetch instruction. 10490 10491'-msecurity' 10492 Enable C-SKY security instructions. 10493 10494'-mtrust' 10495 Enable C-SKY trust instructions. 10496 10497'-mdsp' 10498 Enable DSP instructions. 10499 10500'-medsp' 10501 Enable enhanced DSP instructions. 10502 10503'-mvdsp' 10504 Enable vector DSP instructions. 10505 10506 10507File: as.info, Node: C-SKY Syntax, Prev: C-SKY Options, Up: C-SKY-Dependent 10508 105099.10.2 Syntax 10510------------- 10511 10512'as' implements the standard C-SKY assembler syntax documented in the 10513'C-SKY V2 CPU Applications Binary Interface Standards Manual'. 10514 10515 10516File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: C-SKY-Dependent, Up: Machine Dependencies 10517 105189.11 D10V Dependent Features 10519============================ 10520 10521* Menu: 10522 10523* D10V-Opts:: D10V Options 10524* D10V-Syntax:: Syntax 10525* D10V-Float:: Floating Point 10526* D10V-Opcodes:: Opcodes 10527 10528 10529File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 10530 105319.11.1 D10V Options 10532------------------- 10533 10534The Mitsubishi D10V version of 'as' has a few machine dependent options. 10535 10536'-O' 10537 The D10V can often execute two sub-instructions in parallel. When 10538 this option is used, 'as' will attempt to optimize its output by 10539 detecting when instructions can be executed in parallel. 10540'--nowarnswap' 10541 To optimize execution performance, 'as' will sometimes swap the 10542 order of instructions. Normally this generates a warning. When 10543 this option is used, no warning will be generated when instructions 10544 are swapped. 10545'--gstabs-packing' 10546'--no-gstabs-packing' 10547 'as' packs adjacent short instructions into a single packed 10548 instruction. '--no-gstabs-packing' turns instruction packing off 10549 if '--gstabs' is specified as well; '--gstabs-packing' (the 10550 default) turns instruction packing on even when '--gstabs' is 10551 specified. 10552 10553 10554File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent 10555 105569.11.2 Syntax 10557------------- 10558 10559The D10V syntax is based on the syntax in Mitsubishi's D10V architecture 10560manual. The differences are detailed below. 10561 10562* Menu: 10563 10564* D10V-Size:: Size Modifiers 10565* D10V-Subs:: Sub-Instructions 10566* D10V-Chars:: Special Characters 10567* D10V-Regs:: Register Names 10568* D10V-Addressing:: Addressing Modes 10569* D10V-Word:: @WORD Modifier 10570 10571 10572File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 10573 105749.11.2.1 Size Modifiers 10575....................... 10576 10577The D10V version of 'as' uses the instruction names in the D10V 10578Architecture Manual. However, the names in the manual are sometimes 10579ambiguous. There are instruction names that can assemble to a short or 10580long form opcode. How does the assembler pick the correct form? 'as' 10581will always pick the smallest form if it can. When dealing with a 10582symbol that is not defined yet when a line is being assembled, it will 10583always use the long form. If you need to force the assembler to use 10584either the short or long form of the instruction, you can append either 10585'.s' (short) or '.l' (long) to it. For example, if you are writing an 10586assembly program and you want to do a branch to a symbol that is defined 10587later in your program, you can write 'bra.s foo'. Objdump and GDB will 10588always append '.s' or '.l' to instructions which have both short and 10589long forms. 10590 10591 10592File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax 10593 105949.11.2.2 Sub-Instructions 10595......................... 10596 10597The D10V assembler takes as input a series of instructions, either 10598one-per-line, or in the special two-per-line format described in the 10599next section. Some of these instructions will be short-form or 10600sub-instructions. These sub-instructions can be packed into a single 10601instruction. The assembler will do this automatically. It will also 10602detect when it should not pack instructions. For example, when a label 10603is defined, the next instruction will never be packaged with the 10604previous one. Whenever a branch and link instruction is called, it will 10605not be packaged with the next instruction so the return address will be 10606valid. Nops are automatically inserted when necessary. 10607 10608 If you do not want the assembler automatically making these 10609decisions, you can control the packaging and execution type (parallel or 10610sequential) with the special execution symbols described in the next 10611section. 10612 10613 10614File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax 10615 106169.11.2.3 Special Characters 10617........................... 10618 10619A semicolon (';') can be used anywhere on a line to start a comment that 10620extends to the end of the line. 10621 10622 If a '#' appears as the first character of a line, the whole line is 10623treated as a comment, but in this case the line could also be a logical 10624line number directive (*note Comments::) or a preprocessor control 10625command (*note Preprocessing::). 10626 10627 Sub-instructions may be executed in order, in reverse-order, or in 10628parallel. Instructions listed in the standard one-per-line format will 10629be executed sequentially. To specify the executing order, use the 10630following symbols: 10631'->' 10632 Sequential with instruction on the left first. 10633'<-' 10634 Sequential with instruction on the right first. 10635'||' 10636 Parallel 10637 The D10V syntax allows either one instruction per line, one 10638instruction per line with the execution symbol, or two instructions per 10639line. For example 10640'abs a1 -> abs r0' 10641 Execute these sequentially. The instruction on the right is in the 10642 right container and is executed second. 10643'abs r0 <- abs a1' 10644 Execute these reverse-sequentially. The instruction on the right 10645 is in the right container, and is executed first. 10646'ld2w r2,@r8+ || mac a0,r0,r7' 10647 Execute these in parallel. 10648'ld2w r2,@r8+ ||' 10649'mac a0,r0,r7' 10650 Two-line format. Execute these in parallel. 10651'ld2w r2,@r8+' 10652'mac a0,r0,r7' 10653 Two-line format. Execute these sequentially. Assembler will put 10654 them in the proper containers. 10655'ld2w r2,@r8+ ->' 10656'mac a0,r0,r7' 10657 Two-line format. Execute these sequentially. Same as above but 10658 second instruction will always go into right container. 10659 Since '$' has no special meaning, you may use it in symbol names. 10660 10661 10662File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax 10663 106649.11.2.4 Register Names 10665....................... 10666 10667You can use the predefined symbols 'r0' through 'r15' to refer to the 10668D10V registers. You can also use 'sp' as an alias for 'r15'. The 10669accumulators are 'a0' and 'a1'. There are special register-pair names 10670that may optionally be used in opcodes that require even-numbered 10671registers. Register names are not case sensitive. 10672 10673 Register Pairs 10674'r0-r1' 10675'r2-r3' 10676'r4-r5' 10677'r6-r7' 10678'r8-r9' 10679'r10-r11' 10680'r12-r13' 10681'r14-r15' 10682 10683 The D10V also has predefined symbols for these control registers and 10684status bits: 10685'psw' 10686 Processor Status Word 10687'bpsw' 10688 Backup Processor Status Word 10689'pc' 10690 Program Counter 10691'bpc' 10692 Backup Program Counter 10693'rpt_c' 10694 Repeat Count 10695'rpt_s' 10696 Repeat Start address 10697'rpt_e' 10698 Repeat End address 10699'mod_s' 10700 Modulo Start address 10701'mod_e' 10702 Modulo End address 10703'iba' 10704 Instruction Break Address 10705'f0' 10706 Flag 0 10707'f1' 10708 Flag 1 10709'c' 10710 Carry flag 10711 10712 10713File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax 10714 107159.11.2.5 Addressing Modes 10716......................... 10717 10718'as' understands the following addressing modes for the D10V. 'RN' in 10719the following refers to any of the numbered registers, but _not_ the 10720control registers. 10721'RN' 10722 Register direct 10723'@RN' 10724 Register indirect 10725'@RN+' 10726 Register indirect with post-increment 10727'@RN-' 10728 Register indirect with post-decrement 10729'@-SP' 10730 Register indirect with pre-decrement 10731'@(DISP, RN)' 10732 Register indirect with displacement 10733'ADDR' 10734 PC relative address (for branch or rep). 10735'#IMM' 10736 Immediate data (the '#' is optional and ignored) 10737 10738 10739File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 10740 107419.11.2.6 @WORD Modifier 10742....................... 10743 10744Any symbol followed by '@word' will be replaced by the symbol's value 10745shifted right by 2. This is used in situations such as loading a 10746register with the address of a function (or any other code fragment). 10747For example, if you want to load a register with the location of the 10748function 'main' then jump to that function, you could do it as follows: 10749 ldi r2, main@word 10750 jmp r2 10751 10752 10753File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent 10754 107559.11.3 Floating Point 10756--------------------- 10757 10758The D10V has no hardware floating point, but the '.float' and '.double' 10759directives generates IEEE floating-point numbers for compatibility with 10760other development tools. 10761 10762 10763File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 10764 107659.11.4 Opcodes 10766-------------- 10767 10768For detailed information on the D10V machine instruction set, see 'D10V 10769Architecture: A VLIW Microprocessor for Multimedia Applications' 10770(Mitsubishi Electric Corp.). 'as' implements all the standard D10V 10771opcodes. The only changes are those described in the section on size 10772modifiers 10773 10774 10775File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies 10776 107779.12 D30V Dependent Features 10778============================ 10779 10780* Menu: 10781 10782* D30V-Opts:: D30V Options 10783* D30V-Syntax:: Syntax 10784* D30V-Float:: Floating Point 10785* D30V-Opcodes:: Opcodes 10786 10787 10788File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 10789 107909.12.1 D30V Options 10791------------------- 10792 10793The Mitsubishi D30V version of 'as' has a few machine dependent options. 10794 10795'-O' 10796 The D30V can often execute two sub-instructions in parallel. When 10797 this option is used, 'as' will attempt to optimize its output by 10798 detecting when instructions can be executed in parallel. 10799 10800'-n' 10801 When this option is used, 'as' will issue a warning every time it 10802 adds a nop instruction. 10803 10804'-N' 10805 When this option is used, 'as' will issue a warning if it needs to 10806 insert a nop after a 32-bit multiply before a load or 16-bit 10807 multiply instruction. 10808 10809 10810File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent 10811 108129.12.2 Syntax 10813------------- 10814 10815The D30V syntax is based on the syntax in Mitsubishi's D30V architecture 10816manual. The differences are detailed below. 10817 10818* Menu: 10819 10820* D30V-Size:: Size Modifiers 10821* D30V-Subs:: Sub-Instructions 10822* D30V-Chars:: Special Characters 10823* D30V-Guarded:: Guarded Execution 10824* D30V-Regs:: Register Names 10825* D30V-Addressing:: Addressing Modes 10826 10827 10828File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 10829 108309.12.2.1 Size Modifiers 10831....................... 10832 10833The D30V version of 'as' uses the instruction names in the D30V 10834Architecture Manual. However, the names in the manual are sometimes 10835ambiguous. There are instruction names that can assemble to a short or 10836long form opcode. How does the assembler pick the correct form? 'as' 10837will always pick the smallest form if it can. When dealing with a 10838symbol that is not defined yet when a line is being assembled, it will 10839always use the long form. If you need to force the assembler to use 10840either the short or long form of the instruction, you can append either 10841'.s' (short) or '.l' (long) to it. For example, if you are writing an 10842assembly program and you want to do a branch to a symbol that is defined 10843later in your program, you can write 'bra.s foo'. Objdump and GDB will 10844always append '.s' or '.l' to instructions which have both short and 10845long forms. 10846 10847 10848File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax 10849 108509.12.2.2 Sub-Instructions 10851......................... 10852 10853The D30V assembler takes as input a series of instructions, either 10854one-per-line, or in the special two-per-line format described in the 10855next section. Some of these instructions will be short-form or 10856sub-instructions. These sub-instructions can be packed into a single 10857instruction. The assembler will do this automatically. It will also 10858detect when it should not pack instructions. For example, when a label 10859is defined, the next instruction will never be packaged with the 10860previous one. Whenever a branch and link instruction is called, it will 10861not be packaged with the next instruction so the return address will be 10862valid. Nops are automatically inserted when necessary. 10863 10864 If you do not want the assembler automatically making these 10865decisions, you can control the packaging and execution type (parallel or 10866sequential) with the special execution symbols described in the next 10867section. 10868 10869 10870File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax 10871 108729.12.2.3 Special Characters 10873........................... 10874 10875A semicolon (';') can be used anywhere on a line to start a comment that 10876extends to the end of the line. 10877 10878 If a '#' appears as the first character of a line, the whole line is 10879treated as a comment, but in this case the line could also be a logical 10880line number directive (*note Comments::) or a preprocessor control 10881command (*note Preprocessing::). 10882 10883 Sub-instructions may be executed in order, in reverse-order, or in 10884parallel. Instructions listed in the standard one-per-line format will 10885be executed sequentially unless you use the '-O' option. 10886 10887 To specify the executing order, use the following symbols: 10888'->' 10889 Sequential with instruction on the left first. 10890 10891'<-' 10892 Sequential with instruction on the right first. 10893 10894'||' 10895 Parallel 10896 10897 The D30V syntax allows either one instruction per line, one 10898instruction per line with the execution symbol, or two instructions per 10899line. For example 10900'abs r2,r3 -> abs r4,r5' 10901 Execute these sequentially. The instruction on the right is in the 10902 right container and is executed second. 10903 10904'abs r2,r3 <- abs r4,r5' 10905 Execute these reverse-sequentially. The instruction on the right 10906 is in the right container, and is executed first. 10907 10908'abs r2,r3 || abs r4,r5' 10909 Execute these in parallel. 10910 10911'ldw r2,@(r3,r4) ||' 10912'mulx r6,r8,r9' 10913 Two-line format. Execute these in parallel. 10914 10915'mulx a0,r8,r9' 10916'stw r2,@(r3,r4)' 10917 Two-line format. Execute these sequentially unless '-O' option is 10918 used. If the '-O' option is used, the assembler will determine if 10919 the instructions could be done in parallel (the above two 10920 instructions can be done in parallel), and if so, emit them as 10921 parallel instructions. The assembler will put them in the proper 10922 containers. In the above example, the assembler will put the 'stw' 10923 instruction in left container and the 'mulx' instruction in the 10924 right container. 10925 10926'stw r2,@(r3,r4) ->' 10927'mulx a0,r8,r9' 10928 Two-line format. Execute the 'stw' instruction followed by the 10929 'mulx' instruction sequentially. The first instruction goes in the 10930 left container and the second instruction goes into right 10931 container. The assembler will give an error if the machine 10932 ordering constraints are violated. 10933 10934'stw r2,@(r3,r4) <-' 10935'mulx a0,r8,r9' 10936 Same as previous example, except that the 'mulx' instruction is 10937 executed before the 'stw' instruction. 10938 10939 Since '$' has no special meaning, you may use it in symbol names. 10940 10941 10942File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax 10943 109449.12.2.4 Guarded Execution 10945.......................... 10946 10947'as' supports the full range of guarded execution directives for each 10948instruction. Just append the directive after the instruction proper. 10949The directives are: 10950 10951'/tx' 10952 Execute the instruction if flag f0 is true. 10953'/fx' 10954 Execute the instruction if flag f0 is false. 10955'/xt' 10956 Execute the instruction if flag f1 is true. 10957'/xf' 10958 Execute the instruction if flag f1 is false. 10959'/tt' 10960 Execute the instruction if both flags f0 and f1 are true. 10961'/tf' 10962 Execute the instruction if flag f0 is true and flag f1 is false. 10963 10964 10965File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax 10966 109679.12.2.5 Register Names 10968....................... 10969 10970You can use the predefined symbols 'r0' through 'r63' to refer to the 10971D30V registers. You can also use 'sp' as an alias for 'r63' and 'link' 10972as an alias for 'r62'. The accumulators are 'a0' and 'a1'. 10973 10974 The D30V also has predefined symbols for these control registers and 10975status bits: 10976'psw' 10977 Processor Status Word 10978'bpsw' 10979 Backup Processor Status Word 10980'pc' 10981 Program Counter 10982'bpc' 10983 Backup Program Counter 10984'rpt_c' 10985 Repeat Count 10986'rpt_s' 10987 Repeat Start address 10988'rpt_e' 10989 Repeat End address 10990'mod_s' 10991 Modulo Start address 10992'mod_e' 10993 Modulo End address 10994'iba' 10995 Instruction Break Address 10996'f0' 10997 Flag 0 10998'f1' 10999 Flag 1 11000'f2' 11001 Flag 2 11002'f3' 11003 Flag 3 11004'f4' 11005 Flag 4 11006'f5' 11007 Flag 5 11008'f6' 11009 Flag 6 11010'f7' 11011 Flag 7 11012's' 11013 Same as flag 4 (saturation flag) 11014'v' 11015 Same as flag 5 (overflow flag) 11016'va' 11017 Same as flag 6 (sticky overflow flag) 11018'c' 11019 Same as flag 7 (carry/borrow flag) 11020'b' 11021 Same as flag 7 (carry/borrow flag) 11022 11023 11024File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 11025 110269.12.2.6 Addressing Modes 11027......................... 11028 11029'as' understands the following addressing modes for the D30V. 'RN' in 11030the following refers to any of the numbered registers, but _not_ the 11031control registers. 11032'RN' 11033 Register direct 11034'@RN' 11035 Register indirect 11036'@RN+' 11037 Register indirect with post-increment 11038'@RN-' 11039 Register indirect with post-decrement 11040'@-SP' 11041 Register indirect with pre-decrement 11042'@(DISP, RN)' 11043 Register indirect with displacement 11044'ADDR' 11045 PC relative address (for branch or rep). 11046'#IMM' 11047 Immediate data (the '#' is optional and ignored) 11048 11049 11050File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent 11051 110529.12.3 Floating Point 11053--------------------- 11054 11055The D30V has no hardware floating point, but the '.float' and '.double' 11056directives generates IEEE floating-point numbers for compatibility with 11057other development tools. 11058 11059 11060File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 11061 110629.12.4 Opcodes 11063-------------- 11064 11065For detailed information on the D30V machine instruction set, see 'D30V 11066Architecture: A VLIW Microprocessor for Multimedia Applications' 11067(Mitsubishi Electric Corp.). 'as' implements all the standard D30V 11068opcodes. The only changes are those described in the section on size 11069modifiers 11070 11071 11072File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies 11073 110749.13 Epiphany Dependent Features 11075================================ 11076 11077* Menu: 11078 11079* Epiphany Options:: Options 11080* Epiphany Syntax:: Epiphany Syntax 11081 11082 11083File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent 11084 110859.13.1 Options 11086-------------- 11087 11088'as' has two additional command-line options for the Epiphany 11089architecture. 11090 11091'-mepiphany' 11092 Specifies that the both 32 and 16 bit instructions are allowed. 11093 This is the default behavior. 11094 11095'-mepiphany16' 11096 Restricts the permitted instructions to just the 16 bit set. 11097 11098 11099File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent 11100 111019.13.2 Epiphany Syntax 11102---------------------- 11103 11104* Menu: 11105 11106* Epiphany-Chars:: Special Characters 11107 11108 11109File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax 11110 111119.13.2.1 Special Characters 11112........................... 11113 11114The presence of a ';' on a line indicates the start of a comment that 11115extends to the end of the current line. 11116 11117 If a '#' appears as the first character of a line then the whole line 11118is treated as a comment, but in this case the line could also be a 11119logical line number directive (*note Comments::) or a preprocessor 11120control command (*note Preprocessing::). 11121 11122 The '`' character can be used to separate statements on the same 11123line. 11124 11125 11126File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies 11127 111289.14 H8/300 Dependent Features 11129============================== 11130 11131* Menu: 11132 11133* H8/300 Options:: Options 11134* H8/300 Syntax:: Syntax 11135* H8/300 Floating Point:: Floating Point 11136* H8/300 Directives:: H8/300 Machine Directives 11137* H8/300 Opcodes:: Opcodes 11138 11139 11140File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent 11141 111429.14.1 Options 11143-------------- 11144 11145The Renesas H8/300 version of 'as' has one machine-dependent option: 11146 11147'-h-tick-hex' 11148 Support H'00 style hex constants in addition to 0x00 style. 11149 11150'-mach=NAME' 11151 Sets the H8300 machine variant. The following machine names are 11152 recognised: 'h8300h', 'h8300hn', 'h8300s', 'h8300sn', 'h8300sx' and 11153 'h8300sxn'. 11154 11155 11156File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent 11157 111589.14.2 Syntax 11159------------- 11160 11161* Menu: 11162 11163* H8/300-Chars:: Special Characters 11164* H8/300-Regs:: Register Names 11165* H8/300-Addressing:: Addressing Modes 11166 11167 11168File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 11169 111709.14.2.1 Special Characters 11171........................... 11172 11173';' is the line comment character. 11174 11175 '$' can be used instead of a newline to separate statements. 11176Therefore _you may not use '$' in symbol names_ on the H8/300. 11177 11178 11179File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax 11180 111819.14.2.2 Register Names 11182....................... 11183 11184You can use predefined symbols of the form 'rNh' and 'rNl' to refer to 11185the H8/300 registers as sixteen 8-bit general-purpose registers. N is a 11186digit from '0' to '7'); for instance, both 'r0h' and 'r7l' are valid 11187register names. 11188 11189 You can also use the eight predefined symbols 'rN' to refer to the 11190H8/300 registers as 16-bit registers (you must use this form for 11191addressing). 11192 11193 On the H8/300H, you can also use the eight predefined symbols 'erN' 11194('er0' ... 'er7') to refer to the 32-bit general purpose registers. 11195 11196 The two control registers are called 'pc' (program counter; a 16-bit 11197register, except on the H8/300H where it is 24 bits) and 'ccr' 11198(condition code register; an 8-bit register). 'r7' is used as the stack 11199pointer, and can also be called 'sp'. 11200 11201 11202File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax 11203 112049.14.2.3 Addressing Modes 11205......................... 11206 11207as understands the following addressing modes for the H8/300: 11208'rN' 11209 Register direct 11210 11211'@rN' 11212 Register indirect 11213 11214'@(D, rN)' 11215'@(D:16, rN)' 11216'@(D:24, rN)' 11217 Register indirect: 16-bit or 24-bit displacement D from register N. 11218 (24-bit displacements are only meaningful on the H8/300H.) 11219 11220'@rN+' 11221 Register indirect with post-increment 11222 11223'@-rN' 11224 Register indirect with pre-decrement 11225 11226'@AA' 11227'@AA:8' 11228'@AA:16' 11229'@AA:24' 11230 Absolute address 'aa'. (The address size ':24' only makes sense on 11231 the H8/300H.) 11232 11233'#XX' 11234'#XX:8' 11235'#XX:16' 11236'#XX:32' 11237 Immediate data XX. You may specify the ':8', ':16', or ':32' for 11238 clarity, if you wish; but 'as' neither requires this nor uses 11239 it--the data size required is taken from context. 11240 11241'@@AA' 11242'@@AA:8' 11243 Memory indirect. You may specify the ':8' for clarity, if you 11244 wish; but 'as' neither requires this nor uses it. 11245 11246 11247File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent 11248 112499.14.3 Floating Point 11250--------------------- 11251 11252The H8/300 family has no hardware floating point, but the '.float' 11253directive generates IEEE floating-point numbers for compatibility with 11254other development tools. 11255 11256 11257File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent 11258 112599.14.4 H8/300 Machine Directives 11260-------------------------------- 11261 11262'as' has the following machine-dependent directives for the H8/300: 11263 11264'.h8300h' 11265 Recognize and emit additional instructions for the H8/300H variant, 11266 and also make '.int' emit 32-bit numbers rather than the usual 11267 (16-bit) for the H8/300 family. 11268 11269'.h8300s' 11270 Recognize and emit additional instructions for the H8S variant, and 11271 also make '.int' emit 32-bit numbers rather than the usual (16-bit) 11272 for the H8/300 family. 11273 11274'.h8300hn' 11275 Recognize and emit additional instructions for the H8/300H variant 11276 in normal mode, and also make '.int' emit 32-bit numbers rather 11277 than the usual (16-bit) for the H8/300 family. 11278 11279'.h8300sn' 11280 Recognize and emit additional instructions for the H8S variant in 11281 normal mode, and also make '.int' emit 32-bit numbers rather than 11282 the usual (16-bit) for the H8/300 family. 11283 11284 On the H8/300 family (including the H8/300H) '.word' directives 11285generate 16-bit numbers. 11286 11287 11288File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent 11289 112909.14.5 Opcodes 11291-------------- 11292 11293For detailed information on the H8/300 machine instruction set, see 11294'H8/300 Series Programming Manual'. For information specific to the 11295H8/300H, see 'H8/300H Series Programming Manual' (Renesas). 11296 11297 'as' implements all the standard H8/300 opcodes. No additional 11298pseudo-instructions are needed on this family. 11299 11300 The following table summarizes the H8/300 opcodes, and their 11301arguments. Entries marked '*' are opcodes used only on the H8/300H. 11302 11303 Legend: 11304 Rs source register 11305 Rd destination register 11306 abs absolute address 11307 imm immediate data 11308 disp:N N-bit displacement from a register 11309 pcrel:N N-bit displacement relative to program counter 11310 11311 add.b #imm,rd * andc #imm,ccr 11312 add.b rs,rd band #imm,rd 11313 add.w rs,rd band #imm,@rd 11314 * add.w #imm,rd band #imm,@abs:8 11315 * add.l rs,rd bra pcrel:8 11316 * add.l #imm,rd * bra pcrel:16 11317 adds #imm,rd bt pcrel:8 11318 addx #imm,rd * bt pcrel:16 11319 addx rs,rd brn pcrel:8 11320 and.b #imm,rd * brn pcrel:16 11321 and.b rs,rd bf pcrel:8 11322 * and.w rs,rd * bf pcrel:16 11323 * and.w #imm,rd bhi pcrel:8 11324 * and.l #imm,rd * bhi pcrel:16 11325 * and.l rs,rd bls pcrel:8 11326 * bls pcrel:16 bld #imm,rd 11327 bcc pcrel:8 bld #imm,@rd 11328 * bcc pcrel:16 bld #imm,@abs:8 11329 bhs pcrel:8 bnot #imm,rd 11330 * bhs pcrel:16 bnot #imm,@rd 11331 bcs pcrel:8 bnot #imm,@abs:8 11332 * bcs pcrel:16 bnot rs,rd 11333 blo pcrel:8 bnot rs,@rd 11334 * blo pcrel:16 bnot rs,@abs:8 11335 bne pcrel:8 bor #imm,rd 11336 * bne pcrel:16 bor #imm,@rd 11337 beq pcrel:8 bor #imm,@abs:8 11338 * beq pcrel:16 bset #imm,rd 11339 bvc pcrel:8 bset #imm,@rd 11340 * bvc pcrel:16 bset #imm,@abs:8 11341 bvs pcrel:8 bset rs,rd 11342 * bvs pcrel:16 bset rs,@rd 11343 bpl pcrel:8 bset rs,@abs:8 11344 * bpl pcrel:16 bsr pcrel:8 11345 bmi pcrel:8 bsr pcrel:16 11346 * bmi pcrel:16 bst #imm,rd 11347 bge pcrel:8 bst #imm,@rd 11348 * bge pcrel:16 bst #imm,@abs:8 11349 blt pcrel:8 btst #imm,rd 11350 * blt pcrel:16 btst #imm,@rd 11351 bgt pcrel:8 btst #imm,@abs:8 11352 * bgt pcrel:16 btst rs,rd 11353 ble pcrel:8 btst rs,@rd 11354 * ble pcrel:16 btst rs,@abs:8 11355 bclr #imm,rd bxor #imm,rd 11356 bclr #imm,@rd bxor #imm,@rd 11357 bclr #imm,@abs:8 bxor #imm,@abs:8 11358 bclr rs,rd cmp.b #imm,rd 11359 bclr rs,@rd cmp.b rs,rd 11360 bclr rs,@abs:8 cmp.w rs,rd 11361 biand #imm,rd cmp.w rs,rd 11362 biand #imm,@rd * cmp.w #imm,rd 11363 biand #imm,@abs:8 * cmp.l #imm,rd 11364 bild #imm,rd * cmp.l rs,rd 11365 bild #imm,@rd daa rs 11366 bild #imm,@abs:8 das rs 11367 bior #imm,rd dec.b rs 11368 bior #imm,@rd * dec.w #imm,rd 11369 bior #imm,@abs:8 * dec.l #imm,rd 11370 bist #imm,rd divxu.b rs,rd 11371 bist #imm,@rd * divxu.w rs,rd 11372 bist #imm,@abs:8 * divxs.b rs,rd 11373 bixor #imm,rd * divxs.w rs,rd 11374 bixor #imm,@rd eepmov 11375 bixor #imm,@abs:8 * eepmovw 11376 * exts.w rd mov.w rs,@abs:16 11377 * exts.l rd * mov.l #imm,rd 11378 * extu.w rd * mov.l rs,rd 11379 * extu.l rd * mov.l @rs,rd 11380 inc rs * mov.l @(disp:16,rs),rd 11381 * inc.w #imm,rd * mov.l @(disp:24,rs),rd 11382 * inc.l #imm,rd * mov.l @rs+,rd 11383 jmp @rs * mov.l @abs:16,rd 11384 jmp abs * mov.l @abs:24,rd 11385 jmp @@abs:8 * mov.l rs,@rd 11386 jsr @rs * mov.l rs,@(disp:16,rd) 11387 jsr abs * mov.l rs,@(disp:24,rd) 11388 jsr @@abs:8 * mov.l rs,@-rd 11389 ldc #imm,ccr * mov.l rs,@abs:16 11390 ldc rs,ccr * mov.l rs,@abs:24 11391 * ldc @abs:16,ccr movfpe @abs:16,rd 11392 * ldc @abs:24,ccr movtpe rs,@abs:16 11393 * ldc @(disp:16,rs),ccr mulxu.b rs,rd 11394 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd 11395 * ldc @rs+,ccr * mulxs.b rs,rd 11396 * ldc @rs,ccr * mulxs.w rs,rd 11397 * mov.b @(disp:24,rs),rd neg.b rs 11398 * mov.b rs,@(disp:24,rd) * neg.w rs 11399 mov.b @abs:16,rd * neg.l rs 11400 mov.b rs,rd nop 11401 mov.b @abs:8,rd not.b rs 11402 mov.b rs,@abs:8 * not.w rs 11403 mov.b rs,rd * not.l rs 11404 mov.b #imm,rd or.b #imm,rd 11405 mov.b @rs,rd or.b rs,rd 11406 mov.b @(disp:16,rs),rd * or.w #imm,rd 11407 mov.b @rs+,rd * or.w rs,rd 11408 mov.b @abs:8,rd * or.l #imm,rd 11409 mov.b rs,@rd * or.l rs,rd 11410 mov.b rs,@(disp:16,rd) orc #imm,ccr 11411 mov.b rs,@-rd pop.w rs 11412 mov.b rs,@abs:8 * pop.l rs 11413 mov.w rs,@rd push.w rs 11414 * mov.w @(disp:24,rs),rd * push.l rs 11415 * mov.w rs,@(disp:24,rd) rotl.b rs 11416 * mov.w @abs:24,rd * rotl.w rs 11417 * mov.w rs,@abs:24 * rotl.l rs 11418 mov.w rs,rd rotr.b rs 11419 mov.w #imm,rd * rotr.w rs 11420 mov.w @rs,rd * rotr.l rs 11421 mov.w @(disp:16,rs),rd rotxl.b rs 11422 mov.w @rs+,rd * rotxl.w rs 11423 mov.w @abs:16,rd * rotxl.l rs 11424 mov.w rs,@(disp:16,rd) rotxr.b rs 11425 mov.w rs,@-rd * rotxr.w rs 11426 * rotxr.l rs * stc ccr,@(disp:24,rd) 11427 bpt * stc ccr,@-rd 11428 rte * stc ccr,@abs:16 11429 rts * stc ccr,@abs:24 11430 shal.b rs sub.b rs,rd 11431 * shal.w rs sub.w rs,rd 11432 * shal.l rs * sub.w #imm,rd 11433 shar.b rs * sub.l rs,rd 11434 * shar.w rs * sub.l #imm,rd 11435 * shar.l rs subs #imm,rd 11436 shll.b rs subx #imm,rd 11437 * shll.w rs subx rs,rd 11438 * shll.l rs * trapa #imm 11439 shlr.b rs xor #imm,rd 11440 * shlr.w rs xor rs,rd 11441 * shlr.l rs * xor.w #imm,rd 11442 sleep * xor.w rs,rd 11443 stc ccr,rd * xor.l #imm,rd 11444 * stc ccr,@rs * xor.l rs,rd 11445 * stc ccr,@(disp:16,rd) xorc #imm,ccr 11446 11447 Four H8/300 instructions ('add', 'cmp', 'mov', 'sub') are defined 11448with variants using the suffixes '.b', '.w', and '.l' to specify the 11449size of a memory operand. 'as' supports these suffixes, but does not 11450require them; since one of the operands is always a register, 'as' can 11451deduce the correct size. 11452 11453 For example, since 'r0' refers to a 16-bit register, 11454 mov r0,@foo 11455is equivalent to 11456 mov.w r0,@foo 11457 11458 If you use the size suffixes, 'as' issues a warning when the suffix 11459and the register size do not match. 11460 11461 11462File: as.info, Node: HPPA-Dependent, Next: i386-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies 11463 114649.15 HPPA Dependent Features 11465============================ 11466 11467* Menu: 11468 11469* HPPA Notes:: Notes 11470* HPPA Options:: Options 11471* HPPA Syntax:: Syntax 11472* HPPA Floating Point:: Floating Point 11473* HPPA Directives:: HPPA Machine Directives 11474* HPPA Opcodes:: Opcodes 11475 11476 11477File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 11478 114799.15.1 Notes 11480------------ 11481 11482As a back end for GNU CC 'as' has been thoroughly tested and should work 11483extremely well. We have tested it only minimally on hand written 11484assembly code and no one has tested it much on the assembly output from 11485the HP compilers. 11486 11487 The format of the debugging sections has changed since the original 11488'as' port (version 1.3X) was released; therefore, you must rebuild all 11489HPPA objects and libraries with the new assembler so that you can debug 11490the final executable. 11491 11492 The HPPA 'as' port generates a small subset of the relocations 11493available in the SOM and ELF object file formats. Additional relocation 11494support will be added as it becomes necessary. 11495 11496 11497File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent 11498 114999.15.2 Options 11500-------------- 11501 11502'as' has no machine-dependent command-line options for the HPPA. 11503 11504 11505File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent 11506 115079.15.3 Syntax 11508------------- 11509 11510The assembler syntax closely follows the HPPA instruction set reference 11511manual; assembler directives and general syntax closely follow the HPPA 11512assembly language reference manual, with a few noteworthy differences. 11513 11514 First, a colon may immediately follow a label definition. This is 11515simply for compatibility with how most assembly language programmers 11516write code. 11517 11518 Some obscure expression parsing problems may affect hand written code 11519which uses the 'spop' instructions, or code which makes significant use 11520of the '!' line separator. 11521 11522 'as' is much less forgiving about missing arguments and other similar 11523oversights than the HP assembler. 'as' notifies you of missing 11524arguments as syntax errors; this is regarded as a feature, not a bug. 11525 11526 Finally, 'as' allows you to use an external symbol without explicitly 11527importing the symbol. _Warning:_ in the future this will be an error 11528for HPPA targets. 11529 11530 Special characters for HPPA targets include: 11531 11532 ';' is the line comment character. 11533 11534 '!' can be used instead of a newline to separate statements. 11535 11536 Since '$' has no special meaning, you may use it in symbol names. 11537 11538 11539File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent 11540 115419.15.4 Floating Point 11542--------------------- 11543 11544The HPPA family uses IEEE floating-point numbers. 11545 11546 11547File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent 11548 115499.15.5 HPPA Assembler Directives 11550-------------------------------- 11551 11552'as' for the HPPA supports many additional directives for compatibility 11553with the native assembler. This section describes them only briefly. 11554For detailed information on HPPA-specific assembler directives, see 11555'HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). 11556 11557 'as' does _not_ support the following assembler directives described 11558in the HP manual: 11559 11560 .endm .liston 11561 .enter .locct 11562 .leave .macro 11563 .listoff 11564 11565 Beyond those implemented for compatibility, 'as' supports one 11566additional assembler directive for the HPPA: '.param'. It conveys 11567register argument locations for static functions. Its syntax closely 11568follows the '.export' directive. 11569 11570 These are the additional directives in 'as' for the HPPA: 11571 11572'.block N' 11573'.blockz N' 11574 Reserve N bytes of storage, and initialize them to zero. 11575 11576'.call' 11577 Mark the beginning of a procedure call. Only the special case with 11578 _no arguments_ is allowed. 11579 11580'.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' 11581 Specify a number of parameters and flags that define the 11582 environment for a procedure. 11583 11584 PARAM may be any of 'frame' (frame size), 'entry_gr' (end of 11585 general register range), 'entry_fr' (end of float register range), 11586 'entry_sr' (end of space register range). 11587 11588 The values for FLAG are 'calls' or 'caller' (proc has subroutines), 11589 'no_calls' (proc does not call subroutines), 'save_rp' (preserve 11590 return pointer), 'save_sp' (proc preserves stack pointer), 11591 'no_unwind' (do not unwind this proc), 'hpux_int' (proc is 11592 interrupt routine). 11593 11594'.code' 11595 Assemble into the standard section called '$TEXT$', subsection 11596 '$CODE$'. 11597 11598'.copyright "STRING"' 11599 In the SOM object format, insert STRING into the object code, 11600 marked as a copyright string. 11601 11602'.copyright "STRING"' 11603 In the ELF object format, insert STRING into the object code, 11604 marked as a version string. 11605 11606'.enter' 11607 Not yet supported; the assembler rejects programs containing this 11608 directive. 11609 11610'.entry' 11611 Mark the beginning of a procedure. 11612 11613'.exit' 11614 Mark the end of a procedure. 11615 11616'.export NAME [ ,TYP ] [ ,PARAM=R ]' 11617 Make a procedure NAME available to callers. TYP, if present, must 11618 be one of 'absolute', 'code' (ELF only, not SOM), 'data', 'entry', 11619 'data', 'entry', 'millicode', 'plabel', 'pri_prog', or 'sec_prog'. 11620 11621 PARAM, if present, provides either relocation information for the 11622 procedure arguments and result, or a privilege level. PARAM may be 11623 'argwN' (where N ranges from '0' to '3', and indicates one of four 11624 one-word arguments); 'rtnval' (the procedure's result); or 11625 'priv_lev' (privilege level). For arguments or the result, R 11626 specifies how to relocate, and must be one of 'no' (not 11627 relocatable), 'gr' (argument is in general register), 'fr' (in 11628 floating point register), or 'fu' (upper half of float register). 11629 For 'priv_lev', R is an integer. 11630 11631'.half N' 11632 Define a two-byte integer constant N; synonym for the portable 'as' 11633 directive '.short'. 11634 11635'.import NAME [ ,TYP ]' 11636 Converse of '.export'; make a procedure available to call. The 11637 arguments use the same conventions as the first two arguments for 11638 '.export'. 11639 11640'.label NAME' 11641 Define NAME as a label for the current assembly location. 11642 11643'.leave' 11644 Not yet supported; the assembler rejects programs containing this 11645 directive. 11646 11647'.origin LC' 11648 Advance location counter to LC. Synonym for the 'as' portable 11649 directive '.org'. 11650 11651'.param NAME [ ,TYP ] [ ,PARAM=R ]' 11652 Similar to '.export', but used for static procedures. 11653 11654'.proc' 11655 Use preceding the first statement of a procedure. 11656 11657'.procend' 11658 Use following the last statement of a procedure. 11659 11660'LABEL .reg EXPR' 11661 Synonym for '.equ'; define LABEL with the absolute expression EXPR 11662 as its value. 11663 11664'.space SECNAME [ ,PARAMS ]' 11665 Switch to section SECNAME, creating a new section by that name if 11666 necessary. You may only use PARAMS when creating a new section, 11667 not when switching to an existing one. SECNAME may identify a 11668 section by number rather than by name. 11669 11670 If specified, the list PARAMS declares attributes of the section, 11671 identified by keywords. The keywords recognized are 'spnum=EXP' 11672 (identify this section by the number EXP, an absolute expression), 11673 'sort=EXP' (order sections according to this sort key when linking; 11674 EXP is an absolute expression), 'unloadable' (section contains no 11675 loadable data), 'notdefined' (this section defined elsewhere), and 11676 'private' (data in this section not available to other programs). 11677 11678'.spnum SECNAM' 11679 Allocate four bytes of storage, and initialize them with the 11680 section number of the section named SECNAM. (You can define the 11681 section number with the HPPA '.space' directive.) 11682 11683'.string "STR"' 11684 Copy the characters in the string STR to the object file. *Note 11685 Strings: Strings, for information on escape sequences you can use 11686 in 'as' strings. 11687 11688 _Warning!_ The HPPA version of '.string' differs from the usual 11689 'as' definition: it does _not_ write a zero byte after copying STR. 11690 11691'.stringz "STR"' 11692 Like '.string', but appends a zero byte after copying STR to object 11693 file. 11694 11695'.subspa NAME [ ,PARAMS ]' 11696'.nsubspa NAME [ ,PARAMS ]' 11697 Similar to '.space', but selects a subsection NAME within the 11698 current section. You may only specify PARAMS when you create a 11699 subsection (in the first instance of '.subspa' for this NAME). 11700 11701 If specified, the list PARAMS declares attributes of the 11702 subsection, identified by keywords. The keywords recognized are 11703 'quad=EXPR' ("quadrant" for this subsection), 'align=EXPR' 11704 (alignment for beginning of this subsection; a power of two), 11705 'access=EXPR' (value for "access rights" field), 'sort=EXPR' 11706 (sorting order for this subspace in link), 'code_only' (subsection 11707 contains only code), 'unloadable' (subsection cannot be loaded into 11708 memory), 'comdat' (subsection is comdat), 'common' (subsection is 11709 common block), 'dup_comm' (subsection may have duplicate names), or 11710 'zero' (subsection is all zeros, do not write in object file). 11711 11712 '.nsubspa' always creates a new subspace with the given name, even 11713 if one with the same name already exists. 11714 11715 'comdat', 'common' and 'dup_comm' can be used to implement various 11716 flavors of one-only support when using the SOM linker. The SOM 11717 linker only supports specific combinations of these flags. The 11718 details are not documented. A brief description is provided here. 11719 11720 'comdat' provides a form of linkonce support. It is useful for 11721 both code and data subspaces. A 'comdat' subspace has a key symbol 11722 marked by the 'is_comdat' flag or 'ST_COMDAT'. Only the first 11723 subspace for any given key is selected. The key symbol becomes 11724 universal in shared links. This is similar to the behavior of 11725 'secondary_def' symbols. 11726 11727 'common' provides Fortran named common support. It is only useful 11728 for data subspaces. Symbols with the flag 'is_common' retain this 11729 flag in shared links. Referencing a 'is_common' symbol in a shared 11730 library from outside the library doesn't work. Thus, 'is_common' 11731 symbols must be output whenever they are needed. 11732 11733 'common' and 'dup_comm' together provide Cobol common support. The 11734 subspaces in this case must all be the same length. Otherwise, 11735 this support is similar to the Fortran common support. 11736 11737 'dup_comm' by itself provides a type of one-only support for code. 11738 Only the first 'dup_comm' subspace is selected. There is a rather 11739 complex algorithm to compare subspaces. Code symbols marked with 11740 the 'dup_common' flag are hidden. This support was intended for 11741 "C++ duplicate inlines". 11742 11743 A simplified technique is used to mark the flags of symbols based 11744 on the flags of their subspace. A symbol with the scope 11745 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with 11746 the corresponding settings of 'comdat', 'common' and 'dup_comm' 11747 from the subspace, respectively. This avoids having to introduce 11748 additional directives to mark these symbols. The HP assembler sets 11749 'is_common' from 'common'. However, it doesn't set the 11750 'dup_common' from 'dup_comm'. It doesn't have 'comdat' support. 11751 11752'.version "STR"' 11753 Write STR as version identifier in object code. 11754 11755 11756File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent 11757 117589.15.6 Opcodes 11759-------------- 11760 11761For detailed information on the HPPA machine instruction set, see 11762'PA-RISC Architecture and Instruction Set Reference Manual' (HP 1176309740-90039). 11764 11765 11766File: as.info, Node: i386-Dependent, Next: IA-64-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies 11767 117689.16 80386 Dependent Features 11769============================= 11770 11771The i386 version 'as' supports both the original Intel 386 architecture 11772in both 16 and 32-bit mode as well as AMD x86-64 architecture extending 11773the Intel architecture to 64-bits. 11774 11775* Menu: 11776 11777* i386-Options:: Options 11778* i386-Directives:: X86 specific directives 11779* i386-Syntax:: Syntactical considerations 11780* i386-Mnemonics:: Instruction Naming 11781* i386-Regs:: Register Naming 11782* i386-Prefixes:: Instruction Prefixes 11783* i386-Memory:: Memory References 11784* i386-Jumps:: Handling of Jump Instructions 11785* i386-Float:: Floating Point 11786* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 11787* i386-LWP:: AMD's Lightweight Profiling Instructions 11788* i386-BMI:: Bit Manipulation Instruction 11789* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 11790* i386-16bit:: Writing 16-bit Code 11791* i386-Arch:: Specifying an x86 CPU architecture 11792* i386-ISA:: AMD64 ISA vs. Intel64 ISA 11793* i386-Bugs:: AT&T Syntax bugs 11794* i386-Notes:: Notes 11795 11796 11797File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 11798 117999.16.1 Options 11800-------------- 11801 11802The i386 version of 'as' has a few machine dependent options: 11803 11804'--32 | --x32 | --64' 11805 Select the word size, either 32 bits or 64 bits. '--32' implies 11806 Intel i386 architecture, while '--x32' and '--64' imply AMD x86-64 11807 architecture with 32-bit or 64-bit word-size respectively. 11808 11809 These options are only available with the ELF object file format, 11810 and require that the necessary BFD support has been included (on a 11811 32-bit platform you have to add -enable-64-bit-bfd to configure 11812 enable 64-bit usage and use x86-64 as target platform). 11813 11814'-n' 11815 By default, x86 GAS replaces multiple nop instructions used for 11816 alignment within code sections with multi-byte nop instructions 11817 such as leal 0(%esi,1),%esi. This switch disables the optimization 11818 if a single byte nop (0x90) is explicitly specified as the fill 11819 byte for alignment. 11820 11821'--divide' 11822 On SVR4-derived platforms, the character '/' is treated as a 11823 comment character, which means that it cannot be used in 11824 expressions. The '--divide' option turns '/' into a normal 11825 character. This does not disable '/' at the beginning of a line 11826 starting a comment, or affect using '#' for starting a comment. 11827 11828'-march=CPU[+EXTENSION...]' 11829 This option specifies the target processor. The assembler will 11830 issue an error message if an attempt is made to assemble an 11831 instruction which will not execute on the target processor. The 11832 following processor names are recognized: 'i8086', 'i186', 'i286', 11833 'i386', 'i486', 'i586', 'i686', 'pentium', 'pentiumpro', 11834 'pentiumii', 'pentiumiii', 'pentium4', 'prescott', 'nocona', 11835 'core', 'core2', 'corei7', 'l1om', 'k1om', 'iamcu', 'k6', 'k6_2', 11836 'athlon', 'opteron', 'k8', 'amdfam10', 'bdver1', 'bdver2', 11837 'bdver3', 'bdver4', 'znver1', 'znver2', 'znver3', 'btver1', 11838 'btver2', 'generic32' and 'generic64'. 11839 11840 In addition to the basic instruction set, the assembler can be told 11841 to accept various extension mnemonics. For example, 11842 '-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The 11843 following extensions are currently supported: '8087', '287', '387', 11844 '687', 'no87', 'no287', 'no387', 'no687', 'cmov', 'nocmov', 'fxsr', 11845 'nofxsr', 'mmx', 'nommx', 'sse', 'sse2', 'sse3', 'sse4a', 'ssse3', 11846 'sse4.1', 'sse4.2', 'sse4', 'nosse', 'nosse2', 'nosse3', 'nosse4a', 11847 'nossse3', 'nosse4.1', 'nosse4.2', 'nosse4', 'avx', 'avx2', 11848 'noavx', 'noavx2', 'adx', 'rdseed', 'prfchw', 'smap', 'mpx', 'sha', 11849 'rdpid', 'ptwrite', 'cet', 'gfni', 'vaes', 'vpclmulqdq', 11850 'prefetchwt1', 'clflushopt', 'se1', 'clwb', 'movdiri', 'movdir64b', 11851 'enqcmd', 'serialize', 'tsxldtrk', 'kl', 'nokl', 'widekl', 11852 'nowidekl', 'hreset', 'avx512f', 'avx512cd', 'avx512er', 11853 'avx512pf', 'avx512vl', 'avx512bw', 'avx512dq', 'avx512ifma', 11854 'avx512vbmi', 'avx512_4fmaps', 'avx512_4vnniw', 'avx512_vpopcntdq', 11855 'avx512_vbmi2', 'avx512_vnni', 'avx512_bitalg', 11856 'avx512_vp2intersect', 'tdx', 'avx512_bf16', 'avx_vnni', 11857 'noavx512f', 'noavx512cd', 'noavx512er', 'noavx512pf', 11858 'noavx512vl', 'noavx512bw', 'noavx512dq', 'noavx512ifma', 11859 'noavx512vbmi', 'noavx512_4fmaps', 'noavx512_4vnniw', 11860 'noavx512_vpopcntdq', 'noavx512_vbmi2', 'noavx512_vnni', 11861 'noavx512_bitalg', 'noavx512_vp2intersect', 'notdx', 11862 'noavx512_bf16', 'noavx_vnni', 'noenqcmd', 'noserialize', 11863 'notsxldtrk', 'amx_int8', 'noamx_int8', 'amx_bf16', 'noamx_bf16', 11864 'amx_tile', 'noamx_tile', 'nouintr', 'nohreset', 'vmx', 'vmfunc', 11865 'smx', 'xsave', 'xsaveopt', 'xsavec', 'xsaves', 'aes', 'pclmul', 11866 'fsgsbase', 'rdrnd', 'f16c', 'bmi2', 'fma', 'movbe', 'ept', 11867 'lzcnt', 'popcnt', 'hle', 'rtm', 'invpcid', 'clflush', 'mwaitx', 11868 'clzero', 'wbnoinvd', 'pconfig', 'waitpkg', 'uintr', 'cldemote', 11869 'rdpru', 'mcommit', 'sev_es', 'lwp', 'fma4', 'xop', 'cx16', 11870 'syscall', 'rdtscp', '3dnow', '3dnowa', 'sse4a', 'sse5', 'snp', 11871 'invlpgb', 'tlbsync', 'svme' and 'padlock'. Note that rather than 11872 extending a basic instruction set, the extension mnemonics starting 11873 with 'no' revoke the respective functionality. 11874 11875 When the '.arch' directive is used with '-march', the '.arch' 11876 directive will take precedent. 11877 11878'-mtune=CPU' 11879 This option specifies a processor to optimize for. When used in 11880 conjunction with the '-march' option, only instructions of the 11881 processor specified by the '-march' option will be generated. 11882 11883 Valid CPU values are identical to the processor list of 11884 '-march=CPU'. 11885 11886'-msse2avx' 11887 This option specifies that the assembler should encode SSE 11888 instructions with VEX prefix. 11889 11890'-msse-check=NONE' 11891'-msse-check=WARNING' 11892'-msse-check=ERROR' 11893 These options control if the assembler should check SSE 11894 instructions. '-msse-check=NONE' will make the assembler not to 11895 check SSE instructions, which is the default. 11896 '-msse-check=WARNING' will make the assembler issue a warning for 11897 any SSE instruction. '-msse-check=ERROR' will make the assembler 11898 issue an error for any SSE instruction. 11899 11900'-mavxscalar=128' 11901'-mavxscalar=256' 11902 These options control how the assembler should encode scalar AVX 11903 instructions. '-mavxscalar=128' will encode scalar AVX 11904 instructions with 128bit vector length, which is the default. 11905 '-mavxscalar=256' will encode scalar AVX instructions with 256bit 11906 vector length. 11907 11908 WARNING: Don't use this for production code - due to CPU errata the 11909 resulting code may not work on certain models. 11910 11911'-mvexwig=0' 11912'-mvexwig=1' 11913 These options control how the assembler should encode VEX.W-ignored 11914 (WIG) VEX instructions. '-mvexwig=0' will encode WIG VEX 11915 instructions with vex.w = 0, which is the default. '-mvexwig=1' 11916 will encode WIG EVEX instructions with vex.w = 1. 11917 11918 WARNING: Don't use this for production code - due to CPU errata the 11919 resulting code may not work on certain models. 11920 11921'-mevexlig=128' 11922'-mevexlig=256' 11923'-mevexlig=512' 11924 These options control how the assembler should encode 11925 length-ignored (LIG) EVEX instructions. '-mevexlig=128' will 11926 encode LIG EVEX instructions with 128bit vector length, which is 11927 the default. '-mevexlig=256' and '-mevexlig=512' will encode LIG 11928 EVEX instructions with 256bit and 512bit vector length, 11929 respectively. 11930 11931'-mevexwig=0' 11932'-mevexwig=1' 11933 These options control how the assembler should encode w-ignored 11934 (WIG) EVEX instructions. '-mevexwig=0' will encode WIG EVEX 11935 instructions with evex.w = 0, which is the default. '-mevexwig=1' 11936 will encode WIG EVEX instructions with evex.w = 1. 11937 11938'-mmnemonic=ATT' 11939'-mmnemonic=INTEL' 11940 This option specifies instruction mnemonic for matching 11941 instructions. The '.att_mnemonic' and '.intel_mnemonic' directives 11942 will take precedent. 11943 11944'-msyntax=ATT' 11945'-msyntax=INTEL' 11946 This option specifies instruction syntax when processing 11947 instructions. The '.att_syntax' and '.intel_syntax' directives 11948 will take precedent. 11949 11950'-mnaked-reg' 11951 This option specifies that registers don't require a '%' prefix. 11952 The '.att_syntax' and '.intel_syntax' directives will take 11953 precedent. 11954 11955'-madd-bnd-prefix' 11956 This option forces the assembler to add BND prefix to all branches, 11957 even if such prefix was not explicitly specified in the source 11958 code. 11959 11960'-mno-shared' 11961 On ELF target, the assembler normally optimizes out non-PLT 11962 relocations against defined non-weak global branch targets with 11963 default visibility. The '-mshared' option tells the assembler to 11964 generate code which may go into a shared library where all non-weak 11965 global branch targets with default visibility can be preempted. 11966 The resulting code is slightly bigger. This option only affects 11967 the handling of branch instructions. 11968 11969'-mbig-obj' 11970 On PE/COFF target this option forces the use of big object file 11971 format, which allows more than 32768 sections. 11972 11973'-momit-lock-prefix=NO' 11974'-momit-lock-prefix=YES' 11975 These options control how the assembler should encode lock prefix. 11976 This option is intended as a workaround for processors, that fail 11977 on lock prefix. This option can only be safely used with 11978 single-core, single-thread computers '-momit-lock-prefix=YES' will 11979 omit all lock prefixes. '-momit-lock-prefix=NO' will encode lock 11980 prefix as usual, which is the default. 11981 11982'-mfence-as-lock-add=NO' 11983'-mfence-as-lock-add=YES' 11984 These options control how the assembler should encode lfence, 11985 mfence and sfence. '-mfence-as-lock-add=YES' will encode lfence, 11986 mfence and sfence as 'lock addl $0x0, (%rsp)' in 64-bit mode and 11987 'lock addl $0x0, (%esp)' in 32-bit mode. '-mfence-as-lock-add=NO' 11988 will encode lfence, mfence and sfence as usual, which is the 11989 default. 11990 11991'-mrelax-relocations=NO' 11992'-mrelax-relocations=YES' 11993 These options control whether the assembler should generate relax 11994 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX 11995 and R_X86_64_REX_GOTPCRELX, in 64-bit mode. 11996 '-mrelax-relocations=YES' will generate relax relocations. 11997 '-mrelax-relocations=NO' will not generate relax relocations. The 11998 default can be controlled by a configure option 11999 '--enable-x86-relax-relocations'. 12000 12001'-malign-branch-boundary=NUM' 12002 This option controls how the assembler should align branches with 12003 segment prefixes or NOP. NUM must be a power of 2. It should be 0 12004 or no less than 16. Branches will be aligned within NUM byte 12005 boundary. '-malign-branch-boundary=0', which is the default, 12006 doesn't align branches. 12007 12008'-malign-branch=TYPE[+TYPE...]' 12009 This option specifies types of branches to align. TYPE is 12010 combination of 'jcc', which aligns conditional jumps, 'fused', 12011 which aligns fused conditional jumps, 'jmp', which aligns 12012 unconditional jumps, 'call' which aligns calls, 'ret', which aligns 12013 rets, 'indirect', which aligns indirect jumps and calls. The 12014 default is '-malign-branch=jcc+fused+jmp'. 12015 12016'-malign-branch-prefix-size=NUM' 12017 This option specifies the maximum number of prefixes on an 12018 instruction to align branches. NUM should be between 0 and 5. The 12019 default NUM is 5. 12020 12021'-mbranches-within-32B-boundaries' 12022 This option aligns conditional jumps, fused conditional jumps and 12023 unconditional jumps within 32 byte boundary with up to 5 segment 12024 prefixes on an instruction. It is equivalent to 12025 '-malign-branch-boundary=32' '-malign-branch=jcc+fused+jmp' 12026 '-malign-branch-prefix-size=5'. The default doesn't align 12027 branches. 12028 12029'-mlfence-after-load=NO' 12030'-mlfence-after-load=YES' 12031 These options control whether the assembler should generate lfence 12032 after load instructions. '-mlfence-after-load=YES' will generate 12033 lfence. '-mlfence-after-load=NO' will not generate lfence, which 12034 is the default. 12035 12036'-mlfence-before-indirect-branch=NONE' 12037'-mlfence-before-indirect-branch=ALL' 12038'-mlfence-before-indirect-branch=REGISTER' 12039'-mlfence-before-indirect-branch=MEMORY' 12040 These options control whether the assembler should generate lfence 12041 before indirect near branch instructions. 12042 '-mlfence-before-indirect-branch=ALL' will generate lfence before 12043 indirect near branch via register and issue a warning before 12044 indirect near branch via memory. It also implicitly sets 12045 '-mlfence-before-ret=SHL' when there's no explicit 12046 '-mlfence-before-ret='. '-mlfence-before-indirect-branch=REGISTER' 12047 will generate lfence before indirect near branch via register. 12048 '-mlfence-before-indirect-branch=MEMORY' will issue a warning 12049 before indirect near branch via memory. 12050 '-mlfence-before-indirect-branch=NONE' will not generate lfence nor 12051 issue warning, which is the default. Note that lfence won't be 12052 generated before indirect near branch via register with 12053 '-mlfence-after-load=YES' since lfence will be generated after 12054 loading branch target register. 12055 12056'-mlfence-before-ret=NONE' 12057'-mlfence-before-ret=SHL' 12058'-mlfence-before-ret=OR' 12059'-mlfence-before-ret=YES' 12060'-mlfence-before-ret=NOT' 12061 These options control whether the assembler should generate lfence 12062 before ret. '-mlfence-before-ret=OR' will generate generate or 12063 instruction with lfence. '-mlfence-before-ret=SHL/YES' will 12064 generate shl instruction with lfence. '-mlfence-before-ret=NOT' 12065 will generate not instruction with lfence. 12066 '-mlfence-before-ret=NONE' will not generate lfence, which is the 12067 default. 12068 12069'-mx86-used-note=NO' 12070'-mx86-used-note=YES' 12071 These options control whether the assembler should generate 12072 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU 12073 property notes. The default can be controlled by the 12074 '--enable-x86-used-note' configure option. 12075 12076'-mevexrcig=RNE' 12077'-mevexrcig=RD' 12078'-mevexrcig=RU' 12079'-mevexrcig=RZ' 12080 These options control how the assembler should encode SAE-only EVEX 12081 instructions. '-mevexrcig=RNE' will encode RC bits of EVEX 12082 instruction with 00, which is the default. '-mevexrcig=RD', 12083 '-mevexrcig=RU' and '-mevexrcig=RZ' will encode SAE-only EVEX 12084 instructions with 01, 10 and 11 RC bits, respectively. 12085 12086'-mamd64' 12087'-mintel64' 12088 This option specifies that the assembler should accept only AMD64 12089 or Intel64 ISA in 64-bit mode. The default is to accept common, 12090 Intel64 only and AMD64 ISAs. 12091 12092'-O0 | -O | -O1 | -O2 | -Os' 12093 Optimize instruction encoding with smaller instruction size. '-O' 12094 and '-O1' encode 64-bit register load instructions with 64-bit 12095 immediate as 32-bit register load instructions with 31-bit or 12096 32-bits immediates, encode 64-bit register clearing instructions 12097 with 32-bit register clearing instructions, encode 256-bit/512-bit 12098 VEX/EVEX vector register clearing instructions with 128-bit VEX 12099 vector register clearing instructions, encode 128-bit/256-bit EVEX 12100 vector register load/store instructions with VEX vector register 12101 load/store instructions, and encode 128-bit/256-bit EVEX packed 12102 integer logical instructions with 128-bit/256-bit VEX packed 12103 integer logical. 12104 12105 '-O2' includes '-O1' optimization plus encodes 256-bit/512-bit EVEX 12106 vector register clearing instructions with 128-bit EVEX vector 12107 register clearing instructions. In 64-bit mode VEX encoded 12108 instructions with commutative source operands will also have their 12109 source operands swapped if this allows using the 2-byte VEX prefix 12110 form instead of the 3-byte one. Certain forms of AND as well as OR 12111 with the same (register) operand specified twice will also be 12112 changed to TEST. 12113 12114 '-Os' includes '-O2' optimization plus encodes 16-bit, 32-bit and 12115 64-bit register tests with immediate as 8-bit register test with 12116 immediate. '-O0' turns off this optimization. 12117 12118 12119File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent 12120 121219.16.2 x86 specific Directives 12122------------------------------ 12123 12124'.lcomm SYMBOL , LENGTH[, ALIGNMENT]' 12125 Reserve LENGTH (an absolute expression) bytes for a local common 12126 denoted by SYMBOL. The section and value of SYMBOL are those of 12127 the new local common. The addresses are allocated in the bss 12128 section, so that at run-time the bytes start off zeroed. Since 12129 SYMBOL is not declared global, it is normally not visible to 'ld'. 12130 The optional third parameter, ALIGNMENT, specifies the desired 12131 alignment of the symbol in the bss section. 12132 12133 This directive is only available for COFF based x86 targets. 12134 12135'.largecomm SYMBOL , LENGTH[, ALIGNMENT]' 12136 This directive behaves in the same way as the 'comm' directive 12137 except that the data is placed into the .LBSS section instead of 12138 the .BSS section *note Comm::. 12139 12140 The directive is intended to be used for data which requires a 12141 large amount of space, and it is only available for ELF based 12142 x86_64 targets. 12143 12144'.value EXPRESSION [, EXPRESSION]' 12145 This directive behaves in the same way as the '.short' directive, 12146 taking a series of comma separated expressions and storing them as 12147 two-byte wide values into the current section. 12148 12149 12150File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent 12151 121529.16.3 i386 Syntactical Considerations 12153-------------------------------------- 12154 12155* Menu: 12156 12157* i386-Variations:: AT&T Syntax versus Intel Syntax 12158* i386-Chars:: Special Characters 12159 12160 12161File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax 12162 121639.16.3.1 AT&T Syntax versus Intel Syntax 12164........................................ 12165 12166'as' now supports assembly using Intel assembler syntax. 12167'.intel_syntax' selects Intel mode, and '.att_syntax' switches back to 12168the usual AT&T mode for compatibility with the output of 'gcc'. Either 12169of these directives may have an optional argument, 'prefix', or 12170'noprefix' specifying whether registers require a '%' prefix. AT&T 12171System V/386 assembler syntax is quite different from Intel syntax. We 12172mention these differences because almost all 80386 documents use Intel 12173syntax. Notable differences between the two syntaxes are: 12174 12175 * AT&T immediate operands are preceded by '$'; Intel immediate 12176 operands are undelimited (Intel 'push 4' is AT&T 'pushl $4'). AT&T 12177 register operands are preceded by '%'; Intel register operands are 12178 undelimited. AT&T absolute (as opposed to PC relative) jump/call 12179 operands are prefixed by '*'; they are undelimited in Intel syntax. 12180 12181 * AT&T and Intel syntax use the opposite order for source and 12182 destination operands. Intel 'add eax, 4' is 'addl $4, %eax'. The 12183 'source, dest' convention is maintained for compatibility with 12184 previous Unix assemblers. Note that 'bound', 'invlpga', and 12185 instructions with 2 immediate operands, such as the 'enter' 12186 instruction, do _not_ have reversed order. *note i386-Bugs::. 12187 12188 * In AT&T syntax the size of memory operands is determined from the 12189 last character of the instruction mnemonic. Mnemonic suffixes of 12190 'b', 'w', 'l' and 'q' specify byte (8-bit), word (16-bit), long 12191 (32-bit) and quadruple word (64-bit) memory references. Mnemonic 12192 suffixes of 'x', 'y' and 'z' specify xmm (128-bit vector), ymm 12193 (256-bit vector) and zmm (512-bit vector) memory references, only 12194 when there's no other way to disambiguate an instruction. Intel 12195 syntax accomplishes this by prefixing memory operands (_not_ the 12196 instruction mnemonics) with 'byte ptr', 'word ptr', 'dword ptr', 12197 'qword ptr', 'xmmword ptr', 'ymmword ptr' and 'zmmword ptr'. Thus, 12198 Intel syntax 'mov al, byte ptr FOO' is 'movb FOO, %al' in AT&T 12199 syntax. In Intel syntax, 'fword ptr', 'tbyte ptr' and 'oword ptr' 12200 specify 48-bit, 80-bit and 128-bit memory references. 12201 12202 In 64-bit code, 'movabs' can be used to encode the 'mov' 12203 instruction with the 64-bit displacement or immediate operand. 12204 12205 * Immediate form long jumps and calls are 'lcall/ljmp $SECTION, 12206 $OFFSET' in AT&T syntax; the Intel syntax is 'call/jmp far 12207 SECTION:OFFSET'. Also, the far return instruction is 'lret 12208 $STACK-ADJUST' in AT&T syntax; Intel syntax is 'ret far 12209 STACK-ADJUST'. 12210 12211 * The AT&T assembler does not provide support for multiple section 12212 programs. Unix style systems expect all programs to be single 12213 sections. 12214 12215 12216File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax 12217 122189.16.3.2 Special Characters 12219........................... 12220 12221The presence of a '#' appearing anywhere on a line indicates the start 12222of a comment that extends to the end of that line. 12223 12224 If a '#' appears as the first character of a line then the whole line 12225is treated as a comment, but in this case the line can also be a logical 12226line number directive (*note Comments::) or a preprocessor control 12227command (*note Preprocessing::). 12228 12229 If the '--divide' command-line option has not been specified then the 12230'/' character appearing anywhere on a line also introduces a line 12231comment. 12232 12233 The ';' character can be used to separate statements on the same 12234line. 12235 12236 12237File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent 12238 122399.16.4 i386-Mnemonics 12240--------------------- 12241 122429.16.4.1 Instruction Naming 12243........................... 12244 12245Instruction mnemonics are suffixed with one character modifiers which 12246specify the size of operands. The letters 'b', 'w', 'l' and 'q' specify 12247byte, word, long and quadruple word operands. If no suffix is specified 12248by an instruction then 'as' tries to fill in the missing suffix based on 12249the destination register operand (the last one by convention). Thus, 12250'mov %ax, %bx' is equivalent to 'movw %ax, %bx'; also, 'mov $1, %bx' is 12251equivalent to 'movw $1, bx'. Note that this is incompatible with the 12252AT&T Unix assembler which assumes that a missing mnemonic suffix implies 12253long operand size. (This incompatibility does not affect compiler 12254output since compilers always explicitly specify the mnemonic suffix.) 12255 12256 When there is no sizing suffix and no (suitable) register operands to 12257deduce the size of memory operands, with a few exceptions and where long 12258operand size is possible in the first place, operand size will default 12259to long in 32- and 64-bit modes. Similarly it will default to short in 1226016-bit mode. Noteworthy exceptions are 12261 12262 * Instructions with an implicit on-stack operand as well as branches, 12263 which default to quad in 64-bit mode. 12264 12265 * Sign- and zero-extending moves, which default to byte size source 12266 operands. 12267 12268 * Floating point insns with integer operands, which default to short 12269 (for perhaps historical reasons). 12270 12271 * CRC32 with a 64-bit destination, which defaults to a quad source 12272 operand. 12273 12274 Different encoding options can be specified via pseudo prefixes: 12275 12276 * '{disp8}' - prefer 8-bit displacement. 12277 12278 * '{disp32}' - prefer 32-bit displacement. 12279 12280 * '{disp16}' - prefer 16-bit displacement. 12281 12282 * '{load}' - prefer load-form instruction. 12283 12284 * '{store}' - prefer store-form instruction. 12285 12286 * '{vex}' - encode with VEX prefix. 12287 12288 * '{vex3}' - encode with 3-byte VEX prefix. 12289 12290 * '{evex}' - encode with EVEX prefix. 12291 12292 * '{rex}' - prefer REX prefix for integer and legacy vector 12293 instructions (x86-64 only). Note that this differs from the 'rex' 12294 prefix which generates REX prefix unconditionally. 12295 12296 * '{nooptimize}' - disable instruction size optimization. 12297 12298 Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix 12299by default. The pseudo '{vex}' prefix can be used to encode mnemonics 12300of Intel VNNI instructions with the VEX prefix. 12301 12302 The Intel-syntax conversion instructions 12303 12304 * 'cbw' -- sign-extend byte in '%al' to word in '%ax', 12305 12306 * 'cwde' -- sign-extend word in '%ax' to long in '%eax', 12307 12308 * 'cwd' -- sign-extend word in '%ax' to long in '%dx:%ax', 12309 12310 * 'cdq' -- sign-extend dword in '%eax' to quad in '%edx:%eax', 12311 12312 * 'cdqe' -- sign-extend dword in '%eax' to quad in '%rax' (x86-64 12313 only), 12314 12315 * 'cqo' -- sign-extend quad in '%rax' to octuple in '%rdx:%rax' 12316 (x86-64 only), 12317 12318are called 'cbtw', 'cwtl', 'cwtd', 'cltd', 'cltq', and 'cqto' in AT&T 12319naming. 'as' accepts either naming for these instructions. 12320 12321 The Intel-syntax extension instructions 12322 12323 * 'movsx' -- sign-extend 'reg8/mem8' to 'reg16'. 12324 12325 * 'movsx' -- sign-extend 'reg8/mem8' to 'reg32'. 12326 12327 * 'movsx' -- sign-extend 'reg8/mem8' to 'reg64' (x86-64 only). 12328 12329 * 'movsx' -- sign-extend 'reg16/mem16' to 'reg32' 12330 12331 * 'movsx' -- sign-extend 'reg16/mem16' to 'reg64' (x86-64 only). 12332 12333 * 'movsxd' -- sign-extend 'reg32/mem32' to 'reg64' (x86-64 only). 12334 12335 * 'movzx' -- zero-extend 'reg8/mem8' to 'reg16'. 12336 12337 * 'movzx' -- zero-extend 'reg8/mem8' to 'reg32'. 12338 12339 * 'movzx' -- zero-extend 'reg8/mem8' to 'reg64' (x86-64 only). 12340 12341 * 'movzx' -- zero-extend 'reg16/mem16' to 'reg32' 12342 12343 * 'movzx' -- zero-extend 'reg16/mem16' to 'reg64' (x86-64 only). 12344 12345are called 'movsbw/movsxb/movsx', 'movsbl/movsxb/movsx', 12346'movsbq/movsxb/movsx', 'movswl/movsxw', 'movswq/movsxw', 12347'movslq/movsxl', 'movzbw/movzxb/movzx', 'movzbl/movzxb/movzx', 12348'movzbq/movzxb/movzx', 'movzwl/movzxw' and 'movzwq/movzxw' in AT&T 12349syntax. 12350 12351 Far call/jump instructions are 'lcall' and 'ljmp' in AT&T syntax, but 12352are 'call far' and 'jump far' in Intel convention. 12353 123549.16.4.2 AT&T Mnemonic versus Intel Mnemonic 12355............................................ 12356 12357'as' supports assembly using Intel mnemonic. '.intel_mnemonic' selects 12358Intel mnemonic with Intel syntax, and '.att_mnemonic' switches back to 12359the usual AT&T mnemonic with AT&T syntax for compatibility with the 12360output of 'gcc'. Several x87 instructions, 'fadd', 'fdiv', 'fdivp', 12361'fdivr', 'fdivrp', 'fmul', 'fsub', 'fsubp', 'fsubr' and 'fsubrp', are 12362implemented in AT&T System V/386 assembler with different mnemonics from 12363those in Intel IA32 specification. 'gcc' generates those instructions 12364with AT&T mnemonic. 12365 12366 * 'movslq' with AT&T mnemonic only accepts 64-bit destination 12367 register. 'movsxd' should be used to encode 16-bit or 32-bit 12368 destination register with both AT&T and Intel mnemonics. 12369 12370 12371File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent 12372 123739.16.5 Register Naming 12374---------------------- 12375 12376Register operands are always prefixed with '%'. The 80386 registers 12377consist of 12378 12379 * the 8 32-bit registers '%eax' (the accumulator), '%ebx', '%ecx', 12380 '%edx', '%edi', '%esi', '%ebp' (the frame pointer), and '%esp' (the 12381 stack pointer). 12382 12383 * the 8 16-bit low-ends of these: '%ax', '%bx', '%cx', '%dx', '%di', 12384 '%si', '%bp', and '%sp'. 12385 12386 * the 8 8-bit registers: '%ah', '%al', '%bh', '%bl', '%ch', '%cl', 12387 '%dh', and '%dl' (These are the high-bytes and low-bytes of '%ax', 12388 '%bx', '%cx', and '%dx') 12389 12390 * the 6 section registers '%cs' (code section), '%ds' (data section), 12391 '%ss' (stack section), '%es', '%fs', and '%gs'. 12392 12393 * the 5 processor control registers '%cr0', '%cr2', '%cr3', '%cr4', 12394 and '%cr8'. 12395 12396 * the 6 debug registers '%db0', '%db1', '%db2', '%db3', '%db6', and 12397 '%db7'. 12398 12399 * the 2 test registers '%tr6' and '%tr7'. 12400 12401 * the 8 floating point register stack '%st' or equivalently '%st(0)', 12402 '%st(1)', '%st(2)', '%st(3)', '%st(4)', '%st(5)', '%st(6)', and 12403 '%st(7)'. These registers are overloaded by 8 MMX registers 12404 '%mm0', '%mm1', '%mm2', '%mm3', '%mm4', '%mm5', '%mm6' and '%mm7'. 12405 12406 * the 8 128-bit SSE registers registers '%xmm0', '%xmm1', '%xmm2', 12407 '%xmm3', '%xmm4', '%xmm5', '%xmm6' and '%xmm7'. 12408 12409 The AMD x86-64 architecture extends the register set by: 12410 12411 * enhancing the 8 32-bit registers to 64-bit: '%rax' (the 12412 accumulator), '%rbx', '%rcx', '%rdx', '%rdi', '%rsi', '%rbp' (the 12413 frame pointer), '%rsp' (the stack pointer) 12414 12415 * the 8 extended registers '%r8'-'%r15'. 12416 12417 * the 8 32-bit low ends of the extended registers: '%r8d'-'%r15d'. 12418 12419 * the 8 16-bit low ends of the extended registers: '%r8w'-'%r15w'. 12420 12421 * the 8 8-bit low ends of the extended registers: '%r8b'-'%r15b'. 12422 12423 * the 4 8-bit registers: '%sil', '%dil', '%bpl', '%spl'. 12424 12425 * the 8 debug registers: '%db8'-'%db15'. 12426 12427 * the 8 128-bit SSE registers: '%xmm8'-'%xmm15'. 12428 12429 With the AVX extensions more registers were made available: 12430 12431 * the 16 256-bit SSE '%ymm0'-'%ymm15' (only the first 8 available in 12432 32-bit mode). The bottom 128 bits are overlaid with the 12433 'xmm0'-'xmm15' registers. 12434 12435 The AVX512 extensions added the following registers: 12436 12437 * the 32 512-bit registers '%zmm0'-'%zmm31' (only the first 8 12438 available in 32-bit mode). The bottom 128 bits are overlaid with 12439 the '%xmm0'-'%xmm31' registers and the first 256 bits are overlaid 12440 with the '%ymm0'-'%ymm31' registers. 12441 12442 * the 8 mask registers '%k0'-'%k7'. 12443 12444 12445File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent 12446 124479.16.6 Instruction Prefixes 12448--------------------------- 12449 12450Instruction prefixes are used to modify the following instruction. They 12451are used to repeat string instructions, to provide section overrides, to 12452perform bus lock operations, and to change operand and address sizes. 12453(Most instructions that normally operate on 32-bit operands will use 1245416-bit operands if the instruction has an "operand size" prefix.) 12455Instruction prefixes are best written on the same line as the 12456instruction they act upon. For example, the 'scas' (scan string) 12457instruction is repeated with: 12458 12459 repne scas %es:(%edi),%al 12460 12461 You may also place prefixes on the lines immediately preceding the 12462instruction, but this circumvents checks that 'as' does with prefixes, 12463and will not work with all prefixes. 12464 12465 Here is a list of instruction prefixes: 12466 12467 * Section override prefixes 'cs', 'ds', 'ss', 'es', 'fs', 'gs'. 12468 These are automatically added by specifying using the 12469 SECTION:MEMORY-OPERAND form for memory references. 12470 12471 * Operand/Address size prefixes 'data16' and 'addr16' change 32-bit 12472 operands/addresses into 16-bit operands/addresses, while 'data32' 12473 and 'addr32' change 16-bit ones (in a '.code16' section) into 12474 32-bit operands/addresses. These prefixes _must_ appear on the 12475 same line of code as the instruction they modify. For example, in 12476 a 16-bit '.code16' section, you might write: 12477 12478 addr32 jmpl *(%ebx) 12479 12480 * The bus lock prefix 'lock' inhibits interrupts during execution of 12481 the instruction it precedes. (This is only valid with certain 12482 instructions; see a 80386 manual for details). 12483 12484 * The wait for coprocessor prefix 'wait' waits for the coprocessor to 12485 complete the current instruction. This should never be needed for 12486 the 80386/80387 combination. 12487 12488 * The 'rep', 'repe', and 'repne' prefixes are added to string 12489 instructions to make them repeat '%ecx' times ('%cx' times if the 12490 current address size is 16-bits). 12491 * The 'rex' family of prefixes is used by x86-64 to encode extensions 12492 to i386 instruction set. The 'rex' prefix has four bits -- an 12493 operand size overwrite ('64') used to change operand size from 12494 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 12495 register set. 12496 12497 You may write the 'rex' prefixes directly. The 'rex64xyz' 12498 instruction emits 'rex' prefix with all the bits set. By omitting 12499 the '64', 'x', 'y' or 'z' you may write other prefixes as well. 12500 Normally, there is no need to write the prefixes explicitly, since 12501 gas will automatically generate them based on the instruction 12502 operands. 12503 12504 12505File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent 12506 125079.16.7 Memory References 12508------------------------ 12509 12510An Intel syntax indirect memory reference of the form 12511 12512 SECTION:[BASE + INDEX*SCALE + DISP] 12513 12514is translated into the AT&T syntax 12515 12516 SECTION:DISP(BASE, INDEX, SCALE) 12517 12518where BASE and INDEX are the optional 32-bit base and index registers, 12519DISP is the optional displacement, and SCALE, taking the values 1, 2, 4, 12520and 8, multiplies INDEX to calculate the address of the operand. If no 12521SCALE is specified, SCALE is taken to be 1. SECTION specifies the 12522optional section register for the memory operand, and may override the 12523default section register (see a 80386 manual for section register 12524defaults). Note that section overrides in AT&T syntax _must_ be 12525preceded by a '%'. If you specify a section override which coincides 12526with the default section register, 'as' does _not_ output any section 12527register override prefixes to assemble the given instruction. Thus, 12528section overrides can be specified to emphasize which section register 12529is used for a given memory operand. 12530 12531 Here are some examples of Intel and AT&T style memory references: 12532 12533AT&T: '-4(%ebp)', Intel: '[ebp - 4]' 12534 BASE is '%ebp'; DISP is '-4'. SECTION is missing, and the default 12535 section is used ('%ss' for addressing with '%ebp' as the base 12536 register). INDEX, SCALE are both missing. 12537 12538AT&T: 'foo(,%eax,4)', Intel: '[foo + eax*4]' 12539 INDEX is '%eax' (scaled by a SCALE 4); DISP is 'foo'. All other 12540 fields are missing. The section register here defaults to '%ds'. 12541 12542AT&T: 'foo(,1)'; Intel '[foo]' 12543 This uses the value pointed to by 'foo' as a memory operand. Note 12544 that BASE and INDEX are both missing, but there is only _one_ ','. 12545 This is a syntactic exception. 12546 12547AT&T: '%gs:foo'; Intel 'gs:foo' 12548 This selects the contents of the variable 'foo' with section 12549 register SECTION being '%gs'. 12550 12551 Absolute (as opposed to PC relative) call and jump operands must be 12552prefixed with '*'. If no '*' is specified, 'as' always chooses PC 12553relative addressing for jump/call labels. 12554 12555 Any instruction that has a memory operand, but no register operand, 12556_must_ specify its size (byte, word, long, or quadruple) with an 12557instruction mnemonic suffix ('b', 'w', 'l' or 'q', respectively). 12558 12559 The x86-64 architecture adds an RIP (instruction pointer relative) 12560addressing. This addressing mode is specified by using 'rip' as a base 12561register. Only constant offsets are valid. For example: 12562 12563AT&T: '1234(%rip)', Intel: '[rip + 1234]' 12564 Points to the address 1234 bytes past the end of the current 12565 instruction. 12566 12567AT&T: 'symbol(%rip)', Intel: '[rip + symbol]' 12568 Points to the 'symbol' in RIP relative way, this is shorter than 12569 the default absolute addressing. 12570 12571 Other addressing modes remain unchanged in x86-64 architecture, 12572except registers used are 64-bit instead of 32-bit. 12573 12574 12575File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent 12576 125779.16.8 Handling of Jump Instructions 12578------------------------------------ 12579 12580Jump instructions are always optimized to use the smallest possible 12581displacements. This is accomplished by using byte (8-bit) displacement 12582jumps whenever the target is sufficiently close. If a byte displacement 12583is insufficient a long displacement is used. We do not support word 12584(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 12585instruction with the 'data16' instruction prefix), since the 80386 12586insists upon masking '%eip' to 16 bits after the word displacement is 12587added. (See also *note i386-Arch::) 12588 12589 Note that the 'jcxz', 'jecxz', 'loop', 'loopz', 'loope', 'loopnz' and 12590'loopne' instructions only come in byte displacements, so that if you 12591use these instructions ('gcc' does not use them) you may get an error 12592message (and incorrect code). The AT&T 80386 assembler tries to get 12593around this problem by expanding 'jcxz foo' to 12594 12595 jcxz cx_zero 12596 jmp cx_nonzero 12597 cx_zero: jmp foo 12598 cx_nonzero: 12599 12600 12601File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 12602 126039.16.9 Floating Point 12604--------------------- 12605 12606All 80387 floating point types except packed BCD are supported. (BCD 12607support may be added without much difficulty). These data types are 1260816-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 12609and extended (80-bit) precision floating point. Each supported type has 12610an instruction mnemonic suffix and a constructor associated with it. 12611Instruction mnemonic suffixes specify the operand's data type. 12612Constructors build these data types into memory. 12613 12614 * Floating point constructors are '.float' or '.single', '.double', 12615 and '.tfloat' for 32-, 64-, and 80-bit formats. These correspond 12616 to instruction mnemonic suffixes 's', 'l', and 't'. 't' stands for 12617 80-bit (ten byte) real. The 80387 only supports this format via 12618 the 'fldt' (load 80-bit real to stack top) and 'fstpt' (store 12619 80-bit real and pop stack) instructions. 12620 12621 * Integer constructors are '.word', '.long' or '.int', and '.quad' 12622 for the 16-, 32-, and 64-bit integer formats. The corresponding 12623 instruction mnemonic suffixes are 's' (short), 'l' (long), and 'q' 12624 (quad). As with the 80-bit real format, the 64-bit 'q' format is 12625 only present in the 'fildq' (load quad integer to stack top) and 12626 'fistpq' (store quad integer and pop stack) instructions. 12627 12628 Register to register operations should not use instruction mnemonic 12629suffixes. 'fstl %st, %st(1)' will give a warning, and be assembled as 12630if you wrote 'fst %st, %st(1)', since all register to register 12631operations use 80-bit floating point operands. (Contrast this with 12632'fstl %st, mem', which converts '%st' from 80-bit to 64-bit floating 12633point format, then stores the result in the 4 byte location 'mem') 12634 12635 12636File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent 12637 126389.16.10 Intel's MMX and AMD's 3DNow! SIMD Operations 12639---------------------------------------------------- 12640 12641'as' supports Intel's MMX instruction set (SIMD instructions for integer 12642data), available on Intel's Pentium MMX processors and Pentium II 12643processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and 12644probably others. It also supports AMD's 3DNow! instruction set (SIMD 12645instructions for 32-bit floating point data) available on AMD's K6-2 12646processor and possibly others in the future. 12647 12648 Currently, 'as' does not support Intel's floating point SIMD, Katmai 12649(KNI). 12650 12651 The eight 64-bit MMX operands, also used by 3DNow!, are called 12652'%mm0', '%mm1', ... '%mm7'. They contain eight 8-bit integers, four 1265316-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 12654floating point values. The MMX registers cannot be used at the same 12655time as the floating point stack. 12656 12657 See Intel and AMD documentation, keeping in mind that the operand 12658order in instructions is reversed from the Intel syntax. 12659 12660 12661File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent 12662 126639.16.11 AMD's Lightweight Profiling Instructions 12664------------------------------------------------ 12665 12666'as' supports AMD's Lightweight Profiling (LWP) instruction set, 12667available on AMD's Family 15h (Orochi) processors. 12668 12669 LWP enables applications to collect and manage performance data, and 12670react to performance events. The collection of performance data 12671requires no context switches. LWP runs in the context of a thread and 12672so several counters can be used independently across multiple threads. 12673LWP can be used in both 64-bit and legacy 32-bit modes. 12674 12675 For detailed information on the LWP instruction set, see the 'AMD 12676Lightweight Profiling Specification' available at Lightweight Profiling 12677Specification (http://developer.amd.com/cpu/LWP). 12678 12679 12680File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent 12681 126829.16.12 Bit Manipulation Instructions 12683------------------------------------- 12684 12685'as' supports the Bit Manipulation (BMI) instruction set. 12686 12687 BMI instructions provide several instructions implementing individual 12688bit manipulation operations such as isolation, masking, setting, or 12689resetting. 12690 12691 12692File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent 12693 126949.16.13 AMD's Trailing Bit Manipulation Instructions 12695---------------------------------------------------- 12696 12697'as' supports AMD's Trailing Bit Manipulation (TBM) instruction set, 12698available on AMD's BDVER2 processors (Trinity and Viperfish). 12699 12700 TBM instructions provide instructions implementing individual bit 12701manipulation operations such as isolating, masking, setting, resetting, 12702complementing, and operations on trailing zeros and ones. 12703 12704 12705File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent 12706 127079.16.14 Writing 16-bit Code 12708--------------------------- 12709 12710While 'as' normally writes only "pure" 32-bit i386 code or 64-bit x86-64 12711code depending on the default configuration, it also supports writing 12712code to run in real mode or in 16-bit protected mode code segments. To 12713do this, put a '.code16' or '.code16gcc' directive before the assembly 12714language instructions to be run in 16-bit mode. You can switch 'as' to 12715writing 32-bit code with the '.code32' directive or 64-bit code with the 12716'.code64' directive. 12717 12718 '.code16gcc' provides experimental support for generating 16-bit code 12719from gcc, and differs from '.code16' in that 'call', 'ret', 'enter', 12720'leave', 'push', 'pop', 'pusha', 'popa', 'pushf', and 'popf' 12721instructions default to 32-bit size. This is so that the stack pointer 12722is manipulated in the same way over function calls, allowing access to 12723function parameters at the same stack offsets as in 32-bit mode. 12724'.code16gcc' also automatically adds address size prefixes where 12725necessary to use the 32-bit addressing modes that gcc generates. 12726 12727 The code which 'as' generates in 16-bit mode will not necessarily run 12728on a 16-bit pre-80386 processor. To write code that runs on such a 12729processor, you must refrain from using _any_ 32-bit constructs which 12730require 'as' to output address or operand size prefixes. 12731 12732 Note that writing 16-bit code instructions by explicitly specifying a 12733prefix or an instruction mnemonic suffix within a 32-bit code section 12734generates different machine instructions than those generated for a 1273516-bit code segment. In a 32-bit code section, the following code 12736generates the machine opcode bytes '66 6a 04', which pushes the value 12737'4' onto the stack, decrementing '%esp' by 2. 12738 12739 pushw $4 12740 12741 The same code in a 16-bit code section would generate the machine 12742opcode bytes '6a 04' (i.e., without the operand size prefix), which is 12743correct since the processor default operand size is assumed to be 16 12744bits in a 16-bit code section. 12745 12746 12747File: as.info, Node: i386-Arch, Next: i386-ISA, Prev: i386-16bit, Up: i386-Dependent 12748 127499.16.15 Specifying CPU Architecture 12750----------------------------------- 12751 12752'as' may be told to assemble for a particular CPU (sub-)architecture 12753with the '.arch CPU_TYPE' directive. This directive enables a warning 12754when gas detects an instruction that is not supported on the CPU 12755specified. The choices for CPU_TYPE are: 12756 12757'i8086' 'i186' 'i286' 'i386' 12758'i486' 'i586' 'i686' 'pentium' 12759'pentiumpro' 'pentiumii' 'pentiumiii' 'pentium4' 12760'prescott' 'nocona' 'core' 'core2' 12761'corei7' 'l1om' 'k1om' 'iamcu' 12762'k6' 'k6_2' 'athlon' 'k8' 12763'amdfam10' 'bdver1' 'bdver2' 'bdver3' 12764'bdver4' 'znver1' 'znver2' 'znver3' 12765'btver1' 'btver2' 'generic32' 'generic64' 12766'.cmov' '.fxsr' '.mmx' 12767'.sse' '.sse2' '.sse3' '.sse4a' 12768'.ssse3' '.sse4.1' '.sse4.2' '.sse4' 12769'.avx' '.vmx' '.smx' '.ept' 12770'.clflush' '.movbe' '.xsave' '.xsaveopt' 12771'.aes' '.pclmul' '.fma' '.fsgsbase' 12772'.rdrnd' '.f16c' '.avx2' '.bmi2' 12773'.lzcnt' '.popcnt' '.invpcid' '.vmfunc' 12774'.hle' 12775'.rtm' '.adx' '.rdseed' '.prfchw' 12776'.smap' '.mpx' '.sha' '.prefetchwt1' 12777'.clflushopt' '.xsavec' '.xsaves' '.se1' 12778'.avx512f' '.avx512cd' '.avx512er' '.avx512pf' 12779'.avx512vl' '.avx512bw' '.avx512dq' '.avx512ifma' 12780'.avx512vbmi' '.avx512_4fmaps''.avx512_4vnniw' 12781'.avx512_vpopcntdq''.avx512_vbmi2''.avx512_vnni' 12782'.avx512_bitalg''.avx512_bf16''.avx512_vp2intersect' 12783'.tdx' '.avx_vnni' 12784'.clwb' '.rdpid' '.ptwrite' 12785'.ibt' 12786'.wbnoinvd' '.pconfig' '.waitpkg' '.cldemote' 12787'.shstk' '.gfni' '.vaes' '.vpclmulqdq' 12788'.movdiri' '.movdir64b' '.enqcmd' '.tsxldtrk' 12789'.amx_int8' '.amx_bf16' '.amx_tile' 12790'.kl' '.widekl' '.uintr' '.hreset' 12791'.3dnow' '.3dnowa' '.sse4a' '.sse5' 12792'.syscall' '.rdtscp' '.svme' 12793'.lwp' '.fma4' '.xop' '.cx16' 12794'.padlock' '.clzero' '.mwaitx' '.rdpru' 12795'.mcommit' '.sev_es' '.snp' '.invlpgb' 12796'.tlbsync' 12797 12798 Apart from the warning, there are only two other effects on 'as' 12799operation; Firstly, if you specify a CPU other than 'i486', then shift 12800by one instructions such as 'sarl $1, %eax' will automatically use a two 12801byte opcode sequence. The larger three byte opcode sequence is used on 12802the 486 (and when no architecture is specified) because it executes 12803faster on the 486. Note that you can explicitly request the two byte 12804opcode by writing 'sarl %eax'. Secondly, if you specify 'i8086', 12805'i186', or 'i286', _and_ '.code16' or '.code16gcc' then byte offset 12806conditional jumps will be promoted when necessary to a two instruction 12807sequence consisting of a conditional jump of the opposite sense around 12808an unconditional jump to the target. 12809 12810 Following the CPU architecture (but not a sub-architecture, which are 12811those starting with a dot), you may specify 'jumps' or 'nojumps' to 12812control automatic promotion of conditional jumps. 'jumps' is the 12813default, and enables jump promotion; All external jumps will be of the 12814long variety, and file-local jumps will be promoted as necessary. 12815(*note i386-Jumps::) 'nojumps' leaves external conditional jumps as byte 12816offset jumps, and warns about file-local conditional jumps that 'as' 12817promotes. Unconditional jumps are treated as for 'jumps'. 12818 12819 For example 12820 12821 .arch i8086,nojumps 12822 12823 12824File: as.info, Node: i386-ISA, Next: i386-Bugs, Prev: i386-Arch, Up: i386-Dependent 12825 128269.16.16 AMD64 ISA vs. Intel64 ISA 12827--------------------------------- 12828 12829There are some discrepancies between AMD64 and Intel64 ISAs. 12830 12831 * For 'movsxd' with 16-bit destination register, AMD64 supports 12832 32-bit source operand and Intel64 supports 16-bit source operand. 12833 12834 * For far branches (with explicit memory operand), both ISAs support 12835 32- and 16-bit operand size. Intel64 additionally supports 64-bit 12836 operand size, encoded as 'ljmpq' and 'lcallq' in AT&T syntax and 12837 with an explicit 'tbyte ptr' operand size specifier in Intel 12838 syntax. 12839 12840 * 'lfs', 'lgs', and 'lss' similarly allow for 16- and 32-bit operand 12841 size (32- and 48-bit memory operand) in both ISAs, while Intel64 12842 additionally supports 64-bit operand sise (80-bit memory operands). 12843 12844 12845File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-ISA, Up: i386-Dependent 12846 128479.16.17 AT&T Syntax bugs 12848------------------------ 12849 12850The UnixWare assembler, and probably other AT&T derived ix86 Unix 12851assemblers, generate floating point instructions with reversed source 12852and destination registers in certain cases. Unfortunately, gcc and 12853possibly many other programs use this reversed syntax, so we're stuck 12854with it. 12855 12856 For example 12857 12858 fsub %st,%st(3) 12859results in '%st(3)' being updated to '%st - %st(3)' rather than the 12860expected '%st(3) - %st'. This happens with all the non-commutative 12861arithmetic floating point operations with two register operands where 12862the source register is '%st' and the destination register is '%st(i)'. 12863 12864 12865File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 12866 128679.16.18 Notes 12868------------- 12869 12870There is some trickery concerning the 'mul' and 'imul' instructions that 12871deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies 12872(base opcode '0xf6'; extension 4 for 'mul' and 5 for 'imul') can be 12873output only in the one operand form. Thus, 'imul %ebx, %eax' does _not_ 12874select the expanding multiply; the expanding multiply would clobber the 12875'%edx' register, and this would confuse 'gcc' output. Use 'imul %ebx' 12876to get the 64-bit product in '%edx:%eax'. 12877 12878 We have added a two operand form of 'imul' when the first operand is 12879an immediate mode expression and the second operand is a register. This 12880is just a shorthand, so that, multiplying '%eax' by 69, for example, can 12881be done with 'imul $69, %eax' rather than 'imul $69, %eax, %eax'. 12882 12883 12884File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 12885 128869.17 IA-64 Dependent Features 12887============================= 12888 12889* Menu: 12890 12891* IA-64 Options:: Options 12892* IA-64 Syntax:: Syntax 12893* IA-64 Opcodes:: Opcodes 12894 12895 12896File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 12897 128989.17.1 Options 12899-------------- 12900 12901'-mconstant-gp' 12902 This option instructs the assembler to mark the resulting object 12903 file as using the "constant GP" model. With this model, it is 12904 assumed that the entire program uses a single global pointer (GP) 12905 value. Note that this option does not in any fashion affect the 12906 machine code emitted by the assembler. All it does is turn on the 12907 EF_IA_64_CONS_GP flag in the ELF file header. 12908 12909'-mauto-pic' 12910 This option instructs the assembler to mark the resulting object 12911 file as using the "constant GP without function descriptor" data 12912 model. This model is like the "constant GP" model, except that it 12913 additionally does away with function descriptors. What this means 12914 is that the address of a function refers directly to the function's 12915 code entry-point. Normally, such an address would refer to a 12916 function descriptor, which contains both the code entry-point and 12917 the GP-value needed by the function. Note that this option does 12918 not in any fashion affect the machine code emitted by the 12919 assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP 12920 flag in the ELF file header. 12921 12922'-milp32' 12923'-milp64' 12924'-mlp64' 12925'-mp64' 12926 These options select the data model. The assembler defaults to 12927 '-mlp64' (LP64 data model). 12928 12929'-mle' 12930'-mbe' 12931 These options select the byte order. The '-mle' option selects 12932 little-endian byte order (default) and '-mbe' selects big-endian 12933 byte order. Note that IA-64 machine code always uses little-endian 12934 byte order. 12935 12936'-mtune=itanium1' 12937'-mtune=itanium2' 12938 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default 12939 is ITANIUM2. 12940 12941'-munwind-check=warning' 12942'-munwind-check=error' 12943 These options control what the assembler will do when performing 12944 consistency checks on unwind directives. '-munwind-check=warning' 12945 will make the assembler issue a warning when an unwind directive 12946 check fails. This is the default. '-munwind-check=error' will 12947 make the assembler issue an error when an unwind directive check 12948 fails. 12949 12950'-mhint.b=ok' 12951'-mhint.b=warning' 12952'-mhint.b=error' 12953 These options control what the assembler will do when the 'hint.b' 12954 instruction is used. '-mhint.b=ok' will make the assembler accept 12955 'hint.b'. '-mint.b=warning' will make the assembler issue a 12956 warning when 'hint.b' is used. '-mhint.b=error' will make the 12957 assembler treat 'hint.b' as an error, which is the default. 12958 12959'-x' 12960'-xexplicit' 12961 These options turn on dependency violation checking. 12962 12963'-xauto' 12964 This option instructs the assembler to automatically insert stop 12965 bits where necessary to remove dependency violations. This is the 12966 default mode. 12967 12968'-xnone' 12969 This option turns off dependency violation checking. 12970 12971'-xdebug' 12972 This turns on debug output intended to help tracking down bugs in 12973 the dependency violation checker. 12974 12975'-xdebugn' 12976 This is a shortcut for -xnone -xdebug. 12977 12978'-xdebugx' 12979 This is a shortcut for -xexplicit -xdebug. 12980 12981 12982File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 12983 129849.17.2 Syntax 12985------------- 12986 12987The assembler syntax closely follows the IA-64 Assembly Language 12988Reference Guide. 12989 12990* Menu: 12991 12992* IA-64-Chars:: Special Characters 12993* IA-64-Regs:: Register Names 12994* IA-64-Bits:: Bit Names 12995* IA-64-Relocs:: Relocations 12996 12997 12998File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 12999 130009.17.2.1 Special Characters 13001........................... 13002 13003'//' is the line comment token. 13004 13005 ';' can be used instead of a newline to separate statements. 13006 13007 13008File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 13009 130109.17.2.2 Register Names 13011....................... 13012 13013The 128 integer registers are referred to as 'rN'. The 128 13014floating-point registers are referred to as 'fN'. The 128 application 13015registers are referred to as 'arN'. The 128 control registers are 13016referred to as 'crN'. The 64 one-bit predicate registers are referred 13017to as 'pN'. The 8 branch registers are referred to as 'bN'. In 13018addition, the assembler defines a number of aliases: 'gp' ('r1'), 'sp' 13019('r12'), 'rp' ('b0'), 'ret0' ('r8'), 'ret1' ('r9'), 'ret2' ('r10'), 13020'ret3' ('r9'), 'fargN' ('f8+N'), and 'fretN' ('f8+N'). 13021 13022 For convenience, the assembler also defines aliases for all named 13023application and control registers. For example, 'ar.bsp' refers to the 13024register backing store pointer ('ar17'). Similarly, 'cr.eoi' refers to 13025the end-of-interrupt register ('cr67'). 13026 13027 13028File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 13029 130309.17.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 13031........................................................ 13032 13033The assembler defines bit masks for each of the bits in the IA-64 13034processor status register. For example, 'psr.ic' corresponds to a value 13035of 0x2000. These masks are primarily intended for use with the 13036'ssm'/'sum' and 'rsm'/'rum' instructions, but they can be used anywhere 13037else where an integer constant is expected. 13038 13039 13040File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 13041 130429.17.2.4 Relocations 13043.................... 13044 13045In addition to the standard IA-64 relocations, the following relocations 13046are implemented by 'as': 13047 13048'@slotcount(V)' 13049 Convert the address offset V into a slot count. This pseudo 13050 function is available only on VMS. The expression V must be known 13051 at assembly time: it can't reference undefined symbols or symbols 13052 in different sections. 13053 13054 13055File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 13056 130579.17.3 Opcodes 13058-------------- 13059 13060For detailed information on the IA-64 machine instruction set, see the 13061IA-64 Architecture Handbook 13062(http://developer.intel.com/design/itanium/arch_spec.htm). 13063 13064 13065File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 13066 130679.18 IP2K Dependent Features 13068============================ 13069 13070* Menu: 13071 13072* IP2K-Opts:: IP2K Options 13073* IP2K-Syntax:: IP2K Syntax 13074 13075 13076File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent 13077 130789.18.1 IP2K Options 13079------------------- 13080 13081The Ubicom IP2K version of 'as' has a few machine dependent options: 13082 13083'-mip2022ext' 13084 'as' can assemble the extended IP2022 instructions, but it will 13085 only do so if this is specifically allowed via this command line 13086 option. 13087 13088'-mip2022' 13089 This option restores the assembler's default behaviour of not 13090 permitting the extended IP2022 instructions to be assembled. 13091 13092 13093File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent 13094 130959.18.2 IP2K Syntax 13096------------------ 13097 13098* Menu: 13099 13100* IP2K-Chars:: Special Characters 13101 13102 13103File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax 13104 131059.18.2.1 Special Characters 13106........................... 13107 13108The presence of a ';' on a line indicates the start of a comment that 13109extends to the end of the current line. 13110 13111 If a '#' appears as the first character of a line, the whole line is 13112treated as a comment, but in this case the line can also be a logical 13113line number directive (*note Comments::) or a preprocessor control 13114command (*note Preprocessing::). 13115 13116 The IP2K assembler does not currently support a line separator 13117character. 13118 13119 13120File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 13121 131229.19 LM32 Dependent Features 13123============================ 13124 13125* Menu: 13126 13127* LM32 Options:: Options 13128* LM32 Syntax:: Syntax 13129* LM32 Opcodes:: Opcodes 13130 13131 13132File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 13133 131349.19.1 Options 13135-------------- 13136 13137'-mmultiply-enabled' 13138 Enable multiply instructions. 13139 13140'-mdivide-enabled' 13141 Enable divide instructions. 13142 13143'-mbarrel-shift-enabled' 13144 Enable barrel-shift instructions. 13145 13146'-msign-extend-enabled' 13147 Enable sign extend instructions. 13148 13149'-muser-enabled' 13150 Enable user defined instructions. 13151 13152'-micache-enabled' 13153 Enable instruction cache related CSRs. 13154 13155'-mdcache-enabled' 13156 Enable data cache related CSRs. 13157 13158'-mbreak-enabled' 13159 Enable break instructions. 13160 13161'-mall-enabled' 13162 Enable all instructions and CSRs. 13163 13164 13165File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 13166 131679.19.2 Syntax 13168------------- 13169 13170* Menu: 13171 13172* LM32-Regs:: Register Names 13173* LM32-Modifiers:: Relocatable Expression Modifiers 13174* LM32-Chars:: Special Characters 13175 13176 13177File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 13178 131799.19.2.1 Register Names 13180....................... 13181 13182LM32 has 32 x 32-bit general purpose registers 'r0', 'r1', ... 'r31'. 13183 13184 The following aliases are defined: 'gp' - 'r26', 'fp' - 'r27', 'sp' - 13185'r28', 'ra' - 'r29', 'ea' - 'r30', 'ba' - 'r31'. 13186 13187 LM32 has the following Control and Status Registers (CSRs). 13188 13189'IE' 13190 Interrupt enable. 13191'IM' 13192 Interrupt mask. 13193'IP' 13194 Interrupt pending. 13195'ICC' 13196 Instruction cache control. 13197'DCC' 13198 Data cache control. 13199'CC' 13200 Cycle counter. 13201'CFG' 13202 Configuration. 13203'EBA' 13204 Exception base address. 13205'DC' 13206 Debug control. 13207'DEBA' 13208 Debug exception base address. 13209'JTX' 13210 JTAG transmit. 13211'JRX' 13212 JTAG receive. 13213'BP0' 13214 Breakpoint 0. 13215'BP1' 13216 Breakpoint 1. 13217'BP2' 13218 Breakpoint 2. 13219'BP3' 13220 Breakpoint 3. 13221'WP0' 13222 Watchpoint 0. 13223'WP1' 13224 Watchpoint 1. 13225'WP2' 13226 Watchpoint 2. 13227'WP3' 13228 Watchpoint 3. 13229 13230 13231File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax 13232 132339.19.2.2 Relocatable Expression Modifiers 13234......................................... 13235 13236The assembler supports several modifiers when using relocatable 13237addresses in LM32 instruction operands. The general syntax is the 13238following: 13239 13240 modifier(relocatable-expression) 13241 13242'lo' 13243 13244 This modifier allows you to use bits 0 through 15 of an address 13245 expression as 16 bit relocatable expression. 13246 13247'hi' 13248 13249 This modifier allows you to use bits 16 through 23 of an address 13250 expression as 16 bit relocatable expression. 13251 13252 For example 13253 13254 ori r4, r4, lo(sym+10) 13255 orhi r4, r4, hi(sym+10) 13256 13257'gp' 13258 13259 This modified creates a 16-bit relocatable expression that is the 13260 offset of the symbol from the global pointer. 13261 13262 mva r4, gp(sym) 13263 13264'got' 13265 13266 This modifier places a symbol in the GOT and creates a 16-bit 13267 relocatable expression that is the offset into the GOT of this 13268 symbol. 13269 13270 lw r4, (gp+got(sym)) 13271 13272'gotofflo16' 13273 13274 This modifier allows you to use the bits 0 through 15 of an address 13275 which is an offset from the GOT. 13276 13277'gotoffhi16' 13278 13279 This modifier allows you to use the bits 16 through 31 of an 13280 address which is an offset from the GOT. 13281 13282 orhi r4, r4, gotoffhi16(lsym) 13283 addi r4, r4, gotofflo16(lsym) 13284 13285 13286File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax 13287 132889.19.2.3 Special Characters 13289........................... 13290 13291The presence of a '#' on a line indicates the start of a comment that 13292extends to the end of the current line. Note that if a line starts with 13293a '#' character then it can also be a logical line number directive 13294(*note Comments::) or a preprocessor control command (*note 13295Preprocessing::). 13296 13297 A semicolon (';') can be used to separate multiple statements on the 13298same line. 13299 13300 13301File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 13302 133039.19.3 Opcodes 13304-------------- 13305 13306For detailed information on the LM32 machine instruction set, see 13307<http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/>. 13308 13309 'as' implements all the standard LM32 opcodes. 13310 13311 13312File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 13313 133149.20 M32C Dependent Features 13315============================ 13316 13317'as' can assemble code for several different members of the Renesas M32C 13318family. Normally the default is to assemble code for the M16C 13319microprocessor. The '-m32c' option may be used to change the default to 13320the M32C microprocessor. 13321 13322* Menu: 13323 13324* M32C-Opts:: M32C Options 13325* M32C-Syntax:: M32C Syntax 13326 13327 13328File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent 13329 133309.20.1 M32C Options 13331------------------- 13332 13333The Renesas M32C version of 'as' has these machine-dependent options: 13334 13335'-m32c' 13336 Assemble M32C instructions. 13337 13338'-m16c' 13339 Assemble M16C instructions (default). 13340 13341'-relax' 13342 Enable support for link-time relaxations. 13343 13344'-h-tick-hex' 13345 Support H'00 style hex constants in addition to 0x00 style. 13346 13347 13348File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent 13349 133509.20.2 M32C Syntax 13351------------------ 13352 13353* Menu: 13354 13355* M32C-Modifiers:: Symbolic Operand Modifiers 13356* M32C-Chars:: Special Characters 13357 13358 13359File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax 13360 133619.20.2.1 Symbolic Operand Modifiers 13362................................... 13363 13364The assembler supports several modifiers when using symbol addresses in 13365M32C instruction operands. The general syntax is the following: 13366 13367 %modifier(symbol) 13368 13369'%dsp8' 13370'%dsp16' 13371 13372 These modifiers override the assembler's assumptions about how big 13373 a symbol's address is. Normally, when it sees an operand like 13374 'sym[a0]' it assumes 'sym' may require the widest displacement 13375 field (16 bits for '-m16c', 24 bits for '-m32c'). These modifiers 13376 tell it to assume the address will fit in an 8 or 16 bit 13377 (respectively) unsigned displacement. Note that, of course, if it 13378 doesn't actually fit you will get linker errors. Example: 13379 13380 mov.w %dsp8(sym)[a0],r1 13381 mov.b #0,%dsp8(sym)[a0] 13382 13383'%hi8' 13384 13385 This modifier allows you to load bits 16 through 23 of a 24 bit 13386 address into an 8 bit register. This is useful with, for example, 13387 the M16C 'smovf' instruction, which expects a 20 bit address in 13388 'r1h' and 'a0'. Example: 13389 13390 mov.b #%hi8(sym),r1h 13391 mov.w #%lo16(sym),a0 13392 smovf.b 13393 13394'%lo16' 13395 13396 Likewise, this modifier allows you to load bits 0 through 15 of a 13397 24 bit address into a 16 bit register. 13398 13399'%hi16' 13400 13401 This modifier allows you to load bits 16 through 31 of a 32 bit 13402 address into a 16 bit register. While the M32C family only has 24 13403 bits of address space, it does support addresses in pairs of 16 bit 13404 registers (like 'a1a0' for the 'lde' instruction). This modifier 13405 is for loading the upper half in such cases. Example: 13406 13407 mov.w #%hi16(sym),a1 13408 mov.w #%lo16(sym),a0 13409 ... 13410 lde.w [a1a0],r1 13411 13412 13413File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax 13414 134159.20.2.2 Special Characters 13416........................... 13417 13418The presence of a ';' character on a line indicates the start of a 13419comment that extends to the end of that line. 13420 13421 If a '#' appears as the first character of a line, the whole line is 13422treated as a comment, but in this case the line can also be a logical 13423line number directive (*note Comments::) or a preprocessor control 13424command (*note Preprocessing::). 13425 13426 The '|' character can be used to separate statements on the same 13427line. 13428 13429 13430File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 13431 134329.21 M32R Dependent Features 13433============================ 13434 13435* Menu: 13436 13437* M32R-Opts:: M32R Options 13438* M32R-Directives:: M32R Directives 13439* M32R-Warnings:: M32R Warnings 13440 13441 13442File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 13443 134449.21.1 M32R Options 13445------------------- 13446 13447The Renesas M32R version of 'as' has a few machine dependent options: 13448 13449'-m32rx' 13450 'as' can assemble code for several different members of the Renesas 13451 M32R family. Normally the default is to assemble code for the M32R 13452 microprocessor. This option may be used to change the default to 13453 the M32RX microprocessor, which adds some more instructions to the 13454 basic M32R instruction set, and some additional parameters to some 13455 of the original instructions. 13456 13457'-m32r2' 13458 This option changes the target processor to the M32R2 13459 microprocessor. 13460 13461'-m32r' 13462 This option can be used to restore the assembler's default 13463 behaviour of assembling for the M32R microprocessor. This can be 13464 useful if the default has been changed by a previous command-line 13465 option. 13466 13467'-little' 13468 This option tells the assembler to produce little-endian code and 13469 data. The default is dependent upon how the toolchain was 13470 configured. 13471 13472'-EL' 13473 This is a synonym for _-little_. 13474 13475'-big' 13476 This option tells the assembler to produce big-endian code and 13477 data. 13478 13479'-EB' 13480 This is a synonym for _-big_. 13481 13482'-KPIC' 13483 This option specifies that the output of the assembler should be 13484 marked as position-independent code (PIC). 13485 13486'-parallel' 13487 This option tells the assembler to attempts to combine two 13488 sequential instructions into a single, parallel instruction, where 13489 it is legal to do so. 13490 13491'-no-parallel' 13492 This option disables a previously enabled _-parallel_ option. 13493 13494'-no-bitinst' 13495 This option disables the support for the extended bit-field 13496 instructions provided by the M32R2. If this support needs to be 13497 re-enabled the _-bitinst_ switch can be used to restore it. 13498 13499'-O' 13500 This option tells the assembler to attempt to optimize the 13501 instructions that it produces. This includes filling delay slots 13502 and converting sequential instructions into parallel ones. This 13503 option implies _-parallel_. 13504 13505'-warn-explicit-parallel-conflicts' 13506 Instructs 'as' to produce warning messages when questionable 13507 parallel instructions are encountered. This option is enabled by 13508 default, but 'gcc' disables it when it invokes 'as' directly. 13509 Questionable instructions are those whose behaviour would be 13510 different if they were executed sequentially. For example the code 13511 fragment 'mv r1, r2 || mv r3, r1' produces a different result from 13512 'mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then 13513 r2 into r1, whereas the later moves r2 into r1 and r3. 13514 13515'-Wp' 13516 This is a shorter synonym for the 13517 _-warn-explicit-parallel-conflicts_ option. 13518 13519'-no-warn-explicit-parallel-conflicts' 13520 Instructs 'as' not to produce warning messages when questionable 13521 parallel instructions are encountered. 13522 13523'-Wnp' 13524 This is a shorter synonym for the 13525 _-no-warn-explicit-parallel-conflicts_ option. 13526 13527'-ignore-parallel-conflicts' 13528 This option tells the assembler's to stop checking parallel 13529 instructions for constraint violations. This ability is provided 13530 for hardware vendors testing chip designs and should not be used 13531 under normal circumstances. 13532 13533'-no-ignore-parallel-conflicts' 13534 This option restores the assembler's default behaviour of checking 13535 parallel instructions to detect constraint violations. 13536 13537'-Ip' 13538 This is a shorter synonym for the _-ignore-parallel-conflicts_ 13539 option. 13540 13541'-nIp' 13542 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 13543 option. 13544 13545'-warn-unmatched-high' 13546 This option tells the assembler to produce a warning message if a 13547 '.high' pseudo op is encountered without a matching '.low' pseudo 13548 op. The presence of such an unmatched pseudo op usually indicates 13549 a programming error. 13550 13551'-no-warn-unmatched-high' 13552 Disables a previously enabled _-warn-unmatched-high_ option. 13553 13554'-Wuh' 13555 This is a shorter synonym for the _-warn-unmatched-high_ option. 13556 13557'-Wnuh' 13558 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 13559 13560 13561File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 13562 135639.21.2 M32R Directives 13564---------------------- 13565 13566The Renesas M32R version of 'as' has a few architecture specific 13567directives: 13568 13569'low EXPRESSION' 13570 The 'low' directive computes the value of its expression and places 13571 the lower 16-bits of the result into the immediate-field of the 13572 instruction. For example: 13573 13574 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 13575 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 13576 13577'high EXPRESSION' 13578 The 'high' directive computes the value of its expression and 13579 places the upper 16-bits of the result into the immediate-field of 13580 the instruction. For example: 13581 13582 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 13583 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 13584 13585'shigh EXPRESSION' 13586 The 'shigh' directive is very similar to the 'high' directive. It 13587 also computes the value of its expression and places the upper 13588 16-bits of the result into the immediate-field of the instruction. 13589 The difference is that 'shigh' also checks to see if the lower 13590 16-bits could be interpreted as a signed number, and if so it 13591 assumes that a borrow will occur from the upper-16 bits. To 13592 compensate for this the 'shigh' directive pre-biases the upper 16 13593 bit value by adding one to it. For example: 13594 13595 For example: 13596 13597 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 13598 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 13599 13600 In the second example the lower 16-bits are 0x8000. If these are 13601 treated as a signed value and sign extended to 32-bits then the 13602 value becomes 0xffff8000. If this value is then added to 13603 0x00010000 then the result is 0x00008000. 13604 13605 This behaviour is to allow for the different semantics of the 'or3' 13606 and 'add3' instructions. The 'or3' instruction treats its 16-bit 13607 immediate argument as unsigned whereas the 'add3' treats its 16-bit 13608 immediate as a signed value. So for example: 13609 13610 seth r0, #shigh(0x00008000) 13611 add3 r0, r0, #low(0x00008000) 13612 13613 Produces the correct result in r0, whereas: 13614 13615 seth r0, #shigh(0x00008000) 13616 or3 r0, r0, #low(0x00008000) 13617 13618 Stores 0xffff8000 into r0. 13619 13620 Note - the 'shigh' directive does not know where in the assembly 13621 source code the lower 16-bits of the value are going set, so it 13622 cannot check to make sure that an 'or3' instruction is being used 13623 rather than an 'add3' instruction. It is up to the programmer to 13624 make sure that correct directives are used. 13625 13626'.m32r' 13627 The directive performs a similar thing as the _-m32r_ command line 13628 option. It tells the assembler to only accept M32R instructions 13629 from now on. An instructions from later M32R architectures are 13630 refused. 13631 13632'.m32rx' 13633 The directive performs a similar thing as the _-m32rx_ command line 13634 option. It tells the assembler to start accepting the extra 13635 instructions in the M32RX ISA as well as the ordinary M32R ISA. 13636 13637'.m32r2' 13638 The directive performs a similar thing as the _-m32r2_ command line 13639 option. It tells the assembler to start accepting the extra 13640 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 13641 13642'.little' 13643 The directive performs a similar thing as the _-little_ command 13644 line option. It tells the assembler to start producing 13645 little-endian code and data. This option should be used with care 13646 as producing mixed-endian binary files is fraught with danger. 13647 13648'.big' 13649 The directive performs a similar thing as the _-big_ command line 13650 option. It tells the assembler to start producing big-endian code 13651 and data. This option should be used with care as producing 13652 mixed-endian binary files is fraught with danger. 13653 13654 13655File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 13656 136579.21.3 M32R Warnings 13658-------------------- 13659 13660There are several warning and error messages that can be produced by 13661'as' which are specific to the M32R: 13662 13663'output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' 13664 This message is only produced if warnings for explicit parallel 13665 conflicts have been enabled. It indicates that the assembler has 13666 encountered a parallel instruction in which the destination 13667 register of the left hand instruction is used as an input register 13668 in the right hand instruction. For example in this code fragment 13669 'mv r1, r2 || neg r3, r1' register r1 is the destination of the 13670 move instruction and the input to the neg instruction. 13671 13672'output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' 13673 This message is only produced if warnings for explicit parallel 13674 conflicts have been enabled. It indicates that the assembler has 13675 encountered a parallel instruction in which the destination 13676 register of the right hand instruction is used as an input register 13677 in the left hand instruction. For example in this code fragment 13678 'mv r1, r2 || neg r2, r3' register r2 is the destination of the neg 13679 instruction and the input to the move instruction. 13680 13681'instruction '...' is for the M32RX only' 13682 This message is produced when the assembler encounters an 13683 instruction which is only supported by the M32Rx processor, and the 13684 '-m32rx' command-line flag has not been specified to allow assembly 13685 of such instructions. 13686 13687'unknown instruction '...'' 13688 This message is produced when the assembler encounters an 13689 instruction which it does not recognize. 13690 13691'only the NOP instruction can be issued in parallel on the m32r' 13692 This message is produced when the assembler encounters a parallel 13693 instruction which does not involve a NOP instruction and the 13694 '-m32rx' command-line flag has not been specified. Only the M32Rx 13695 processor is able to execute two instructions in parallel. 13696 13697'instruction '...' cannot be executed in parallel.' 13698 This message is produced when the assembler encounters a parallel 13699 instruction which is made up of one or two instructions which 13700 cannot be executed in parallel. 13701 13702'Instructions share the same execution pipeline' 13703 This message is produced when the assembler encounters a parallel 13704 instruction whose components both use the same execution pipeline. 13705 13706'Instructions write to the same destination register.' 13707 This message is produced when the assembler encounters a parallel 13708 instruction where both components attempt to modify the same 13709 register. For example these code fragments will produce this 13710 message: 'mv r1, r2 || neg r1, r3' 'jl r0 || mv r14, r1' 'st r2, 13711 @-r1 || mv r1, r3' 'mv r1, r2 || ld r0, @r1+' 'cmp r1, r2 || addx 13712 r3, r4' (Both write to the condition bit) 13713 13714 13715File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 13716 137179.22 M680x0 Dependent Features 13718============================== 13719 13720* Menu: 13721 13722* M68K-Opts:: M680x0 Options 13723* M68K-Syntax:: Syntax 13724* M68K-Moto-Syntax:: Motorola Syntax 13725* M68K-Float:: Floating Point 13726* M68K-Directives:: 680x0 Machine Directives 13727* M68K-opcodes:: Opcodes 13728 13729 13730File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 13731 137329.22.1 M680x0 Options 13733--------------------- 13734 13735The Motorola 680x0 version of 'as' has a few machine dependent options: 13736 13737'-march=ARCHITECTURE' 13738 This option specifies a target architecture. The following 13739 architectures are recognized: '68000', '68010', '68020', '68030', 13740 '68040', '68060', 'cpu32', 'isaa', 'isaaplus', 'isab', 'isac' and 13741 'cfv4e'. 13742 13743'-mcpu=CPU' 13744 This option specifies a target cpu. When used in conjunction with 13745 the '-march' option, the cpu must be within the specified 13746 architecture. Also, the generic features of the architecture are 13747 used for instruction generation, rather than those of the specific 13748 chip. 13749 13750'-m[no-]68851' 13751'-m[no-]68881' 13752'-m[no-]div' 13753'-m[no-]usp' 13754'-m[no-]float' 13755'-m[no-]mac' 13756'-m[no-]emac' 13757 13758 Enable or disable various architecture specific features. If a 13759 chip or architecture by default supports an option (for instance 13760 '-march=isaaplus' includes the '-mdiv' option), explicitly 13761 disabling the option will override the default. 13762 13763'-l' 13764 You can use the '-l' option to shorten the size of references to 13765 undefined symbols. If you do not use the '-l' option, references 13766 to undefined symbols are wide enough for a full 'long' (32 bits). 13767 (Since 'as' cannot know where these symbols end up, 'as' can only 13768 allocate space for the linker to fill in later. Since 'as' does 13769 not know how far away these symbols are, it allocates as much space 13770 as it can.) If you use this option, the references are only one 13771 word wide (16 bits). This may be useful if you want the object 13772 file to be as small as possible, and you know that the relevant 13773 symbols are always less than 17 bits away. 13774 13775'--register-prefix-optional' 13776 For some configurations, especially those where the compiler 13777 normally does not prepend an underscore to the names of user 13778 variables, the assembler requires a '%' before any use of a 13779 register name. This is intended to let the assembler distinguish 13780 between C variables and functions named 'a0' through 'a7', and so 13781 on. The '%' is always accepted, but is not required for certain 13782 configurations, notably 'sun3'. The '--register-prefix-optional' 13783 option may be used to permit omitting the '%' even for 13784 configurations for which it is normally required. If this is done, 13785 it will generally be impossible to refer to C variables and 13786 functions with the same names as register names. 13787 13788'--bitwise-or' 13789 Normally the character '|' is treated as a comment character, which 13790 means that it can not be used in expressions. The '--bitwise-or' 13791 option turns '|' into a normal character. In this mode, you must 13792 either use C style comments, or start comments with a '#' character 13793 at the beginning of a line. 13794 13795'--base-size-default-16 --base-size-default-32' 13796 If you use an addressing mode with a base register without 13797 specifying the size, 'as' will normally use the full 32 bit value. 13798 For example, the addressing mode '%a0@(%d0)' is equivalent to 13799 '%a0@(%d0:l)'. You may use the '--base-size-default-16' option to 13800 tell 'as' to default to using the 16 bit value. In this case, 13801 '%a0@(%d0)' is equivalent to '%a0@(%d0:w)'. You may use the 13802 '--base-size-default-32' option to restore the default behaviour. 13803 13804'--disp-size-default-16 --disp-size-default-32' 13805 If you use an addressing mode with a displacement, and the value of 13806 the displacement is not known, 'as' will normally assume that the 13807 value is 32 bits. For example, if the symbol 'disp' has not been 13808 defined, 'as' will assemble the addressing mode '%a0@(disp,%d0)' as 13809 though 'disp' is a 32 bit value. You may use the 13810 '--disp-size-default-16' option to tell 'as' to instead assume that 13811 the displacement is 16 bits. In this case, 'as' will assemble 13812 '%a0@(disp,%d0)' as though 'disp' is a 16 bit value. You may use 13813 the '--disp-size-default-32' option to restore the default 13814 behaviour. 13815 13816'--pcrel' 13817 Always keep branches PC-relative. In the M680x0 architecture all 13818 branches are defined as PC-relative. However, on some processors 13819 they are limited to word displacements maximum. When 'as' needs a 13820 long branch that is not available, it normally emits an absolute 13821 jump instead. This option disables this substitution. When this 13822 option is given and no long branches are available, only word 13823 branches will be emitted. An error message will be generated if a 13824 word branch cannot reach its target. This option has no effect on 13825 68020 and other processors that have long branches. *note Branch 13826 Improvement: M68K-Branch. 13827 13828'-m68000' 13829 'as' can assemble code for several different members of the 13830 Motorola 680x0 family. The default depends upon how 'as' was 13831 configured when it was built; normally, the default is to assemble 13832 code for the 68020 microprocessor. The following options may be 13833 used to change the default. These options control which 13834 instructions and addressing modes are permitted. The members of 13835 the 680x0 family are very similar. For detailed information about 13836 the differences, see the Motorola manuals. 13837 13838 '-m68000' 13839 '-m68ec000' 13840 '-m68hc000' 13841 '-m68hc001' 13842 '-m68008' 13843 '-m68302' 13844 '-m68306' 13845 '-m68307' 13846 '-m68322' 13847 '-m68356' 13848 Assemble for the 68000. '-m68008', '-m68302', and so on are 13849 synonyms for '-m68000', since the chips are the same from the 13850 point of view of the assembler. 13851 13852 '-m68010' 13853 Assemble for the 68010. 13854 13855 '-m68020' 13856 '-m68ec020' 13857 Assemble for the 68020. This is normally the default. 13858 13859 '-m68030' 13860 '-m68ec030' 13861 Assemble for the 68030. 13862 13863 '-m68040' 13864 '-m68ec040' 13865 Assemble for the 68040. 13866 13867 '-m68060' 13868 '-m68ec060' 13869 Assemble for the 68060. 13870 13871 '-mcpu32' 13872 '-m68330' 13873 '-m68331' 13874 '-m68332' 13875 '-m68333' 13876 '-m68334' 13877 '-m68336' 13878 '-m68340' 13879 '-m68341' 13880 '-m68349' 13881 '-m68360' 13882 Assemble for the CPU32 family of chips. 13883 13884 '-m5200' 13885 '-m5202' 13886 '-m5204' 13887 '-m5206' 13888 '-m5206e' 13889 '-m521x' 13890 '-m5249' 13891 '-m528x' 13892 '-m5307' 13893 '-m5407' 13894 '-m547x' 13895 '-m548x' 13896 '-mcfv4' 13897 '-mcfv4e' 13898 Assemble for the ColdFire family of chips. 13899 13900 '-m68881' 13901 '-m68882' 13902 Assemble 68881 floating point instructions. This is the 13903 default for the 68020, 68030, and the CPU32. The 68040 and 13904 68060 always support floating point instructions. 13905 13906 '-mno-68881' 13907 Do not assemble 68881 floating point instructions. This is 13908 the default for 68000 and the 68010. The 68040 and 68060 13909 always support floating point instructions, even if this 13910 option is used. 13911 13912 '-m68851' 13913 Assemble 68851 MMU instructions. This is the default for the 13914 68020, 68030, and 68060. The 68040 accepts a somewhat 13915 different set of MMU instructions; '-m68851' and '-m68040' 13916 should not be used together. 13917 13918 '-mno-68851' 13919 Do not assemble 68851 MMU instructions. This is the default 13920 for the 68000, 68010, and the CPU32. The 68040 accepts a 13921 somewhat different set of MMU instructions. 13922 13923 13924File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 13925 139269.22.2 Syntax 13927------------- 13928 13929This syntax for the Motorola 680x0 was developed at MIT. 13930 13931 The 680x0 version of 'as' uses instructions names and syntax 13932compatible with the Sun assembler. Intervening periods are ignored; for 13933example, 'movl' is equivalent to 'mov.l'. 13934 13935 In the following table APC stands for any of the address registers 13936('%a0' through '%a7'), the program counter ('%pc'), the zero-address 13937relative to the program counter ('%zpc'), a suppressed address register 13938('%za0' through '%za7'), or it may be omitted entirely. The use of SIZE 13939means one of 'w' or 'l', and it may be omitted, along with the leading 13940colon, unless a scale is also specified. The use of SCALE means one of 13941'1', '2', '4', or '8', and it may always be omitted along with the 13942leading colon. 13943 13944 The following addressing modes are understood: 13945"Immediate" 13946 '#NUMBER' 13947 13948"Data Register" 13949 '%d0' through '%d7' 13950 13951"Address Register" 13952 '%a0' through '%a7' 13953 '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is 13954 also known as '%fp', the Frame Pointer. 13955 13956"Address Register Indirect" 13957 '%a0@' through '%a7@' 13958 13959"Address Register Postincrement" 13960 '%a0@+' through '%a7@+' 13961 13962"Address Register Predecrement" 13963 '%a0@-' through '%a7@-' 13964 13965"Indirect Plus Offset" 13966 'APC@(NUMBER)' 13967 13968"Index" 13969 'APC@(NUMBER,REGISTER:SIZE:SCALE)' 13970 13971 The NUMBER may be omitted. 13972 13973"Postindex" 13974 'APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' 13975 13976 The ONUMBER or the REGISTER, but not both, may be omitted. 13977 13978"Preindex" 13979 'APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' 13980 13981 The NUMBER may be omitted. Omitting the REGISTER produces the 13982 Postindex addressing mode. 13983 13984"Absolute" 13985 'SYMBOL', or 'DIGITS', optionally followed by ':b', ':w', or ':l'. 13986 13987 13988File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 13989 139909.22.3 Motorola Syntax 13991---------------------- 13992 13993The standard Motorola syntax for this chip differs from the syntax 13994already discussed (*note Syntax: M68K-Syntax.). 'as' can accept 13995Motorola syntax for operands, even if MIT syntax is used for other 13996operands in the same instruction. The two kinds of syntax are fully 13997compatible. 13998 13999 In the following table APC stands for any of the address registers 14000('%a0' through '%a7'), the program counter ('%pc'), the zero-address 14001relative to the program counter ('%zpc'), or a suppressed address 14002register ('%za0' through '%za7'). The use of SIZE means one of 'w' or 14003'l', and it may always be omitted along with the leading dot. The use 14004of SCALE means one of '1', '2', '4', or '8', and it may always be 14005omitted along with the leading asterisk. 14006 14007 The following additional addressing modes are understood: 14008 14009"Address Register Indirect" 14010 '(%a0)' through '(%a7)' 14011 '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is 14012 also known as '%fp', the Frame Pointer. 14013 14014"Address Register Postincrement" 14015 '(%a0)+' through '(%a7)+' 14016 14017"Address Register Predecrement" 14018 '-(%a0)' through '-(%a7)' 14019 14020"Indirect Plus Offset" 14021 'NUMBER(%A0)' through 'NUMBER(%A7)', or 'NUMBER(%PC)'. 14022 14023 The NUMBER may also appear within the parentheses, as in 14024 '(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted 14025 (with an address register, omitting the NUMBER produces Address 14026 Register Indirect mode). 14027 14028"Index" 14029 'NUMBER(APC,REGISTER.SIZE*SCALE)' 14030 14031 The NUMBER may be omitted, or it may appear within the parentheses. 14032 The APC may be omitted. The REGISTER and the APC may appear in 14033 either order. If both APC and REGISTER are address registers, and 14034 the SIZE and SCALE are omitted, then the first register is taken as 14035 the base register, and the second as the index register. 14036 14037"Postindex" 14038 '([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' 14039 14040 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 14041 NUMBER or the APC may be omitted, but not both. 14042 14043"Preindex" 14044 '([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' 14045 14046 The NUMBER, or the APC, or the REGISTER, or any two of them, may be 14047 omitted. The ONUMBER may be omitted. The REGISTER and the APC may 14048 appear in either order. If both APC and REGISTER are address 14049 registers, and the SIZE and SCALE are omitted, then the first 14050 register is taken as the base register, and the second as the index 14051 register. 14052 14053 14054File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 14055 140569.22.4 Floating Point 14057--------------------- 14058 14059Packed decimal (P) format floating literals are not supported. Feel 14060free to add the code! 14061 14062 The floating point formats generated by directives are these. 14063 14064'.float' 14065 'Single' precision floating point constants. 14066 14067'.double' 14068 'Double' precision floating point constants. 14069 14070'.extend' 14071'.ldouble' 14072 'Extended' precision ('long double') floating point constants. 14073 14074 14075File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 14076 140779.22.5 680x0 Machine Directives 14078------------------------------- 14079 14080In order to be compatible with the Sun assembler the 680x0 assembler 14081understands the following directives. 14082 14083'.data1' 14084 This directive is identical to a '.data 1' directive. 14085 14086'.data2' 14087 This directive is identical to a '.data 2' directive. 14088 14089'.even' 14090 This directive is a special case of the '.align' directive; it 14091 aligns the output to an even byte boundary. 14092 14093'.skip' 14094 This directive is identical to a '.space' directive. 14095 14096'.arch NAME' 14097 Select the target architecture and extension features. Valid 14098 values for NAME are the same as for the '-march' command-line 14099 option. This directive cannot be specified after any instructions 14100 have been assembled. If it is given multiple times, or in 14101 conjunction with the '-march' option, all uses must be for the same 14102 architecture and extension set. 14103 14104'.cpu NAME' 14105 Select the target cpu. Valid values for NAME are the same as for 14106 the '-mcpu' command-line option. This directive cannot be 14107 specified after any instructions have been assembled. If it is 14108 given multiple times, or in conjunction with the '-mopt' option, 14109 all uses must be for the same cpu. 14110 14111 14112File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 14113 141149.22.6 Opcodes 14115-------------- 14116 14117* Menu: 14118 14119* M68K-Branch:: Branch Improvement 14120* M68K-Chars:: Special Characters 14121 14122 14123File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 14124 141259.22.6.1 Branch Improvement 14126........................... 14127 14128Certain pseudo opcodes are permitted for branch instructions. They 14129expand to the shortest branch instruction that reach the target. 14130Generally these mnemonics are made by substituting 'j' for 'b' at the 14131start of a Motorola mnemonic. 14132 14133 The following table summarizes the pseudo-operations. A '*' flags 14134cases that are more fully described after the table: 14135 14136 Displacement 14137 +------------------------------------------------------------ 14138 | 68020 68000/10, not PC-relative OK 14139 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 14140 +------------------------------------------------------------ 14141 jbsr |bsrs bsrw bsrl jsr 14142 jra |bras braw bral jmp 14143 * jXX |bXXs bXXw bXXl bNXs;jmp 14144 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 14145 fjXX | N/A fbXXw fbXXl N/A 14146 14147 XX: condition 14148 NX: negative of condition XX 14149 14150 '*'--see full description below 14151 '**'--this expansion mode is disallowed by '--pcrel' 14152 14153'jbsr' 14154'jra' 14155 These are the simplest jump pseudo-operations; they always map to 14156 one particular machine instruction, depending on the displacement 14157 to the branch target. This instruction will be a byte or word 14158 branch is that is sufficient. Otherwise, a long branch will be 14159 emitted if available. If no long branches are available and the 14160 '--pcrel' option is not given, an absolute long jump will be 14161 emitted instead. If no long branches are available, the '--pcrel' 14162 option is given, and a word branch cannot reach the target, an 14163 error message is generated. 14164 14165 In addition to standard branch operands, 'as' allows these 14166 pseudo-operations to have all operands that are allowed for jsr and 14167 jmp, substituting these instructions if the operand given is not 14168 valid for a branch instruction. 14169 14170'jXX' 14171 Here, 'jXX' stands for an entire family of pseudo-operations, where 14172 XX is a conditional branch or condition-code test. The full list 14173 of pseudo-ops in this family is: 14174 jhi jls jcc jcs jne jeq jvc 14175 jvs jpl jmi jge jlt jgt jle 14176 14177 Usually, each of these pseudo-operations expands to a single branch 14178 instruction. However, if a word branch is not sufficient, no long 14179 branches are available, and the '--pcrel' option is not given, 'as' 14180 issues a longer code fragment in terms of NX, the opposite 14181 condition to XX. For example, under these conditions: 14182 jXX foo 14183 gives 14184 bNXs oof 14185 jmp foo 14186 oof: 14187 14188'dbXX' 14189 The full family of pseudo-operations covered here is 14190 dbhi dbls dbcc dbcs dbne dbeq dbvc 14191 dbvs dbpl dbmi dbge dblt dbgt dble 14192 dbf dbra dbt 14193 14194 Motorola 'dbXX' instructions allow word displacements only. When a 14195 word displacement is sufficient, each of these pseudo-operations 14196 expands to the corresponding Motorola instruction. When a word 14197 displacement is not sufficient and long branches are available, 14198 when the source reads 'dbXX foo', 'as' emits 14199 dbXX oo1 14200 bras oo2 14201 oo1:bral foo 14202 oo2: 14203 14204 If, however, long branches are not available and the '--pcrel' 14205 option is not given, 'as' emits 14206 dbXX oo1 14207 bras oo2 14208 oo1:jmp foo 14209 oo2: 14210 14211'fjXX' 14212 This family includes 14213 fjne fjeq fjge fjlt fjgt fjle fjf 14214 fjt fjgl fjgle fjnge fjngl fjngle fjngt 14215 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 14216 fjor fjseq fjsf fjsne fjst fjueq fjuge 14217 fjugt fjule fjult fjun 14218 14219 Each of these pseudo-operations always expands to a single Motorola 14220 coprocessor branch instruction, word or long. All Motorola 14221 coprocessor branch instructions allow both word and long 14222 displacements. 14223 14224 14225File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 14226 142279.22.6.2 Special Characters 14228........................... 14229 14230Line comments are introduced by the '|' character appearing anywhere on 14231a line, unless the '--bitwise-or' command-line option has been 14232specified. 14233 14234 An asterisk ('*') as the first character on a line marks the start of 14235a line comment as well. 14236 14237 A hash character ('#') as the first character on a line also marks 14238the start of a line comment, but in this case it could also be a logical 14239line number directive (*note Comments::) or a preprocessor control 14240command (*note Preprocessing::). If the hash character appears 14241elsewhere on a line it is used to introduce an immediate value. (This 14242is for compatibility with Sun's assembler). 14243 14244 Multiple statements on the same line can appear if they are separated 14245by the ';' character. 14246 14247 14248File: as.info, Node: M68HC11-Dependent, Next: S12Z-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 14249 142509.23 M68HC11 and M68HC12 Dependent Features 14251=========================================== 14252 14253* Menu: 14254 14255* M68HC11-Opts:: M68HC11 and M68HC12 Options 14256* M68HC11-Syntax:: Syntax 14257* M68HC11-Modifiers:: Symbolic Operand Modifiers 14258* M68HC11-Directives:: Assembler Directives 14259* M68HC11-Float:: Floating Point 14260* M68HC11-opcodes:: Opcodes 14261 14262 14263File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 14264 142659.23.1 M68HC11 and M68HC12 Options 14266---------------------------------- 14267 14268The Motorola 68HC11 and 68HC12 version of 'as' have a few machine 14269dependent options. 14270 14271'-m68hc11' 14272 This option switches the assembler into the M68HC11 mode. In this 14273 mode, the assembler only accepts 68HC11 operands and mnemonics. It 14274 produces code for the 68HC11. 14275 14276'-m68hc12' 14277 This option switches the assembler into the M68HC12 mode. In this 14278 mode, the assembler also accepts 68HC12 operands and mnemonics. It 14279 produces code for the 68HC12. A few 68HC11 instructions are 14280 replaced by some 68HC12 instructions as recommended by Motorola 14281 specifications. 14282 14283'-m68hcs12' 14284 This option switches the assembler into the M68HCS12 mode. This 14285 mode is similar to '-m68hc12' but specifies to assemble for the 14286 68HCS12 series. The only difference is on the assembling of the 14287 'movb' and 'movw' instruction when a PC-relative operand is used. 14288 14289'-mm9s12x' 14290 This option switches the assembler into the M9S12X mode. This mode 14291 is similar to '-m68hc12' but specifies to assemble for the S12X 14292 series which is a superset of the HCS12. 14293 14294'-mm9s12xg' 14295 This option switches the assembler into the XGATE mode for the RISC 14296 co-processor featured on some S12X-family chips. 14297 14298'--xgate-ramoffset' 14299 This option instructs the linker to offset RAM addresses from S12X 14300 address space into XGATE address space. 14301 14302'-mshort' 14303 This option controls the ABI and indicates to use a 16-bit integer 14304 ABI. It has no effect on the assembled instructions. This is the 14305 default. 14306 14307'-mlong' 14308 This option controls the ABI and indicates to use a 32-bit integer 14309 ABI. 14310 14311'-mshort-double' 14312 This option controls the ABI and indicates to use a 32-bit float 14313 ABI. This is the default. 14314 14315'-mlong-double' 14316 This option controls the ABI and indicates to use a 64-bit float 14317 ABI. 14318 14319'--strict-direct-mode' 14320 You can use the '--strict-direct-mode' option to disable the 14321 automatic translation of direct page mode addressing into extended 14322 mode when the instruction does not support direct mode. For 14323 example, the 'clr' instruction does not support direct page mode 14324 addressing. When it is used with the direct page mode, 'as' will 14325 ignore it and generate an absolute addressing. This option 14326 prevents 'as' from doing this, and the wrong usage of the direct 14327 page mode will raise an error. 14328 14329'--short-branches' 14330 The '--short-branches' option turns off the translation of relative 14331 branches into absolute branches when the branch offset is out of 14332 range. By default 'as' transforms the relative branch ('bsr', 14333 'bgt', 'bge', 'beq', 'bne', 'ble', 'blt', 'bhi', 'bcc', 'bls', 14334 'bcs', 'bmi', 'bvs', 'bvs', 'bra') into an absolute branch when the 14335 offset is out of the -128 .. 127 range. In that case, the 'bsr' 14336 instruction is translated into a 'jsr', the 'bra' instruction is 14337 translated into a 'jmp' and the conditional branches instructions 14338 are inverted and followed by a 'jmp'. This option disables these 14339 translations and 'as' will generate an error if a relative branch 14340 is out of range. This option does not affect the optimization 14341 associated to the 'jbra', 'jbsr' and 'jbXX' pseudo opcodes. 14342 14343'--force-long-branches' 14344 The '--force-long-branches' option forces the translation of 14345 relative branches into absolute branches. This option does not 14346 affect the optimization associated to the 'jbra', 'jbsr' and 'jbXX' 14347 pseudo opcodes. 14348 14349'--print-insn-syntax' 14350 You can use the '--print-insn-syntax' option to obtain the syntax 14351 description of the instruction when an error is detected. 14352 14353'--print-opcodes' 14354 The '--print-opcodes' option prints the list of all the 14355 instructions with their syntax. The first item of each line 14356 represents the instruction name and the rest of the line indicates 14357 the possible operands for that instruction. The list is printed in 14358 alphabetical order. Once the list is printed 'as' exits. 14359 14360'--generate-example' 14361 The '--generate-example' option is similar to '--print-opcodes' but 14362 it generates an example for each instruction instead. 14363 14364 14365File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 14366 143679.23.2 Syntax 14368------------- 14369 14370In the M68HC11 syntax, the instruction name comes first and it may be 14371followed by one or several operands (up to three). Operands are 14372separated by comma (','). In the normal mode, 'as' will complain if too 14373many operands are specified for a given instruction. In the MRI mode 14374(turned on with '-M' option), it will treat them as comments. Example: 14375 14376 inx 14377 lda #23 14378 bset 2,x #4 14379 brclr *bot #8 foo 14380 14381 The presence of a ';' character or a '!' character anywhere on a line 14382indicates the start of a comment that extends to the end of that line. 14383 14384 A '*' or a '#' character at the start of a line also introduces a 14385line comment, but these characters do not work elsewhere on the line. 14386If the first character of the line is a '#' then as well as starting a 14387comment, the line could also be logical line number directive (*note 14388Comments::) or a preprocessor control command (*note Preprocessing::). 14389 14390 The M68HC11 assembler does not currently support a line separator 14391character. 14392 14393 The following addressing modes are understood for 68HC11 and 68HC12: 14394"Immediate" 14395 '#NUMBER' 14396 14397"Address Register" 14398 'NUMBER,X', 'NUMBER,Y' 14399 14400 The NUMBER may be omitted in which case 0 is assumed. 14401 14402"Direct Addressing mode" 14403 '*SYMBOL', or '*DIGITS' 14404 14405"Absolute" 14406 'SYMBOL', or 'DIGITS' 14407 14408 The M68HC12 has other more complex addressing modes. All of them are 14409supported and they are represented below: 14410 14411"Constant Offset Indexed Addressing Mode" 14412 'NUMBER,REG' 14413 14414 The NUMBER may be omitted in which case 0 is assumed. The register 14415 can be either 'X', 'Y', 'SP' or 'PC'. The assembler will use the 14416 smaller post-byte definition according to the constant value (5-bit 14417 constant offset, 9-bit constant offset or 16-bit constant offset). 14418 If the constant is not known by the assembler it will use the 14419 16-bit constant offset post-byte and the value will be resolved at 14420 link time. 14421 14422"Offset Indexed Indirect" 14423 '[NUMBER,REG]' 14424 14425 The register can be either 'X', 'Y', 'SP' or 'PC'. 14426 14427"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 14428 'NUMBER,-REG' 'NUMBER,+REG' 'NUMBER,REG-' 'NUMBER,REG+' 14429 14430 The number must be in the range '-8'..'+8' and must not be 0. The 14431 register can be either 'X', 'Y', 'SP' or 'PC'. 14432 14433"Accumulator Offset" 14434 'ACC,REG' 14435 14436 The accumulator register can be either 'A', 'B' or 'D'. The 14437 register can be either 'X', 'Y', 'SP' or 'PC'. 14438 14439"Accumulator D offset indexed-indirect" 14440 '[D,REG]' 14441 14442 The register can be either 'X', 'Y', 'SP' or 'PC'. 14443 14444 For example: 14445 14446 ldab 1024,sp 14447 ldd [10,x] 14448 orab 3,+x 14449 stab -2,y- 14450 ldx a,pc 14451 sty [d,sp] 14452 14453 14454File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 14455 144569.23.3 Symbolic Operand Modifiers 14457--------------------------------- 14458 14459The assembler supports several modifiers when using symbol addresses in 1446068HC11 and 68HC12 instruction operands. The general syntax is the 14461following: 14462 14463 %modifier(symbol) 14464 14465'%addr' 14466 This modifier indicates to the assembler and linker to use the 14467 16-bit physical address corresponding to the symbol. This is 14468 intended to be used on memory window systems to map a symbol in the 14469 memory bank window. If the symbol is in a memory expansion part, 14470 the physical address corresponds to the symbol address within the 14471 memory bank window. If the symbol is not in a memory expansion 14472 part, this is the symbol address (using or not using the %addr 14473 modifier has no effect in that case). 14474 14475'%page' 14476 This modifier indicates to use the memory page number corresponding 14477 to the symbol. If the symbol is in a memory expansion part, its 14478 page number is computed by the linker as a number used to map the 14479 page containing the symbol in the memory bank window. If the 14480 symbol is not in a memory expansion part, the page number is 0. 14481 14482'%hi' 14483 This modifier indicates to use the 8-bit high part of the physical 14484 address of the symbol. 14485 14486'%lo' 14487 This modifier indicates to use the 8-bit low part of the physical 14488 address of the symbol. 14489 14490 For example a 68HC12 call to a function 'foo_example' stored in 14491memory expansion part could be written as follows: 14492 14493 call %addr(foo_example),%page(foo_example) 14494 14495 and this is equivalent to 14496 14497 call foo_example 14498 14499 And for 68HC11 it could be written as follows: 14500 14501 ldab #%page(foo_example) 14502 stab _page_switch 14503 jsr %addr(foo_example) 14504 14505 14506File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 14507 145089.23.4 Assembler Directives 14509--------------------------- 14510 14511The 68HC11 and 68HC12 version of 'as' have the following specific 14512assembler directives: 14513 14514'.relax' 14515 The relax directive is used by the 'GNU Compiler' to emit a 14516 specific relocation to mark a group of instructions for linker 14517 relaxation. The sequence of instructions within the group must be 14518 known to the linker so that relaxation can be performed. 14519 14520'.mode [mshort|mlong|mshort-double|mlong-double]' 14521 This directive specifies the ABI. It overrides the '-mshort', 14522 '-mlong', '-mshort-double' and '-mlong-double' options. 14523 14524'.far SYMBOL' 14525 This directive marks the symbol as a 'far' symbol meaning that it 14526 uses a 'call/rtc' calling convention as opposed to 'jsr/rts'. 14527 During a final link, the linker will identify references to the 14528 'far' symbol and will verify the proper calling convention. 14529 14530'.interrupt SYMBOL' 14531 This directive marks the symbol as an interrupt entry point. This 14532 information is then used by the debugger to correctly unwind the 14533 frame across interrupts. 14534 14535'.xrefb SYMBOL' 14536 This directive is defined for compatibility with the 'Specification 14537 for Motorola 8 and 16-Bit Assembly Language Input Standard' and is 14538 ignored. 14539 14540 14541File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 14542 145439.23.5 Floating Point 14544--------------------- 14545 14546Packed decimal (P) format floating literals are not supported. Feel 14547free to add the code! 14548 14549 The floating point formats generated by directives are these. 14550 14551'.float' 14552 'Single' precision floating point constants. 14553 14554'.double' 14555 'Double' precision floating point constants. 14556 14557'.extend' 14558'.ldouble' 14559 'Extended' precision ('long double') floating point constants. 14560 14561 14562File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 14563 145649.23.6 Opcodes 14565-------------- 14566 14567* Menu: 14568 14569* M68HC11-Branch:: Branch Improvement 14570 14571 14572File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 14573 145749.23.6.1 Branch Improvement 14575........................... 14576 14577Certain pseudo opcodes are permitted for branch instructions. They 14578expand to the shortest branch instruction that reach the target. 14579Generally these mnemonics are made by prepending 'j' to the start of 14580Motorola mnemonic. These pseudo opcodes are not affected by the 14581'--short-branches' or '--force-long-branches' options. 14582 14583 The following table summarizes the pseudo-operations. 14584 14585 Displacement Width 14586 +-------------------------------------------------------------+ 14587 | Options | 14588 | --short-branches --force-long-branches | 14589 +--------------------------+----------------------------------+ 14590 Op |BYTE WORD | BYTE WORD | 14591 +--------------------------+----------------------------------+ 14592 bsr | bsr <pc-rel> <error> | jsr <abs> | 14593 bra | bra <pc-rel> <error> | jmp <abs> | 14594 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 14595 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 14596 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 14597 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 14598 | jmp <abs> | | 14599 +--------------------------+----------------------------------+ 14600 XX: condition 14601 NX: negative of condition XX 14602 14603 14604'jbsr' 14605'jbra' 14606 These are the simplest jump pseudo-operations; they always map to 14607 one particular machine instruction, depending on the displacement 14608 to the branch target. 14609 14610'jbXX' 14611 Here, 'jbXX' stands for an entire family of pseudo-operations, 14612 where XX is a conditional branch or condition-code test. The full 14613 list of pseudo-ops in this family is: 14614 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 14615 jbcs jbne jblt jble jbls jbvc jbmi 14616 14617 For the cases of non-PC relative displacements and long 14618 displacements, 'as' issues a longer code fragment in terms of NX, 14619 the opposite condition to XX. For example, for the non-PC relative 14620 case: 14621 jbXX foo 14622 gives 14623 bNXs oof 14624 jmp foo 14625 oof: 14626 14627 14628File: as.info, Node: S12Z-Dependent, Next: Meta-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 14629 146309.24 S12Z Dependent Features 14631============================ 14632 14633The Freescale S12Z version of 'as' has a few machine dependent features. 14634 14635* Menu: 14636 14637* S12Z Options:: S12Z Options 14638* S12Z Syntax:: Syntax 14639 14640 14641File: as.info, Node: S12Z Options, Next: S12Z Syntax, Up: S12Z-Dependent 14642 146439.24.1 S12Z Options 14644------------------- 14645 14646The S12Z version of 'as' recognizes the following options: 14647 14648'-mreg-prefix=PREFIX' 14649 You can use the '-mreg-prefix=PFX' option to indicate that the 14650 assembler should expect all register names to be prefixed with the 14651 string PFX. 14652 14653 For an explanation of what this means and why it might be needed, 14654 see *note S12Z Register Notation::. 14655 14656'-mdollar-hex' 14657 The '-mdollar-hex' option affects the way that literal hexadecimal 14658 constants are represented. When this option is specified, the 14659 assembler will consider the '$' character as the start of a 14660 hexadecimal integer constant. Without this option, the standard 14661 value of '0x' is expected. 14662 14663 If you use this option, then you cannot have symbol names starting 14664 with '$'. '-mdollar-hex' is implied if the '--traditional-format' 14665 (*note traditional-format::) is used. 14666 14667 14668File: as.info, Node: S12Z Syntax, Prev: S12Z Options, Up: S12Z-Dependent 14669 146709.24.2 Syntax 14671------------- 14672 14673* Menu: 14674 14675* S12Z Syntax Overview:: General description 14676* S12Z Addressing Modes:: Operands and their semantics 14677* S12Z Register Notation:: How to refer to registers 14678 14679 14680File: as.info, Node: S12Z Syntax Overview, Next: S12Z Addressing Modes, Up: S12Z Syntax 14681 146829.24.2.1 Overview 14683................. 14684 14685In the S12Z syntax, the instruction name comes first and it may be 14686followed by one, or by several operands. In most cases the maximum 14687number of operands is three. Operands are separated by a comma (','). 14688A comma however does not act as a separator if it appears within 14689parentheses ('()') or within square brackets ('[]'). 'as' will complain 14690if too many, too few or inappropriate operands are specified for a given 14691instruction. 14692 14693 Some instructions accept and (in certain situations require) a suffix 14694indicating the size of the operand. The suffix is separated from the 14695instruction name by a period ('.') and may be one of 'b', 'w', 'p' or 14696'l' indicating 'byte' (a single byte), 'word' (2 bytes), 'pointer' (3 14697bytes) or 'long' (4 bytes) respectively. 14698 14699 Example: 14700 14701 bset.b 0xA98, #5 14702 mov.b #6, 0x2409 14703 ld d0, #4 14704 mov.l (d0, x), 0x2409 14705 inc d0 14706 cmp d0, #12 14707 blt *-4 14708 lea x, 0x2409 14709 st y, (1, x) 14710 14711 The presence of a ';' character anywhere on a line indicates the 14712start of a comment that extends to the end of that line. 14713 14714 A '*' or a '#' character at the start of a line also introduces a 14715line comment, but these characters do not work elsewhere on the line. 14716If the first character of the line is a '#' then as well as starting a 14717comment, the line could also be logical line number directive (*note 14718Comments::) or a preprocessor control command (*note Preprocessing::). 14719 14720 The S12Z assembler does not currently support a line separator 14721character. 14722 14723 14724File: as.info, Node: S12Z Addressing Modes, Next: S12Z Register Notation, Prev: S12Z Syntax Overview, Up: S12Z Syntax 14725 147269.24.2.2 Addressing Modes 14727......................... 14728 14729The following addressing modes are understood for the S12Z. 14730"Immediate" 14731 '#NUMBER' 14732 14733"Immediate Bit Field" 14734 '#WIDTH:OFFSET' 14735 14736 Bit field instructions in the immediate mode require the width and 14737 offset to be specified. The WIDTH parameter specifies the number 14738 of bits in the field. It should be a number in the range [1,32]. 14739 OFFSET determines the position within the field where the operation 14740 should start. It should be a number in the range [0,31]. 14741 14742"Relative" 14743 '*SYMBOL', or '*[+-]DIGITS' 14744 14745 Program counter relative addresses have a width of 15 bits. Thus, 14746 they must be within the range [-32768, 32767]. 14747 14748"Register" 14749 'REG' 14750 14751 Some instructions accept a register as an operand. In general, REG 14752 may be a data register ('D0', 'D1' ... 'D7'), the 'X' register or 14753 the 'Y' register. 14754 14755 A few instructions accept as an argument the stack pointer register 14756 ('S'), and/or the program counter ('P'). 14757 14758 Some very special instructions accept arguments which refer to the 14759 condition code register. For these arguments the syntax is 'CCR', 14760 'CCH' or 'CCL' which refer to the complete condition code register, 14761 the condition code register high byte and the condition code 14762 register low byte respectively. 14763 14764"Absolute Direct" 14765 'SYMBOL', or 'DIGITS' 14766 14767"Absolute Indirect" 14768 '[SYMBOL', or 'DIGITS]' 14769 14770"Constant Offset Indexed" 14771 '(NUMBER,REG)' 14772 14773 REG may be either 'X', 'Y', 'S' or 'P' or one of the data registers 14774 'D0', 'D1' ... 'D7'. If any of the registers 'D2' ... 'D5' are 14775 specified, then the register value is treated as a signed value. 14776 Otherwise it is treated as unsigned. NUMBER may be any integer in 14777 the range [-8388608,8388607]. 14778 14779"Offset Indexed Indirect" 14780 '[NUMBER,REG]' 14781 14782 REG may be either 'X', 'Y', 'S' or 'P'. NUMBER may be any integer 14783 in the range [-8388608,8388607]. 14784 14785"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 14786 '-REG', '+REG', 'REG-' or 'REG+' 14787 14788 This addressing mode is typically used to access a value at an 14789 address, and simultaneously to increment/decrement the register 14790 pointing to that address. Thus REG may be any of the 24 bit 14791 registers 'X', 'Y', or 'S'. Pre-increment and post-decrement are 14792 not available for register 'S' (only post-increment and 14793 pre-decrement are available). 14794 14795"Register Offset Direct" 14796 '(DATA-REG,REG)' 14797 14798 REG can be either 'X', 'Y', or 'S'. DATA-REG must be one of the 14799 data registers 'D0', 'D1' ... 'D7'. If any of the registers 'D2' 14800 ... 'D5' are specified, then the register value is treated as a 14801 signed value. Otherwise it is treated as unsigned. 14802 14803"Register Offset Indirect" 14804 '[DATA-REG,REG]' 14805 14806 REG can be either 'X' or 'Y'. DATA-REG must be one of the data 14807 registers 'D0', 'D1' ... 'D7'. If any of the registers 'D2' ... 14808 'D5' are specified, then the register value is treated as a signed 14809 value. Otherwise it is treated as unsigned. 14810 14811 For example: 14812 14813 trap #197 ;; Immediate mode 14814 bra *+49 ;; Relative mode 14815 bra .L0 ;; ditto 14816 jmp 0xFE0034 ;; Absolute direct mode 14817 jmp [0xFD0012] ;; Absolute indirect mode 14818 inc.b (4,x) ;; Constant offset indexed mode 14819 jsr (45, d0) ;; ditto 14820 dec.w [4,y] ;; Constant offset indexed indirect mode 14821 clr.p (-s) ;; Pre-decrement mode 14822 neg.l (d0, s) ;; Register offset direct mode 14823 com.b [d1, x] ;; Register offset indirect mode 14824 psh cch ;; Register mode 14825 14826 14827File: as.info, Node: S12Z Register Notation, Prev: S12Z Addressing Modes, Up: S12Z Syntax 14828 148299.24.2.3 Register Notation 14830.......................... 14831 14832Without a register prefix (*note S12Z Options::), S12Z assembler code is 14833expected in the traditional format like this: 14834 lea s, (-2,s) 14835 st d2, (0,s) 14836 ld x, symbol 14837 tfr d2, d6 14838 cmp d6, #1532 14839 14840However, if 'as' is started with (for example) '-mreg-prefix=%' then all 14841register names must be prefixed with '%' as follows: 14842 lea %s, (-2,%s) 14843 st %d2, (0,%s) 14844 ld %x, symbol 14845 tfr %d2, %d6 14846 cmp %d6, #1532 14847 14848 The register prefix feature is intended to be used by compilers to 14849avoid ambiguity between symbols and register names. Consider the 14850following assembler instruction: 14851 st d0, d1 14852The destination operand of this instruction could either refer to the 14853register 'D1', or it could refer to the symbol named "d1". If the 14854latter is intended then 'as' must be invoked with '-mreg-prefix=PFX' and 14855the code written as 14856 st PFXd0, d1 14857where PFX is the chosen register prefix. For this reason, compiler 14858back-ends should choose a register prefix which cannot be confused with 14859a symbol name. 14860 14861 14862File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: S12Z-Dependent, Up: Machine Dependencies 14863 148649.25 Meta Dependent Features 14865============================ 14866 14867* Menu: 14868 14869* Meta Options:: Options 14870* Meta Syntax:: Meta Assembler Syntax 14871 14872 14873File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent 14874 148759.25.1 Options 14876-------------- 14877 14878The Imagination Technologies Meta architecture is implemented in a 14879number of versions, with each new version adding new features such as 14880instructions and registers. For precise details of what instructions 14881each core supports, please see the chip's technical reference manual. 14882 14883 The following table lists all available Meta options. 14884 14885'-mcpu=metac11' 14886 Generate code for Meta 1.1. 14887 14888'-mcpu=metac12' 14889 Generate code for Meta 1.2. 14890 14891'-mcpu=metac21' 14892 Generate code for Meta 2.1. 14893 14894'-mfpu=metac21' 14895 Allow code to use FPU hardware of Meta 2.1. 14896 14897 14898File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent 14899 149009.25.2 Syntax 14901------------- 14902 14903* Menu: 14904 14905* Meta-Chars:: Special Characters 14906* Meta-Regs:: Register Names 14907 14908 14909File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax 14910 149119.25.2.1 Special Characters 14912........................... 14913 14914'!' is the line comment character. 14915 14916 You can use ';' instead of a newline to separate statements. 14917 14918 Since '$' has no special meaning, you may use it in symbol names. 14919 14920 14921File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax 14922 149239.25.2.2 Register Names 14924....................... 14925 14926Registers can be specified either using their mnemonic names, such as 14927'D0Re0', or using the unit plus register number separated by a '.', such 14928as 'D0.0'. 14929 14930 14931File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies 14932 149339.26 MicroBlaze Dependent Features 14934================================== 14935 14936The Xilinx MicroBlaze processor family includes several variants, all 14937using the same core instruction set. This chapter covers features of 14938the GNU assembler that are specific to the MicroBlaze architecture. For 14939details about the MicroBlaze instruction set, please see the 'MicroBlaze 14940Processor Reference Guide (UG081)' available at www.xilinx.com. 14941 14942* Menu: 14943 14944* MicroBlaze Directives:: Directives for MicroBlaze Processors. 14945* MicroBlaze Syntax:: Syntax for the MicroBlaze 14946 14947 14948File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent 14949 149509.26.1 Directives 14951----------------- 14952 14953A number of assembler directives are available for MicroBlaze. 14954 14955'.data8 EXPRESSION,...' 14956 This directive is an alias for '.byte'. Each expression is 14957 assembled into an eight-bit value. 14958 14959'.data16 EXPRESSION,...' 14960 This directive is an alias for '.hword'. Each expression is 14961 assembled into an 16-bit value. 14962 14963'.data32 EXPRESSION,...' 14964 This directive is an alias for '.word'. Each expression is 14965 assembled into an 32-bit value. 14966 14967'.ent NAME[,LABEL]' 14968 This directive is an alias for '.func' denoting the start of 14969 function NAME at (optional) LABEL. 14970 14971'.end NAME[,LABEL]' 14972 This directive is an alias for '.endfunc' denoting the end of 14973 function NAME. 14974 14975'.gpword LABEL,...' 14976 This directive is an alias for '.rva'. The resolved address of 14977 LABEL is stored in the data section. 14978 14979'.weakext LABEL' 14980 Declare that LABEL is a weak external symbol. 14981 14982'.rodata' 14983 Switch to .rodata section. Equivalent to '.section .rodata' 14984 14985'.sdata2' 14986 Switch to .sdata2 section. Equivalent to '.section .sdata2' 14987 14988'.sdata' 14989 Switch to .sdata section. Equivalent to '.section .sdata' 14990 14991'.bss' 14992 Switch to .bss section. Equivalent to '.section .bss' 14993 14994'.sbss' 14995 Switch to .sbss section. Equivalent to '.section .sbss' 14996 14997 14998File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent 14999 150009.26.2 Syntax for the MicroBlaze 15001-------------------------------- 15002 15003* Menu: 15004 15005* MicroBlaze-Chars:: Special Characters 15006 15007 15008File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax 15009 150109.26.2.1 Special Characters 15011........................... 15012 15013The presence of a '#' on a line indicates the start of a comment that 15014extends to the end of the current line. 15015 15016 If a '#' appears as the first character of a line, the whole line is 15017treated as a comment, but in this case the line can also be a logical 15018line number directive (*note Comments::) or a preprocessor control 15019command (*note Preprocessing::). 15020 15021 The ';' character can be used to separate statements on the same 15022line. 15023 15024 15025File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 15026 150279.27 MIPS Dependent Features 15028============================ 15029 15030GNU 'as' for MIPS architectures supports several different MIPS 15031processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 15032information about the MIPS instruction set, see 'MIPS RISC 15033Architecture', by Kane and Heindrich (Prentice-Hall). For an overview 15034of MIPS assembly conventions, see "Appendix D: Assembly Language 15035Programming" in the same work. 15036 15037* Menu: 15038 15039* MIPS Options:: Assembler options 15040* MIPS Macros:: High-level assembly macros 15041* MIPS Symbol Sizes:: Directives to override the size of symbols 15042* MIPS Small Data:: Controlling the use of small data accesses 15043* MIPS ISA:: Directives to override the ISA level 15044* MIPS assembly options:: Directives to control code generation 15045* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 15046* MIPS insn:: Directive to mark data as an instruction 15047* MIPS FP ABIs:: Marking which FP ABI is in use 15048* MIPS NaN Encodings:: Directives to record which NaN encoding is being used 15049* MIPS Option Stack:: Directives to save and restore options 15050* MIPS ASE Instruction Generation Overrides:: Directives to control 15051 generation of MIPS ASE instructions 15052* MIPS Floating-Point:: Directives to override floating-point options 15053* MIPS Syntax:: MIPS specific syntactical considerations 15054 15055 15056File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent 15057 150589.27.1 Assembler options 15059------------------------ 15060 15061The MIPS configurations of GNU 'as' support these special options: 15062 15063'-G NUM' 15064 Set the "small data" limit to N bytes. The default limit is 8 15065 bytes. *Note Controlling the use of small data accesses: MIPS 15066 Small Data. 15067 15068'-EB' 15069'-EL' 15070 Any MIPS configuration of 'as' can select big-endian or 15071 little-endian output at run time (unlike the other GNU development 15072 tools, which must be configured for one or the other). Use '-EB' 15073 to select big-endian output, and '-EL' for little-endian. 15074 15075'-KPIC' 15076 Generate SVR4-style PIC. This option tells the assembler to 15077 generate SVR4-style position-independent macro expansions. It also 15078 tells the assembler to mark the output file as PIC. 15079 15080'-mvxworks-pic' 15081 Generate VxWorks PIC. This option tells the assembler to generate 15082 VxWorks-style position-independent macro expansions. 15083 15084'-mips1' 15085'-mips2' 15086'-mips3' 15087'-mips4' 15088'-mips5' 15089'-mips32' 15090'-mips32r2' 15091'-mips32r3' 15092'-mips32r5' 15093'-mips32r6' 15094'-mips64' 15095'-mips64r2' 15096'-mips64r3' 15097'-mips64r5' 15098'-mips64r6' 15099 Generate code for a particular MIPS Instruction Set Architecture 15100 level. '-mips1' corresponds to the R2000 and R3000 processors, 15101 '-mips2' to the R6000 processor, '-mips3' to the R4000 processor, 15102 and '-mips4' to the R8000 and R10000 processors. '-mips5', 15103 '-mips32', '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6', 15104 '-mips64', '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6' 15105 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 15106 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 15107 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 15108 ISA processors, respectively. You can also switch instruction sets 15109 during the assembly; see *note Directives to override the ISA 15110 level: MIPS ISA. 15111 15112'-mgp32' 15113'-mfp32' 15114 Some macros have different expansions for 32-bit and 64-bit 15115 registers. The register sizes are normally inferred from the ISA 15116 and ABI, but these flags force a certain group of registers to be 15117 treated as 32 bits wide at all times. '-mgp32' controls the size 15118 of general-purpose registers and '-mfp32' controls the size of 15119 floating-point registers. 15120 15121 The '.set gp=32' and '.set fp=32' directives allow the size of 15122 registers to be changed for parts of an object. The default value 15123 is restored by '.set gp=default' and '.set fp=default'. 15124 15125 On some MIPS variants there is a 32-bit mode flag; when this flag 15126 is set, 64-bit instructions generate a trap. Also, some 32-bit 15127 OSes only save the 32-bit registers on a context switch, so it is 15128 essential never to use the 64-bit registers. 15129 15130'-mgp64' 15131'-mfp64' 15132 Assume that 64-bit registers are available. This is provided in 15133 the interests of symmetry with '-mgp32' and '-mfp32'. 15134 15135 The '.set gp=64' and '.set fp=64' directives allow the size of 15136 registers to be changed for parts of an object. The default value 15137 is restored by '.set gp=default' and '.set fp=default'. 15138 15139'-mfpxx' 15140 Make no assumptions about whether 32-bit or 64-bit floating-point 15141 registers are available. This is provided to support having 15142 modules compatible with either '-mfp32' or '-mfp64'. This option 15143 can only be used with MIPS II and above. 15144 15145 The '.set fp=xx' directive allows a part of an object to be marked 15146 as not making assumptions about 32-bit or 64-bit FP registers. The 15147 default value is restored by '.set fp=default'. 15148 15149'-modd-spreg' 15150'-mno-odd-spreg' 15151 Enable use of floating-point operations on odd-numbered 15152 single-precision registers when supported by the ISA. '-mfpxx' 15153 implies '-mno-odd-spreg', otherwise the default is '-modd-spreg' 15154 15155'-mips16' 15156'-no-mips16' 15157 Generate code for the MIPS 16 processor. This is equivalent to 15158 putting '.module mips16' at the start of the assembly file. 15159 '-no-mips16' turns off this option. 15160 15161'-mmips16e2' 15162'-mno-mips16e2' 15163 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is 15164 equivalent to putting '.module mips16e2' at the start of the 15165 assembly file. '-mno-mips16e2' turns off this option. 15166 15167'-mmicromips' 15168'-mno-micromips' 15169 Generate code for the microMIPS processor. This is equivalent to 15170 putting '.module micromips' at the start of the assembly file. 15171 '-mno-micromips' turns off this option. This is equivalent to 15172 putting '.module nomicromips' at the start of the assembly file. 15173 15174'-msmartmips' 15175'-mno-smartmips' 15176 Enables the SmartMIPS extensions to the MIPS32 instruction set, 15177 which provides a number of new instructions which target smartcard 15178 and cryptographic applications. This is equivalent to putting 15179 '.module smartmips' at the start of the assembly file. 15180 '-mno-smartmips' turns off this option. 15181 15182'-mips3d' 15183'-no-mips3d' 15184 Generate code for the MIPS-3D Application Specific Extension. This 15185 tells the assembler to accept MIPS-3D instructions. '-no-mips3d' 15186 turns off this option. 15187 15188'-mdmx' 15189'-no-mdmx' 15190 Generate code for the MDMX Application Specific Extension. This 15191 tells the assembler to accept MDMX instructions. '-no-mdmx' turns 15192 off this option. 15193 15194'-mdsp' 15195'-mno-dsp' 15196 Generate code for the DSP Release 1 Application Specific Extension. 15197 This tells the assembler to accept DSP Release 1 instructions. 15198 '-mno-dsp' turns off this option. 15199 15200'-mdspr2' 15201'-mno-dspr2' 15202 Generate code for the DSP Release 2 Application Specific Extension. 15203 This option implies '-mdsp'. This tells the assembler to accept 15204 DSP Release 2 instructions. '-mno-dspr2' turns off this option. 15205 15206'-mdspr3' 15207'-mno-dspr3' 15208 Generate code for the DSP Release 3 Application Specific Extension. 15209 This option implies '-mdsp' and '-mdspr2'. This tells the 15210 assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns 15211 off this option. 15212 15213'-mmt' 15214'-mno-mt' 15215 Generate code for the MT Application Specific Extension. This 15216 tells the assembler to accept MT instructions. '-mno-mt' turns off 15217 this option. 15218 15219'-mmcu' 15220'-mno-mcu' 15221 Generate code for the MCU Application Specific Extension. This 15222 tells the assembler to accept MCU instructions. '-mno-mcu' turns 15223 off this option. 15224 15225'-mmsa' 15226'-mno-msa' 15227 Generate code for the MIPS SIMD Architecture Extension. This tells 15228 the assembler to accept MSA instructions. '-mno-msa' turns off 15229 this option. 15230 15231'-mxpa' 15232'-mno-xpa' 15233 Generate code for the MIPS eXtended Physical Address (XPA) 15234 Extension. This tells the assembler to accept XPA instructions. 15235 '-mno-xpa' turns off this option. 15236 15237'-mvirt' 15238'-mno-virt' 15239 Generate code for the Virtualization Application Specific 15240 Extension. This tells the assembler to accept Virtualization 15241 instructions. '-mno-virt' turns off this option. 15242 15243'-mcrc' 15244'-mno-crc' 15245 Generate code for the cyclic redundancy check (CRC) Application 15246 Specific Extension. This tells the assembler to accept CRC 15247 instructions. '-mno-crc' turns off this option. 15248 15249'-mginv' 15250'-mno-ginv' 15251 Generate code for the Global INValidate (GINV) Application Specific 15252 Extension. This tells the assembler to accept GINV instructions. 15253 '-mno-ginv' turns off this option. 15254 15255'-mloongson-mmi' 15256'-mno-loongson-mmi' 15257 Generate code for the Loongson MultiMedia extensions Instructions 15258 (MMI) Application Specific Extension. This tells the assembler to 15259 accept MMI instructions. '-mno-loongson-mmi' turns off this 15260 option. 15261 15262'-mloongson-cam' 15263'-mno-loongson-cam' 15264 Generate code for the Loongson Content Address Memory (CAM) 15265 Application Specific Extension. This tells the assembler to accept 15266 CAM instructions. '-mno-loongson-cam' turns off this option. 15267 15268'-mloongson-ext' 15269'-mno-loongson-ext' 15270 Generate code for the Loongson EXTensions (EXT) instructions 15271 Application Specific Extension. This tells the assembler to accept 15272 EXT instructions. '-mno-loongson-ext' turns off this option. 15273 15274'-mloongson-ext2' 15275'-mno-loongson-ext2' 15276 Generate code for the Loongson EXTensions R2 (EXT2) instructions 15277 Application Specific Extension. This tells the assembler to accept 15278 EXT2 instructions. '-mno-loongson-ext2' turns off this option. 15279 15280'-minsn32' 15281'-mno-insn32' 15282 Only use 32-bit instruction encodings when generating code for the 15283 microMIPS processor. This option inhibits the use of any 16-bit 15284 instructions. This is equivalent to putting '.set insn32' at the 15285 start of the assembly file. '-mno-insn32' turns off this option. 15286 This is equivalent to putting '.set noinsn32' at the start of the 15287 assembly file. By default '-mno-insn32' is selected, allowing all 15288 instructions to be used. 15289 15290'-mfix7000' 15291'-mno-fix7000' 15292 Cause nops to be inserted if the read of the destination register 15293 of an mfhi or mflo instruction occurs in the following two 15294 instructions. 15295 15296'-mfix-rm7000' 15297'-mno-fix-rm7000' 15298 Cause nops to be inserted if a dmult or dmultu instruction is 15299 followed by a load instruction. 15300 15301'-mfix-loongson2f-jump' 15302'-mno-fix-loongson2f-jump' 15303 Eliminate instruction fetch from outside 256M region to work around 15304 the Loongson2F 'jump' instructions. Without it, under extreme 15305 cases, the kernel may crash. The issue has been solved in latest 15306 processor batches, but this fix has no side effect to them. 15307 15308'-mfix-loongson2f-nop' 15309'-mno-fix-loongson2f-nop' 15310 Replace nops by 'or at,at,zero' to work around the Loongson2F 'nop' 15311 errata. Without it, under extreme cases, the CPU might deadlock. 15312 The issue has been solved in later Loongson2F batches, but this fix 15313 has no side effect to them. 15314 15315'-mfix-loongson3-llsc' 15316'-mno-fix-loongson3-llsc' 15317 Insert 'sync' before 'll' and 'lld' to work around Loongson3 LLSC 15318 errata. Without it, under extrame cases, the CPU might deadlock. 15319 The default can be controlled by the 15320 '--enable-mips-fix-loongson3-llsc=[yes|no]' configure option. 15321 15322'-mfix-vr4120' 15323'-mno-fix-vr4120' 15324 Insert nops to work around certain VR4120 errata. This option is 15325 intended to be used on GCC-generated code: it is not designed to 15326 catch all problems in hand-written assembler code. 15327 15328'-mfix-vr4130' 15329'-mno-fix-vr4130' 15330 Insert nops to work around the VR4130 'mflo'/'mfhi' errata. 15331 15332'-mfix-24k' 15333'-mno-fix-24k' 15334 Insert nops to work around the 24K 'eret'/'deret' errata. 15335 15336'-mfix-cn63xxp1' 15337'-mno-fix-cn63xxp1' 15338 Replace 'pref' hints 0 - 4 and 6 - 24 with hint 28 to work around 15339 certain CN63XXP1 errata. 15340 15341'-mfix-r5900' 15342'-mno-fix-r5900' 15343 Do not attempt to schedule the preceding instruction into the delay 15344 slot of a branch instruction placed at the end of a short loop of 15345 six instructions or fewer and always schedule a 'nop' instruction 15346 there instead. The short loop bug under certain conditions causes 15347 loops to execute only once or twice, due to a hardware bug in the 15348 R5900 chip. 15349 15350'-m4010' 15351'-no-m4010' 15352 Generate code for the LSI R4010 chip. This tells the assembler to 15353 accept the R4010-specific instructions ('addciu', 'ffc', etc.), and 15354 to not schedule 'nop' instructions around accesses to the 'HI' and 15355 'LO' registers. '-no-m4010' turns off this option. 15356 15357'-m4650' 15358'-no-m4650' 15359 Generate code for the MIPS R4650 chip. This tells the assembler to 15360 accept the 'mad' and 'madu' instruction, and to not schedule 'nop' 15361 instructions around accesses to the 'HI' and 'LO' registers. 15362 '-no-m4650' turns off this option. 15363 15364'-m3900' 15365'-no-m3900' 15366'-m4100' 15367'-no-m4100' 15368 For each option '-mNNNN', generate code for the MIPS RNNNN chip. 15369 This tells the assembler to accept instructions specific to that 15370 chip, and to schedule for that chip's hazards. 15371 15372'-march=CPU' 15373 Generate code for a particular MIPS CPU. It is exactly equivalent 15374 to '-mCPU', except that there are more value of CPU understood. 15375 Valid CPU value are: 15376 15377 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 15378 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 15379 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 15380 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 15381 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 15382 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 15383 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 15384 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, 15385 interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc, 5kf, 15386 20kc, 25kf, sb1, sb1a, i6400, i6500, p6600, loongson2e, 15387 loongson2f, gs464, gs464e, gs264e, octeon, octeon+, octeon2, 15388 octeon3, xlr, xlp 15389 15390 For compatibility reasons, 'Nx' and 'Bfx' are accepted as synonyms 15391 for 'Nf1_1'. These values are deprecated. 15392 15393'-mtune=CPU' 15394 Schedule and tune for a particular MIPS CPU. Valid CPU values are 15395 identical to '-march=CPU'. 15396 15397'-mabi=ABI' 15398 Record which ABI the source code uses. The recognized arguments 15399 are: '32', 'n32', 'o64', '64' and 'eabi'. 15400 15401'-msym32' 15402'-mno-sym32' 15403 Equivalent to adding '.set sym32' or '.set nosym32' to the 15404 beginning of the assembler input. *Note MIPS Symbol Sizes::. 15405 15406'-nocpp' 15407 This option is ignored. It is accepted for command-line 15408 compatibility with other assemblers, which use it to turn off C 15409 style preprocessing. With GNU 'as', there is no need for '-nocpp', 15410 because the GNU assembler itself never runs the C preprocessor. 15411 15412'-msoft-float' 15413'-mhard-float' 15414 Disable or enable floating-point instructions. Note that by 15415 default floating-point instructions are always allowed even with 15416 CPU targets that don't have support for these instructions. 15417 15418'-msingle-float' 15419'-mdouble-float' 15420 Disable or enable double-precision floating-point operations. Note 15421 that by default double-precision floating-point operations are 15422 always allowed even with CPU targets that don't have support for 15423 these operations. 15424 15425'--construct-floats' 15426'--no-construct-floats' 15427 The '--no-construct-floats' option disables the construction of 15428 double width floating point constants by loading the two halves of 15429 the value into the two single width floating point registers that 15430 make up the double width register. This feature is useful if the 15431 processor support the FR bit in its status register, and this bit 15432 is known (by the programmer) to be set. This bit prevents the 15433 aliasing of the double width register by the single width 15434 registers. 15435 15436 By default '--construct-floats' is selected, allowing construction 15437 of these floating point constants. 15438 15439'--relax-branch' 15440'--no-relax-branch' 15441 The '--relax-branch' option enables the relaxation of out-of-range 15442 branches. Any branches whose target cannot be reached directly are 15443 converted to a small instruction sequence including an 15444 inverse-condition branch to the physically next instruction, and a 15445 jump to the original target is inserted between the two 15446 instructions. In PIC code the jump will involve further 15447 instructions for address calculation. 15448 15449 The 'BC1ANY2F', 'BC1ANY2T', 'BC1ANY4F', 'BC1ANY4T', 'BPOSGE32' and 15450 'BPOSGE64' instructions are excluded from relaxation, because they 15451 have no complementing counterparts. They could be relaxed with the 15452 use of a longer sequence involving another branch, however this has 15453 not been implemented and if their target turns out of reach, they 15454 produce an error even if branch relaxation is enabled. 15455 15456 Also no MIPS16 branches are ever relaxed. 15457 15458 By default '--no-relax-branch' is selected, causing any 15459 out-of-range branches to produce an error. 15460 15461'-mignore-branch-isa' 15462'-mno-ignore-branch-isa' 15463 Ignore branch checks for invalid transitions between ISA modes. 15464 15465 The semantics of branches does not provide for an ISA mode switch, 15466 so in most cases the ISA mode a branch has been encoded for has to 15467 be the same as the ISA mode of the branch's target label. If the 15468 ISA modes do not match, then such a branch, if taken, will cause 15469 the ISA mode to remain unchanged and instructions that follow will 15470 be executed in the wrong ISA mode causing the program to misbehave 15471 or crash. 15472 15473 In the case of the 'BAL' instruction it may be possible to relax it 15474 to an equivalent 'JALX' instruction so that the ISA mode is 15475 switched at the run time as required. For other branches no 15476 relaxation is possible and therefore GAS has checks implemented 15477 that verify in branch assembly that the two ISA modes match, and 15478 report an error otherwise so that the problem with code can be 15479 diagnosed at the assembly time rather than at the run time. 15480 15481 However some assembly code, including generated code produced by 15482 some versions of GCC, may incorrectly include branches to data 15483 labels, which appear to require a mode switch but are either dead 15484 or immediately followed by valid instructions encoded for the same 15485 ISA the branch has been encoded for. While not strictly correct at 15486 the source level such code will execute as intended, so to help 15487 with these cases '-mignore-branch-isa' is supported which disables 15488 ISA mode checks for branches. 15489 15490 By default '-mno-ignore-branch-isa' is selected, causing any 15491 invalid branch requiring a transition between ISA modes to produce 15492 an error. 15493 15494'-mnan=ENCODING' 15495 This option indicates whether the source code uses the IEEE 2008 15496 NaN encoding ('-mnan=2008') or the original MIPS encoding 15497 ('-mnan=legacy'). It is equivalent to adding a '.nan' directive to 15498 the beginning of the source file. *Note MIPS NaN Encodings::. 15499 15500 '-mnan=legacy' is the default if no '-mnan' option or '.nan' 15501 directive is used. 15502 15503'--trap' 15504'--no-break' 15505 'as' automatically macro expands certain division and 15506 multiplication instructions to check for overflow and division by 15507 zero. This option causes 'as' to generate code to take a trap 15508 exception rather than a break exception when an error is detected. 15509 The trap instructions are only supported at Instruction Set 15510 Architecture level 2 and higher. 15511 15512'--break' 15513'--no-trap' 15514 Generate code to take a break exception rather than a trap 15515 exception when an error is detected. This is the default. 15516 15517'-mpdr' 15518'-mno-pdr' 15519 Control generation of '.pdr' sections. Off by default on IRIX, on 15520 elsewhere. 15521 15522'-mshared' 15523'-mno-shared' 15524 When generating code using the Unix calling conventions (selected 15525 by '-KPIC' or '-mcall_shared'), gas will normally generate code 15526 which can go into a shared library. The '-mno-shared' option tells 15527 gas to generate code which uses the calling convention, but can not 15528 go into a shared library. The resulting code is slightly more 15529 efficient. This option only affects the handling of the '.cpload' 15530 and '.cpsetup' pseudo-ops. 15531 15532 15533File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent 15534 155359.27.2 High-level assembly macros 15536--------------------------------- 15537 15538MIPS assemblers have traditionally provided a wider range of 15539instructions than the MIPS architecture itself. These extra 15540instructions are usually referred to as "macro" instructions (1). 15541 15542 Some MIPS macro instructions extend an underlying architectural 15543instruction while others are entirely new. An example of the former 15544type is 'and', which allows the third operand to be either a register or 15545an arbitrary immediate value. Examples of the latter type include 15546'bgt', which branches to the third operand when the first operand is 15547greater than the second operand, and 'ulh', which implements an 15548unaligned 2-byte load. 15549 15550 One of the most common extensions provided by macros is to expand 15551memory offsets to the full address range (32 or 64 bits) and to allow 15552symbolic offsets such as 'my_data + 4' to be used in place of integer 15553constants. For example, the architectural instruction 'lbu' allows only 15554a signed 16-bit offset, whereas the macro 'lbu' allows code such as 'lbu 15555$4,array+32769($5)'. The implementation of these symbolic offsets 15556depends on several factors, such as whether the assembler is generating 15557SVR4-style PIC (selected by '-KPIC', *note Assembler options: MIPS 15558Options.), the size of symbols (*note Directives to override the size of 15559symbols: MIPS Symbol Sizes.), and the small data limit (*note 15560Controlling the use of small data accesses: MIPS Small Data.). 15561 15562 Sometimes it is undesirable to have one assembly instruction expand 15563to several machine instructions. The directive '.set nomacro' tells the 15564assembler to warn when this happens. '.set macro' restores the default 15565behavior. 15566 15567 Some macro instructions need a temporary register to store 15568intermediate results. This register is usually '$1', also known as 15569'$at', but it can be changed to any core register REG using '.set 15570at=REG'. Note that '$at' always refers to '$1' regardless of which 15571register is being used as the temporary register. 15572 15573 Implicit uses of the temporary register in macros could interfere 15574with explicit uses in the assembly code. The assembler therefore warns 15575whenever it sees an explicit use of the temporary register. The 15576directive '.set noat' silences this warning while '.set at' restores the 15577default behavior. It is safe to use '.set noat' while '.set nomacro' is 15578in effect since single-instruction macros never need a temporary 15579register. 15580 15581 Note that while the GNU assembler provides these macros for 15582compatibility, it does not make any attempt to optimize them with the 15583surrounding code. 15584 15585 ---------- Footnotes ---------- 15586 15587 (1) The term "macro" is somewhat overloaded here, since these macros 15588have no relation to those defined by '.macro', *note '.macro': Macro. 15589 15590 15591File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent 15592 155939.27.3 Directives to override the size of symbols 15594------------------------------------------------- 15595 15596The n64 ABI allows symbols to have any 64-bit value. Although this 15597provides a great deal of flexibility, it means that some macros have 15598much longer expansions than their 32-bit counterparts. For example, the 15599non-PIC expansion of 'dla $4,sym' is usually: 15600 15601 lui $4,%highest(sym) 15602 lui $1,%hi(sym) 15603 daddiu $4,$4,%higher(sym) 15604 daddiu $1,$1,%lo(sym) 15605 dsll32 $4,$4,0 15606 daddu $4,$4,$1 15607 15608 whereas the 32-bit expansion is simply: 15609 15610 lui $4,%hi(sym) 15611 daddiu $4,$4,%lo(sym) 15612 15613 n64 code is sometimes constructed in such a way that all symbolic 15614constants are known to have 32-bit values, and in such cases, it's 15615preferable to use the 32-bit expansion instead of the 64-bit expansion. 15616 15617 You can use the '.set sym32' directive to tell the assembler that, 15618from this point on, all expressions of the form 'SYMBOL' or 'SYMBOL + 15619OFFSET' have 32-bit values. For example: 15620 15621 .set sym32 15622 dla $4,sym 15623 lw $4,sym+16 15624 sw $4,sym+0x8000($4) 15625 15626 will cause the assembler to treat 'sym', 'sym+16' and 'sym+0x8000' as 1562732-bit values. The handling of non-symbolic addresses is not affected. 15628 15629 The directive '.set nosym32' ends a '.set sym32' block and reverts to 15630the normal behavior. It is also possible to change the symbol size 15631using the command-line options '-msym32' and '-mno-sym32'. 15632 15633 These options and directives are always accepted, but at present, 15634they have no effect for anything other than n64. 15635 15636 15637File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent 15638 156399.27.4 Controlling the use of small data accesses 15640------------------------------------------------- 15641 15642It often takes several instructions to load the address of a symbol. 15643For example, when 'addr' is a 32-bit symbol, the non-PIC expansion of 15644'dla $4,addr' is usually: 15645 15646 lui $4,%hi(addr) 15647 daddiu $4,$4,%lo(addr) 15648 15649 The sequence is much longer when 'addr' is a 64-bit symbol. *Note 15650Directives to override the size of symbols: MIPS Symbol Sizes. 15651 15652 In order to cut down on this overhead, most embedded MIPS systems set 15653aside a 64-kilobyte "small data" area and guarantee that all data of 15654size N and smaller will be placed in that area. The limit N is passed 15655to both the assembler and the linker using the command-line option '-G 15656N', *note Assembler options: MIPS Options. Note that the same value of 15657N must be used when linking and when assembling all input files to the 15658link; any inconsistency could cause a relocation overflow error. 15659 15660 The size of an object in the '.bss' section is set by the '.comm' or 15661'.lcomm' directive that defines it. The size of an external object may 15662be set with the '.extern' directive. For example, '.extern sym,4' 15663declares that the object at 'sym' is 4 bytes in length, while leaving 15664'sym' otherwise undefined. 15665 15666 When no '-G' option is given, the default limit is 8 bytes. The 15667option '-G 0' prevents any data from being automatically classified as 15668small. 15669 15670 It is also possible to mark specific objects as small by putting them 15671in the special sections '.sdata' and '.sbss', which are "small" 15672counterparts of '.data' and '.bss' respectively. The toolchain will 15673treat such data as small regardless of the '-G' setting. 15674 15675 On startup, systems that support a small data area are expected to 15676initialize register '$28', also known as '$gp', in such a way that small 15677data can be accessed using a 16-bit offset from that register. For 15678example, when 'addr' is small data, the 'dla $4,addr' instruction above 15679is equivalent to: 15680 15681 daddiu $4,$28,%gp_rel(addr) 15682 15683 Small data is not supported for SVR4-style PIC. 15684 15685 15686File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent 15687 156889.27.5 Directives to override the ISA level 15689------------------------------------------- 15690 15691GNU 'as' supports an additional directive to change the MIPS Instruction 15692Set Architecture level on the fly: '.set mipsN'. N should be a number 15693from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 1569464r6. The values other than 0 make the assembler accept instructions 15695for the corresponding ISA level, from that point on in the assembly. 15696'.set mipsN' affects not only which instructions are permitted, but also 15697how certain macros are expanded. '.set mips0' restores the ISA level to 15698its original level: either the level you selected with command-line 15699options, or the default for your configuration. You can use this 15700feature to permit specific MIPS III instructions while assembling in 32 15701bit mode. Use this directive with care! 15702 15703 The '.set arch=CPU' directive provides even finer control. It 15704changes the effective CPU target and allows the assembler to use 15705instructions specific to a particular CPU. All CPUs supported by the 15706'-march' command-line option are also selectable by this directive. The 15707original value is restored by '.set arch=default'. 15708 15709 The directive '.set mips16' puts the assembler into MIPS 16 mode, in 15710which it will assemble instructions for the MIPS 16 processor. Use 15711'.set nomips16' to return to normal 32 bit mode. 15712 15713 Traditional MIPS assemblers do not support this directive. 15714 15715 The directive '.set micromips' puts the assembler into microMIPS 15716mode, in which it will assemble instructions for the microMIPS 15717processor. Use '.set nomicromips' to return to normal 32 bit mode. 15718 15719 Traditional MIPS assemblers do not support this directive. 15720 15721 15722File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent 15723 157249.27.6 Directives to control code generation 15725-------------------------------------------- 15726 15727The '.module' directive allows command-line options to be set directly 15728from assembly. The format of the directive matches the '.set' directive 15729but only those options which are relevant to a whole module are 15730supported. The effect of a '.module' directive is the same as the 15731corresponding command-line option. Where '.set' directives support 15732returning to a default then the '.module' directives do not as they 15733define the defaults. 15734 15735 These module-level directives must appear first in assembly. 15736 15737 Traditional MIPS assemblers do not support this directive. 15738 15739 The directive '.set insn32' makes the assembler only use 32-bit 15740instruction encodings when generating code for the microMIPS processor. 15741This directive inhibits the use of any 16-bit instructions from that 15742point on in the assembly. The '.set noinsn32' directive allows 16-bit 15743instructions to be accepted. 15744 15745 Traditional MIPS assemblers do not support this directive. 15746 15747 15748File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent 15749 157509.27.7 Directives for extending MIPS 16 bit instructions 15751-------------------------------------------------------- 15752 15753By default, MIPS 16 instructions are automatically extended to 32 bits 15754when necessary. The directive '.set noautoextend' will turn this off. 15755When '.set noautoextend' is in effect, any 32 bit instruction must be 15756explicitly extended with the '.e' modifier (e.g., 'li.e $4,1000'). The 15757directive '.set autoextend' may be used to once again automatically 15758extend instructions when necessary. 15759 15760 This directive is only meaningful when in MIPS 16 mode. Traditional 15761MIPS assemblers do not support this directive. 15762 15763 15764File: as.info, Node: MIPS insn, Next: MIPS FP ABIs, Prev: MIPS autoextend, Up: MIPS-Dependent 15765 157669.27.8 Directive to mark data as an instruction 15767----------------------------------------------- 15768 15769The '.insn' directive tells 'as' that the following data is actually 15770instructions. This makes a difference in MIPS 16 and microMIPS modes: 15771when loading the address of a label which precedes instructions, 'as' 15772automatically adds 1 to the value, so that jumping to the loaded address 15773will do the right thing. 15774 15775 The '.global' and '.globl' directives supported by 'as' will by 15776default mark the symbol as pointing to a region of data not code. This 15777means that, for example, any instructions following such a symbol will 15778not be disassembled by 'objdump' as it will regard them as data. To 15779change this behavior an optional section name can be placed after the 15780symbol name in the '.global' directive. If this section exists and is 15781known to be a code section, then the symbol will be marked as pointing 15782at code not data. Ie the syntax for the directive is: 15783 15784 '.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', 15785 15786 Here is a short example: 15787 15788 .global foo .text, bar, baz .data 15789 foo: 15790 nop 15791 bar: 15792 .word 0x0 15793 baz: 15794 .word 0x1 15795 15796 15797 15798File: as.info, Node: MIPS FP ABIs, Next: MIPS NaN Encodings, Prev: MIPS insn, Up: MIPS-Dependent 15799 158009.27.9 Directives to control the FP ABI 15801--------------------------------------- 15802 15803* Menu: 15804 15805* MIPS FP ABI History:: History of FP ABIs 15806* MIPS FP ABI Variants:: Supported FP ABIs 15807* MIPS FP ABI Selection:: Automatic selection of FP ABI 15808* MIPS FP ABI Compatibility:: Linking different FP ABI variants 15809 15810 15811File: as.info, Node: MIPS FP ABI History, Next: MIPS FP ABI Variants, Up: MIPS FP ABIs 15812 158139.27.9.1 History of FP ABIs 15814........................... 15815 15816The MIPS ABIs support a variety of different floating-point extensions 15817where calling-convention and register sizes vary for floating-point 15818data. The extensions exist to support a wide variety of optional 15819architecture features. The resulting ABI variants are generally 15820incompatible with each other and must be tracked carefully. 15821 15822 Traditionally the use of an explicit '.gnu_attribute 4, N' directive 15823is used to indicate which ABI is in use by a specific module. It was 15824then left to the user to ensure that command-line options and the 15825selected ABI were compatible with some potential for inconsistencies. 15826 15827 15828File: as.info, Node: MIPS FP ABI Variants, Next: MIPS FP ABI Selection, Prev: MIPS FP ABI History, Up: MIPS FP ABIs 15829 158309.27.9.2 Supported FP ABIs 15831.......................... 15832 15833The supported floating-point ABI variants are: 15834 15835'0 - No floating-point' 15836 This variant is used to indicate that floating-point is not used 15837 within the module at all and therefore has no impact on the ABI. 15838 This is the default. 15839 15840'1 - Double-precision' 15841 This variant indicates that double-precision support is used. For 15842 64-bit ABIs this means that 64-bit wide floating-point registers 15843 are required. For 32-bit ABIs this means that 32-bit wide 15844 floating-point registers are required and double-precision 15845 operations use pairs of registers. 15846 15847'2 - Single-precision' 15848 This variant indicates that single-precision support is used. 15849 Double precision operations will be supported via soft-float 15850 routines. 15851 15852'3 - Soft-float' 15853 This variant indicates that although floating-point support is used 15854 all operations are emulated in software. This means the ABI is 15855 modified to pass all floating-point data in general-purpose 15856 registers. 15857 15858'4 - Deprecated' 15859 This variant existed as an initial attempt at supporting 64-bit 15860 wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This 15861 has been superseded by 5, 6 and 7. 15862 15863'5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU' 15864 This variant is used by 32-bit ABIs to indicate that the 15865 floating-point code in the module has been designed to operate 15866 correctly with either 32-bit wide or 64-bit wide floating-point 15867 registers. Double-precision support is used. Only O32 currently 15868 supports this variant and requires a minimum architecture of MIPS 15869 II. 15870 15871'6 - Double-precision 32-bit FPU, 64-bit FPU' 15872 This variant is used by 32-bit ABIs to indicate that the 15873 floating-point code in the module requires 64-bit wide 15874 floating-point registers. Double-precision support is used. Only 15875 O32 currently supports this variant and requires a minimum 15876 architecture of MIPS32r2. 15877 15878'7 - Double-precision compat 32-bit FPU, 64-bit FPU' 15879 This variant is used by 32-bit ABIs to indicate that the 15880 floating-point code in the module requires 64-bit wide 15881 floating-point registers. Double-precision support is used. This 15882 differs from the previous ABI as it restricts use of odd-numbered 15883 single-precision registers. Only O32 currently supports this 15884 variant and requires a minimum architecture of MIPS32r2. 15885 15886 15887File: as.info, Node: MIPS FP ABI Selection, Next: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Variants, Up: MIPS FP ABIs 15888 158899.27.9.3 Automatic selection of FP ABI 15890...................................... 15891 15892In order to simplify and add safety to the process of selecting the 15893correct floating-point ABI, the assembler will automatically infer the 15894correct '.gnu_attribute 4, N' directive based on command-line options 15895and '.module' overrides. Where an explicit '.gnu_attribute 4, N' 15896directive has been seen then a warning will be raised if it does not 15897match an inferred setting. 15898 15899 The floating-point ABI is inferred as follows. If '-msoft-float' has 15900been used the module will be marked as soft-float. If '-msingle-float' 15901has been used then the module will be marked as single-precision. The 15902remaining ABIs are then selected based on the FP register width. 15903Double-precision is selected if the width of GP and FP registers match 15904and the special double-precision variants for 32-bit ABIs are then 15905selected depending on '-mfpxx', '-mfp64' and '-mno-odd-spreg'. 15906 15907 15908File: as.info, Node: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Selection, Up: MIPS FP ABIs 15909 159109.27.9.4 Linking different FP ABI variants 15911.......................................... 15912 15913Modules using the default FP ABI (no floating-point) can be linked with 15914any other (singular) FP ABI variant. 15915 15916 Special compatibility support exists for O32 with the four 15917double-precision FP ABI variants. The '-mfpxx' FP ABI is specifically 15918designed to be compatible with the standard double-precision ABI and the 15919'-mfp64' FP ABIs. This makes it desirable for O32 modules to be built 15920as '-mfpxx' to ensure the maximum compatibility with other modules 15921produced for more specific needs. The only FP ABIs which cannot be 15922linked together are the standard double-precision ABI and the full 15923'-mfp64' ABI with '-modd-spreg'. 15924 15925 15926File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS FP ABIs, Up: MIPS-Dependent 15927 159289.27.10 Directives to record which NaN encoding is being used 15929------------------------------------------------------------- 15930 15931The IEEE 754 floating-point standard defines two types of not-a-number 15932(NaN) data: "signalling" NaNs and "quiet" NaNs. The original version of 15933the standard did not specify how these two types should be 15934distinguished. Most implementations followed the i387 model, in which 15935the first bit of the significand is set for quiet NaNs and clear for 15936signalling NaNs. However, the original MIPS implementation assigned the 15937opposite meaning to the bit, so that it was set for signalling NaNs and 15938clear for quiet NaNs. 15939 15940 The 2008 revision of the standard formally suggested the i387 choice 15941and as from Sep 2012 the current release of the MIPS architecture 15942therefore optionally supports that form. Code that uses one NaN 15943encoding would usually be incompatible with code that uses the other NaN 15944encoding, so MIPS ELF objects have a flag ('EF_MIPS_NAN2008') to record 15945which encoding is being used. 15946 15947 Assembly files can use the '.nan' directive to select between the two 15948encodings. '.nan 2008' says that the assembly file uses the IEEE 15949754-2008 encoding while '.nan legacy' says that the file uses the 15950original MIPS encoding. If several '.nan' directives are given, the 15951final setting is the one that is used. 15952 15953 The command-line options '-mnan=legacy' and '-mnan=2008' can be used 15954instead of '.nan legacy' and '.nan 2008' respectively. However, any 15955'.nan' directive overrides the command-line setting. 15956 15957 '.nan legacy' is the default if no '.nan' directive or '-mnan' option 15958is given. 15959 15960 Note that GNU 'as' does not produce NaNs itself and therefore these 15961directives do not affect code generation. They simply control the 15962setting of the 'EF_MIPS_NAN2008' flag. 15963 15964 Traditional MIPS assemblers do not support these directives. 15965 15966 15967File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent 15968 159699.27.11 Directives to save and restore options 15970---------------------------------------------- 15971 15972The directives '.set push' and '.set pop' may be used to save and 15973restore the current settings for all the options which are controlled by 15974'.set'. The '.set push' directive saves the current settings on a 15975stack. The '.set pop' directive pops the stack and restores the 15976settings. 15977 15978 These directives can be useful inside an macro which must change an 15979option such as the ISA level or instruction reordering but does not want 15980to change the state of the code which invoked the macro. 15981 15982 Traditional MIPS assemblers do not support these directives. 15983 15984 15985File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent 15986 159879.27.12 Directives to control generation of MIPS ASE instructions 15988----------------------------------------------------------------- 15989 15990The directive '.set mips3d' makes the assembler accept instructions from 15991the MIPS-3D Application Specific Extension from that point on in the 15992assembly. The '.set nomips3d' directive prevents MIPS-3D instructions 15993from being accepted. 15994 15995 The directive '.set smartmips' makes the assembler accept 15996instructions from the SmartMIPS Application Specific Extension to the 15997MIPS32 ISA from that point on in the assembly. The '.set nosmartmips' 15998directive prevents SmartMIPS instructions from being accepted. 15999 16000 The directive '.set mdmx' makes the assembler accept instructions 16001from the MDMX Application Specific Extension from that point on in the 16002assembly. The '.set nomdmx' directive prevents MDMX instructions from 16003being accepted. 16004 16005 The directive '.set dsp' makes the assembler accept instructions from 16006the DSP Release 1 Application Specific Extension from that point on in 16007the assembly. The '.set nodsp' directive prevents DSP Release 1 16008instructions from being accepted. 16009 16010 The directive '.set dspr2' makes the assembler accept instructions 16011from the DSP Release 2 Application Specific Extension from that point on 16012in the assembly. This directive implies '.set dsp'. The '.set nodspr2' 16013directive prevents DSP Release 2 instructions from being accepted. 16014 16015 The directive '.set dspr3' makes the assembler accept instructions 16016from the DSP Release 3 Application Specific Extension from that point on 16017in the assembly. This directive implies '.set dsp' and '.set dspr2'. 16018The '.set nodspr3' directive prevents DSP Release 3 instructions from 16019being accepted. 16020 16021 The directive '.set mt' makes the assembler accept instructions from 16022the MT Application Specific Extension from that point on in the 16023assembly. The '.set nomt' directive prevents MT instructions from being 16024accepted. 16025 16026 The directive '.set mcu' makes the assembler accept instructions from 16027the MCU Application Specific Extension from that point on in the 16028assembly. The '.set nomcu' directive prevents MCU instructions from 16029being accepted. 16030 16031 The directive '.set msa' makes the assembler accept instructions from 16032the MIPS SIMD Architecture Extension from that point on in the assembly. 16033The '.set nomsa' directive prevents MSA instructions from being 16034accepted. 16035 16036 The directive '.set virt' makes the assembler accept instructions 16037from the Virtualization Application Specific Extension from that point 16038on in the assembly. The '.set novirt' directive prevents Virtualization 16039instructions from being accepted. 16040 16041 The directive '.set xpa' makes the assembler accept instructions from 16042the XPA Extension from that point on in the assembly. The '.set noxpa' 16043directive prevents XPA instructions from being accepted. 16044 16045 The directive '.set mips16e2' makes the assembler accept instructions 16046from the MIPS16e2 Application Specific Extension from that point on in 16047the assembly, whenever in MIPS16 mode. The '.set nomips16e2' directive 16048prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. 16049Neither directive affects the state of MIPS16 mode being active itself 16050which has separate controls. 16051 16052 The directive '.set crc' makes the assembler accept instructions from 16053the CRC Extension from that point on in the assembly. The '.set nocrc' 16054directive prevents CRC instructions from being accepted. 16055 16056 The directive '.set ginv' makes the assembler accept instructions 16057from the GINV Extension from that point on in the assembly. The '.set 16058noginv' directive prevents GINV instructions from being accepted. 16059 16060 The directive '.set loongson-mmi' makes the assembler accept 16061instructions from the MMI Extension from that point on in the assembly. 16062The '.set noloongson-mmi' directive prevents MMI instructions from being 16063accepted. 16064 16065 The directive '.set loongson-cam' makes the assembler accept 16066instructions from the Loongson CAM from that point on in the assembly. 16067The '.set noloongson-cam' directive prevents Loongson CAM instructions 16068from being accepted. 16069 16070 The directive '.set loongson-ext' makes the assembler accept 16071instructions from the Loongson EXT from that point on in the assembly. 16072The '.set noloongson-ext' directive prevents Loongson EXT instructions 16073from being accepted. 16074 16075 The directive '.set loongson-ext2' makes the assembler accept 16076instructions from the Loongson EXT2 from that point on in the assembly. 16077This directive implies '.set loognson-ext'. The '.set noloongson-ext2' 16078directive prevents Loongson EXT2 instructions from being accepted. 16079 16080 Traditional MIPS assemblers do not support these directives. 16081 16082 16083File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent 16084 160859.27.13 Directives to override floating-point options 16086----------------------------------------------------- 16087 16088The directives '.set softfloat' and '.set hardfloat' provide finer 16089control of disabling and enabling float-point instructions. These 16090directives always override the default (that hard-float instructions are 16091accepted) or the command-line options ('-msoft-float' and 16092'-mhard-float'). 16093 16094 The directives '.set singlefloat' and '.set doublefloat' provide 16095finer control of disabling and enabling double-precision float-point 16096operations. These directives always override the default (that 16097double-precision operations are accepted) or the command-line options 16098('-msingle-float' and '-mdouble-float'). 16099 16100 Traditional MIPS assemblers do not support these directives. 16101 16102 16103File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent 16104 161059.27.14 Syntactical considerations for the MIPS assembler 16106--------------------------------------------------------- 16107 16108* Menu: 16109 16110* MIPS-Chars:: Special Characters 16111 16112 16113File: as.info, Node: MIPS-Chars, Up: MIPS Syntax 16114 161159.27.14.1 Special Characters 16116............................ 16117 16118The presence of a '#' on a line indicates the start of a comment that 16119extends to the end of the current line. 16120 16121 If a '#' appears as the first character of a line, the whole line is 16122treated as a comment, but in this case the line can also be a logical 16123line number directive (*note Comments::) or a preprocessor control 16124command (*note Preprocessing::). 16125 16126 The ';' character can be used to separate statements on the same 16127line. 16128 16129 16130File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 16131 161329.28 MMIX Dependent Features 16133============================ 16134 16135* Menu: 16136 16137* MMIX-Opts:: Command-line Options 16138* MMIX-Expand:: Instruction expansion 16139* MMIX-Syntax:: Syntax 16140* MMIX-mmixal:: Differences to 'mmixal' syntax and semantics 16141 16142 16143File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 16144 161459.28.1 Command-line Options 16146--------------------------- 16147 16148The MMIX version of 'as' has some machine-dependent options. 16149 16150 When '--fixed-special-register-names' is specified, only the register 16151names specified in *note MMIX-Regs:: are recognized in the instructions 16152'PUT' and 'GET'. 16153 16154 You can use the '--globalize-symbols' to make all symbols global. 16155This option is useful when splitting up a 'mmixal' program into several 16156files. 16157 16158 The '--gnu-syntax' turns off most syntax compatibility with 'mmixal'. 16159Its usability is currently doubtful. 16160 16161 The '--relax' option is not fully supported, but will eventually make 16162the object file prepared for linker relaxation. 16163 16164 If you want to avoid inadvertently calling a predefined symbol and 16165would rather get an error, for example when using 'as' with a compiler 16166or other machine-generated code, specify '--no-predefined-syms'. This 16167turns off built-in predefined definitions of all such symbols, including 16168rounding-mode symbols, segment symbols, 'BIT' symbols, and 'TRAP' 16169symbols used in 'mmix' "system calls". It also turns off predefined 16170special-register names, except when used in 'PUT' and 'GET' 16171instructions. 16172 16173 By default, some instructions are expanded to fit the size of the 16174operand or an external symbol (*note MMIX-Expand::). By passing 16175'--no-expand', no such expansion will be done, instead causing errors at 16176link time if the operand does not fit. 16177 16178 The 'mmixal' documentation (*note mmixsite::) specifies that global 16179registers allocated with the 'GREG' directive (*note MMIX-greg::) and 16180initialized to the same non-zero value, will refer to the same global 16181register. This isn't strictly enforceable in 'as' since the final 16182addresses aren't known until link-time, but it will do an effort unless 16183the '--no-merge-gregs' option is specified. (Register merging isn't yet 16184implemented in 'ld'.) 16185 16186 'as' will warn every time it expands an instruction to fit an operand 16187unless the option '-x' is specified. It is believed that this behaviour 16188is more useful than just mimicking 'mmixal''s behaviour, in which 16189instructions are only expanded if the '-x' option is specified, and 16190assembly fails otherwise, when an instruction needs to be expanded. It 16191needs to be kept in mind that 'mmixal' is both an assembler and linker, 16192while 'as' will expand instructions that at link stage can be 16193contracted. (Though linker relaxation isn't yet implemented in 'ld'.) 16194The option '-x' also implies '--linker-allocated-gregs'. 16195 16196 If instruction expansion is enabled, 'as' can expand a 'PUSHJ' 16197instruction into a series of instructions. The shortest expansion is to 16198not expand it, but just mark the call as redirectable to a stub, which 16199'ld' creates at link-time, but only if the original 'PUSHJ' instruction 16200is found not to reach the target. The stub consists of the necessary 16201instructions to form a jump to the target. This happens if 'as' can 16202assert that the 'PUSHJ' instruction can reach such a stub. The option 16203'--no-pushj-stubs' disables this shorter expansion, and the longer 16204series of instructions is then created at assembly-time. The option 16205'--no-stubs' is a synonym, intended for compatibility with future 16206releases, where generation of stubs for other instructions may be 16207implemented. 16208 16209 Usually a two-operand-expression (*note GREG-base::) without a 16210matching 'GREG' directive is treated as an error by 'as'. When the 16211option '--linker-allocated-gregs' is in effect, they are instead passed 16212through to the linker, which will allocate as many global registers as 16213is needed. 16214 16215 16216File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 16217 162189.28.2 Instruction expansion 16219---------------------------- 16220 16221When 'as' encounters an instruction with an operand that is either not 16222known or does not fit the operand size of the instruction, 'as' (and 16223'ld') will expand the instruction into a sequence of instructions 16224semantically equivalent to the operand fitting the instruction. 16225Expansion will take place for the following instructions: 16226 16227'GETA' 16228 Expands to a sequence of four instructions: 'SETL', 'INCML', 16229 'INCMH' and 'INCH'. The operand must be a multiple of four. 16230Conditional branches 16231 A branch instruction is turned into a branch with the complemented 16232 condition and prediction bit over five instructions; four 16233 instructions setting '$255' to the operand value, which like with 16234 'GETA' must be a multiple of four, and a final 'GO $255,$255,0'. 16235'PUSHJ' 16236 Similar to expansion for conditional branches; four instructions 16237 set '$255' to the operand value, followed by a 'PUSHGO 16238 $255,$255,0'. 16239'JMP' 16240 Similar to conditional branches and 'PUSHJ'. The final instruction 16241 is 'GO $255,$255,0'. 16242 16243 The linker 'ld' is expected to shrink these expansions for code 16244assembled with '--relax' (though not currently implemented). 16245 16246 16247File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 16248 162499.28.3 Syntax 16250------------- 16251 16252The assembly syntax is supposed to be upward compatible with that 16253described in Sections 1.3 and 1.4 of 'The Art of Computer Programming, 16254Volume 1'. Draft versions of those chapters as well as other MMIX 16255information is located at 16256<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>. Most code 16257examples from the mmixal package located there should work unmodified 16258when assembled and linked as single files, with a few noteworthy 16259exceptions (*note MMIX-mmixal::). 16260 16261 Before an instruction is emitted, the current location is aligned to 16262the next four-byte boundary. If a label is defined at the beginning of 16263the line, its value will be the aligned value. 16264 16265 In addition to the traditional hex-prefix '0x', a hexadecimal number 16266can also be specified by the prefix character '#'. 16267 16268 After all operands to an MMIX instruction or directive have been 16269specified, the rest of the line is ignored, treated as a comment. 16270 16271* Menu: 16272 16273* MMIX-Chars:: Special Characters 16274* MMIX-Symbols:: Symbols 16275* MMIX-Regs:: Register Names 16276* MMIX-Pseudos:: Assembler Directives 16277 16278 16279File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 16280 162819.28.3.1 Special Characters 16282........................... 16283 16284The characters '*' and '#' are line comment characters; each start a 16285comment at the beginning of a line, but only at the beginning of a line. 16286A '#' prefixes a hexadecimal number if found elsewhere on a line. If a 16287'#' appears at the start of a line the whole line is treated as a 16288comment, but the line can also act as a logical line number directive 16289(*note Comments::) or a preprocessor control command (*note 16290Preprocessing::). 16291 16292 Two other characters, '%' and '!', each start a comment anywhere on 16293the line. Thus you can't use the 'modulus' and 'not' operators in 16294expressions normally associated with these two characters. 16295 16296 A ';' is a line separator, treated as a new-line, so separate 16297instructions can be specified on a single line. 16298 16299 16300File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 16301 163029.28.3.2 Symbols 16303................ 16304 16305The character ':' is permitted in identifiers. There are two exceptions 16306to it being treated as any other symbol character: if a symbol begins 16307with ':', it means that the symbol is in the global namespace and that 16308the current prefix should not be prepended to that symbol (*note 16309MMIX-prefix::). The ':' is then not considered part of the symbol. For 16310a symbol in the label position (first on a line), a ':' at the end of a 16311symbol is silently stripped off. A label is permitted, but not 16312required, to be followed by a ':', as with many other assembly formats. 16313 16314 The character '@' in an expression, is a synonym for '.', the current 16315location. 16316 16317 In addition to the common forward and backward local symbol formats 16318(*note Symbol Names::), they can be specified with upper-case 'B' and 16319'F', as in '8B' and '9F'. A local label defined for the current 16320position is written with a 'H' appended to the number: 16321 3H LDB $0,$1,2 16322 This and traditional local-label formats cannot be mixed: a label 16323must be defined and referred to using the same format. 16324 16325 There's a minor caveat: just as for the ordinary local symbols, the 16326local symbols are translated into ordinary symbols using control 16327characters are to hide the ordinal number of the symbol. Unfortunately, 16328these symbols are not translated back in error messages. Thus you may 16329see confusing error messages when local symbols are used. Control 16330characters '\003' (control-C) and '\004' (control-D) are used for the 16331MMIX-specific local-symbol syntax. 16332 16333 The symbol 'Main' is handled specially; it is always global. 16334 16335 By defining the symbols '__.MMIX.start..text' and 16336'__.MMIX.start..data', the address of respectively the '.text' and 16337'.data' segments of the final program can be defined, though when 16338linking more than one object file, the code or data in the object file 16339containing the symbol is not guaranteed to be start at that position; 16340just the final executable. *Note MMIX-loc::. 16341 16342 16343File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 16344 163459.28.3.3 Register names 16346....................... 16347 16348Local and global registers are specified as '$0' to '$255'. The 16349recognized special register names are 'rJ', 'rA', 'rB', 'rC', 'rD', 16350'rE', 'rF', 'rG', 'rH', 'rI', 'rK', 'rL', 'rM', 'rN', 'rO', 'rP', 'rQ', 16351'rR', 'rS', 'rT', 'rU', 'rV', 'rW', 'rX', 'rY', 'rZ', 'rBB', 'rTT', 16352'rWW', 'rXX', 'rYY' and 'rZZ'. A leading ':' is optional for special 16353register names. 16354 16355 Local and global symbols can be equated to register names and used in 16356place of ordinary registers. 16357 16358 Similarly for special registers, local and global symbols can be 16359used. Also, symbols equated from numbers and constant expressions are 16360allowed in place of a special register, except when either of the 16361options '--no-predefined-syms' and '--fixed-special-register-names' are 16362specified. Then only the special register names above are allowed for 16363the instructions having a special register operand; 'GET' and 'PUT'. 16364 16365 16366File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 16367 163689.28.3.4 Assembler Directives 16369............................. 16370 16371'LOC' 16372 16373 The 'LOC' directive sets the current location to the value of the 16374 operand field, which may include changing sections. If the operand 16375 is a constant, the section is set to either '.data' if the value is 16376 '0x2000000000000000' or larger, else it is set to '.text'. Within 16377 a section, the current location may only be changed to 16378 monotonically higher addresses. A LOC expression must be a 16379 previously defined symbol or a "pure" constant. 16380 16381 An example, which sets the label PREV to the current location, and 16382 updates the current location to eight bytes forward: 16383 prev LOC @+8 16384 16385 When a LOC has a constant as its operand, a symbol 16386 '__.MMIX.start..text' or '__.MMIX.start..data' is defined depending 16387 on the address as mentioned above. Each such symbol is interpreted 16388 as special by the linker, locating the section at that address. 16389 Note that if multiple files are linked, the first object file with 16390 that section will be mapped to that address (not necessarily the 16391 file with the LOC definition). 16392 16393'LOCAL' 16394 16395 Example: 16396 LOCAL external_symbol 16397 LOCAL 42 16398 .local asymbol 16399 16400 This directive-operation generates a link-time assertion that the 16401 operand does not correspond to a global register. The operand is 16402 an expression that at link-time resolves to a register symbol or a 16403 number. A number is treated as the register having that number. 16404 There is one restriction on the use of this directive: the 16405 pseudo-directive must be placed in a section with contents, code or 16406 data. 16407 16408'IS' 16409 16410 The 'IS' directive: 16411 asymbol IS an_expression 16412 sets the symbol 'asymbol' to 'an_expression'. A symbol may not be 16413 set more than once using this directive. Local labels may be set 16414 using this directive, for example: 16415 5H IS @+4 16416 16417'GREG' 16418 16419 This directive reserves a global register, gives it an initial 16420 value and optionally gives it a symbolic name. Some examples: 16421 16422 areg GREG 16423 breg GREG data_value 16424 GREG data_buffer 16425 .greg creg, another_data_value 16426 16427 The symbolic register name can be used in place of a (non-special) 16428 register. If a value isn't provided, it defaults to zero. Unless 16429 the option '--no-merge-gregs' is specified, non-zero registers 16430 allocated with this directive may be eliminated by 'as'; another 16431 register with the same value used in its place. Any of the 16432 instructions 'CSWAP', 'GO', 'LDA', 'LDBU', 'LDB', 'LDHT', 'LDOU', 16433 'LDO', 'LDSF', 'LDTU', 'LDT', 'LDUNC', 'LDVTS', 'LDWU', 'LDW', 16434 'PREGO', 'PRELD', 'PREST', 'PUSHGO', 'STBU', 'STB', 'STCO', 'STHT', 16435 'STOU', 'STSF', 'STTU', 'STT', 'STUNC', 'SYNCD', 'SYNCID', can have 16436 a value nearby an initial value in place of its second and third 16437 operands. Here, "nearby" is defined as within the range 0...255 16438 from the initial value of such an allocated register. 16439 16440 buffer1 BYTE 0,0,0,0,0 16441 buffer2 BYTE 0,0,0,0,0 16442 ... 16443 GREG buffer1 16444 LDOU $42,buffer2 16445 In the example above, the 'Y' field of the 'LDOUI' instruction 16446 (LDOU with a constant Z) will be replaced with the global register 16447 allocated for 'buffer1', and the 'Z' field will have the value 5, 16448 the offset from 'buffer1' to 'buffer2'. The result is equivalent 16449 to this code: 16450 buffer1 BYTE 0,0,0,0,0 16451 buffer2 BYTE 0,0,0,0,0 16452 ... 16453 tmpreg GREG buffer1 16454 LDOU $42,tmpreg,(buffer2-buffer1) 16455 16456 Global registers allocated with this directive are allocated in 16457 order higher-to-lower within a file. Other than that, the exact 16458 order of register allocation and elimination is undefined. For 16459 example, the order is undefined when more than one file with such 16460 directives are linked together. With the options '-x' and 16461 '--linker-allocated-gregs', 'GREG' directives for two-operand cases 16462 like the one mentioned above can be omitted. Sufficient global 16463 registers will then be allocated by the linker. 16464 16465'BYTE' 16466 16467 The 'BYTE' directive takes a series of operands separated by a 16468 comma. If an operand is a string (*note Strings::), each character 16469 of that string is emitted as a byte. Other operands must be 16470 constant expressions without forward references, in the range 16471 0...255. If you need operands having expressions with forward 16472 references, use '.byte' (*note Byte::). An operand can be omitted, 16473 defaulting to a zero value. 16474 16475'WYDE' 16476'TETRA' 16477'OCTA' 16478 16479 The directives 'WYDE', 'TETRA' and 'OCTA' emit constants of two, 16480 four and eight bytes size respectively. Before anything else 16481 happens for the directive, the current location is aligned to the 16482 respective constant-size boundary. If a label is defined at the 16483 beginning of the line, its value will be that after the alignment. 16484 A single operand can be omitted, defaulting to a zero value emitted 16485 for the directive. Operands can be expressed as strings (*note 16486 Strings::), in which case each character in the string is emitted 16487 as a separate constant of the size indicated by the directive. 16488 16489'PREFIX' 16490 16491 The 'PREFIX' directive sets a symbol name prefix to be prepended to 16492 all symbols (except local symbols, *note MMIX-Symbols::), that are 16493 not prefixed with ':', until the next 'PREFIX' directive. Such 16494 prefixes accumulate. For example, 16495 PREFIX a 16496 PREFIX b 16497 c IS 0 16498 defines a symbol 'abc' with the value 0. 16499 16500'BSPEC' 16501'ESPEC' 16502 16503 A pair of 'BSPEC' and 'ESPEC' directives delimit a section of 16504 special contents (without specified semantics). Example: 16505 BSPEC 42 16506 TETRA 1,2,3 16507 ESPEC 16508 The single operand to 'BSPEC' must be number in the range 0...255. 16509 The 'BSPEC' number 80 is used by the GNU binutils implementation. 16510 16511 16512File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 16513 165149.28.4 Differences to 'mmixal' 16515------------------------------ 16516 16517The binutils 'as' and 'ld' combination has a few differences in function 16518compared to 'mmixal' (*note mmixsite::). 16519 16520 The replacement of a symbol with a GREG-allocated register (*note 16521GREG-base::) is not handled the exactly same way in 'as' as in 'mmixal'. 16522This is apparent in the 'mmixal' example file 'inout.mms', where 16523different registers with different offsets, eventually yielding the same 16524address, are used in the first instruction. This type of difference 16525should however not affect the function of any program unless it has 16526specific assumptions about the allocated register number. 16527 16528 Line numbers (in the 'mmo' object format) are currently not 16529supported. 16530 16531 Expression operator precedence is not that of mmixal: operator 16532precedence is that of the C programming language. It's recommended to 16533use parentheses to explicitly specify wanted operator precedence 16534whenever more than one type of operators are used. 16535 16536 The serialize unary operator '&', the fractional division operator 16537'//', the logical not operator '!' and the modulus operator '%' are not 16538available. 16539 16540 Symbols are not global by default, unless the option 16541'--globalize-symbols' is passed. Use the '.global' directive to 16542globalize symbols (*note Global::). 16543 16544 Operand syntax is a bit stricter with 'as' than 'mmixal'. For 16545example, you can't say 'addu 1,2,3', instead you must write 'addu 16546$1,$2,3'. 16547 16548 You can't LOC to a lower address than those already visited (i.e., 16549"backwards"). 16550 16551 A LOC directive must come before any emitted code. 16552 16553 Predefined symbols are visible as file-local symbols after use. (In 16554the ELF file, that is--the linked mmo file has no notion of a file-local 16555symbol.) 16556 16557 Some mapping of constant expressions to sections in LOC expressions 16558is attempted, but that functionality is easily confused and should be 16559avoided unless compatibility with 'mmixal' is required. A LOC 16560expression to '0x2000000000000000' or higher, maps to the '.data' 16561section and lower addresses map to the '.text' section (*note 16562MMIX-loc::). 16563 16564 The code and data areas are each contiguous. Sparse programs with 16565far-away LOC directives will take up the same amount of space as a 16566contiguous program with zeros filled in the gaps between the LOC 16567directives. If you need sparse programs, you might try and get the 16568wanted effect with a linker script and splitting up the code parts into 16569sections (*note Section::). Assembly code for this, to be compatible 16570with 'mmixal', would look something like: 16571 .if 0 16572 LOC away_expression 16573 .else 16574 .section away,"ax" 16575 .fi 16576 'as' will not execute the LOC directive and 'mmixal' ignores the 16577lines with '.'. This construct can be used generally to help 16578compatibility. 16579 16580 Symbols can't be defined twice-not even to the same value. 16581 16582 Instruction mnemonics are recognized case-insensitive, though the 16583'IS' and 'GREG' pseudo-operations must be specified in upper-case 16584characters. 16585 16586 There's no unicode support. 16587 16588 The following is a list of programs in 'mmix.tar.gz', available at 16589<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last checked 16590with the version dated 2001-08-25 (md5sum 16591c393470cfc86fac040487d22d2bf0172) that assemble with 'mmixal' but do not 16592assemble with 'as': 16593 16594'silly.mms' 16595 LOC to a previous address. 16596'sim.mms' 16597 Redefines symbol 'Done'. 16598'test.mms' 16599 Uses the serial operator '&'. 16600 16601 16602File: as.info, Node: MSP430-Dependent, Next: NDS32-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 16603 166049.29 MSP 430 Dependent Features 16605=============================== 16606 16607* Menu: 16608 16609* MSP430 Options:: Options 16610* MSP430 Syntax:: Syntax 16611* MSP430 Floating Point:: Floating Point 16612* MSP430 Directives:: MSP 430 Machine Directives 16613* MSP430 Opcodes:: Opcodes 16614* MSP430 Profiling Capability:: Profiling Capability 16615 16616 16617File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 16618 166199.29.1 Options 16620-------------- 16621 16622'-mmcu' 16623 selects the mcu architecture. If the architecture is 430Xv2 then 16624 this also enables NOP generation unless the '-mN' is also 16625 specified. 16626 16627'-mcpu' 16628 selects the cpu architecture. If the architecture is 430Xv2 then 16629 this also enables NOP generation unless the '-mN' is also 16630 specified. 16631 16632'-msilicon-errata=NAME[,NAME...]' 16633 Implements a fixup for named silicon errata. Multiple silicon 16634 errata can be specified by multiple uses of the '-msilicon-errata' 16635 option and/or by including the errata names, separated by commas, 16636 on an individual '-msilicon-errata' option. Errata names currently 16637 recognised by the assembler are: 16638 16639 'cpu4' 16640 'PUSH #4' and 'PUSH #8' need longer encodings on the MSP430. 16641 This option is enabled by default, and cannot be disabled. 16642 'cpu8' 16643 Do not set the 'SP' to an odd value. 16644 'cpu11' 16645 Do not update the 'SR' and the 'PC' in the same instruction. 16646 'cpu12' 16647 Do not use the 'PC' in a 'CMP' or 'BIT' instruction. 16648 'cpu13' 16649 Do not use an arithmetic instruction to modify the 'SR'. 16650 'cpu19' 16651 Insert 'NOP' after 'CPUOFF'. 16652 16653'-msilicon-errata-warn=NAME[,NAME...]' 16654 Like the '-msilicon-errata' option except that instead of fixing 16655 the specified errata, a warning message is issued instead. This 16656 option can be used alongside '-msilicon-errata' to generate 16657 messages whenever a problem is fixed, or on its own in order to 16658 inspect code for potential problems. 16659 16660'-mP' 16661 enables polymorph instructions handler. 16662 16663'-mQ' 16664 enables relaxation at assembly time. DANGEROUS! 16665 16666'-ml' 16667 indicates that the input uses the large code model. 16668 16669'-mn' 16670 enables the generation of a NOP instruction following any 16671 instruction that might change the interrupts enabled/disabled 16672 state. The pipelined nature of the MSP430 core means that any 16673 instruction that changes the interrupt state ('EINT', 'DINT', 'BIC 16674 #8, SR', 'BIS #8, SR' or 'MOV.W <>, SR') must be followed by a NOP 16675 instruction in order to ensure the correct processing of 16676 interrupts. By default it is up to the programmer to supply these 16677 NOP instructions, but this command-line option enables the 16678 automatic insertion by the assembler, if they are missing. 16679 16680'-mN' 16681 disables the generation of a NOP instruction following any 16682 instruction that might change the interrupts enabled/disabled 16683 state. This is the default behaviour. 16684 16685'-my' 16686 tells the assembler to generate a warning message if a NOP does not 16687 immediately follow an instruction that enables or disables 16688 interrupts. This is the default. 16689 16690 Note that this option can be stacked with the '-mn' option so that 16691 the assembler will both warn about missing NOP instructions and 16692 then insert them automatically. 16693 16694'-mY' 16695 disables warnings about missing NOP instructions. 16696 16697'-md' 16698 mark the object file as one that requires data to copied from ROM 16699 to RAM at execution startup. Disabled by default. 16700 16701'-mdata-region=REGION' 16702 Select the region data will be placed in. Region placement is 16703 performed by the compiler and linker. The only effect this option 16704 will have on the assembler is that if UPPER or EITHER is selected, 16705 then the symbols to initialise high data and bss will be defined. 16706 Valid REGION values are: 16707 'none' 16708 'lower' 16709 'upper' 16710 'either' 16711 16712 16713File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 16714 167159.29.2 Syntax 16716------------- 16717 16718* Menu: 16719 16720* MSP430-Macros:: Macros 16721* MSP430-Chars:: Special Characters 16722* MSP430-Regs:: Register Names 16723* MSP430-Ext:: Assembler Extensions 16724 16725 16726File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 16727 167289.29.2.1 Macros 16729............... 16730 16731The macro syntax used on the MSP 430 is like that described in the MSP 16732430 Family Assembler Specification. Normal 'as' macros should still 16733work. 16734 16735 Additional built-in macros are: 16736 16737'llo(exp)' 16738 Extracts least significant word from 32-bit expression 'exp'. 16739 16740'lhi(exp)' 16741 Extracts most significant word from 32-bit expression 'exp'. 16742 16743'hlo(exp)' 16744 Extracts 3rd word from 64-bit expression 'exp'. 16745 16746'hhi(exp)' 16747 Extracts 4rd word from 64-bit expression 'exp'. 16748 16749 They normally being used as an immediate source operand. 16750 mov #llo(1), r10 ; == mov #1, r10 16751 mov #lhi(1), r10 ; == mov #0, r10 16752 16753 16754File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 16755 167569.29.2.2 Special Characters 16757........................... 16758 16759A semicolon (';') appearing anywhere on a line starts a comment that 16760extends to the end of that line. 16761 16762 If a '#' appears as the first character of a line then the whole line 16763is treated as a comment, but it can also be a logical line number 16764directive (*note Comments::) or a preprocessor control command (*note 16765Preprocessing::). 16766 16767 Multiple statements can appear on the same line provided that they 16768are separated by the '{' character. 16769 16770 The character '$' in jump instructions indicates current location and 16771implemented only for TI syntax compatibility. 16772 16773 16774File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 16775 167769.29.2.3 Register Names 16777....................... 16778 16779General-purpose registers are represented by predefined symbols of the 16780form 'rN' (for global registers), where N represents a number between 16781'0' and '15'. The leading letters may be in either upper or lower case; 16782for example, 'r13' and 'R7' are both valid register names. 16783 16784 Register names 'PC', 'SP' and 'SR' cannot be used as register names 16785and will be treated as variables. Use 'r0', 'r1', and 'r2' instead. 16786 16787 16788File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 16789 167909.29.2.4 Assembler Extensions 16791............................. 16792 16793'@rN' 16794 As destination operand being treated as '0(rn)' 16795 16796'0(rN)' 16797 As source operand being treated as '@rn' 16798 16799'jCOND +N' 16800 Skips next N bytes followed by jump instruction and equivalent to 16801 'jCOND $+N+2' 16802 16803 Also, there are some instructions, which cannot be found in other 16804assemblers. These are branch instructions, which has different opcodes 16805upon jump distance. They all got PC relative addressing mode. 16806 16807'beq label' 16808 A polymorph instruction which is 'jeq label' in case if jump 16809 distance within allowed range for cpu's jump instruction. If not, 16810 this unrolls into a sequence of 16811 jne $+6 16812 br label 16813 16814'bne label' 16815 A polymorph instruction which is 'jne label' or 'jeq +4; br label' 16816 16817'blt label' 16818 A polymorph instruction which is 'jl label' or 'jge +4; br label' 16819 16820'bltn label' 16821 A polymorph instruction which is 'jn label' or 'jn +2; jmp +4; br 16822 label' 16823 16824'bltu label' 16825 A polymorph instruction which is 'jlo label' or 'jhs +2; br label' 16826 16827'bge label' 16828 A polymorph instruction which is 'jge label' or 'jl +4; br label' 16829 16830'bgeu label' 16831 A polymorph instruction which is 'jhs label' or 'jlo +4; br label' 16832 16833'bgt label' 16834 A polymorph instruction which is 'jeq +2; jge label' or 'jeq +6; jl 16835 +4; br label' 16836 16837'bgtu label' 16838 A polymorph instruction which is 'jeq +2; jhs label' or 'jeq +6; 16839 jlo +4; br label' 16840 16841'bleu label' 16842 A polymorph instruction which is 'jeq label; jlo label' or 'jeq +2; 16843 jhs +4; br label' 16844 16845'ble label' 16846 A polymorph instruction which is 'jeq label; jl label' or 'jeq +2; 16847 jge +4; br label' 16848 16849'jump label' 16850 A polymorph instruction which is 'jmp label' or 'br label' 16851 16852 16853File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 16854 168559.29.3 Floating Point 16856--------------------- 16857 16858The MSP 430 family uses IEEE 32-bit floating-point numbers. 16859 16860 16861File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 16862 168639.29.4 MSP 430 Machine Directives 16864--------------------------------- 16865 16866'.file' 16867 This directive is ignored; it is accepted for compatibility with 16868 other MSP 430 assemblers. 16869 16870 _Warning:_ in other versions of the GNU assembler, '.file' is 16871 used for the directive called '.app-file' in the MSP 430 16872 support. 16873 16874'.line' 16875 This directive is ignored; it is accepted for compatibility with 16876 other MSP 430 assemblers. 16877 16878'.arch' 16879 Sets the target microcontroller in the same way as the '-mmcu' 16880 command-line option. 16881 16882'.cpu' 16883 Sets the target architecture in the same way as the '-mcpu' 16884 command-line option. 16885 16886'.profiler' 16887 This directive instructs assembler to add new profile entry to the 16888 object file. 16889 16890'.refsym' 16891 This directive instructs assembler to add an undefined reference to 16892 the symbol following the directive. The maximum symbol name length 16893 is 1023 characters. No relocation is created for this symbol; it 16894 will exist purely for pulling in object files from archives. Note 16895 that this reloc is not sufficient to prevent garbage collection; 16896 use a KEEP() directive in the linker file to preserve such objects. 16897 16898'.mspabi_attribute' 16899 This directive tells the assembler what the MSPABI build attributes 16900 for this file are. This is used for validating the command line 16901 options passed to the assembler against the options the original 16902 source file was compiled with. The expected format is: 16903 '.mspabi_attribute tag_name, tag_value' For example, to set the tag 16904 'OFBA_MSPABI_Tag_ISA' to 'MSP430X': '.mspabi_attribute 4, 2' 16905 16906 See the 'MSP430 EABI, document slaa534' for the details on tag 16907 names and values. 16908 16909 16910File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 16911 169129.29.5 Opcodes 16913-------------- 16914 16915'as' implements all the standard MSP 430 opcodes. No additional 16916pseudo-instructions are needed on this family. 16917 16918 For information on the 430 machine instruction set, see 'MSP430 16919User's Manual, document slau049d', Texas Instrument, Inc. 16920 16921 16922File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 16923 169249.29.6 Profiling Capability 16925--------------------------- 16926 16927It is a performance hit to use gcc's profiling approach for this tiny 16928target. Even more - jtag hardware facility does not perform any 16929profiling functions. However we've got gdb's built-in simulator where 16930we can do anything. 16931 16932 We define new section '.profiler' which holds all profiling 16933information. We define new pseudo operation '.profiler' which will 16934instruct assembler to add new profile entry to the object file. Profile 16935should take place at the present address. 16936 16937 Pseudo operation format: 16938 16939 '.profiler flags,function_to_profile [, cycle_corrector, extra]' 16940 16941 where: 16942 16943 'flags' is a combination of the following characters: 16944 16945 's' 16946 function entry 16947 'x' 16948 function exit 16949 'i' 16950 function is in init section 16951 'f' 16952 function is in fini section 16953 'l' 16954 library call 16955 'c' 16956 libc standard call 16957 'd' 16958 stack value demand 16959 'I' 16960 interrupt service routine 16961 'P' 16962 prologue start 16963 'p' 16964 prologue end 16965 'E' 16966 epilogue start 16967 'e' 16968 epilogue end 16969 'j' 16970 long jump / sjlj unwind 16971 'a' 16972 an arbitrary code fragment 16973 't' 16974 extra parameter saved (a constant value like frame size) 16975 16976'function_to_profile' 16977 a function address 16978'cycle_corrector' 16979 a value which should be added to the cycle counter, zero if 16980 omitted. 16981'extra' 16982 any extra parameter, zero if omitted. 16983 16984 For example: 16985 .global fxx 16986 .type fxx,@function 16987 fxx: 16988 .LFrameOffset_fxx=0x08 16989 .profiler "scdP", fxx ; function entry. 16990 ; we also demand stack value to be saved 16991 push r11 16992 push r10 16993 push r9 16994 push r8 16995 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 16996 ; (this is a prologue end) 16997 ; note, that spare var filled with 16998 ; the farme size 16999 mov r15,r8 17000 ... 17001 .profiler cdE,fxx ; check stack 17002 pop r8 17003 pop r9 17004 pop r10 17005 pop r11 17006 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 17007 ret ; cause 'ret' insn takes 3 cycles 17008 17009 17010File: as.info, Node: NDS32-Dependent, Next: NiosII-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 17011 170129.30 NDS32 Dependent Features 17013============================= 17014 17015The NDS32 processors family includes high-performance and low-power 1701632-bit processors for high-end to low-end. GNU 'as' for NDS32 17017architectures supports NDS32 ISA version 3. For detail about NDS32 17018instruction set, please see the AndeStar ISA User Manual which is 17019available at http://www.andestech.com/en/index/index.htm 17020 17021* Menu: 17022 17023* NDS32 Options:: Assembler options 17024* NDS32 Syntax:: High-level assembly macros 17025 17026 17027File: as.info, Node: NDS32 Options, Next: NDS32 Syntax, Up: NDS32-Dependent 17028 170299.30.1 NDS32 Options 17030-------------------- 17031 17032The NDS32 configurations of GNU 'as' support these special options: 17033 17034'-O1' 17035 Optimize for performance. 17036 17037'-Os' 17038 Optimize for space. 17039 17040'-EL' 17041 Produce little endian data output. 17042 17043'-EB' 17044 Produce little endian data output. 17045 17046'-mpic' 17047 Generate PIC. 17048 17049'-mno-fp-as-gp-relax' 17050 Suppress fp-as-gp relaxation for this file. 17051 17052'-mb2bb-relax' 17053 Back-to-back branch optimization. 17054 17055'-mno-all-relax' 17056 Suppress all relaxation for this file. 17057 17058'-march=<arch name>' 17059 Assemble for architecture <arch name> which could be v3, v3j, v3m, 17060 v3f, v3s, v2, v2j, v2f, v2s. 17061 17062'-mbaseline=<baseline>' 17063 Assemble for baseline <baseline> which could be v2, v3, v3m. 17064 17065'-mfpu-freg=FREG' 17066 Specify a FPU configuration. 17067 '0 8 SP / 4 DP registers' 17068 '1 16 SP / 8 DP registers' 17069 '2 32 SP / 16 DP registers' 17070 '3 32 SP / 32 DP registers' 17071 17072'-mabi=ABI' 17073 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. 17074 17075'-m[no-]mac' 17076 Enable/Disable Multiply instructions support. 17077 17078'-m[no-]div' 17079 Enable/Disable Divide instructions support. 17080 17081'-m[no-]16bit-ext' 17082 Enable/Disable 16-bit extension 17083 17084'-m[no-]dx-regs' 17085 Enable/Disable d0/d1 registers 17086 17087'-m[no-]perf-ext' 17088 Enable/Disable Performance extension 17089 17090'-m[no-]perf2-ext' 17091 Enable/Disable Performance extension 2 17092 17093'-m[no-]string-ext' 17094 Enable/Disable String extension 17095 17096'-m[no-]reduced-regs' 17097 Enable/Disable Reduced Register configuration (GPR16) option 17098 17099'-m[no-]audio-isa-ext' 17100 Enable/Disable AUDIO ISA extension 17101 17102'-m[no-]fpu-sp-ext' 17103 Enable/Disable FPU SP extension 17104 17105'-m[no-]fpu-dp-ext' 17106 Enable/Disable FPU DP extension 17107 17108'-m[no-]fpu-fma' 17109 Enable/Disable FPU fused-multiply-add instructions 17110 17111'-mall-ext' 17112 Turn on all extensions and instructions support 17113 17114 17115File: as.info, Node: NDS32 Syntax, Prev: NDS32 Options, Up: NDS32-Dependent 17116 171179.30.2 Syntax 17118------------- 17119 17120* Menu: 17121 17122* NDS32-Chars:: Special Characters 17123* NDS32-Regs:: Register Names 17124* NDS32-Ops:: Pseudo Instructions 17125 17126 17127File: as.info, Node: NDS32-Chars, Next: NDS32-Regs, Up: NDS32 Syntax 17128 171299.30.2.1 Special Characters 17130........................... 17131 17132Use '#' at column 1 and '!' anywhere in the line except inside quotes. 17133 17134 Multiple instructions in a line are allowed though not recommended 17135and should be separated by ';'. 17136 17137 Assembler is not case-sensitive in general except user defined label. 17138For example, 'jral F1' is different from 'jral f1' while it is the same 17139as 'JRAL F1'. 17140 17141 17142File: as.info, Node: NDS32-Regs, Next: NDS32-Ops, Prev: NDS32-Chars, Up: NDS32 Syntax 17143 171449.30.2.2 Register Names 17145....................... 17146 17147'General purpose registers (GPR)' 17148 There are 32 32-bit general purpose registers $r0 to $r31. 17149 17150'Accumulators d0 and d1' 17151 64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo. 17152 17153'Assembler reserved register $ta' 17154 Register $ta ($r15) is reserved for assembler using. 17155 17156'Operating system reserved registers $p0 and $p1' 17157 Registers $p0 ($r26) and $p1 ($r27) are used by operating system as 17158 scratch registers. 17159 17160'Frame pointer $fp' 17161 Register $r28 is regarded as the frame pointer. 17162 17163'Global pointer' 17164 Register $r29 is regarded as the global pointer. 17165 17166'Link pointer' 17167 Register $r30 is regarded as the link pointer. 17168 17169'Stack pointer' 17170 Register $r31 is regarded as the stack pointer. 17171 17172 17173File: as.info, Node: NDS32-Ops, Prev: NDS32-Regs, Up: NDS32 Syntax 17174 171759.30.2.3 Pseudo Instructions 17176............................ 17177 17178'li rt5,imm32' 17179 load 32-bit integer into register rt5. 'sethi rt5,hi20(imm32)' and 17180 then 'ori rt5,reg,lo12(imm32)'. 17181 17182'la rt5,var' 17183 Load 32-bit address of var into register rt5. 'sethi 17184 rt5,hi20(var)' and then 'ori reg,rt5,lo12(var)' 17185 17186'l.[bhw] rt5,var' 17187 Load value of var into register rt5. 'sethi $ta,hi20(var)' and 17188 then 'l[bhw]i rt5,[$ta+lo12(var)]' 17189 17190'l.[bh]s rt5,var' 17191 Load value of var into register rt5. 'sethi $ta,hi20(var)' and 17192 then 'l[bh]si rt5,[$ta+lo12(var)]' 17193 17194'l.[bhw]p rt5,var,inc' 17195 Load value of var into register rt5 and increment $ta by amount 17196 inc. 'la $ta,var' and then 'l[bhw]i.bi rt5,[$ta],inc' 17197 17198'l.[bhw]pc rt5,inc' 17199 Continue loading value of var into register rt5 and increment $ta 17200 by amount inc. 'l[bhw]i.bi rt5,[$ta],inc.' 17201 17202'l.[bh]sp rt5,var,inc' 17203 Load value of var into register rt5 and increment $ta by amount 17204 inc. 'la $ta,var' and then 'l[bh]si.bi rt5,[$ta],inc' 17205 17206'l.[bh]spc rt5,inc' 17207 Continue loading value of var into register rt5 and increment $ta 17208 by amount inc. 'l[bh]si.bi rt5,[$ta],inc.' 17209 17210's.[bhw] rt5,var' 17211 Store register rt5 to var. 'sethi $ta,hi20(var)' and then 's[bhw]i 17212 rt5,[$ta+lo12(var)]' 17213 17214's.[bhw]p rt5,var,inc' 17215 Store register rt5 to var and increment $ta by amount inc. 'la 17216 $ta,var' and then 's[bhw]i.bi rt5,[$ta],inc' 17217 17218's.[bhw]pc rt5,inc' 17219 Continue storing register rt5 to var and increment $ta by amount 17220 inc. 's[bhw]i.bi rt5,[$ta],inc.' 17221 17222'not rt5,ra5' 17223 Alias of 'nor rt5,ra5,ra5'. 17224 17225'neg rt5,ra5' 17226 Alias of 'subri rt5,ra5,0'. 17227 17228'br rb5' 17229 Depending on how it is assembled, it is translated into 'r5 rb5' or 17230 'jr rb5'. 17231 17232'b label' 17233 Branch to label depending on how it is assembled, it is translated 17234 into 'j8 label', 'j label', or "'la $ta,label' 'br $ta'". 17235 17236'bral rb5' 17237 Alias of jral br5 depending on how it is assembled, it is 17238 translated into 'jral5 rb5' or 'jral rb5'. 17239 17240'bal fname' 17241 Alias of jal fname depending on how it is assembled, it is 17242 translated into 'jal fname' or "'la $ta,fname' 'bral $ta'". 17243 17244'call fname' 17245 Call function fname same as 'jal fname'. 17246 17247'move rt5,ra5' 17248 For 16-bit, this is 'mov55 rt5,ra5'. For no 16-bit, this is 'ori 17249 rt5,ra5,0'. 17250 17251'move rt5,var' 17252 This is the same as 'l.w rt5,var'. 17253 17254'move rt5,imm32' 17255 This is the same as 'li rt5,imm32'. 17256 17257'pushm ra5,rb5' 17258 Push contents of registers from ra5 to rb5 into stack. 17259 17260'push ra5' 17261 Push content of register ra5 into stack. (same 'pushm ra5,ra5'). 17262 17263'push.d var' 17264 Push value of double-word variable var into stack. 17265 17266'push.w var' 17267 Push value of word variable var into stack. 17268 17269'push.h var' 17270 Push value of half-word variable var into stack. 17271 17272'push.b var' 17273 Push value of byte variable var into stack. 17274 17275'pusha var' 17276 Push 32-bit address of variable var into stack. 17277 17278'pushi imm32' 17279 Push 32-bit immediate value into stack. 17280 17281'popm ra5,rb5' 17282 Pop top of stack values into registers ra5 to rb5. 17283 17284'pop rt5' 17285 Pop top of stack value into register. (same as 'popm rt5,rt5'.) 17286 17287'pop.d var,ra5' 17288 Pop value of double-word variable var from stack using register ra5 17289 as 2nd scratch register. (1st is $ta) 17290 17291'pop.w var,ra5' 17292 Pop value of word variable var from stack using register ra5. 17293 17294'pop.h var,ra5' 17295 Pop value of half-word variable var from stack using register ra5. 17296 17297'pop.b var,ra5' 17298 Pop value of byte variable var from stack using register ra5. 17299 17300 17301File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: NDS32-Dependent, Up: Machine Dependencies 17302 173039.31 Nios II Dependent Features 17304=============================== 17305 17306* Menu: 17307 17308* Nios II Options:: Options 17309* Nios II Syntax:: Syntax 17310* Nios II Relocations:: Relocations 17311* Nios II Directives:: Nios II Machine Directives 17312* Nios II Opcodes:: Opcodes 17313 17314 17315File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent 17316 173179.31.1 Options 17318-------------- 17319 17320'-relax-section' 17321 Replace identified out-of-range branches with PC-relative 'jmp' 17322 sequences when possible. The generated code sequences are suitable 17323 for use in position-independent code, but there is a practical 17324 limit on the extended branch range because of the length of the 17325 sequences. This option is the default. 17326 17327'-relax-all' 17328 Replace branch instructions not determinable to be in range and all 17329 call instructions with 'jmp' and 'callr' sequences (respectively). 17330 This option generates absolute relocations against the target 17331 symbols and is not appropriate for position-independent code. 17332 17333'-no-relax' 17334 Do not replace any branches or calls. 17335 17336'-EB' 17337 Generate big-endian output. 17338 17339'-EL' 17340 Generate little-endian output. This is the default. 17341 17342'-march=ARCHITECTURE' 17343 This option specifies the target architecture. The assembler 17344 issues an error message if an attempt is made to assemble an 17345 instruction which will not execute on the target architecture. The 17346 following architecture names are recognized: 'r1', 'r2'. The 17347 default is 'r1'. 17348 17349 17350File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent 17351 173529.31.2 Syntax 17353------------- 17354 17355* Menu: 17356 17357* Nios II Chars:: Special Characters 17358 17359 17360File: as.info, Node: Nios II Chars, Up: Nios II Syntax 17361 173629.31.2.1 Special Characters 17363........................... 17364 17365'#' is the line comment character. ';' is the line separator character. 17366 17367 17368File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent 17369 173709.31.3 Nios II Machine Relocations 17371---------------------------------- 17372 17373'%hiadj(EXPRESSION)' 17374 Extract the upper 16 bits of EXPRESSION and add one if the 15th bit 17375 is set. 17376 17377 The value of '%hiadj(EXPRESSION)' is: 17378 ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01) 17379 17380 The '%hiadj' relocation is intended to be used with the 'addi', 17381 'ld' or 'st' instructions along with a '%lo', in order to load a 17382 32-bit constant. 17383 17384 movhi r2, %hiadj(symbol) 17385 addi r2, r2, %lo(symbol) 17386 17387'%hi(EXPRESSION)' 17388 Extract the upper 16 bits of EXPRESSION. 17389 17390'%lo(EXPRESSION)' 17391 Extract the lower 16 bits of EXPRESSION. 17392 17393'%gprel(EXPRESSION)' 17394 Subtract the value of the symbol '_gp' from EXPRESSION. 17395 17396 The intention of the '%gprel' relocation is to have a fast small 17397 area of memory which only takes a 16-bit immediate to access. 17398 17399 .section .sdata 17400 fastint: 17401 .int 123 17402 .section .text 17403 ldw r4, %gprel(fastint)(gp) 17404 17405'%call(EXPRESSION)' 17406'%call_lo(EXPRESSION)' 17407'%call_hiadj(EXPRESSION)' 17408'%got(EXPRESSION)' 17409'%got_lo(EXPRESSION)' 17410'%got_hiadj(EXPRESSION)' 17411'%gotoff(EXPRESSION)' 17412'%gotoff_lo(EXPRESSION)' 17413'%gotoff_hiadj(EXPRESSION)' 17414'%tls_gd(EXPRESSION)' 17415'%tls_ie(EXPRESSION)' 17416'%tls_le(EXPRESSION)' 17417'%tls_ldm(EXPRESSION)' 17418'%tls_ldo(EXPRESSION)' 17419 17420 These relocations support the ABI for Linux Systems documented in 17421 the 'Nios II Processor Reference Handbook'. 17422 17423 17424File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent 17425 174269.31.4 Nios II Machine Directives 17427--------------------------------- 17428 17429'.align EXPRESSION [, EXPRESSION]' 17430 This is the generic '.align' directive, however this aligns to a 17431 power of two. 17432 17433'.half EXPRESSION' 17434 Create an aligned constant 2 bytes in size. 17435 17436'.word EXPRESSION' 17437 Create an aligned constant 4 bytes in size. 17438 17439'.dword EXPRESSION' 17440 Create an aligned constant 8 bytes in size. 17441 17442'.2byte EXPRESSION' 17443 Create an unaligned constant 2 bytes in size. 17444 17445'.4byte EXPRESSION' 17446 Create an unaligned constant 4 bytes in size. 17447 17448'.8byte EXPRESSION' 17449 Create an unaligned constant 8 bytes in size. 17450 17451'.16byte EXPRESSION' 17452 Create an unaligned constant 16 bytes in size. 17453 17454'.set noat' 17455 Allows assembly code to use 'at' register without warning. Macro 17456 or relaxation expansions generate warnings. 17457 17458'.set at' 17459 Assembly code using 'at' register generates warnings, and macro 17460 expansion and relaxation are enabled. 17461 17462'.set nobreak' 17463 Allows assembly code to use 'ba' and 'bt' registers without 17464 warning. 17465 17466'.set break' 17467 Turns warnings back on for using 'ba' and 'bt' registers. 17468 17469'.set norelax' 17470 Do not replace any branches or calls. 17471 17472'.set relaxsection' 17473 Replace identified out-of-range branches with 'jmp' sequences 17474 (default). 17475 17476'.set relaxsection' 17477 Replace all branch and call instructions with 'jmp' and 'callr' 17478 sequences. 17479 17480'.set ...' 17481 All other '.set' are the normal use. 17482 17483 17484File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent 17485 174869.31.5 Opcodes 17487-------------- 17488 17489'as' implements all the standard Nios II opcodes documented in the 'Nios 17490II Processor Reference Handbook', including the assembler 17491pseudo-instructions. 17492 17493 17494File: as.info, Node: NS32K-Dependent, Next: OpenRISC-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies 17495 174969.32 NS32K Dependent Features 17497============================= 17498 17499* Menu: 17500 17501* NS32K Syntax:: Syntax 17502 17503 17504File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent 17505 175069.32.1 Syntax 17507------------- 17508 17509* Menu: 17510 17511* NS32K-Chars:: Special Characters 17512 17513 17514File: as.info, Node: NS32K-Chars, Up: NS32K Syntax 17515 175169.32.1.1 Special Characters 17517........................... 17518 17519The presence of a '#' appearing anywhere on a line indicates the start 17520of a comment that extends to the end of that line. 17521 17522 If a '#' appears as the first character of a line then the whole line 17523is treated as a comment, but in this case the line can also be a logical 17524line number directive (*note Comments::) or a preprocessor control 17525command (*note Preprocessing::). 17526 17527 If Sequent compatibility has been configured into the assembler then 17528the '|' character appearing as the first character on a line will also 17529indicate the start of a line comment. 17530 17531 The ';' character can be used to separate statements on the same 17532line. 17533 17534 17535File: as.info, Node: OpenRISC-Dependent, Next: PDP-11-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies 17536 175379.33 OPENRISC Dependent Features 17538================================ 17539 17540* Menu: 17541 17542* OpenRISC-Syntax:: Syntax 17543* OpenRISC-Float:: Floating Point 17544* OpenRISC-Directives:: OpenRISC Machine Directives 17545* OpenRISC-Opcodes:: Opcodes 17546 17547 17548File: as.info, Node: OpenRISC-Syntax, Next: OpenRISC-Float, Up: OpenRISC-Dependent 17549 175509.33.1 OpenRISC Syntax 17551---------------------- 17552 17553The assembler syntax follows the OpenRISC 1000 Architecture Manual. 17554 17555* Menu: 17556 17557* OpenRISC-Chars:: Special Characters 17558* OpenRISC-Regs:: Register Names 17559* OpenRISC-Relocs:: Relocations 17560 17561 17562File: as.info, Node: OpenRISC-Chars, Next: OpenRISC-Regs, Up: OpenRISC-Syntax 17563 175649.33.1.1 Special Characters 17565........................... 17566 17567A '#' character appearing anywhere on a line indicates the start of a 17568comment that extends to the end of that line. 17569 17570 ';' can be used instead of a newline to separate statements. 17571 17572 17573File: as.info, Node: OpenRISC-Regs, Next: OpenRISC-Relocs, Prev: OpenRISC-Chars, Up: OpenRISC-Syntax 17574 175759.33.1.2 Register Names 17576....................... 17577 17578The OpenRISC register file contains 32 general pupose registers. 17579 17580 * The 32 general purpose registers are referred to as 'rN'. 17581 17582 * The stack pointer register 'r1' can be referenced using the alias 17583 'sp'. 17584 17585 * The frame pointer register 'r2' can be referenced using the alias 17586 'fp'. 17587 17588 * The link register 'r9' can be referenced using the alias 'lr'. 17589 17590 Floating point operations use the same general purpose registers. 17591The instructions 'lf.itof.s' (single precision) and 'lf.itof.d' (double 17592precision) can be used to convert integer values to floating point. 17593Likewise, instructions 'lf.ftoi.s' (single precision) and 'lf.ftoi.d' 17594(double precision) can be used to convert floating point to integer. 17595 17596 OpenRISC also contains privileged special purpose registers (SPRs). 17597The SPRs are accessed using the 'l.mfspr' and 'l.mtspr' instructions. 17598 17599 17600File: as.info, Node: OpenRISC-Relocs, Prev: OpenRISC-Regs, Up: OpenRISC-Syntax 17601 176029.33.1.3 Relocations 17603.................... 17604 17605ELF relocations are available as defined in the OpenRISC architecture 17606specification. 17607 17608 'R_OR1K_HI_16_IN_INSN' is obtained using 'hi' and 17609'R_OR1K_LO_16_IN_INSN' and 'R_OR1K_SLO16' are obtained using 'lo'. For 17610signed offsets 'R_OR1K_AHI16' is obtained from 'ha'. For example: 17611 17612 l.movhi r5, hi(symbol) 17613 l.ori r5, r5, lo(symbol) 17614 17615 l.movhi r5, ha(symbol) 17616 l.addi r5, r5, lo(symbol) 17617 17618 These "high" mnemonics extract bits 31:16 of their operand, and the 17619"low" mnemonics extract bits 15:0 of their operand. 17620 17621 The PC relative relocation 'R_OR1K_GOTPC_HI16' can be obtained by 17622enclosing an operand inside of 'gotpchi'. Likewise, the 17623'R_OR1K_GOTPC_LO16' relocation can be obtained using 'gotpclo'. These 17624are mostly used when assembling PIC code. For example, the standard PIC 17625sequence on OpenRISC to get the base of the global offset table, PC 17626relative, into a register, can be performed as: 17627 17628 l.jal 0x8 17629 l.movhi r17, gotpchi(_GLOBAL_OFFSET_TABLE_-4) 17630 l.ori r17, r17, gotpclo(_GLOBAL_OFFSET_TABLE_+0) 17631 l.add r17, r17, r9 17632 17633 Several relocations exist to allow the link editor to perform GOT 17634data references. The 'R_OR1K_GOT16' relocation can obtained by 17635enclosing an operand inside of 'got'. For example, assuming the GOT 17636base is in register 'r17'. 17637 17638 l.lwz r19, got(a)(r17) 17639 l.lwz r21, 0(r19) 17640 17641 Also, several relocations exist for local GOT references. The 17642'R_OR1K_GOTOFF_AHI16' relocation can obtained by enclosing an operand 17643inside of 'gotoffha'. Likewise, 'R_OR1K_GOTOFF_LO16' and 17644'R_OR1K_GOTOFF_SLO16' can be obtained by enclosing an operand inside of 17645'gotofflo'. For example, assuming the GOT base is in register 'rl7': 17646 17647 l.movhi r19, gotoffha(symbol) 17648 l.add r19, r19, r17 17649 l.lwz r19, gotofflo(symbol)(r19) 17650 17651 The above PC relative relocations use a 'l.jal' (jump) instruction 17652and reading of the link register to load the PC. OpenRISC also supports 17653page offset PC relative locations without a jump instruction using the 17654'l.adrp' instruction. By default the 'l.adrp' instruction will create 17655an 'R_OR1K_PCREL_PG21' relocation. Likewise, 'BFD_RELOC_OR1K_LO13' and 17656'BFD_RELOC_OR1K_SLO13' can be obtained by enclosing an operand inside of 17657'po'. For example: 17658 17659 l.adrp r3, symbol 17660 l.ori r4, r3, po(symbol) 17661 l.lbz r5, po(symbol)(r3) 17662 l.sb po(symbol)(r3), r6 17663 17664 Likewise the page offset relocations can be used with GOT references. 17665The relocation 'R_OR1K_GOT_PG21' can be obtained by enclosing an 17666'l.adrp' immediate operand inside of 'got'. Likewise, 'R_OR1K_GOT_LO13' 17667can be obtained by enclosing an operand inside of 'gotpo'. For example 17668to load the value of a GOT symbol into register 'r5' we can do: 17669 17670 l.adrp r17, got(_GLOBAL_OFFSET_TABLE_) 17671 l.lwz r5, gotpo(symbol)(r17) 17672 17673 There are many relocations that can be requested for access to thread 17674local storage variables. All of the OpenRISC TLS mnemonics are 17675supported: 17676 17677 * 'R_OR1K_TLS_GD_HI16' is requested using 'tlsgdhi'. 17678 * 'R_OR1K_TLS_GD_LO16' is requested using 'tlsgdlo'. 17679 * 'R_OR1K_TLS_GD_PG21' is requested using 'tldgd'. 17680 * 'R_OR1K_TLS_GD_LO13' is requested using 'tlsgdpo'. 17681 17682 * 'R_OR1K_TLS_LDM_HI16' is requested using 'tlsldmhi'. 17683 * 'R_OR1K_TLS_LDM_LO16' is requested using 'tlsldmlo'. 17684 * 'R_OR1K_TLS_LDM_PG21' is requested using 'tldldm'. 17685 * 'R_OR1K_TLS_LDM_LO13' is requested using 'tlsldmpo'. 17686 17687 * 'R_OR1K_TLS_LDO_HI16' is requested using 'dtpoffhi'. 17688 * 'R_OR1K_TLS_LDO_LO16' is requested using 'dtpofflo'. 17689 17690 * 'R_OR1K_TLS_IE_HI16' is requested using 'gottpoffhi'. 17691 * 'R_OR1K_TLS_IE_AHI16' is requested using 'gottpoffha'. 17692 * 'R_OR1K_TLS_IE_LO16' is requested using 'gottpofflo'. 17693 * 'R_OR1K_TLS_IE_PG21' is requested using 'gottp'. 17694 * 'R_OR1K_TLS_IE_LO13' is requested using 'gottppo'. 17695 17696 * 'R_OR1K_TLS_LE_HI16' is requested using 'tpoffhi'. 17697 * 'R_OR1K_TLS_LE_AHI16' is requested using 'tpoffha'. 17698 * 'R_OR1K_TLS_LE_LO16' is requested using 'tpofflo'. 17699 * 'R_OR1K_TLS_LE_SLO16' also is requested using 'tpofflo' depending 17700 on the instruction format. 17701 17702 Here are some example TLS model sequences. 17703 17704 First, General Dynamic: 17705 17706 l.movhi r17, tlsgdhi(symbol) 17707 l.ori r17, r17, tlsgdlo(symbol) 17708 l.add r17, r17, r16 17709 l.or r3, r17, r17 17710 l.jal plt(__tls_get_addr) 17711 l.nop 17712 17713 Initial Exec: 17714 17715 l.movhi r17, gottpoffhi(symbol) 17716 l.add r17, r17, r16 17717 l.lwz r17, gottpofflo(symbol)(r17) 17718 l.add r17, r17, r10 17719 l.lbs r17, 0(r17) 17720 17721 And finally, Local Exec: 17722 17723 l.movhi r17, tpoffha(symbol) 17724 l.add r17, r17, r10 17725 l.addi r17, r17, tpofflo(symbol) 17726 l.lbs r17, 0(r17) 17727 17728 17729File: as.info, Node: OpenRISC-Float, Next: OpenRISC-Directives, Prev: OpenRISC-Syntax, Up: OpenRISC-Dependent 17730 177319.33.2 Floating Point 17732--------------------- 17733 17734OpenRISC uses IEEE floating-point numbers. 17735 17736 17737File: as.info, Node: OpenRISC-Directives, Next: OpenRISC-Opcodes, Prev: OpenRISC-Float, Up: OpenRISC-Dependent 17738 177399.33.3 OpenRISC Machine Directives 17740---------------------------------- 17741 17742The OpenRISC version of 'as' supports the following additional machine 17743directives: 17744 17745'.align' 17746 This must be followed by the desired alignment in bytes. 17747 17748'.word' 17749 On the OpenRISC, the '.word' directive produces a 32 bit value. 17750 17751'.nodelay' 17752 On the OpenRISC, the '.nodelay' directive sets a flag in elf 17753 binaries indicating that the binary is generated catering for no 17754 delay slots. 17755 17756'.proc' 17757 This directive is ignored. Any text following it on the same line 17758 is also ignored. 17759 17760'.endproc' 17761 This directive is ignored. Any text following it on the same line 17762 is also ignored. 17763 17764 17765File: as.info, Node: OpenRISC-Opcodes, Prev: OpenRISC-Directives, Up: OpenRISC-Dependent 17766 177679.33.4 Opcodes 17768-------------- 17769 17770For detailed information on the OpenRISC machine instruction set, see 17771<http://www.openrisc.io/architecture/>. 17772 17773 'as' implements all the standard OpenRISC opcodes. 17774 17775 17776File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: OpenRISC-Dependent, Up: Machine Dependencies 17777 177789.34 PDP-11 Dependent Features 17779============================== 17780 17781* Menu: 17782 17783* PDP-11-Options:: Options 17784* PDP-11-Pseudos:: Assembler Directives 17785* PDP-11-Syntax:: DEC Syntax versus BSD Syntax 17786* PDP-11-Mnemonics:: Instruction Naming 17787* PDP-11-Synthetic:: Synthetic Instructions 17788 17789 17790File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 17791 177929.34.1 Options 17793-------------- 17794 17795The PDP-11 version of 'as' has a rich set of machine dependent options. 17796 177979.34.1.1 Code Generation Options 17798................................ 17799 17800'-mpic | -mno-pic' 17801 Generate position-independent (or position-dependent) code. 17802 17803 The default is to generate position-independent code. 17804 178059.34.1.2 Instruction Set Extension Options 17806.......................................... 17807 17808These options enables or disables the use of extensions over the base 17809line instruction set as introduced by the first PDP-11 CPU: the KA11. 17810Most options come in two variants: a '-m'EXTENSION that enables 17811EXTENSION, and a '-mno-'EXTENSION that disables EXTENSION. 17812 17813 The default is to enable all extensions. 17814 17815'-mall | -mall-extensions' 17816 Enable all instruction set extensions. 17817 17818'-mno-extensions' 17819 Disable all instruction set extensions. 17820 17821'-mcis | -mno-cis' 17822 Enable (or disable) the use of the commercial instruction set, 17823 which consists of these instructions: 'ADDNI', 'ADDN', 'ADDPI', 17824 'ADDP', 'ASHNI', 'ASHN', 'ASHPI', 'ASHP', 'CMPCI', 'CMPC', 'CMPNI', 17825 'CMPN', 'CMPPI', 'CMPP', 'CVTLNI', 'CVTLN', 'CVTLPI', 'CVTLP', 17826 'CVTNLI', 'CVTNL', 'CVTNPI', 'CVTNP', 'CVTPLI', 'CVTPL', 'CVTPNI', 17827 'CVTPN', 'DIVPI', 'DIVP', 'L2DR', 'L3DR', 'LOCCI', 'LOCC', 'MATCI', 17828 'MATC', 'MOVCI', 'MOVC', 'MOVRCI', 'MOVRC', 'MOVTCI', 'MOVTC', 17829 'MULPI', 'MULP', 'SCANCI', 'SCANC', 'SKPCI', 'SKPC', 'SPANCI', 17830 'SPANC', 'SUBNI', 'SUBN', 'SUBPI', and 'SUBP'. 17831 17832'-mcsm | -mno-csm' 17833 Enable (or disable) the use of the 'CSM' instruction. 17834 17835'-meis | -mno-eis' 17836 Enable (or disable) the use of the extended instruction set, which 17837 consists of these instructions: 'ASHC', 'ASH', 'DIV', 'MARK', 17838 'MUL', 'RTT', 'SOB' 'SXT', and 'XOR'. 17839 17840'-mfis | -mkev11' 17841'-mno-fis | -mno-kev11' 17842 Enable (or disable) the use of the KEV11 floating-point 17843 instructions: 'FADD', 'FDIV', 'FMUL', and 'FSUB'. 17844 17845'-mfpp | -mfpu | -mfp-11' 17846'-mno-fpp | -mno-fpu | -mno-fp-11' 17847 Enable (or disable) the use of FP-11 floating-point instructions: 17848 'ABSF', 'ADDF', 'CFCC', 'CLRF', 'CMPF', 'DIVF', 'LDCFF', 'LDCIF', 17849 'LDEXP', 'LDF', 'LDFPS', 'MODF', 'MULF', 'NEGF', 'SETD', 'SETF', 17850 'SETI', 'SETL', 'STCFF', 'STCFI', 'STEXP', 'STF', 'STFPS', 'STST', 17851 'SUBF', and 'TSTF'. 17852 17853'-mlimited-eis | -mno-limited-eis' 17854 Enable (or disable) the use of the limited extended instruction 17855 set: 'MARK', 'RTT', 'SOB', 'SXT', and 'XOR'. 17856 17857 The -mno-limited-eis options also implies -mno-eis. 17858 17859'-mmfpt | -mno-mfpt' 17860 Enable (or disable) the use of the 'MFPT' instruction. 17861 17862'-mmultiproc | -mno-multiproc' 17863 Enable (or disable) the use of multiprocessor instructions: 17864 'TSTSET' and 'WRTLCK'. 17865 17866'-mmxps | -mno-mxps' 17867 Enable (or disable) the use of the 'MFPS' and 'MTPS' instructions. 17868 17869'-mspl | -mno-spl' 17870 Enable (or disable) the use of the 'SPL' instruction. 17871 17872 Enable (or disable) the use of the microcode instructions: 'LDUB', 17873 'MED', and 'XFC'. 17874 178759.34.1.3 CPU Model Options 17876.......................... 17877 17878These options enable the instruction set extensions supported by a 17879particular CPU, and disables all other extensions. 17880 17881'-mka11' 17882 KA11 CPU. Base line instruction set only. 17883 17884'-mkb11' 17885 KB11 CPU. Enable extended instruction set and 'SPL'. 17886 17887'-mkd11a' 17888 KD11-A CPU. Enable limited extended instruction set. 17889 17890'-mkd11b' 17891 KD11-B CPU. Base line instruction set only. 17892 17893'-mkd11d' 17894 KD11-D CPU. Base line instruction set only. 17895 17896'-mkd11e' 17897 KD11-E CPU. Enable extended instruction set, 'MFPS', and 'MTPS'. 17898 17899'-mkd11f | -mkd11h | -mkd11q' 17900 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction 17901 set, 'MFPS', and 'MTPS'. 17902 17903'-mkd11k' 17904 KD11-K CPU. Enable extended instruction set, 'LDUB', 'MED', 'MFPS', 17905 'MFPT', 'MTPS', and 'XFC'. 17906 17907'-mkd11z' 17908 KD11-Z CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT', 17909 'MTPS', and 'SPL'. 17910 17911'-mf11' 17912 F11 CPU. Enable extended instruction set, 'MFPS', 'MFPT', and 17913 'MTPS'. 17914 17915'-mj11' 17916 J11 CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT', 17917 'MTPS', 'SPL', 'TSTSET', and 'WRTLCK'. 17918 17919'-mt11' 17920 T11 CPU. Enable limited extended instruction set, 'MFPS', and 17921 'MTPS'. 17922 179239.34.1.4 Machine Model Options 17924.............................. 17925 17926These options enable the instruction set extensions supported by a 17927particular machine model, and disables all other extensions. 17928 17929'-m11/03' 17930 Same as '-mkd11f'. 17931 17932'-m11/04' 17933 Same as '-mkd11d'. 17934 17935'-m11/05 | -m11/10' 17936 Same as '-mkd11b'. 17937 17938'-m11/15 | -m11/20' 17939 Same as '-mka11'. 17940 17941'-m11/21' 17942 Same as '-mt11'. 17943 17944'-m11/23 | -m11/24' 17945 Same as '-mf11'. 17946 17947'-m11/34' 17948 Same as '-mkd11e'. 17949 17950'-m11/34a' 17951 Ame as '-mkd11e' '-mfpp'. 17952 17953'-m11/35 | -m11/40' 17954 Same as '-mkd11a'. 17955 17956'-m11/44' 17957 Same as '-mkd11z'. 17958 17959'-m11/45 | -m11/50 | -m11/55 | -m11/70' 17960 Same as '-mkb11'. 17961 17962'-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' 17963 Same as '-mj11'. 17964 17965'-m11/60' 17966 Same as '-mkd11k'. 17967 17968 17969File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 17970 179719.34.2 Assembler Directives 17972--------------------------- 17973 17974The PDP-11 version of 'as' has a few machine dependent assembler 17975directives. 17976 17977'.bss' 17978 Switch to the 'bss' section. 17979 17980'.even' 17981 Align the location counter to an even number. 17982 17983 17984File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 17985 179869.34.3 PDP-11 Assembly Language Syntax 17987-------------------------------------- 17988 17989'as' supports both DEC syntax and BSD syntax. The only difference is 17990that in DEC syntax, a '#' character is used to denote an immediate 17991constants, while in BSD syntax the character for this purpose is '$'. 17992 17993 general-purpose registers are named 'r0' through 'r7'. Mnemonic 17994alternatives for 'r6' and 'r7' are 'sp' and 'pc', respectively. 17995 17996 Floating-point registers are named 'ac0' through 'ac3', or 17997alternatively 'fr0' through 'fr3'. 17998 17999 Comments are started with a '#' or a '/' character, and extend to the 18000end of the line. (FIXME: clash with immediates?) 18001 18002 Multiple statements on the same line can be separated by the ';' 18003character. 18004 18005 18006File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 18007 180089.34.4 Instruction Naming 18009------------------------- 18010 18011Some instructions have alternative names. 18012 18013'BCC' 18014 'BHIS' 18015 18016'BCS' 18017 'BLO' 18018 18019'L2DR' 18020 'L2D' 18021 18022'L3DR' 18023 'L3D' 18024 18025'SYS' 18026 'TRAP' 18027 18028 18029File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 18030 180319.34.5 Synthetic Instructions 18032----------------------------- 18033 18034The 'JBR' and 'J'CC synthetic instructions are not supported yet. 18035 18036 18037File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 18038 180399.35 picoJava Dependent Features 18040================================ 18041 18042* Menu: 18043 18044* PJ Options:: Options 18045* PJ Syntax:: PJ Syntax 18046 18047 18048File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent 18049 180509.35.1 Options 18051-------------- 18052 18053'as' has two additional command-line options for the picoJava 18054architecture. 18055'-ml' 18056 This option selects little endian data output. 18057 18058'-mb' 18059 This option selects big endian data output. 18060 18061 18062File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent 18063 180649.35.2 PJ Syntax 18065---------------- 18066 18067* Menu: 18068 18069* PJ-Chars:: Special Characters 18070 18071 18072File: as.info, Node: PJ-Chars, Up: PJ Syntax 18073 180749.35.2.1 Special Characters 18075........................... 18076 18077The presence of a '!' or '/' on a line indicates the start of a comment 18078that extends to the end of the current line. 18079 18080 If a '#' appears as the first character of a line then the whole line 18081is treated as a comment, but in this case the line could also be a 18082logical line number directive (*note Comments::) or a preprocessor 18083control command (*note Preprocessing::). 18084 18085 The ';' character can be used to separate statements on the same 18086line. 18087 18088 18089File: as.info, Node: PPC-Dependent, Next: PRU-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 18090 180919.36 PowerPC Dependent Features 18092=============================== 18093 18094* Menu: 18095 18096* PowerPC-Opts:: Options 18097* PowerPC-Pseudo:: PowerPC Assembler Directives 18098* PowerPC-Syntax:: PowerPC Syntax 18099 18100 18101File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 18102 181039.36.1 Options 18104-------------- 18105 18106The PowerPC chip family includes several successive levels, using the 18107same core instruction set, but including a few additional instructions 18108at each level. There are exceptions to this however. For details on 18109what instructions each variant supports, please see the chip's 18110architecture reference manual. 18111 18112 The following table lists all available PowerPC options. 18113 18114'-a32' 18115 Generate ELF32 or XCOFF32. 18116 18117'-a64' 18118 Generate ELF64 or XCOFF64. 18119 18120'-K PIC' 18121 Set EF_PPC_RELOCATABLE_LIB in ELF flags. 18122 18123'-mpwrx | -mpwr2' 18124 Generate code for POWER/2 (RIOS2). 18125 18126'-mpwr' 18127 Generate code for POWER (RIOS1) 18128 18129'-m601' 18130 Generate code for PowerPC 601. 18131 18132'-mppc, -mppc32, -m603, -m604' 18133 Generate code for PowerPC 603/604. 18134 18135'-m403, -m405' 18136 Generate code for PowerPC 403/405. 18137 18138'-m440' 18139 Generate code for PowerPC 440. BookE and some 405 instructions. 18140 18141'-m464' 18142 Generate code for PowerPC 464. 18143 18144'-m476' 18145 Generate code for PowerPC 476. 18146 18147'-m7400, -m7410, -m7450, -m7455' 18148 Generate code for PowerPC 7400/7410/7450/7455. 18149 18150'-m750cl, -mgekko, -mbroadway' 18151 Generate code for PowerPC 750CL/Gekko/Broadway. 18152 18153'-m821, -m850, -m860' 18154 Generate code for PowerPC 821/850/860. 18155 18156'-mppc64, -m620' 18157 Generate code for PowerPC 620/625/630. 18158 18159'-me500, -me500x2' 18160 Generate code for Motorola e500 core complex. 18161 18162'-me500mc' 18163 Generate code for Freescale e500mc core complex. 18164 18165'-me500mc64' 18166 Generate code for Freescale e500mc64 core complex. 18167 18168'-me5500' 18169 Generate code for Freescale e5500 core complex. 18170 18171'-me6500' 18172 Generate code for Freescale e6500 core complex. 18173 18174'-mspe' 18175 Generate code for Motorola SPE instructions. 18176 18177'-mspe2' 18178 Generate code for Freescale SPE2 instructions. 18179 18180'-mtitan' 18181 Generate code for AppliedMicro Titan core complex. 18182 18183'-mppc64bridge' 18184 Generate code for PowerPC 64, including bridge insns. 18185 18186'-mbooke' 18187 Generate code for 32-bit BookE. 18188 18189'-ma2' 18190 Generate code for A2 architecture. 18191 18192'-me300' 18193 Generate code for PowerPC e300 family. 18194 18195'-maltivec' 18196 Generate code for processors with AltiVec instructions. 18197 18198'-mvle' 18199 Generate code for Freescale PowerPC VLE instructions. 18200 18201'-mvsx' 18202 Generate code for processors with Vector-Scalar (VSX) instructions. 18203 18204'-mhtm' 18205 Generate code for processors with Hardware Transactional Memory 18206 instructions. 18207 18208'-mpower4, -mpwr4' 18209 Generate code for Power4 architecture. 18210 18211'-mpower5, -mpwr5, -mpwr5x' 18212 Generate code for Power5 architecture. 18213 18214'-mpower6, -mpwr6' 18215 Generate code for Power6 architecture. 18216 18217'-mpower7, -mpwr7' 18218 Generate code for Power7 architecture. 18219 18220'-mpower8, -mpwr8' 18221 Generate code for Power8 architecture. 18222 18223'-mpower9, -mpwr9' 18224 Generate code for Power9 architecture. 18225 18226'-mpower10, -mpwr10' 18227 Generate code for Power10 architecture. 18228 18229'-mcell' 18230'-mcell' 18231 Generate code for Cell Broadband Engine architecture. 18232 18233'-mcom' 18234 Generate code Power/PowerPC common instructions. 18235 18236'-many' 18237 Generate code for any architecture (PWR/PWRX/PPC). 18238 18239'-mregnames' 18240 Allow symbolic names for registers. 18241 18242'-mno-regnames' 18243 Do not allow symbolic names for registers. 18244 18245'-mrelocatable' 18246 Support for GCC's -mrelocatable option. 18247 18248'-mrelocatable-lib' 18249 Support for GCC's -mrelocatable-lib option. 18250 18251'-memb' 18252 Set PPC_EMB bit in ELF flags. 18253 18254'-mlittle, -mlittle-endian, -le' 18255 Generate code for a little endian machine. 18256 18257'-mbig, -mbig-endian, -be' 18258 Generate code for a big endian machine. 18259 18260'-msolaris' 18261 Generate code for Solaris. 18262 18263'-mno-solaris' 18264 Do not generate code for Solaris. 18265 18266'-nops=COUNT' 18267 If an alignment directive inserts more than COUNT nops, put a 18268 branch at the beginning to skip execution of the nops. 18269 18270 18271File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent 18272 182739.36.2 PowerPC Assembler Directives 18274----------------------------------- 18275 18276A number of assembler directives are available for PowerPC. The 18277following table is far from complete. 18278 18279'.machine "string"' 18280 This directive allows you to change the machine for which code is 18281 generated. '"string"' may be any of the -m cpu selection options 18282 (without the -m) enclosed in double quotes, '"push"', or '"pop"'. 18283 '.machine "push"' saves the currently selected cpu, which may be 18284 restored with '.machine "pop"'. 18285 18286 18287File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent 18288 182899.36.3 PowerPC Syntax 18290--------------------- 18291 18292* Menu: 18293 18294* PowerPC-Chars:: Special Characters 18295 18296 18297File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax 18298 182999.36.3.1 Special Characters 18300........................... 18301 18302The presence of a '#' on a line indicates the start of a comment that 18303extends to the end of the current line. 18304 18305 If a '#' appears as the first character of a line then the whole line 18306is treated as a comment, but in this case the line could also be a 18307logical line number directive (*note Comments::) or a preprocessor 18308control command (*note Preprocessing::). 18309 18310 If the assembler has been configured for the ppc-*-solaris* target 18311then the '!' character also acts as a line comment character. This can 18312be disabled via the '-mno-solaris' command-line option. 18313 18314 The ';' character can be used to separate statements on the same 18315line. 18316 18317 18318File: as.info, Node: PRU-Dependent, Next: RISC-V-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 18319 183209.37 PRU Dependent Features 18321=========================== 18322 18323* Menu: 18324 18325* PRU Options:: Options 18326* PRU Syntax:: Syntax 18327* PRU Relocations:: Relocations 18328* PRU Directives:: PRU Machine Directives 18329* PRU Opcodes:: Opcodes 18330 18331 18332File: as.info, Node: PRU Options, Next: PRU Syntax, Up: PRU-Dependent 18333 183349.37.1 Options 18335-------------- 18336 18337'-mlink-relax' 18338 Assume that LD would optimize LDI32 instructions by checking the 18339 upper 16 bits of the EXPRESSION. If they are all zeros, then LD 18340 would shorten the LDI32 instruction to a single LDI. In such case 18341 'as' will output DIFF relocations for diff expressions. 18342 18343'-mno-link-relax' 18344 Assume that LD would not optimize LDI32 instructions. As a 18345 consequence, DIFF relocations will not be emitted. 18346 18347'-mno-warn-regname-label' 18348 Do not warn if a label name matches a register name. Usually 18349 assembler programmers will want this warning to be emitted. C 18350 compilers may want to turn this off. 18351 18352 18353File: as.info, Node: PRU Syntax, Next: PRU Relocations, Prev: PRU Options, Up: PRU-Dependent 18354 183559.37.2 Syntax 18356------------- 18357 18358* Menu: 18359 18360* PRU Chars:: Special Characters 18361 18362 18363File: as.info, Node: PRU Chars, Up: PRU Syntax 18364 183659.37.2.1 Special Characters 18366........................... 18367 18368'#' and ';' are the line comment characters. 18369 18370 18371File: as.info, Node: PRU Relocations, Next: PRU Directives, Prev: PRU Syntax, Up: PRU-Dependent 18372 183739.37.3 PRU Machine Relocations 18374------------------------------ 18375 18376'%pmem(EXPRESSION)' 18377 Convert EXPRESSION from byte-address to a word-address. In other 18378 words, shift right by two. 18379 18380'%label(EXPRESSION)' 18381 Mark the given operand as a label. This is useful if you need to 18382 jump to a label that matches a register name. 18383 18384 r1: 18385 jmp r1 ; Will jump to register R1 18386 jmp %label(r1) ; Will jump to label r1 18387 18388 18389File: as.info, Node: PRU Directives, Next: PRU Opcodes, Prev: PRU Relocations, Up: PRU-Dependent 18390 183919.37.4 PRU Machine Directives 18392----------------------------- 18393 18394'.align EXPRESSION [, EXPRESSION]' 18395 This is the generic '.align' directive, however this aligns to a 18396 power of two. 18397 18398'.word EXPRESSION' 18399 Create an aligned constant 4 bytes in size. 18400 18401'.dword EXPRESSION' 18402 Create an aligned constant 8 bytes in size. 18403 18404'.2byte EXPRESSION' 18405 Create an unaligned constant 2 bytes in size. 18406 18407'.4byte EXPRESSION' 18408 Create an unaligned constant 4 bytes in size. 18409 18410'.8byte EXPRESSION' 18411 Create an unaligned constant 8 bytes in size. 18412 18413'.16byte EXPRESSION' 18414 Create an unaligned constant 16 bytes in size. 18415 18416'.set no_warn_regname_label' 18417 Do not output warnings when a label name matches a register name. 18418 Equivalent to passing the '-mno-warn-regname-label' command-line 18419 option. 18420 18421 18422File: as.info, Node: PRU Opcodes, Prev: PRU Directives, Up: PRU-Dependent 18423 184249.37.5 Opcodes 18425-------------- 18426 18427'as' implements all the standard PRU core V3 opcodes in the original 18428pasm assembler. Older cores are not supported by 'as'. 18429 18430 GAS also implements the LDI32 pseudo instruction for loading a 32-bit 18431immediate value into a register. 18432 18433 ldi32 sp, __stack_top 18434 ldi32 r14, 0x12345678 18435 18436 18437File: as.info, Node: RISC-V-Dependent, Next: RL78-Dependent, Prev: PRU-Dependent, Up: Machine Dependencies 18438 184399.38 RISC-V Dependent Features 18440============================== 18441 18442* Menu: 18443 18444* RISC-V-Options:: RISC-V Options 18445* RISC-V-Directives:: RISC-V Directives 18446* RISC-V-Modifiers:: RISC-V Assembler Modifiers 18447* RISC-V-Formats:: RISC-V Instruction Formats 18448* RISC-V-ATTRIBUTE:: RISC-V Object Attribute 18449 18450 18451File: as.info, Node: RISC-V-Options, Next: RISC-V-Directives, Up: RISC-V-Dependent 18452 184539.38.1 RISC-V Options 18454--------------------- 18455 18456The following table lists all available RISC-V specific options. 18457 18458'-fpic' 18459'-fPIC' 18460 Generate position-independent code 18461 18462'-fno-pic' 18463 Don't generate position-independent code (default) 18464 18465'-march=ISA' 18466 Select the base isa, as specified by ISA. For example 18467 -march=rv32ima. If this option and the architecture attributes 18468 aren't set, then assembler will check the default configure setting 18469 -with-arch=ISA. 18470 18471'-misa-spec=ISAspec' 18472 Select the default isa spec version. If the version of ISA isn't 18473 set by -march, then assembler helps to set the version according to 18474 the default chosen spec. If this option isn't set, then assembler 18475 will check the default configure setting -with-isa-spec=ISAspec. 18476 18477'-mpriv-spec=PRIVspec' 18478 Select the privileged spec version. We can decide whether the CSR 18479 is valid or not according to the chosen spec. If this option and 18480 the privilege attributes aren't set, then assembler will check the 18481 default configure setting -with-priv-spec=PRIVspec. 18482 18483'-mabi=ABI' 18484 Selects the ABI, which is either "ilp32" or "lp64", optionally 18485 followed by "f", "d", or "q" to indicate single-precision, 18486 double-precision, or quad-precision floating-point calling 18487 convention, or none to indicate the soft-float calling convention. 18488 Also, "ilp32" can optionally be followed by "e" to indicate the RVE 18489 ABI, which is always soft-float. 18490 18491'-mrelax' 18492 Take advantage of linker relaxations to reduce the number of 18493 instructions required to materialize symbol addresses. (default) 18494 18495'-mno-relax' 18496 Don't do linker relaxations. 18497 18498'-march-attr' 18499 Generate the default contents for the riscv elf attribute section 18500 if the .attribute directives are not set. This section is used to 18501 record the information that a linker or runtime loader needs to 18502 check compatibility. This information includes ISA string, stack 18503 alignment requirement, unaligned memory accesses, and the major, 18504 minor and revision version of privileged specification. 18505 18506'-mno-arch-attr' 18507 Don't generate the default riscv elf attribute section if the 18508 .attribute directives are not set. 18509 18510'-mcsr-check' 18511 Enable the CSR checking for the ISA-dependent CRS and the read-only 18512 CSR. The ISA-dependent CSR are only valid when the specific ISA is 18513 set. The read-only CSR can not be written by the CSR instructions. 18514 18515'-mno-csr-check' 18516 Don't do CSR checking. 18517 18518'-mlittle-endian' 18519 Generate code for a little endian machine. 18520 18521'-mbig-endian' 18522 Generate code for a big endian machine. 18523 18524 18525File: as.info, Node: RISC-V-Directives, Next: RISC-V-Modifiers, Prev: RISC-V-Options, Up: RISC-V-Dependent 18526 185279.38.2 RISC-V Directives 18528------------------------ 18529 18530The following table lists all available RISC-V specific directives. 18531 18532'.align SIZE-LOG-2' 18533 Align to the given boundary, with the size given as log2 the number 18534 of bytes to align to. 18535 18536'.half VALUE' 18537'.word VALUE' 18538'.dword VALUE' 18539 Emits a half-word, word, or double-word value at the current 18540 position. 18541 18542'.dtprelword VALUE' 18543'.dtpreldword VALUE' 18544 Emits a DTP-relative word (or double-word) at the current position. 18545 This is meant to be used by the compiler in shared libraries for 18546 DWARF debug info for thread local variables. 18547 18548'.bss' 18549 Sets the current section to the BSS section. 18550 18551'.uleb128 VALUE' 18552'.sleb128 VALUE' 18553 Emits a signed or unsigned LEB128 value at the current position. 18554 This only accepts constant expressions, because symbol addresses 18555 can change with relaxation, and we don't support relocations to 18556 modify LEB128 values at link time. 18557 18558'.option ARGUMENT' 18559 Modifies RISC-V specific assembler options inline with the assembly 18560 code. This is used when particular instruction sequences must be 18561 assembled with a specific set of options. For example, since we 18562 relax addressing sequences to shorter GP-relative sequences when 18563 possible the initial load of GP must not be relaxed and should be 18564 emitted as something like 18565 18566 .option push 18567 .option norelax 18568 la gp, __global_pointer$ 18569 .option pop 18570 18571 in order to produce after linker relaxation the expected 18572 18573 auipc gp, %pcrel_hi(__global_pointer$) 18574 addi gp, gp, %pcrel_lo(__global_pointer$) 18575 18576 instead of just 18577 18578 addi gp, gp, 0 18579 18580 It's not expected that options are changed in this manner during 18581 regular use, but there are a handful of esoteric cases like the one 18582 above where users need to disable particular features of the 18583 assembler for particular code sequences. The complete list of 18584 option arguments is shown below: 18585 18586 'push' 18587 'pop' 18588 Pushes or pops the current option stack. These should be used 18589 whenever changing an option in line with assembly code in 18590 order to ensure the user's command-line options are respected 18591 for the bulk of the file being assembled. 18592 18593 'rvc' 18594 'norvc' 18595 Enables or disables the generation of compressed instructions. 18596 Instructions are opportunistically compressed by the RISC-V 18597 assembler when possible, but sometimes this behavior is not 18598 desirable. 18599 18600 'pic' 18601 'nopic' 18602 Enables or disables position-independent code generation. 18603 Unless you really know what you're doing, this should only be 18604 at the top of a file. 18605 18606 'relax' 18607 'norelax' 18608 Enables or disables relaxation. The RISC-V assembler and 18609 linker opportunistically relax some code sequences, but 18610 sometimes this behavior is not desirable. 18611 18612'csr-check' 18613'no-csr-check' 18614 Enables or disables the CSR checking. 18615 18616'.insn VALUE' 18617'.insn VALUE' 18618 This directive permits the numeric representation of an 18619 instructions and makes the assembler insert the operands according 18620 to one of the instruction formats for '.insn' (*note 18621 RISC-V-Formats::). For example, the instruction 'add a0, a1, a2' 18622 could be written as '.insn r 0x33, 0, 0, a0, a1, a2'. 18623 18624'.attribute TAG, VALUE' 18625 Set the object attribute TAG to VALUE. 18626 18627 The TAG is either an attribute number, or one of the following: 18628 'Tag_RISCV_arch', 'Tag_RISCV_stack_align', 18629 'Tag_RISCV_unaligned_access', 'Tag_RISCV_priv_spec', 18630 'Tag_RISCV_priv_spec_minor', 'Tag_RISCV_priv_spec_revision'. 18631 18632 18633File: as.info, Node: RISC-V-Modifiers, Next: RISC-V-Formats, Prev: RISC-V-Directives, Up: RISC-V-Dependent 18634 186359.38.3 RISC-V Assembler Modifiers 18636--------------------------------- 18637 18638The RISC-V assembler supports following modifiers for relocatable 18639addresses used in RISC-V instruction operands. However, we also support 18640some pseudo instructions that are easier to use than these modifiers. 18641 18642'%lo(SYMBOL)' 18643 The low 12 bits of absolute address for SYMBOL. 18644 18645'%hi(SYMBOL)' 18646 The high 20 bits of absolute address for SYMBOL. This is usually 18647 used with the %lo modifier to represent a 32-bit absolute address. 18648 18649 lui a0, %hi(SYMBOL) // R_RISCV_HI20 18650 addi a0, a0, %lo(SYMBOL) // R_RISCV_LO12_I 18651 18652 lui a0, %hi(SYMBOL) // R_RISCV_HI20 18653 load/store a0, %lo(SYMBOL)(a0) // R_RISCV_LO12_I/S 18654 18655'%pcrel_lo(LABEL)' 18656 The low 12 bits of relative address between pc and SYMBOL. The 18657 SYMBOL is related to the high part instruction which is marked by 18658 LABEL. 18659 18660'%pcrel_hi(SYMBOL)' 18661 The high 20 bits of relative address between pc and SYMBOL. This 18662 is usually used with the %pcrel_lo modifier to represent a +/-2GB 18663 pc-relative range. 18664 18665 LABEL: 18666 auipc a0, %pcrel_hi(SYMBOL) // R_RISCV_PCREL_HI20 18667 addi a0, a0, %pcrel_lo(LABEL) // R_RISCV_PCREL_LO12_I 18668 18669 LABEL: 18670 auipc a0, %pcrel_hi(SYMBOL) // R_RISCV_PCREL_HI20 18671 load/store a0, %pcrel_lo(LABEL)(a0) // R_RISCV_PCREL_LO12_I/S 18672 18673 Or you can use the pseudo lla/lw/sw/... instruction to do this. 18674 18675 lla a0, SYMBOL 18676 18677'%got_pcrel_hi(SYMBOL)' 18678 The high 20 bits of relative address between pc and the GOT entry 18679 of SYMBOL. This is usually used with the %pcrel_lo modifier to 18680 access the GOT entry. 18681 18682 LABEL: 18683 auipc a0, %got_pcrel_hi(SYMBOL) // R_RISCV_GOT_HI20 18684 addi a0, a0, %pcrel_lo(LABEL) // R_RISCV_PCREL_LO12_I 18685 18686 LABEL: 18687 auipc a0, %got_pcrel_hi(SYMBOL) // R_RISCV_GOT_HI20 18688 load/store a0, %pcrel_lo(LABEL)(a0) // R_RISCV_PCREL_LO12_I/S 18689 18690 Also, the pseudo la instruction with PIC has similar behavior. 18691 18692'%tprel_add(SYMBOL)' 18693 This is used purely to associate the R_RISCV_TPREL_ADD relocation 18694 for TLS relaxation. This one is only valid as the fourth operand 18695 to the normally 3 operand add instruction. 18696 18697'%tprel_lo(SYMBOL)' 18698 The low 12 bits of relative address between tp and SYMBOL. 18699 18700'%tprel_hi(SYMBOL)' 18701 The high 20 bits of relative address between tp and SYMBOL. This 18702 is usually used with the %tprel_lo and %tprel_add modifiers to 18703 access the thread local variable SYMBOL in TLS Local Exec. 18704 18705 lui a5, %tprel_hi(SYMBOL) // R_RISCV_TPREL_HI20 18706 add a5, a5, tp, %tprel_add(SYMBOL) // R_RISCV_TPREL_ADD 18707 load/store t0, %tprel_lo(SYMBOL)(a5) // R_RISCV_TPREL_LO12_I/S 18708 18709'%tls_ie_pcrel_hi(SYMBOL)' 18710 The high 20 bits of relative address between pc and GOT entry. It 18711 is usually used with the %pcrel_lo modifier to access the thread 18712 local variable SYMBOL in TLS Initial Exec. 18713 18714 la.tls.ie a5, SYMBOL 18715 add a5, a5, tp 18716 load/store t0, 0(a5) 18717 18718 The pseudo la.tls.ie instruction can be expended to 18719 18720 LABEL: 18721 auipc a5, %tls_ie_pcrel_hi(SYMBOL) // R_RISCV_TLS_GOT_HI20 18722 load a5, %pcrel_lo(LABEL)(a5) // R_RISCV_PCREL_LO12_I 18723 18724'%tls_gd_pcrel_hi(SYMBOL)' 18725 The high 20 bits of relative address between pc and GOT entry. It 18726 is usually used with the %pcrel_lo modifier to access the thread 18727 local variable SYMBOL in TLS Global Dynamic. 18728 18729 la.tls.gd a0, SYMBOL 18730 call __tls_get_addr@plt 18731 mv a5, a0 18732 load/store t0, 0(a5) 18733 18734 The pseudo la.tls.gd instruction can be expended to 18735 18736 LABEL: 18737 auipc a0, %tls_gd_pcrel_hi(SYMBOL) // R_RISCV_TLS_GD_HI20 18738 addi a0, a0, %pcrel_lo(LABEL) // R_RISCV_PCREL_LO12_I 18739 18740 18741File: as.info, Node: RISC-V-Formats, Next: RISC-V-ATTRIBUTE, Prev: RISC-V-Modifiers, Up: RISC-V-Dependent 18742 187439.38.4 RISC-V Instruction Formats 18744--------------------------------- 18745 18746The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15 18747instruction formats where some of the formats have multiple variants. 18748For the '.insn' pseudo directive the assembler recognizes some of the 18749formats. Typically, the most general variant of the instruction format 18750is used by the '.insn' directive. 18751 18752 The following table lists the abbreviations used in the table of 18753instruction formats: 18754 18755 opcode Unsigned immediate or opcode name for 7-bits opcode. 18756 opcode2 Unsigned immediate or opcode name for 2-bits opcode. 18757 func7 Unsigned immediate for 7-bits function code. 18758 func6 Unsigned immediate for 6-bits function code. 18759 func4 Unsigned immediate for 4-bits function code. 18760 func3 Unsigned immediate for 3-bits function code. 18761 func2 Unsigned immediate for 2-bits function code. 18762 rd Destination register number for operand x, can be GPR or FPR. 18763 rd' Destination register number for operand x, 18764 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 18765 rs1 First source register number for operand x, can be GPR or FPR. 18766 rs1' First source register number for operand x, 18767 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 18768 rs2 Second source register number for operand x, can be GPR or FPR. 18769 rs2' Second source register number for operand x, 18770 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 18771 simm12 Sign-extended 12-bit immediate for operand x. 18772 simm20 Sign-extended 20-bit immediate for operand x. 18773 simm6 Sign-extended 6-bit immediate for operand x. 18774 uimm5 Unsigned 5-bit immediate for operand x. 18775 uimm6 Unsigned 6-bit immediate for operand x. 18776 uimm8 Unsigned 8-bit immediate for operand x. 18777 symbol Symbol or lable reference for operand x. 18778 18779 The following table lists all available opcode name: 18780 18781'C0' 18782'C1' 18783'C2' 18784 Opcode space for compressed instructions. 18785 18786'LOAD' 18787 Opcode space for load instructions. 18788 18789'LOAD_FP' 18790 Opcode space for floating-point load instructions. 18791 18792'STORE' 18793 Opcode space for store instructions. 18794 18795'STORE_FP' 18796 Opcode space for floating-point store instructions. 18797 18798'AUIPC' 18799 Opcode space for auipc instruction. 18800 18801'LUI' 18802 Opcode space for lui instruction. 18803 18804'BRANCH' 18805 Opcode space for branch instructions. 18806 18807'JAL' 18808 Opcode space for jal instruction. 18809 18810'JALR' 18811 Opcode space for jalr instruction. 18812 18813'OP' 18814 Opcode space for ALU instructions. 18815 18816'OP_32' 18817 Opcode space for 32-bits ALU instructions. 18818 18819'OP_IMM' 18820 Opcode space for ALU with immediate instructions. 18821 18822'OP_IMM_32' 18823 Opcode space for 32-bits ALU with immediate instructions. 18824 18825'OP_FP' 18826 Opcode space for floating-point operation instructions. 18827 18828'MADD' 18829 Opcode space for madd instruction. 18830 18831'MSUB' 18832 Opcode space for msub instruction. 18833 18834'NMADD' 18835 Opcode space for nmadd instruction. 18836 18837'NMSUB' 18838 Opcode space for msub instruction. 18839 18840'AMO' 18841 Opcode space for atomic memory operation instructions. 18842 18843'MISC_MEM' 18844 Opcode space for misc instructions. 18845 18846'SYSTEM' 18847 Opcode space for system instructions. 18848 18849'CUSTOM_0' 18850'CUSTOM_1' 18851'CUSTOM_2' 18852'CUSTOM_3' 18853 Opcode space for customize instructions. 18854 18855 An instruction is two or four bytes in length and must be aligned on 18856a 2 byte boundary. The first two bits of the instruction specify the 18857length of the instruction, 00, 01 and 10 indicates a two byte 18858instruction, 11 indicates a four byte instruction. 18859 18860 The following table lists the RISC-V instruction formats that are 18861available with the '.insn' pseudo directive: 18862 18863'R type: .insn r opcode6, func3, func7, rd, rs1, rs2' 18864 +-------+-----+-----+-------+----+---------+ 18865 | func7 | rs2 | rs1 | func3 | rd | opcode6 | 18866 +-------+-----+-----+-------+----+---------+ 18867 31 25 20 15 12 7 0 18868 18869'R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3' 18870'R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3' 18871 +-----+-------+-----+-----+-------+----+---------+ 18872 | rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 | 18873 +-----+-------+-----+-----+-------+----+---------+ 18874 31 27 25 20 15 12 7 0 18875 18876'I type: .insn i opcode6, func3, rd, rs1, simm12' 18877'I type: .insn i opcode6, func3, rd, simm12(rs1)' 18878 +--------------+-----+-------+----+---------+ 18879 | simm12[11:0] | rs1 | func3 | rd | opcode6 | 18880 +--------------+-----+-------+----+---------+ 18881 31 20 15 12 7 0 18882 18883'S type: .insn s opcode6, func3, rs2, simm12(rs1)' 18884 +--------------+-----+-----+-------+-------------+---------+ 18885 | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 | 18886 +--------------+-----+-----+-------+-------------+---------+ 18887 31 25 20 15 12 7 0 18888 18889'B type: .insn s opcode6, func3, rs1, rs2, symbol' 18890'SB type: .insn sb opcode6, func3, rs1, rs2, symbol' 18891 +-----------------+-----+-----+-------+----------------+---------+ 18892 | simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 | 18893 +-----------------+-----+-----+-------+----------------+---------+ 18894 31 25 20 15 12 7 0 18895 18896'U type: .insn u opcode6, rd, simm20' 18897 +--------------------------+----+---------+ 18898 | simm20[20|10:1|11|19:12] | rd | opcode6 | 18899 +--------------------------+----+---------+ 18900 31 12 7 0 18901 18902'J type: .insn j opcode6, rd, symbol' 18903'UJ type: .insn uj opcode6, rd, symbol' 18904 +------------+--------------+------------+---------------+----+---------+ 18905 | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 | 18906 +------------+--------------+------------+---------------+----+---------+ 18907 31 30 21 20 12 7 0 18908 18909'CR type: .insn cr opcode2, func4, rd, rs2' 18910 +-------+--------+-----+---------+ 18911 | func4 | rd/rs1 | rs2 | opcode2 | 18912 +-------+--------+-----+---------+ 18913 15 12 7 2 0 18914 18915'CI type: .insn ci opcode2, func3, rd, simm6' 18916 +-------+----------+--------+------------+---------+ 18917 | func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 | 18918 +-------+----------+--------+------------+---------+ 18919 15 13 12 7 2 0 18920 18921'CIW type: .insn ciw opcode2, func3, rd', uimm8' 18922 +-------+------------+-----+---------+ 18923 | func3 | uimm8[7:0] | rd' | opcode2 | 18924 +-------+-------- ---+-----+---------+ 18925 15 13 5 2 0 18926 18927'CSS type: .insn css opcode2, func3, rd, uimm6' 18928 +-------+------------+----+---------+ 18929 | func3 | uimm6[5:0] | rd | opcode2 | 18930 +-------+------------+----+---------+ 18931 15 13 7 2 0 18932 18933'CL type: .insn cl opcode2, func3, rd', uimm5(rs1')' 18934 +-------+------------+------+------------+------+---------+ 18935 | func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 | 18936 +-------+------------+------+------------+------+---------+ 18937 15 13 10 7 5 2 0 18938 18939'CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')' 18940 +-------+------------+------+------------+------+---------+ 18941 | func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 | 18942 +-------+------------+------+------------+------+---------+ 18943 15 13 10 7 5 2 0 18944 18945'CA type: .insn ca opcode2, func6, func2, rd', rs2'' 18946 +-- ----+----------+-------+------+---------+ 18947 | func6 | rd'/rs1' | func2 | rs2' | opcode2 | 18948 +-------+----------+-------+------+---------+ 18949 15 10 7 5 2 0 18950 18951'CB type: .insn cb opcode2, func3, rs1', symbol' 18952 +-------+--------------+------+------------------+---------+ 18953 | func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 | 18954 +-------+--------------+------+------------------+---------+ 18955 15 13 10 7 2 0 18956 18957'CJ type: .insn cj opcode2, symbol' 18958 +-------+-------------------------------+---------+ 18959 | func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 | 18960 +-------+-------------------------------+---------+ 18961 15 13 2 0 18962 18963 For the complete list of all instruction format variants see The 18964RISC-V Instruction Set Manual Volume I: User-Level ISA. 18965 18966 18967File: as.info, Node: RISC-V-ATTRIBUTE, Prev: RISC-V-Formats, Up: RISC-V-Dependent 18968 189699.38.5 RISC-V Object Attribute 18970------------------------------ 18971 18972RISC-V attributes have a string value if the tag number is odd and an 18973integer value if the tag number is even. 18974 18975Tag_RISCV_stack_align (4) 18976 Tag_RISCV_strict_align records the N-byte stack alignment for this 18977 object. The default value is 16 for RV32I or RV64I, and 4 for 18978 RV32E. 18979 18980 The smallest value will be used if object files with different 18981 Tag_RISCV_stack_align values are merged. 18982 18983Tag_RISCV_arch (5) 18984 Tag_RISCV_arch contains a string for the target architecture taken 18985 from the option '-march'. Different architectures will be 18986 integrated into a superset when object files are merged. 18987 18988 Note that the version information of the target architecture must 18989 be presented explicitly in the attribute and abbreviations must be 18990 expanded. The version information, if not given by '-march', must 18991 be in accordance with the default specified by the tool. For 18992 example, the architecture 'RV32I' has to be recorded in the 18993 attribute as 'RV32I2P0' in which '2P0' stands for the default 18994 version of its base ISA. On the other hand, the architecture 18995 'RV32G' has to be presented as 'RV32I2P0_M2P0_A2P0_F2P0_D2P0' in 18996 which the abbreviation 'G' is expanded to the 'IMAFD' combination 18997 with default versions of the standard extensions. 18998 18999Tag_RISCV_unaligned_access (6) 19000 Tag_RISCV_unaligned_access is 0 for files that do not allow any 19001 unaligned memory accesses, and 1 for files that do allow unaligned 19002 memory accesses. 19003 19004Tag_RISCV_priv_spec (8) 19005Tag_RISCV_priv_spec_minor (10) 19006Tag_RISCV_priv_spec_revision (12) 19007 Tag_RISCV_priv_spec contains the major/minor/revision version 19008 information of the privileged specification. It will report errors 19009 if object files of different privileged specification versions are 19010 merged. 19011 19012 19013File: as.info, Node: RL78-Dependent, Next: RX-Dependent, Prev: RISC-V-Dependent, Up: Machine Dependencies 19014 190159.39 RL78 Dependent Features 19016============================ 19017 19018* Menu: 19019 19020* RL78-Opts:: RL78 Assembler Command-line Options 19021* RL78-Modifiers:: Symbolic Operand Modifiers 19022* RL78-Directives:: Assembler Directives 19023* RL78-Syntax:: Syntax 19024 19025 19026File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent 19027 190289.39.1 RL78 Options 19029------------------- 19030 19031'relax' 19032 Enable support for link-time relaxation. 19033 19034'norelax' 19035 Disable support for link-time relaxation (default). 19036 19037'mg10' 19038 Mark the generated binary as targeting the G10 variant of the RL78 19039 architecture. 19040 19041'mg13' 19042 Mark the generated binary as targeting the G13 variant of the RL78 19043 architecture. 19044 19045'mg14' 19046'mrl78' 19047 Mark the generated binary as targeting the G14 variant of the RL78 19048 architecture. This is the default. 19049 19050'm32bit-doubles' 19051 Mark the generated binary as one that uses 32-bits to hold the 19052 'double' floating point type. This is the default. 19053 19054'm64bit-doubles' 19055 Mark the generated binary as one that uses 64-bits to hold the 19056 'double' floating point type. 19057 19058 19059File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent 19060 190619.39.2 Symbolic Operand Modifiers 19062--------------------------------- 19063 19064The RL78 has three modifiers that adjust the relocations used by the 19065linker: 19066 19067'%lo16()' 19068 19069 When loading a 20-bit (or wider) address into registers, this 19070 modifier selects the 16 least significant bits. 19071 19072 movw ax,#%lo16(_sym) 19073 19074'%hi16()' 19075 19076 When loading a 20-bit (or wider) address into registers, this 19077 modifier selects the 16 most significant bits. 19078 19079 movw ax,#%hi16(_sym) 19080 19081'%hi8()' 19082 19083 When loading a 20-bit (or wider) address into registers, this 19084 modifier selects the 8 bits that would go into CS or ES (i.e. bits 19085 23..16). 19086 19087 mov es, #%hi8(_sym) 19088 19089 19090File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent 19091 190929.39.3 Assembler Directives 19093--------------------------- 19094 19095In addition to the common directives, the RL78 adds these: 19096 19097'.double' 19098 Output a constant in "double" format, which is either a 32-bit or a 19099 64-bit floating point value, depending upon the setting of the 19100 '-m32bit-doubles'|'-m64bit-doubles' command-line option. 19101 19102'.bss' 19103 Select the BSS section. 19104 19105'.3byte' 19106 Output a constant value in a three byte format. 19107 19108'.int' 19109'.word' 19110 Output a constant value in a four byte format. 19111 19112 19113File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent 19114 191159.39.4 Syntax for the RL78 19116-------------------------- 19117 19118* Menu: 19119 19120* RL78-Chars:: Special Characters 19121 19122 19123File: as.info, Node: RL78-Chars, Up: RL78-Syntax 19124 191259.39.4.1 Special Characters 19126........................... 19127 19128The presence of a ';' appearing anywhere on a line indicates the start 19129of a comment that extends to the end of that line. 19130 19131 If a '#' appears as the first character of a line then the whole line 19132is treated as a comment, but in this case the line can also be a logical 19133line number directive (*note Comments::) or a preprocessor control 19134command (*note Preprocessing::). 19135 19136 The '|' character can be used to separate statements on the same 19137line. 19138 19139 19140File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies 19141 191429.40 RX Dependent Features 19143========================== 19144 19145* Menu: 19146 19147* RX-Opts:: RX Assembler Command-line Options 19148* RX-Modifiers:: Symbolic Operand Modifiers 19149* RX-Directives:: Assembler Directives 19150* RX-Float:: Floating Point 19151* RX-Syntax:: Syntax 19152 19153 19154File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 19155 191569.40.1 RX Options 19157----------------- 19158 19159The Renesas RX port of 'as' has a few target specific command-line 19160options: 19161 19162'-m32bit-doubles' 19163 This option controls the ABI and indicates to use a 32-bit float 19164 ABI. It has no effect on the assembled instructions, but it does 19165 influence the behaviour of the '.double' pseudo-op. This is the 19166 default. 19167 19168'-m64bit-doubles' 19169 This option controls the ABI and indicates to use a 64-bit float 19170 ABI. It has no effect on the assembled instructions, but it does 19171 influence the behaviour of the '.double' pseudo-op. 19172 19173'-mbig-endian' 19174 This option controls the ABI and indicates to use a big-endian data 19175 ABI. It has no effect on the assembled instructions, but it does 19176 influence the behaviour of the '.short', '.hword', '.int', '.word', 19177 '.long', '.quad' and '.octa' pseudo-ops. 19178 19179'-mlittle-endian' 19180 This option controls the ABI and indicates to use a little-endian 19181 data ABI. It has no effect on the assembled instructions, but it 19182 does influence the behaviour of the '.short', '.hword', '.int', 19183 '.word', '.long', '.quad' and '.octa' pseudo-ops. This is the 19184 default. 19185 19186'-muse-conventional-section-names' 19187 This option controls the default names given to the code (.text), 19188 initialised data (.data) and uninitialised data sections (.bss). 19189 19190'-muse-renesas-section-names' 19191 This option controls the default names given to the code (.P), 19192 initialised data (.D_1) and uninitialised data sections (.B_1). 19193 This is the default. 19194 19195'-msmall-data-limit' 19196 This option tells the assembler that the small data limit feature 19197 of the RX port of GCC is being used. This results in the assembler 19198 generating an undefined reference to a symbol called '__gp' for use 19199 by the relocations that are needed to support the small data limit 19200 feature. This option is not enabled by default as it would 19201 otherwise pollute the symbol table. 19202 19203'-mpid' 19204 This option tells the assembler that the position independent data 19205 of the RX port of GCC is being used. This results in the assembler 19206 generating an undefined reference to a symbol called '__pid_base', 19207 and also setting the RX_PID flag bit in the e_flags field of the 19208 ELF header of the object file. 19209 19210'-mint-register=NUM' 19211 This option tells the assembler how many registers have been 19212 reserved for use by interrupt handlers. This is needed in order to 19213 compute the correct values for the '%gpreg' and '%pidreg' meta 19214 registers. 19215 19216'-mgcc-abi' 19217 This option tells the assembler that the old GCC ABI is being used 19218 by the assembled code. With this version of the ABI function 19219 arguments that are passed on the stack are aligned to a 32-bit 19220 boundary. 19221 19222'-mrx-abi' 19223 This option tells the assembler that the official RX ABI is being 19224 used by the assembled code. With this version of the ABI function 19225 arguments that are passed on the stack are aligned to their natural 19226 alignments. This option is the default. 19227 19228'-mcpu=NAME' 19229 This option tells the assembler the target CPU type. Currently the 19230 'rx100', 'rx200', 'rx600', 'rx610', 'rxv2', 'rxv3' and 'rxv3-dfpu' 19231 are recognised as valid cpu names. Attempting to assemble an 19232 instructionnot supported by the indicated cpu type will result in 19233 an error message being generated. 19234 19235'-mno-allow-string-insns' 19236 This option tells the assembler to mark the object file that it is 19237 building as one that does not use the string instructions 'SMOVF', 19238 'SCMPU', 'SMOVB', 'SMOVU', 'SUNTIL' 'SWHILE' or the 'RMPA' 19239 instruction. In addition the mark tells the linker to complain if 19240 an attempt is made to link the binary with another one that does 19241 use any of these instructions. 19242 19243 Note - the inverse of this option, '-mallow-string-insns', is not 19244 needed. The assembler automatically detects the use of the the 19245 instructions in the source code and labels the resulting object 19246 file appropriately. If no string instructions are detected then 19247 the object file is labelled as being one that can be linked with 19248 either string-using or string-banned object files. 19249 19250 19251File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent 19252 192539.40.2 Symbolic Operand Modifiers 19254--------------------------------- 19255 19256The assembler supports one modifier when using symbol addresses in RX 19257instruction operands. The general syntax is the following: 19258 19259 %gp(symbol) 19260 19261 The modifier returns the offset from the __GP symbol to the specified 19262symbol as a 16-bit value. The intent is that this offset should be used 19263in a register+offset move instruction when generating references to 19264small data. Ie, like this: 19265 19266 mov.W %gp(_foo)[%gpreg], r1 19267 19268 The assembler also supports two meta register names which can be used 19269to refer to registers whose values may not be known to the programmer. 19270These meta register names are: 19271 19272'%gpreg' 19273 The small data address register. 19274 19275'%pidreg' 19276 The PID base address register. 19277 19278 Both registers normally have the value r13, but this can change if 19279some registers have been reserved for use by interrupt handlers or if 19280both the small data limit and position independent data features are 19281being used at the same time. 19282 19283 19284File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent 19285 192869.40.3 Assembler Directives 19287--------------------------- 19288 19289The RX version of 'as' has the following specific assembler directives: 19290 19291'.3byte' 19292 Inserts a 3-byte value into the output file at the current 19293 location. 19294 19295'.fetchalign' 19296 If the next opcode following this directive spans a fetch line 19297 boundary (8 byte boundary), the opcode is aligned to that boundary. 19298 If the next opcode does not span a fetch line, this directive has 19299 no effect. Note that one or more labels may be between this 19300 directive and the opcode; those labels are aligned as well. Any 19301 inserted bytes due to alignment will form a NOP opcode. 19302 19303 19304File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent 19305 193069.40.4 Floating Point 19307--------------------- 19308 19309The floating point formats generated by directives are these. 19310 19311'.float' 19312 'Single' precision (32-bit) floating point constants. 19313 19314'.double' 19315 If the '-m64bit-doubles' command-line option has been specified 19316 then then 'double' directive generates 'double' precision (64-bit) 19317 floating point constants, otherwise it generates 'single' precision 19318 (32-bit) floating point constants. To force the generation of 19319 64-bit floating point constants used the 'dc.d' directive instead. 19320 19321 19322File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent 19323 193249.40.5 Syntax for the RX 19325------------------------ 19326 19327* Menu: 19328 19329* RX-Chars:: Special Characters 19330 19331 19332File: as.info, Node: RX-Chars, Up: RX-Syntax 19333 193349.40.5.1 Special Characters 19335........................... 19336 19337The presence of a ';' appearing anywhere on a line indicates the start 19338of a comment that extends to the end of that line. 19339 19340 If a '#' appears as the first character of a line then the whole line 19341is treated as a comment, but in this case the line can also be a logical 19342line number directive (*note Comments::) or a preprocessor control 19343command (*note Preprocessing::). 19344 19345 The '!' character can be used to separate statements on the same 19346line. 19347 19348 19349File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies 19350 193519.41 IBM S/390 Dependent Features 19352================================= 19353 19354The s390 version of 'as' supports two architectures modes and eleven 19355chip levels. The architecture modes are the Enterprise System 19356Architecture (ESA) and the newer z/Architecture mode. The chip levels 19357are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec 19358(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or 19359arch11), z14 (or arch12), z15 (or arch13), or arch14. 19360 19361* Menu: 19362 19363* s390 Options:: Command-line Options. 19364* s390 Characters:: Special Characters. 19365* s390 Syntax:: Assembler Instruction syntax. 19366* s390 Directives:: Assembler Directives. 19367* s390 Floating Point:: Floating Point. 19368 19369 19370File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent 19371 193729.41.1 Options 19373-------------- 19374 19375The following table lists all available s390 specific options: 19376 19377'-m31 | -m64' 19378 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. 19379 19380 These options are only available with the ELF object file format, 19381 and require that the necessary BFD support has been included (on a 19382 31-bit platform you must add -enable-64-bit-bfd on the call to the 19383 configure script to enable 64-bit usage and use s390x as target 19384 platform). 19385 19386'-mesa | -mzarch' 19387 Select the architecture mode, either the Enterprise System 19388 Architecture (esa) mode or the z/Architecture mode (zarch). 19389 19390 The 64-bit instructions are only available with the z/Architecture 19391 mode. The combination of '-m64' and '-mesa' results in a warning 19392 message. 19393 19394'-march=CPU' 19395 This option specifies the target processor. The following 19396 processor names are recognized: 'g5' (or 'arch3'), 'g6', 'z900' (or 19397 'arch5'), 'z990' (or 'arch6'), 'z9-109', 'z9-ec' (or 'arch7'), 19398 'z10' (or 'arch8'), 'z196' (or 'arch9'), 'zEC12' (or 'arch10'), 19399 'z13' (or 'arch11'), 'z14' (or 'arch12'), 'z15' (or 'arch13'), and 19400 'arch14'. 19401 19402 Assembling an instruction that is not supported on the target 19403 processor results in an error message. 19404 19405 The processor names starting with 'arch' refer to the edition 19406 number in the Principle of Operations manual. They can be used as 19407 alternate processor names and have been added for compatibility 19408 with the IBM XL compiler. 19409 19410 'arch3', 'g5' and 'g6' cannot be used with the '-mzarch' option 19411 since the z/Architecture mode is not supported on these processor 19412 levels. 19413 19414 There is no 'arch4' option supported. 'arch4' matches 19415 '-march=arch5 -mesa'. 19416 19417'-mregnames' 19418 Allow symbolic names for registers. 19419 19420'-mno-regnames' 19421 Do not allow symbolic names for registers. 19422 19423'-mwarn-areg-zero' 19424 Warn whenever the operand for a base or index register has been 19425 specified but evaluates to zero. This can indicate the misuse of 19426 general purpose register 0 as an address register. 19427 19428 19429File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 19430 194319.41.2 Special Characters 19432------------------------- 19433 19434'#' is the line comment character. 19435 19436 If a '#' appears as the first character of a line then the whole line 19437is treated as a comment, but in this case the line could also be a 19438logical line number directive (*note Comments::) or a preprocessor 19439control command (*note Preprocessing::). 19440 19441 The ';' character can be used instead of a newline to separate 19442statements. 19443 19444 19445File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent 19446 194479.41.3 Instruction syntax 19448------------------------- 19449 19450The assembler syntax closely follows the syntax outlined in Enterprise 19451Systems Architecture/390 Principles of Operation (SA22-7201) and the 19452z/Architecture Principles of Operation (SA22-7832). 19453 19454 Each instruction has two major parts, the instruction mnemonic and 19455the instruction operands. The instruction format varies. 19456 19457* Menu: 19458 19459* s390 Register:: Register Naming 19460* s390 Mnemonics:: Instruction Mnemonics 19461* s390 Operands:: Instruction Operands 19462* s390 Formats:: Instruction Formats 19463* s390 Aliases:: Instruction Aliases 19464* s390 Operand Modifier:: Instruction Operand Modifier 19465* s390 Instruction Marker:: Instruction Marker 19466* s390 Literal Pool Entries:: Literal Pool Entries 19467 19468 19469File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 19470 194719.41.3.1 Register naming 19472........................ 19473 19474The 'as' recognizes a number of predefined symbols for the various 19475processor registers. A register specification in one of the instruction 19476formats is an unsigned integer between 0 and 15. The specific 19477instruction and the position of the register in the instruction format 19478denotes the type of the register. The register symbols are prefixed 19479with '%': 19480 19481 %rN the 16 general purpose registers, 0 <= N <= 15 19482 %fN the 16 floating point registers, 0 <= N <= 15 19483 %aN the 16 access registers, 0 <= N <= 15 19484 %cN the 16 control registers, 0 <= N <= 15 19485 %lit an alias for the general purpose register %r13 19486 %sp an alias for the general purpose register %r15 19487 19488 19489File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax 19490 194919.41.3.2 Instruction Mnemonics 19492.............................. 19493 19494All instructions documented in the Principles of Operation are supported 19495with the mnemonic and order of operands as described. The instruction 19496mnemonic identifies the instruction format (*note s390 Formats::) and 19497the specific operation code for the instruction. For example, the 'lr' 19498mnemonic denotes the instruction format 'RR' with the operation code 19499'0x18'. 19500 19501 The definition of the various mnemonics follows a scheme, where the 19502first character usually hint at the type of the instruction: 19503 19504 a add instruction, for example 'al' for add logical 32-bit 19505 b branch instruction, for example 'bc' for branch on condition 19506 c compare or convert instruction, for example 'cr' for compare 19507 register 32-bit 19508 d divide instruction, for example 'dlr' devide logical register 19509 64-bit to 32-bit 19510 i insert instruction, for example 'ic' insert character 19511 l load instruction, for example 'ltr' load and test register 19512 mv move instruction, for example 'mvc' move character 19513 m multiply instruction, for example 'mh' multiply halfword 19514 n and instruction, for example 'ni' and immediate 19515 o or instruction, for example 'oc' or character 19516 sla, sll shift left single instruction 19517 sra, srl shift right single instruction 19518 st store instruction, for example 'stm' store multiple 19519 s subtract instruction, for example 'slr' subtract 19520 logical 32-bit 19521 t test or translate instruction, of example 'tm' test under mask 19522 x exclusive or instruction, for example 'xc' exclusive or 19523 character 19524 19525 Certain characters at the end of the mnemonic may describe a property 19526of the instruction: 19527 19528 c the instruction uses a 8-bit character operand 19529 f the instruction extends a 32-bit operand to 64 bit 19530 g the operands are treated as 64-bit values 19531 h the operand uses a 16-bit halfword operand 19532 i the instruction uses an immediate operand 19533 l the instruction uses unsigned, logical operands 19534 m the instruction uses a mask or operates on multiple values 19535 r if r is the last character, the instruction operates on registers 19536 y the instruction uses 20-bit displacements 19537 19538 There are many exceptions to the scheme outlined in the above lists, 19539in particular for the privileged instructions. For non-privileged 19540instruction it works quite well, for example the instruction 'clgfr' c: 19541compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to 1954264-bit extension, r: register operands. The instruction compares an 1954364-bit value in a register with the zero extended 32-bit value from a 19544second register. For a complete list of all mnemonics see appendix B in 19545the Principles of Operation. 19546 19547 19548File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax 19549 195509.41.3.3 Instruction Operands 19551............................. 19552 19553Instruction operands can be grouped into three classes, operands located 19554in registers, immediate operands, and operands in storage. 19555 19556 A register operand can be located in general, floating-point, access, 19557or control register. The register is identified by a four-bit field. 19558The field containing the register operand is called the R field. 19559 19560 Immediate operands are contained within the instruction and can have 195618, 16 or 32 bits. The field containing the immediate operand is called 19562the I field. Dependent on the instruction the I field is either signed 19563or unsigned. 19564 19565 A storage operand consists of an address and a length. The address 19566of a storage operands can be specified in any of these ways: 19567 19568 * The content of a single general R 19569 * The sum of the content of a general register called the base 19570 register B plus the content of a displacement field D 19571 * The sum of the contents of two general registers called the index 19572 register X and the base register B plus the content of a 19573 displacement field 19574 * The sum of the current instruction address and a 32-bit signed 19575 immediate field multiplied by two. 19576 19577 The length of a storage operand can be: 19578 19579 * Implied by the instruction 19580 * Specified by a bitmask 19581 * Specified by a four-bit or eight-bit length field L 19582 * Specified by the content of a general register 19583 19584 The notation for storage operand addresses formed from multiple 19585fields is as follows: 19586 19587'Dn(Bn)' 19588 the address for operand number n is formed from the content of 19589 general register Bn called the base register and the displacement 19590 field Dn. 19591'Dn(Xn,Bn)' 19592 the address for operand number n is formed from the content of 19593 general register Xn called the index register, general register Bn 19594 called the base register and the displacement field Dn. 19595'Dn(Ln,Bn)' 19596 the address for operand number n is formed from the content of 19597 general register Bn called the base register and the displacement 19598 field Dn. The length of the operand n is specified by the field 19599 Ln. 19600 19601 The base registers Bn and the index registers Xn of a storage operand 19602can be skipped. If Bn and Xn are skipped, a zero will be stored to the 19603operand field. The notation changes as follows: 19604 19605 full notation short notation 19606 ---------------------------------------------- 19607 Dn(0,Bn) Dn(Bn) 19608 Dn(0,0) Dn 19609 Dn(0) Dn 19610 Dn(Ln,0) Dn(Ln) 19611 19612 19613File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax 19614 196159.41.3.4 Instruction Formats 19616............................ 19617 19618The Principles of Operation manuals lists 35 instruction formats where 19619some of the formats have multiple variants. For the '.insn' pseudo 19620directive the assembler recognizes some of the formats. Typically, the 19621most general variant of the instruction format is used by the '.insn' 19622directive. 19623 19624 The following table lists the abbreviations used in the table of 19625instruction formats: 19626 19627 OpCode / OpCd Part of the op code. 19628 Bx Base register number for operand x. 19629 Dx Displacement for operand x. 19630 DLx Displacement lower 12 bits for operand x. 19631 DHx Displacement higher 8-bits for operand x. 19632 Rx Register number for operand x. 19633 Xx Index register number for operand x. 19634 Ix Signed immediate for operand x. 19635 Ux Unsigned immediate for operand x. 19636 19637 An instruction is two, four, or six bytes in length and must be 19638aligned on a 2 byte boundary. The first two bits of the instruction 19639specify the length of the instruction, 00 indicates a two byte 19640instruction, 01 and 10 indicates a four byte instruction, and 11 19641indicates a six byte instruction. 19642 19643 The following table lists the s390 instruction formats that are 19644available with the '.insn' pseudo directive: 19645 19646'E format' 19647 +-------------+ 19648 | OpCode | 19649 +-------------+ 19650 0 15 19651 19652'RI format: <insn> R1,I2' 19653 +--------+----+----+------------------+ 19654 | OpCode | R1 |OpCd| I2 | 19655 +--------+----+----+------------------+ 19656 0 8 12 16 31 19657 19658'RIE format: <insn> R1,R3,I2' 19659 +--------+----+----+------------------+--------+--------+ 19660 | OpCode | R1 | R3 | I2 |////////| OpCode | 19661 +--------+----+----+------------------+--------+--------+ 19662 0 8 12 16 32 40 47 19663 19664'RIL format: <insn> R1,I2' 19665 +--------+----+----+------------------------------------+ 19666 | OpCode | R1 |OpCd| I2 | 19667 +--------+----+----+------------------------------------+ 19668 0 8 12 16 47 19669 19670'RILU format: <insn> R1,U2' 19671 +--------+----+----+------------------------------------+ 19672 | OpCode | R1 |OpCd| U2 | 19673 +--------+----+----+------------------------------------+ 19674 0 8 12 16 47 19675 19676'RIS format: <insn> R1,I2,M3,D4(B4)' 19677 +--------+----+----+----+-------------+--------+--------+ 19678 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 19679 +--------+----+----+----+-------------+--------+--------+ 19680 0 8 12 16 20 32 36 47 19681 19682'RR format: <insn> R1,R2' 19683 +--------+----+----+ 19684 | OpCode | R1 | R2 | 19685 +--------+----+----+ 19686 0 8 12 15 19687 19688'RRE format: <insn> R1,R2' 19689 +------------------+--------+----+----+ 19690 | OpCode |////////| R1 | R2 | 19691 +------------------+--------+----+----+ 19692 0 16 24 28 31 19693 19694'RRF format: <insn> R1,R2,R3,M4' 19695 +------------------+----+----+----+----+ 19696 | OpCode | R3 | M4 | R1 | R2 | 19697 +------------------+----+----+----+----+ 19698 0 16 20 24 28 31 19699 19700'RRS format: <insn> R1,R2,M3,D4(B4)' 19701 +--------+----+----+----+-------------+----+----+--------+ 19702 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 19703 +--------+----+----+----+-------------+----+----+--------+ 19704 0 8 12 16 20 32 36 40 47 19705 19706'RS format: <insn> R1,R3,D2(B2)' 19707 +--------+----+----+----+-------------+ 19708 | OpCode | R1 | R3 | B2 | D2 | 19709 +--------+----+----+----+-------------+ 19710 0 8 12 16 20 31 19711 19712'RSE format: <insn> R1,R3,D2(B2)' 19713 +--------+----+----+----+-------------+--------+--------+ 19714 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 19715 +--------+----+----+----+-------------+--------+--------+ 19716 0 8 12 16 20 32 40 47 19717 19718'RSI format: <insn> R1,R3,I2' 19719 +--------+----+----+------------------------------------+ 19720 | OpCode | R1 | R3 | I2 | 19721 +--------+----+----+------------------------------------+ 19722 0 8 12 16 47 19723 19724'RSY format: <insn> R1,R3,D2(B2)' 19725 +--------+----+----+----+-------------+--------+--------+ 19726 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 19727 +--------+----+----+----+-------------+--------+--------+ 19728 0 8 12 16 20 32 40 47 19729 19730'RX format: <insn> R1,D2(X2,B2)' 19731 +--------+----+----+----+-------------+ 19732 | OpCode | R1 | X2 | B2 | D2 | 19733 +--------+----+----+----+-------------+ 19734 0 8 12 16 20 31 19735 19736'RXE format: <insn> R1,D2(X2,B2)' 19737 +--------+----+----+----+-------------+--------+--------+ 19738 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 19739 +--------+----+----+----+-------------+--------+--------+ 19740 0 8 12 16 20 32 40 47 19741 19742'RXF format: <insn> R1,R3,D2(X2,B2)' 19743 +--------+----+----+----+-------------+----+---+--------+ 19744 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 19745 +--------+----+----+----+-------------+----+---+--------+ 19746 0 8 12 16 20 32 36 40 47 19747 19748'RXY format: <insn> R1,D2(X2,B2)' 19749 +--------+----+----+----+-------------+--------+--------+ 19750 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 19751 +--------+----+----+----+-------------+--------+--------+ 19752 0 8 12 16 20 32 36 40 47 19753 19754'S format: <insn> D2(B2)' 19755 +------------------+----+-------------+ 19756 | OpCode | B2 | D2 | 19757 +------------------+----+-------------+ 19758 0 16 20 31 19759 19760'SI format: <insn> D1(B1),I2' 19761 +--------+---------+----+-------------+ 19762 | OpCode | I2 | B1 | D1 | 19763 +--------+---------+----+-------------+ 19764 0 8 16 20 31 19765 19766'SIY format: <insn> D1(B1),U2' 19767 +--------+---------+----+-------------+--------+--------+ 19768 | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 19769 +--------+---------+----+-------------+--------+--------+ 19770 0 8 16 20 32 36 40 47 19771 19772'SIL format: <insn> D1(B1),I2' 19773 +------------------+----+-------------+-----------------+ 19774 | OpCode | B1 | D1 | I2 | 19775 +------------------+----+-------------+-----------------+ 19776 0 16 20 32 47 19777 19778'SS format: <insn> D1(R1,B1),D2(B3),R3' 19779 +--------+----+----+----+-------------+----+------------+ 19780 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 19781 +--------+----+----+----+-------------+----+------------+ 19782 0 8 12 16 20 32 36 47 19783 19784'SSE format: <insn> D1(B1),D2(B2)' 19785 +------------------+----+-------------+----+------------+ 19786 | OpCode | B1 | D1 | B2 | D2 | 19787 +------------------+----+-------------+----+------------+ 19788 0 8 12 16 20 32 36 47 19789 19790'SSF format: <insn> D1(B1),D2(B2),R3' 19791 +--------+----+----+----+-------------+----+------------+ 19792 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 19793 +--------+----+----+----+-------------+----+------------+ 19794 0 8 12 16 20 32 36 47 19795 19796'VRV format: <insn> V1,D2(V2,B2),M3' 19797 +--------+----+----+----+-------------+----+------------+ 19798 | OpCode | V1 | V2 | B2 | D2 | M3 | Opcode | 19799 +--------+----+----+----+-------------+----+------------+ 19800 0 8 12 16 20 32 36 47 19801 19802'VRI format: <insn> V1,V2,I3,M4,M5' 19803 +--------+----+----+-------------+----+----+------------+ 19804 | OpCode | V1 | V2 | I3 | M5 | M4 | Opcode | 19805 +--------+----+----+-------------+----+----+------------+ 19806 0 8 12 16 28 32 36 47 19807 19808'VRX format: <insn> V1,D2(R2,B2),M3' 19809 +--------+----+----+----+-------------+----+------------+ 19810 | OpCode | V1 | R2 | B2 | D2 | M3 | Opcode | 19811 +--------+----+----+----+-------------+----+------------+ 19812 0 8 12 16 20 32 36 47 19813 19814'VRS format: <insn> R1,V3,D2(B2),M4' 19815 +--------+----+----+----+-------------+----+------------+ 19816 | OpCode | R1 | V3 | B2 | D2 | M4 | Opcode | 19817 +--------+----+----+----+-------------+----+------------+ 19818 0 8 12 16 20 32 36 47 19819 19820'VRR format: <insn> V1,V2,V3,M4,M5,M6' 19821 +--------+----+----+----+---+----+----+----+------------+ 19822 | OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 | Opcode | 19823 +--------+----+----+----+---+----+----+----+------------+ 19824 0 8 12 16 24 28 32 36 47 19825 19826'VSI format: <insn> V1,D2(B2),I3' 19827 +--------+---------+----+-------------+----+------------+ 19828 | OpCode | I3 | B2 | D2 | V1 | Opcode | 19829 +--------+---------+----+-------------+----+------------+ 19830 0 8 16 20 32 36 47 19831 19832 For the complete list of all instruction format variants see the 19833Principles of Operation manuals. 19834 19835 19836File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax 19837 198389.41.3.5 Instruction Aliases 19839............................ 19840 19841A specific bit pattern can have multiple mnemonics, for example the bit 19842pattern '0xa7000000' has the mnemonics 'tmh' and 'tmlh'. In addition, 19843there are a number of mnemonics recognized by 'as' that are not present 19844in the Principles of Operation. These are the short forms of the branch 19845instructions, where the condition code mask operand is encoded in the 19846mnemonic. This is relevant for the branch instructions, the compare and 19847branch instructions, and the compare and trap instructions. 19848 19849 For the branch instructions there are 20 condition code strings that 19850can be used as part of the mnemonic in place of a mask operand in the 19851instruction format: 19852 19853 instruction short form 19854 ---------------------------------------------- 19855 bcr M1,R2 b<m>r R2 19856 bc M1,D2(X2,B2) b<m> D2(X2,B2) 19857 brc M1,I2 j<m> I2 19858 brcl M1,I2 jg<m> I2 19859 19860 In the mnemonic for a branch instruction the condition code string 19861<m> can be any of the following: 19862 19863 o jump on overflow / if ones 19864 h jump on A high 19865 p jump on plus 19866 nle jump on not low or equal 19867 l jump on A low 19868 m jump on minus 19869 nhe jump on not high or equal 19870 lh jump on low or high 19871 ne jump on A not equal B 19872 nz jump on not zero / if not zeros 19873 e jump on A equal B 19874 z jump on zero / if zeroes 19875 nlh jump on not low or high 19876 he jump on high or equal 19877 nl jump on A not low 19878 nm jump on not minus / if not mixed 19879 le jump on low or equal 19880 nh jump on A not high 19881 np jump on not plus 19882 no jump on not overflow / if not ones 19883 19884 For the compare and branch, and compare and trap instructions there 19885are 12 condition code strings that can be used as part of the mnemonic 19886in place of a mask operand in the instruction format: 19887 19888 instruction short form 19889 ------------------------------------------------------------ 19890 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) 19891 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) 19892 crj R1,R2,M3,I4 crj<m> R1,R2,I4 19893 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 19894 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) 19895 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) 19896 cij R1,I2,M3,I4 cij<m> R1,I2,I4 19897 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 19898 crt R1,R2,M3 crt<m> R1,R2 19899 cgrt R1,R2,M3 cgrt<m> R1,R2 19900 cit R1,I2,M3 cit<m> R1,I2 19901 cgit R1,I2,M3 cgit<m> R1,I2 19902 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) 19903 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) 19904 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 19905 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 19906 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) 19907 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) 19908 clij R1,I2,M3,I4 clij<m> R1,I2,I4 19909 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 19910 clrt R1,R2,M3 clrt<m> R1,R2 19911 clgrt R1,R2,M3 clgrt<m> R1,R2 19912 clfit R1,I2,M3 clfit<m> R1,I2 19913 clgit R1,I2,M3 clgit<m> R1,I2 19914 19915 In the mnemonic for a compare and branch and compare and trap 19916instruction the condition code string <m> can be any of the following: 19917 19918 h jump on A high 19919 nle jump on not low or equal 19920 l jump on A low 19921 nhe jump on not high or equal 19922 ne jump on A not equal B 19923 lh jump on low or high 19924 e jump on A equal B 19925 nlh jump on not low or high 19926 nl jump on A not low 19927 he jump on high or equal 19928 nh jump on A not high 19929 le jump on low or equal 19930 19931 19932File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax 19933 199349.41.3.6 Instruction Operand Modifier 19935..................................... 19936 19937If a symbol modifier is attached to a symbol in an expression for an 19938instruction operand field, the symbol term is replaced with a reference 19939to an object in the global offset table (GOT) or the procedure linkage 19940table (PLT). The following expressions are allowed: 'symbol@modifier + 19941constant', 'symbol@modifier + label + constant', and 'symbol@modifier - 19942label + constant'. The term 'symbol' is the symbol that will be entered 19943into the GOT or PLT, 'label' is a local label, and 'constant' is an 19944arbitrary expression that the assembler can evaluate to a constant 19945value. 19946 19947 The term '(symbol + constant1)@modifier +/- label + constant2' is 19948also accepted but a warning message is printed and the term is converted 19949to 'symbol@modifier +/- label + constant1 + constant2'. 19950 19951'@got' 19952'@got12' 19953 The @got modifier can be used for displacement fields, 16-bit 19954 immediate fields and 32-bit pc-relative immediate fields. The 19955 @got12 modifier is synonym to @got. The symbol is added to the 19956 GOT. For displacement fields and 16-bit immediate fields the symbol 19957 term is replaced with the offset from the start of the GOT to the 19958 GOT slot for the symbol. For a 32-bit pc-relative field the 19959 pc-relative offset to the GOT slot from the current instruction 19960 address is used. 19961'@gotent' 19962 The @gotent modifier can be used for 32-bit pc-relative immediate 19963 fields. The symbol is added to the GOT and the symbol term is 19964 replaced with the pc-relative offset from the current instruction 19965 to the GOT slot for the symbol. 19966'@gotoff' 19967 The @gotoff modifier can be used for 16-bit immediate fields. The 19968 symbol term is replaced with the offset from the start of the GOT 19969 to the address of the symbol. 19970'@gotplt' 19971 The @gotplt modifier can be used for displacement fields, 16-bit 19972 immediate fields, and 32-bit pc-relative immediate fields. A 19973 procedure linkage table entry is generated for the symbol and a 19974 jump slot for the symbol is added to the GOT. For displacement 19975 fields and 16-bit immediate fields the symbol term is replaced with 19976 the offset from the start of the GOT to the jump slot for the 19977 symbol. For a 32-bit pc-relative field the pc-relative offset to 19978 the jump slot from the current instruction address is used. 19979'@plt' 19980 The @plt modifier can be used for 16-bit and 32-bit pc-relative 19981 immediate fields. A procedure linkage table entry is generated for 19982 the symbol. The symbol term is replaced with the relative offset 19983 from the current instruction to the PLT entry for the symbol. 19984'@pltoff' 19985 The @pltoff modifier can be used for 16-bit immediate fields. The 19986 symbol term is replaced with the offset from the start of the PLT 19987 to the address of the symbol. 19988'@gotntpoff' 19989 The @gotntpoff modifier can be used for displacement fields. The 19990 symbol is added to the static TLS block and the negated offset to 19991 the symbol in the static TLS block is added to the GOT. The symbol 19992 term is replaced with the offset to the GOT slot from the start of 19993 the GOT. 19994'@indntpoff' 19995 The @indntpoff modifier can be used for 32-bit pc-relative 19996 immediate fields. The symbol is added to the static TLS block and 19997 the negated offset to the symbol in the static TLS block is added 19998 to the GOT. The symbol term is replaced with the pc-relative offset 19999 to the GOT slot from the current instruction address. 20000 20001 For more information about the thread local storage modifiers 20002'gotntpoff' and 'indntpoff' see the ELF extension documentation 'ELF 20003Handling For Thread-Local Storage'. 20004 20005 20006File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax 20007 200089.41.3.7 Instruction Marker 20009........................... 20010 20011The thread local storage instruction markers are used by the linker to 20012perform code optimization. 20013 20014':tls_load' 20015 The :tls_load marker is used to flag the load instruction in the 20016 initial exec TLS model that retrieves the offset from the thread 20017 pointer to a thread local storage variable from the GOT. 20018':tls_gdcall' 20019 The :tls_gdcall marker is used to flag the branch-and-save 20020 instruction to the __tls_get_offset function in the global dynamic 20021 TLS model. 20022':tls_ldcall' 20023 The :tls_ldcall marker is used to flag the branch-and-save 20024 instruction to the __tls_get_offset function in the local dynamic 20025 TLS model. 20026 20027 For more information about the thread local storage instruction 20028marker and the linker optimizations see the ELF extension documentation 20029'ELF Handling For Thread-Local Storage'. 20030 20031 20032File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax 20033 200349.41.3.8 Literal Pool Entries 20035............................. 20036 20037A literal pool is a collection of values. To access the values a 20038pointer to the literal pool is loaded to a register, the literal pool 20039register. Usually, register %r13 is used as the literal pool register 20040(*note s390 Register::). Literal pool entries are created by adding the 20041suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 20042instruction operand. The expression is added to the literal pool and 20043the operand is replaced with the offset to the literal in the literal 20044pool. 20045 20046':lit1' 20047 The literal pool entry is created as an 8-bit value. An operand 20048 modifier must not be used for the original expression. 20049':lit2' 20050 The literal pool entry is created as a 16 bit value. The operand 20051 modifier @got may be used in the original expression. The term 20052 'x@got:lit2' will put the got offset for the global symbol x to the 20053 literal pool as 16 bit value. 20054':lit4' 20055 The literal pool entry is created as a 32-bit value. The operand 20056 modifier @got and @plt may be used in the original expression. The 20057 term 'x@got:lit4' will put the got offset for the global symbol x 20058 to the literal pool as a 32-bit value. The term 'x@plt:lit4' will 20059 put the plt offset for the global symbol x to the literal pool as a 20060 32-bit value. 20061':lit8' 20062 The literal pool entry is created as a 64-bit value. The operand 20063 modifier @got and @plt may be used in the original expression. The 20064 term 'x@got:lit8' will put the got offset for the global symbol x 20065 to the literal pool as a 64-bit value. The term 'x@plt:lit8' will 20066 put the plt offset for the global symbol x to the literal pool as a 20067 64-bit value. 20068 20069 The assembler directive '.ltorg' is used to emit all literal pool 20070entries to the current position. 20071 20072 20073File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent 20074 200759.41.4 Assembler Directives 20076--------------------------- 20077 20078'as' for s390 supports all of the standard ELF assembler directives as 20079outlined in the main part of this document. Some directives have been 20080extended and there are some additional directives, which are only 20081available for the s390 'as'. 20082 20083'.insn' 20084 This directive permits the numeric representation of an 20085 instructions and makes the assembler insert the operands according 20086 to one of the instructions formats for '.insn' (*note s390 20087 Formats::). For example, the instruction 'l %r1,24(%r15)' could be 20088 written as '.insn rx,0x58000000,%r1,24(%r15)'. 20089'.short' 20090'.long' 20091'.quad' 20092 This directive places one or more 16-bit (.short), 32-bit (.long), 20093 or 64-bit (.quad) values into the current section. If an ELF or 20094 TLS modifier is used only the following expressions are allowed: 20095 'symbol@modifier + constant', 'symbol@modifier + label + constant', 20096 and 'symbol@modifier - label + constant'. The following modifiers 20097 are available: 20098 '@got' 20099 '@got12' 20100 The @got modifier can be used for .short, .long and .quad. 20101 The @got12 modifier is synonym to @got. The symbol is added 20102 to the GOT. The symbol term is replaced with offset from the 20103 start of the GOT to the GOT slot for the symbol. 20104 '@gotoff' 20105 The @gotoff modifier can be used for .short, .long and .quad. 20106 The symbol term is replaced with the offset from the start of 20107 the GOT to the address of the symbol. 20108 '@gotplt' 20109 The @gotplt modifier can be used for .long and .quad. A 20110 procedure linkage table entry is generated for the symbol and 20111 a jump slot for the symbol is added to the GOT. The symbol 20112 term is replaced with the offset from the start of the GOT to 20113 the jump slot for the symbol. 20114 '@plt' 20115 The @plt modifier can be used for .long and .quad. A 20116 procedure linkage table entry us generated for the symbol. 20117 The symbol term is replaced with the address of the PLT entry 20118 for the symbol. 20119 '@pltoff' 20120 The @pltoff modifier can be used for .short, .long and .quad. 20121 The symbol term is replaced with the offset from the start of 20122 the PLT to the address of the symbol. 20123 '@tlsgd' 20124 '@tlsldm' 20125 The @tlsgd and @tlsldm modifier can be used for .long and 20126 .quad. A tls_index structure for the symbol is added to the 20127 GOT. The symbol term is replaced with the offset from the 20128 start of the GOT to the tls_index structure. 20129 '@gotntpoff' 20130 '@indntpoff' 20131 The @gotntpoff and @indntpoff modifier can be used for .long 20132 and .quad. The symbol is added to the static TLS block and 20133 the negated offset to the symbol in the static TLS block is 20134 added to the GOT. For @gotntpoff the symbol term is replaced 20135 with the offset from the start of the GOT to the GOT slot, for 20136 @indntpoff the symbol term is replaced with the address of the 20137 GOT slot. 20138 '@dtpoff' 20139 The @dtpoff modifier can be used for .long and .quad. The 20140 symbol term is replaced with the offset of the symbol relative 20141 to the start of the TLS block it is contained in. 20142 '@ntpoff' 20143 The @ntpoff modifier can be used for .long and .quad. The 20144 symbol term is replaced with the offset of the symbol relative 20145 to the TCB pointer. 20146 20147 For more information about the thread local storage modifiers see 20148 the ELF extension documentation 'ELF Handling For Thread-Local 20149 Storage'. 20150 20151'.ltorg' 20152 This directive causes the current contents of the literal pool to 20153 be dumped to the current location (*note s390 Literal Pool 20154 Entries::). 20155 20156'.machine STRING[+EXTENSION]...' 20157 20158 This directive allows changing the machine for which code is 20159 generated. 'string' may be any of the '-march=' selection options, 20160 or 'push', or 'pop'. '.machine push' saves the currently selected 20161 cpu, which may be restored with '.machine pop'. Be aware that the 20162 cpu string has to be put into double quotes in case it contains 20163 characters not appropriate for identifiers. So you have to write 20164 '"z9-109"' instead of just 'z9-109'. Extensions can be specified 20165 after the cpu name, separated by plus characters. Valid extensions 20166 are: 'htm', 'nohtm', 'vx', 'novx'. They extend the basic 20167 instruction set with features from a higher cpu level, or remove 20168 support for a feature from the given cpu level. 20169 20170 Example: 'z13+nohtm' allows all instructions of the z13 cpu except 20171 instructions from the HTM facility. 20172 20173'.machinemode string' 20174 This directive allows one to change the architecture mode for which 20175 code is being generated. 'string' may be 'esa', 'zarch', 20176 'zarch_nohighgprs', 'push', or 'pop'. '.machinemode 20177 zarch_nohighgprs' can be used to prevent the 'highgprs' flag from 20178 being set in the ELF header of the output file. This is useful in 20179 situations where the code is gated with a runtime check which makes 20180 sure that the code is only executed on kernels providing the 20181 'highgprs' feature. '.machinemode push' saves the currently 20182 selected mode, which may be restored with '.machinemode pop'. 20183 20184 20185File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent 20186 201879.41.5 Floating Point 20188--------------------- 20189 20190The assembler recognizes both the IEEE floating-point instruction and 20191the hexadecimal floating-point instructions. The floating-point 20192constructors '.float', '.single', and '.double' always emit the IEEE 20193format. To assemble hexadecimal floating-point constants the '.long' 20194and '.quad' directives must be used. 20195 20196 20197File: as.info, Node: SCORE-Dependent, Next: SH-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 20198 201999.42 SCORE Dependent Features 20200============================= 20201 20202* Menu: 20203 20204* SCORE-Opts:: Assembler options 20205* SCORE-Pseudo:: SCORE Assembler Directives 20206* SCORE-Syntax:: Syntax 20207 20208 20209File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent 20210 202119.42.1 Options 20212-------------- 20213 20214The following table lists all available SCORE options. 20215 20216'-G NUM' 20217 This option sets the largest size of an object that can be 20218 referenced implicitly with the 'gp' register. The default value is 20219 8. 20220 20221'-EB' 20222 Assemble code for a big-endian cpu 20223 20224'-EL' 20225 Assemble code for a little-endian cpu 20226 20227'-FIXDD' 20228 Assemble code for fix data dependency 20229 20230'-NWARN' 20231 Assemble code for no warning message for fix data dependency 20232 20233'-SCORE5' 20234 Assemble code for target is SCORE5 20235 20236'-SCORE5U' 20237 Assemble code for target is SCORE5U 20238 20239'-SCORE7' 20240 Assemble code for target is SCORE7, this is default setting 20241 20242'-SCORE3' 20243 Assemble code for target is SCORE3 20244 20245'-march=score7' 20246 Assemble code for target is SCORE7, this is default setting 20247 20248'-march=score3' 20249 Assemble code for target is SCORE3 20250 20251'-USE_R1' 20252 Assemble code for no warning message when using temp register r1 20253 20254'-KPIC' 20255 Generate code for PIC. This option tells the assembler to generate 20256 score position-independent macro expansions. It also tells the 20257 assembler to mark the output file as PIC. 20258 20259'-O0' 20260 Assembler will not perform any optimizations 20261 20262'-V' 20263 Sunplus release version 20264 20265 20266File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent 20267 202689.42.2 SCORE Assembler Directives 20269--------------------------------- 20270 20271A number of assembler directives are available for SCORE. The following 20272table is far from complete. 20273 20274'.set nwarn' 20275 Let the assembler not to generate warnings if the source machine 20276 language instructions happen data dependency. 20277 20278'.set fixdd' 20279 Let the assembler to insert bubbles (32 bit nop instruction / 16 20280 bit nop! Instruction) if the source machine language instructions 20281 happen data dependency. 20282 20283'.set nofixdd' 20284 Let the assembler to generate warnings if the source machine 20285 language instructions happen data dependency. (Default) 20286 20287'.set r1' 20288 Let the assembler not to generate warnings if the source program 20289 uses r1. allow user to use r1 20290 20291'set nor1' 20292 Let the assembler to generate warnings if the source program uses 20293 r1. (Default) 20294 20295'.sdata' 20296 Tell the assembler to add subsequent data into the sdata section 20297 20298'.rdata' 20299 Tell the assembler to add subsequent data into the rdata section 20300 20301'.frame "frame-register", "offset", "return-pc-register"' 20302 Describe a stack frame. "frame-register" is the frame register, 20303 "offset" is the distance from the frame register to the virtual 20304 frame pointer, "return-pc-register" is the return program register. 20305 You must use ".ent" before ".frame" and only one ".frame" can be 20306 used per ".ent". 20307 20308'.mask "bitmask", "frameoffset"' 20309 Indicate which of the integer registers are saved in the current 20310 function's stack frame, this is for the debugger to explain the 20311 frame chain. 20312 20313'.ent "proc-name"' 20314 Set the beginning of the procedure "proc_name". Use this directive 20315 when you want to generate information for the debugger. 20316 20317'.end proc-name' 20318 Set the end of a procedure. Use this directive to generate 20319 information for the debugger. 20320 20321'.bss' 20322 Switch the destination of following statements into the bss 20323 section, which is used for data that is uninitialized anywhere. 20324 20325 20326File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent 20327 203289.42.3 SCORE Syntax 20329------------------- 20330 20331* Menu: 20332 20333* SCORE-Chars:: Special Characters 20334 20335 20336File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax 20337 203389.42.3.1 Special Characters 20339........................... 20340 20341The presence of a '#' appearing anywhere on a line indicates the start 20342of a comment that extends to the end of that line. 20343 20344 If a '#' appears as the first character of a line then the whole line 20345is treated as a comment, but in this case the line can also be a logical 20346line number directive (*note Comments::) or a preprocessor control 20347command (*note Preprocessing::). 20348 20349 The ';' character can be used to separate statements on the same 20350line. 20351 20352 20353File: as.info, Node: SH-Dependent, Next: Sparc-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 20354 203559.43 Renesas / SuperH SH Dependent Features 20356=========================================== 20357 20358* Menu: 20359 20360* SH Options:: Options 20361* SH Syntax:: Syntax 20362* SH Floating Point:: Floating Point 20363* SH Directives:: SH Machine Directives 20364* SH Opcodes:: Opcodes 20365 20366 20367File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 20368 203699.43.1 Options 20370-------------- 20371 20372'as' has following command-line options for the Renesas (formerly 20373Hitachi) / SuperH SH family. 20374 20375'--little' 20376 Generate little endian code. 20377 20378'--big' 20379 Generate big endian code. 20380 20381'--relax' 20382 Alter jump instructions for long displacements. 20383 20384'--small' 20385 Align sections to 4 byte boundaries, not 16. 20386 20387'--dsp' 20388 Enable sh-dsp insns, and disable sh3e / sh4 insns. 20389 20390'--renesas' 20391 Disable optimization with section symbol for compatibility with 20392 Renesas assembler. 20393 20394'--allow-reg-prefix' 20395 Allow '$' as a register name prefix. 20396 20397'--fdpic' 20398 Generate an FDPIC object file. 20399 20400'--isa=sh4 | sh4a' 20401 Specify the sh4 or sh4a instruction set. 20402'--isa=dsp' 20403 Enable sh-dsp insns, and disable sh3e / sh4 insns. 20404'--isa=fp' 20405 Enable sh2e, sh3e, sh4, and sh4a insn sets. 20406'--isa=all' 20407 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 20408 20409'-h-tick-hex' 20410 Support H'00 style hex constants in addition to 0x00 style. 20411 20412 20413File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 20414 204159.43.2 Syntax 20416------------- 20417 20418* Menu: 20419 20420* SH-Chars:: Special Characters 20421* SH-Regs:: Register Names 20422* SH-Addressing:: Addressing Modes 20423 20424 20425File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 20426 204279.43.2.1 Special Characters 20428........................... 20429 20430'!' is the line comment character. 20431 20432 You can use ';' instead of a newline to separate statements. 20433 20434 If a '#' appears as the first character of a line then the whole line 20435is treated as a comment, but in this case the line could also be a 20436logical line number directive (*note Comments::) or a preprocessor 20437control command (*note Preprocessing::). 20438 20439 Since '$' has no special meaning, you may use it in symbol names. 20440 20441 20442File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 20443 204449.43.2.2 Register Names 20445....................... 20446 20447You can use the predefined symbols 'r0', 'r1', 'r2', 'r3', 'r4', 'r5', 20448'r6', 'r7', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', and 'r15' to 20449refer to the SH registers. 20450 20451 The SH also has these control registers: 20452 20453'pr' 20454 procedure register (holds return address) 20455 20456'pc' 20457 program counter 20458 20459'mach' 20460'macl' 20461 high and low multiply accumulator registers 20462 20463'sr' 20464 status register 20465 20466'gbr' 20467 global base register 20468 20469'vbr' 20470 vector base register (for interrupt vectors) 20471 20472 20473File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 20474 204759.43.2.3 Addressing Modes 20476......................... 20477 20478'as' understands the following addressing modes for the SH. 'RN' in the 20479following refers to any of the numbered registers, but _not_ the control 20480registers. 20481 20482'RN' 20483 Register direct 20484 20485'@RN' 20486 Register indirect 20487 20488'@-RN' 20489 Register indirect with pre-decrement 20490 20491'@RN+' 20492 Register indirect with post-increment 20493 20494'@(DISP, RN)' 20495 Register indirect with displacement 20496 20497'@(R0, RN)' 20498 Register indexed 20499 20500'@(DISP, GBR)' 20501 'GBR' offset 20502 20503'@(R0, GBR)' 20504 GBR indexed 20505 20506'ADDR' 20507'@(DISP, PC)' 20508 PC relative address (for branch or for addressing memory). The 20509 'as' implementation allows you to use the simpler form ADDR 20510 anywhere a PC relative address is called for; the alternate form is 20511 supported for compatibility with other assemblers. 20512 20513'#IMM' 20514 Immediate data 20515 20516 20517File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 20518 205199.43.3 Floating Point 20520--------------------- 20521 20522SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 20523SH groups can use '.float' directive to generate IEEE floating-point 20524numbers. 20525 20526 SH2E and SH3E support single-precision floating point calculations as 20527well as entirely PCAPI compatible emulation of double-precision floating 20528point calculations. SH2E and SH3E instructions are a subset of the 20529floating point calculations conforming to the IEEE754 standard. 20530 20531 In addition to single-precision and double-precision floating-point 20532operation capability, the on-chip FPU of SH4 has a 128-bit graphic 20533engine that enables 32-bit floating-point data to be processed 128 bits 20534at a time. It also supports 4 * 4 array operations and inner product 20535operations. Also, a superscalar architecture is employed that enables 20536simultaneous execution of two instructions (including FPU instructions), 20537providing performance of up to twice that of conventional architectures 20538at the same frequency. 20539 20540 20541File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 20542 205439.43.4 SH Machine Directives 20544---------------------------- 20545 20546'uaword' 20547'ualong' 20548'uaquad' 20549 'as' will issue a warning when a misaligned '.word', '.long', or 20550 '.quad' directive is used. You may use '.uaword', '.ualong', or 20551 '.uaquad' to indicate that the value is intentionally misaligned. 20552 20553 20554File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 20555 205569.43.5 Opcodes 20557-------------- 20558 20559For detailed information on the SH machine instruction set, see 20560'SH-Microcomputer User's Manual' (Renesas) or 'SH-4 32-bit CPU Core 20561Architecture' (SuperH) and 'SuperH (SH) 64-Bit RISC Series' (SuperH). 20562 20563 'as' implements all the standard SH opcodes. No additional 20564pseudo-instructions are needed on this family. Note, however, that 20565because 'as' supports a simpler form of PC-relative addressing, you may 20566simply write (for example) 20567 20568 mov.l bar,r0 20569 20570where other assemblers might require an explicit displacement to 'bar' 20571from the program counter: 20572 20573 mov.l @(DISP, PC) 20574 20575 Here is a summary of SH opcodes: 20576 20577 Legend: 20578 Rn a numbered register 20579 Rm another numbered register 20580 #imm immediate data 20581 disp displacement 20582 disp8 8-bit displacement 20583 disp12 12-bit displacement 20584 20585 add #imm,Rn lds.l @Rn+,PR 20586 add Rm,Rn mac.w @Rm+,@Rn+ 20587 addc Rm,Rn mov #imm,Rn 20588 addv Rm,Rn mov Rm,Rn 20589 and #imm,R0 mov.b Rm,@(R0,Rn) 20590 and Rm,Rn mov.b Rm,@-Rn 20591 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 20592 bf disp8 mov.b @(disp,Rm),R0 20593 bra disp12 mov.b @(disp,GBR),R0 20594 bsr disp12 mov.b @(R0,Rm),Rn 20595 bt disp8 mov.b @Rm+,Rn 20596 clrmac mov.b @Rm,Rn 20597 clrt mov.b R0,@(disp,Rm) 20598 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 20599 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 20600 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 20601 cmp/gt Rm,Rn mov.l Rm,@-Rn 20602 cmp/hi Rm,Rn mov.l Rm,@Rn 20603 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 20604 cmp/pl Rn mov.l @(disp,GBR),R0 20605 cmp/pz Rn mov.l @(disp,PC),Rn 20606 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 20607 div0s Rm,Rn mov.l @Rm+,Rn 20608 div0u mov.l @Rm,Rn 20609 div1 Rm,Rn mov.l R0,@(disp,GBR) 20610 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 20611 exts.w Rm,Rn mov.w Rm,@-Rn 20612 extu.b Rm,Rn mov.w Rm,@Rn 20613 extu.w Rm,Rn mov.w @(disp,Rm),R0 20614 jmp @Rn mov.w @(disp,GBR),R0 20615 jsr @Rn mov.w @(disp,PC),Rn 20616 ldc Rn,GBR mov.w @(R0,Rm),Rn 20617 ldc Rn,SR mov.w @Rm+,Rn 20618 ldc Rn,VBR mov.w @Rm,Rn 20619 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 20620 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 20621 ldc.l @Rn+,VBR mova @(disp,PC),R0 20622 lds Rn,MACH movt Rn 20623 lds Rn,MACL muls Rm,Rn 20624 lds Rn,PR mulu Rm,Rn 20625 lds.l @Rn+,MACH neg Rm,Rn 20626 lds.l @Rn+,MACL negc Rm,Rn 20627 nop stc VBR,Rn 20628 not Rm,Rn stc.l GBR,@-Rn 20629 or #imm,R0 stc.l SR,@-Rn 20630 or Rm,Rn stc.l VBR,@-Rn 20631 or.b #imm,@(R0,GBR) sts MACH,Rn 20632 rotcl Rn sts MACL,Rn 20633 rotcr Rn sts PR,Rn 20634 rotl Rn sts.l MACH,@-Rn 20635 rotr Rn sts.l MACL,@-Rn 20636 rte sts.l PR,@-Rn 20637 rts sub Rm,Rn 20638 sett subc Rm,Rn 20639 shal Rn subv Rm,Rn 20640 shar Rn swap.b Rm,Rn 20641 shll Rn swap.w Rm,Rn 20642 shll16 Rn tas.b @Rn 20643 shll2 Rn trapa #imm 20644 shll8 Rn tst #imm,R0 20645 shlr Rn tst Rm,Rn 20646 shlr16 Rn tst.b #imm,@(R0,GBR) 20647 shlr2 Rn xor #imm,R0 20648 shlr8 Rn xor Rm,Rn 20649 sleep xor.b #imm,@(R0,GBR) 20650 stc GBR,Rn xtrct Rm,Rn 20651 stc SR,Rn 20652 20653 20654File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 20655 206569.44 SPARC Dependent Features 20657============================= 20658 20659* Menu: 20660 20661* Sparc-Opts:: Options 20662* Sparc-Aligned-Data:: Option to enforce aligned data 20663* Sparc-Syntax:: Syntax 20664* Sparc-Float:: Floating Point 20665* Sparc-Directives:: Sparc Machine Directives 20666 20667 20668File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 20669 206709.44.1 Options 20671-------------- 20672 20673The SPARC chip family includes several successive versions, using the 20674same core instruction set, but including a few additional instructions 20675at each version. There are exceptions to this however. For details on 20676what instructions each variant supports, please see the chip's 20677architecture reference manual. 20678 20679 By default, 'as' assumes the core instruction set (SPARC v6), but 20680"bumps" the architecture level as needed: it switches to successively 20681higher architectures as it encounters instructions that only exist in 20682the higher levels. 20683 20684 If not configured for SPARC v9 ('sparc64-*-*') GAS will not bump past 20685sparclite by default, an option must be passed to enable the v9 20686instructions. 20687 20688 GAS treats sparclite as being compatible with v8, unless an 20689architecture is explicitly requested. SPARC v9 is always incompatible 20690with sparclite. 20691 20692'-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite' 20693'-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |' 20694'-Av8plusv | -Av8plusm | -Av8plusm8' 20695'-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8' 20696'-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima' 20697'-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6' 20698 Use one of the '-A' options to select one of the SPARC 20699 architectures explicitly. If you select an architecture 20700 explicitly, 'as' reports a fatal error if it encounters an 20701 instruction or feature requiring an incompatible or higher level. 20702 20703 '-Av8plus', '-Av8plusa', '-Av8plusb', '-Av8plusc', '-Av8plusd', and 20704 '-Av8plusv' select a 32 bit environment. 20705 20706 '-Av9', '-Av9a', '-Av9b', '-Av9c', '-Av9d', '-Av9e', '-Av9v' and 20707 '-Av9m' select a 64 bit environment and are not available unless 20708 GAS is explicitly configured with 64 bit environment support. 20709 20710 '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with 20711 UltraSPARC VIS 1.0 extensions. 20712 20713 '-Av8plusb' and '-Av9b' enable the UltraSPARC VIS 2.0 instructions, 20714 as well as the instructions enabled by '-Av8plusa' and '-Av9a'. 20715 20716 '-Av8plusc' and '-Av9c' enable the UltraSPARC Niagara instructions, 20717 as well as the instructions enabled by '-Av8plusb' and '-Av9b'. 20718 20719 '-Av8plusd' and '-Av9d' enable the floating point fused 20720 multiply-add, VIS 3.0, and HPC extension instructions, as well as 20721 the instructions enabled by '-Av8plusc' and '-Av9c'. 20722 20723 '-Av8pluse' and '-Av9e' enable the cryptographic instructions, as 20724 well as the instructions enabled by '-Av8plusd' and '-Av9d'. 20725 20726 '-Av8plusv' and '-Av9v' enable floating point unfused multiply-add, 20727 and integer multiply-add, as well as the instructions enabled by 20728 '-Av8pluse' and '-Av9e'. 20729 20730 '-Av8plusm' and '-Av9m' enable the VIS 4.0, subtract extended, 20731 xmpmul, xmontmul and xmontsqr instructions, as well as the 20732 instructions enabled by '-Av8plusv' and '-Av9v'. 20733 20734 '-Av8plusm8' and '-Av9m8' enable the instructions introduced in the 20735 Oracle SPARC Architecture 2017 and the M8 processor, as well as the 20736 instructions enabled by '-Av8plusm' and '-Av9m'. 20737 20738 '-Asparc' specifies a v9 environment. It is equivalent to '-Av9' 20739 if the word size is 64-bit, and '-Av8plus' otherwise. 20740 20741 '-Asparcvis' specifies a v9a environment. It is equivalent to 20742 '-Av9a' if the word size is 64-bit, and '-Av8plusa' otherwise. 20743 20744 '-Asparcvis2' specifies a v9b environment. It is equivalent to 20745 '-Av9b' if the word size is 64-bit, and '-Av8plusb' otherwise. 20746 20747 '-Asparcfmaf' specifies a v9b environment with the floating point 20748 fused multiply-add instructions enabled. 20749 20750 '-Asparcima' specifies a v9b environment with the integer 20751 multiply-add instructions enabled. 20752 20753 '-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC , 20754 and floating point fused multiply-add instructions enabled. 20755 20756 '-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC, 20757 and floating point unfused multiply-add instructions enabled. 20758 20759 '-Asparc5' is equivalent to '-Av9m'. 20760 20761 '-Asparc6' is equivalent to '-Av9m8'. 20762 20763'-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc' 20764'-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |' 20765'-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b' 20766'-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v' 20767'-xarch=v9m | -xarch=v9m8' 20768'-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2' 20769'-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3' 20770'-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6' 20771 For compatibility with the SunOS v9 assembler. These options are 20772 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, 20773 -Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, 20774 -Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2, 20775 -Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and 20776 -Asparc6 respectively. 20777 20778'-bump' 20779 Warn whenever it is necessary to switch to another level. If an 20780 architecture level is explicitly requested, GAS will not issue 20781 warnings until that level is reached, and will then bump the level 20782 as required (except between incompatible levels). 20783 20784'-32 | -64' 20785 Select the word size, either 32 bits or 64 bits. These options are 20786 only available with the ELF object file format, and require that 20787 the necessary BFD support has been included. 20788 20789'--dcti-couples-detect' 20790 Warn if a DCTI (delayed control transfer instruction) couple is 20791 found when generating code for a variant of the SPARC architecture 20792 in which the execution of the couple is unpredictable, or very 20793 slow. This is disabled by default. 20794 20795 20796File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent 20797 207989.44.2 Enforcing aligned data 20799----------------------------- 20800 20801SPARC GAS normally permits data to be misaligned. For example, it 20802permits the '.long' pseudo-op to be used on a byte boundary. However, 20803the native SunOS assemblers issue an error when they see misaligned 20804data. 20805 20806 You can use the '--enforce-aligned-data' option to make SPARC GAS 20807also issue an error about misaligned data, just as the SunOS assemblers 20808do. 20809 20810 The '--enforce-aligned-data' option is not the default because gcc 20811issues misaligned data pseudo-ops when it initializes certain packed 20812data structures (structures defined using the 'packed' attribute). You 20813may have to assemble with GAS in order to initialize packed data 20814structures in your own code. 20815 20816 20817File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 20818 208199.44.3 Sparc Syntax 20820------------------- 20821 20822The assembler syntax closely follows The Sparc Architecture Manual, 20823versions 8 and 9, as well as most extensions defined by Sun for their 20824UltraSPARC and Niagara line of processors. 20825 20826* Menu: 20827 20828* Sparc-Chars:: Special Characters 20829* Sparc-Regs:: Register Names 20830* Sparc-Constants:: Constant Names 20831* Sparc-Relocs:: Relocations 20832* Sparc-Size-Translations:: Size Translations 20833 20834 20835File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 20836 208379.44.3.1 Special Characters 20838........................... 20839 20840A '!' character appearing anywhere on a line indicates the start of a 20841comment that extends to the end of that line. 20842 20843 If a '#' appears as the first character of a line then the whole line 20844is treated as a comment, but in this case the line could also be a 20845logical line number directive (*note Comments::) or a preprocessor 20846control command (*note Preprocessing::). 20847 20848 ';' can be used instead of a newline to separate statements. 20849 20850 20851File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax 20852 208539.44.3.2 Register Names 20854....................... 20855 20856The Sparc integer register file is broken down into global, outgoing, 20857local, and incoming. 20858 20859 * The 8 global registers are referred to as '%gN'. 20860 20861 * The 8 outgoing registers are referred to as '%oN'. 20862 20863 * The 8 local registers are referred to as '%lN'. 20864 20865 * The 8 incoming registers are referred to as '%iN'. 20866 20867 * The frame pointer register '%i6' can be referenced using the alias 20868 '%fp'. 20869 20870 * The stack pointer register '%o6' can be referenced using the alias 20871 '%sp'. 20872 20873 Floating point registers are simply referred to as '%fN'. When 20874assembling for pre-V9, only 32 floating point registers are available. 20875For V9 and later there are 64, but there are restrictions when 20876referencing the upper 32 registers. They can only be accessed as double 20877or quad, and thus only even or quad numbered accesses are allowed. For 20878example, '%f34' is a legal floating point register, but '%f35' is not. 20879 20880 Floating point registers accessed as double can also be referred 20881using the '%dN' notation, where N is even. Similarly, floating point 20882registers accessed as quad can be referred using the '%qN' notation, 20883where N is a multiple of 4. For example, '%f4' can be denoted as both 20884'%d4' and '%q4'. On the other hand, '%f2' can be denoted as '%d2' but 20885not as '%q2'. 20886 20887 Certain V9 instructions allow access to ancillary state registers. 20888Most simply they can be referred to as '%asrN' where N can be from 16 to 2088931. However, there are some aliases defined to reference ASR registers 20890defined for various UltraSPARC processors: 20891 20892 * The tick compare register is referred to as '%tick_cmpr'. 20893 20894 * The system tick register is referred to as '%stick'. An alias, 20895 '%sys_tick', exists but is deprecated and should not be used by new 20896 software. 20897 20898 * The system tick compare register is referred to as '%stick_cmpr'. 20899 An alias, '%sys_tick_cmpr', exists but is deprecated and should not 20900 be used by new software. 20901 20902 * The software interrupt register is referred to as '%softint'. 20903 20904 * The set software interrupt register is referred to as 20905 '%set_softint'. The mnemonic '%softint_set' is provided as an 20906 alias. 20907 20908 * The clear software interrupt register is referred to as 20909 '%clear_softint'. The mnemonic '%softint_clear' is provided as an 20910 alias. 20911 20912 * The performance instrumentation counters register is referred to as 20913 '%pic'. 20914 20915 * The performance control register is referred to as '%pcr'. 20916 20917 * The graphics status register is referred to as '%gsr'. 20918 20919 * The V9 dispatch control register is referred to as '%dcr'. 20920 20921 Various V9 branch and conditional move instructions allow 20922specification of which set of integer condition codes to test. These 20923are referred to as '%xcc' and '%icc'. 20924 20925 Additionally, GAS supports the so-called "natural" condition codes; 20926these are referred to as '%ncc' and reference to '%icc' if the word size 20927is 32, '%xcc' if the word size is 64. 20928 20929 In V9, there are 4 sets of floating point condition codes which are 20930referred to as '%fccN'. 20931 20932 Several special privileged and non-privileged registers exist: 20933 20934 * The V9 address space identifier register is referred to as '%asi'. 20935 20936 * The V9 restorable windows register is referred to as '%canrestore'. 20937 20938 * The V9 savable windows register is referred to as '%cansave'. 20939 20940 * The V9 clean windows register is referred to as '%cleanwin'. 20941 20942 * The V9 current window pointer register is referred to as '%cwp'. 20943 20944 * The floating-point queue register is referred to as '%fq'. 20945 20946 * The V8 co-processor queue register is referred to as '%cq'. 20947 20948 * The floating point status register is referred to as '%fsr'. 20949 20950 * The other windows register is referred to as '%otherwin'. 20951 20952 * The V9 program counter register is referred to as '%pc'. 20953 20954 * The V9 next program counter register is referred to as '%npc'. 20955 20956 * The V9 processor interrupt level register is referred to as '%pil'. 20957 20958 * The V9 processor state register is referred to as '%pstate'. 20959 20960 * The trap base address register is referred to as '%tba'. 20961 20962 * The V9 tick register is referred to as '%tick'. 20963 20964 * The V9 trap level is referred to as '%tl'. 20965 20966 * The V9 trap program counter is referred to as '%tpc'. 20967 20968 * The V9 trap next program counter is referred to as '%tnpc'. 20969 20970 * The V9 trap state is referred to as '%tstate'. 20971 20972 * The V9 trap type is referred to as '%tt'. 20973 20974 * The V9 condition codes is referred to as '%ccr'. 20975 20976 * The V9 floating-point registers state is referred to as '%fprs'. 20977 20978 * The V9 version register is referred to as '%ver'. 20979 20980 * The V9 window state register is referred to as '%wstate'. 20981 20982 * The Y register is referred to as '%y'. 20983 20984 * The V8 window invalid mask register is referred to as '%wim'. 20985 20986 * The V8 processor state register is referred to as '%psr'. 20987 20988 * The V9 global register level register is referred to as '%gl'. 20989 20990 Several special register names exist for hypervisor mode code: 20991 20992 * The hyperprivileged processor state register is referred to as 20993 '%hpstate'. 20994 20995 * The hyperprivileged trap state register is referred to as 20996 '%htstate'. 20997 20998 * The hyperprivileged interrupt pending register is referred to as 20999 '%hintp'. 21000 21001 * The hyperprivileged trap base address register is referred to as 21002 '%htba'. 21003 21004 * The hyperprivileged implementation version register is referred to 21005 as '%hver'. 21006 21007 * The hyperprivileged system tick offset register is referred to as 21008 '%hstick_offset'. Note that there is no '%hstick' register, the 21009 normal '%stick' is used. 21010 21011 * The hyperprivileged system tick enable register is referred to as 21012 '%hstick_enable'. 21013 21014 * The hyperprivileged system tick compare register is referred to as 21015 '%hstick_cmpr'. 21016 21017 21018File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax 21019 210209.44.3.3 Constants 21021.................. 21022 21023Several Sparc instructions take an immediate operand field for which 21024mnemonic names exist. Two such examples are 'membar' and 'prefetch'. 21025Another example are the set of V9 memory access instruction that allow 21026specification of an address space identifier. 21027 21028 The 'membar' instruction specifies a memory barrier that is the 21029defined by the operand which is a bitmask. The supported mask mnemonics 21030are: 21031 21032 * '#Sync' requests that all operations (including nonmemory reference 21033 operations) appearing prior to the 'membar' must have been 21034 performed and the effects of any exceptions become visible before 21035 any instructions after the 'membar' may be initiated. This 21036 corresponds to 'membar' cmask field bit 2. 21037 21038 * '#MemIssue' requests that all memory reference operations appearing 21039 prior to the 'membar' must have been performed before any memory 21040 operation after the 'membar' may be initiated. This corresponds to 21041 'membar' cmask field bit 1. 21042 21043 * '#Lookaside' requests that a store appearing prior to the 'membar' 21044 must complete before any load following the 'membar' referencing 21045 the same address can be initiated. This corresponds to 'membar' 21046 cmask field bit 0. 21047 21048 * '#StoreStore' defines that the effects of all stores appearing 21049 prior to the 'membar' instruction must be visible to all processors 21050 before the effect of any stores following the 'membar'. Equivalent 21051 to the deprecated 'stbar' instruction. This corresponds to 21052 'membar' mmask field bit 3. 21053 21054 * '#LoadStore' defines all loads appearing prior to the 'membar' 21055 instruction must have been performed before the effect of any 21056 stores following the 'membar' is visible to any other processor. 21057 This corresponds to 'membar' mmask field bit 2. 21058 21059 * '#StoreLoad' defines that the effects of all stores appearing prior 21060 to the 'membar' instruction must be visible to all processors 21061 before loads following the 'membar' may be performed. This 21062 corresponds to 'membar' mmask field bit 1. 21063 21064 * '#LoadLoad' defines that all loads appearing prior to the 'membar' 21065 instruction must have been performed before any loads following the 21066 'membar' may be performed. This corresponds to 'membar' mmask 21067 field bit 0. 21068 21069 These values can be ored together, for example: 21070 21071 membar #Sync 21072 membar #StoreLoad | #LoadLoad 21073 membar #StoreLoad | #StoreStore 21074 21075 The 'prefetch' and 'prefetcha' instructions take a prefetch function 21076code. The following prefetch function code constant mnemonics are 21077available: 21078 21079 * '#n_reads' requests a prefetch for several reads, and corresponds 21080 to a prefetch function code of 0. 21081 21082 '#one_read' requests a prefetch for one read, and corresponds to a 21083 prefetch function code of 1. 21084 21085 '#n_writes' requests a prefetch for several writes (and possibly 21086 reads), and corresponds to a prefetch function code of 2. 21087 21088 '#one_write' requests a prefetch for one write, and corresponds to 21089 a prefetch function code of 3. 21090 21091 '#page' requests a prefetch page, and corresponds to a prefetch 21092 function code of 4. 21093 21094 '#invalidate' requests a prefetch invalidate, and corresponds to a 21095 prefetch function code of 16. 21096 21097 '#unified' requests a prefetch to the nearest unified cache, and 21098 corresponds to a prefetch function code of 17. 21099 21100 '#n_reads_strong' requests a strong prefetch for several reads, and 21101 corresponds to a prefetch function code of 20. 21102 21103 '#one_read_strong' requests a strong prefetch for one read, and 21104 corresponds to a prefetch function code of 21. 21105 21106 '#n_writes_strong' requests a strong prefetch for several writes, 21107 and corresponds to a prefetch function code of 22. 21108 21109 '#one_write_strong' requests a strong prefetch for one write, and 21110 corresponds to a prefetch function code of 23. 21111 21112 Onle one prefetch code may be specified. Here are some examples: 21113 21114 prefetch [%l0 + %l2], #one_read 21115 prefetch [%g2 + 8], #n_writes 21116 prefetcha [%g1] 0x8, #unified 21117 prefetcha [%o0 + 0x10] %asi, #n_reads 21118 21119 The actual behavior of a given prefetch function code is processor 21120 specific. If a processor does not implement a given prefetch 21121 function code, it will treat the prefetch instruction as a nop. 21122 21123 For instructions that accept an immediate address space identifier, 21124 'as' provides many mnemonics corresponding to V9 defined as well as 21125 UltraSPARC and Niagara extended values. For example, '#ASI_P' and 21126 '#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor specific 21127 manuals for details. 21128 21129 21130File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax 21131 211329.44.3.4 Relocations 21133.................... 21134 21135ELF relocations are available as defined in the 32-bit and 64-bit Sparc 21136ELF specifications. 21137 21138 'R_SPARC_HI22' is obtained using '%hi' and 'R_SPARC_LO10' is obtained 21139using '%lo'. Likewise 'R_SPARC_HIX22' is obtained from '%hix' and 21140'R_SPARC_LOX10' is obtained using '%lox'. For example: 21141 21142 sethi %hi(symbol), %g1 21143 or %g1, %lo(symbol), %g1 21144 21145 sethi %hix(symbol), %g1 21146 xor %g1, %lox(symbol), %g1 21147 21148 These "high" mnemonics extract bits 31:10 of their operand, and the 21149"low" mnemonics extract bits 9:0 of their operand. 21150 21151 V9 code model relocations can be requested as follows: 21152 21153 * 'R_SPARC_HH22' is requested using '%hh'. It can also be generated 21154 using '%uhi'. 21155 * 'R_SPARC_HM10' is requested using '%hm'. It can also be generated 21156 using '%ulo'. 21157 * 'R_SPARC_LM22' is requested using '%lm'. 21158 21159 * 'R_SPARC_H44' is requested using '%h44'. 21160 * 'R_SPARC_M44' is requested using '%m44'. 21161 * 'R_SPARC_L44' is requested using '%l44' or '%l34'. 21162 * 'R_SPARC_H34' is requested using '%h34'. 21163 21164 The '%l34' generates a 'R_SPARC_L44' relocation because it calculates 21165the necessary value, and therefore no explicit 'R_SPARC_L34' relocation 21166needed to be created for this purpose. 21167 21168 The '%h34' and '%l34' relocations are used for the abs34 code model. 21169Here is an example abs34 address generation sequence: 21170 21171 sethi %h34(symbol), %g1 21172 sllx %g1, 2, %g1 21173 or %g1, %l34(symbol), %g1 21174 21175 The PC relative relocation 'R_SPARC_PC22' can be obtained by 21176enclosing an operand inside of '%pc22'. Likewise, the 'R_SPARC_PC10' 21177relocation can be obtained using '%pc10'. These are mostly used when 21178assembling PIC code. For example, the standard PIC sequence on Sparc to 21179get the base of the global offset table, PC relative, into a register, 21180can be performed as: 21181 21182 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 21183 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 21184 21185 Several relocations exist to allow the link editor to potentially 21186optimize GOT data references. The 'R_SPARC_GOTDATA_OP_HIX22' relocation 21187can obtained by enclosing an operand inside of '%gdop_hix22'. The 21188'R_SPARC_GOTDATA_OP_LOX10' relocation can obtained by enclosing an 21189operand inside of '%gdop_lox10'. Likewise, 'R_SPARC_GOTDATA_OP' can be 21190obtained by enclosing an operand inside of '%gdop'. For example, 21191assuming the GOT base is in register '%l7': 21192 21193 sethi %gdop_hix22(symbol), %l1 21194 xor %l1, %gdop_lox10(symbol), %l1 21195 ld [%l7 + %l1], %l2, %gdop(symbol) 21196 21197 There are many relocations that can be requested for access to thread 21198local storage variables. All of the Sparc TLS mnemonics are supported: 21199 21200 * 'R_SPARC_TLS_GD_HI22' is requested using '%tgd_hi22'. 21201 * 'R_SPARC_TLS_GD_LO10' is requested using '%tgd_lo10'. 21202 * 'R_SPARC_TLS_GD_ADD' is requested using '%tgd_add'. 21203 * 'R_SPARC_TLS_GD_CALL' is requested using '%tgd_call'. 21204 21205 * 'R_SPARC_TLS_LDM_HI22' is requested using '%tldm_hi22'. 21206 * 'R_SPARC_TLS_LDM_LO10' is requested using '%tldm_lo10'. 21207 * 'R_SPARC_TLS_LDM_ADD' is requested using '%tldm_add'. 21208 * 'R_SPARC_TLS_LDM_CALL' is requested using '%tldm_call'. 21209 21210 * 'R_SPARC_TLS_LDO_HIX22' is requested using '%tldo_hix22'. 21211 * 'R_SPARC_TLS_LDO_LOX10' is requested using '%tldo_lox10'. 21212 * 'R_SPARC_TLS_LDO_ADD' is requested using '%tldo_add'. 21213 21214 * 'R_SPARC_TLS_IE_HI22' is requested using '%tie_hi22'. 21215 * 'R_SPARC_TLS_IE_LO10' is requested using '%tie_lo10'. 21216 * 'R_SPARC_TLS_IE_LD' is requested using '%tie_ld'. 21217 * 'R_SPARC_TLS_IE_LDX' is requested using '%tie_ldx'. 21218 * 'R_SPARC_TLS_IE_ADD' is requested using '%tie_add'. 21219 21220 * 'R_SPARC_TLS_LE_HIX22' is requested using '%tle_hix22'. 21221 * 'R_SPARC_TLS_LE_LOX10' is requested using '%tle_lox10'. 21222 21223 Here are some example TLS model sequences. 21224 21225 First, General Dynamic: 21226 21227 sethi %tgd_hi22(symbol), %l1 21228 add %l1, %tgd_lo10(symbol), %l1 21229 add %l7, %l1, %o0, %tgd_add(symbol) 21230 call __tls_get_addr, %tgd_call(symbol) 21231 nop 21232 21233 Local Dynamic: 21234 21235 sethi %tldm_hi22(symbol), %l1 21236 add %l1, %tldm_lo10(symbol), %l1 21237 add %l7, %l1, %o0, %tldm_add(symbol) 21238 call __tls_get_addr, %tldm_call(symbol) 21239 nop 21240 21241 sethi %tldo_hix22(symbol), %l1 21242 xor %l1, %tldo_lox10(symbol), %l1 21243 add %o0, %l1, %l1, %tldo_add(symbol) 21244 21245 Initial Exec: 21246 21247 sethi %tie_hi22(symbol), %l1 21248 add %l1, %tie_lo10(symbol), %l1 21249 ld [%l7 + %l1], %o0, %tie_ld(symbol) 21250 add %g7, %o0, %o0, %tie_add(symbol) 21251 21252 sethi %tie_hi22(symbol), %l1 21253 add %l1, %tie_lo10(symbol), %l1 21254 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) 21255 add %g7, %o0, %o0, %tie_add(symbol) 21256 21257 And finally, Local Exec: 21258 21259 sethi %tle_hix22(symbol), %l1 21260 add %l1, %tle_lox10(symbol), %l1 21261 add %g7, %l1, %l1 21262 21263 When assembling for 64-bit, and a secondary constant addend is 21264specified in an address expression that would normally generate an 21265'R_SPARC_LO10' relocation, the assembler will emit an 'R_SPARC_OLO10' 21266instead. 21267 21268 21269File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax 21270 212719.44.3.5 Size Translations 21272.......................... 21273 21274Often it is desirable to write code in an operand size agnostic manner. 21275'as' provides support for this via operand size opcode translations. 21276Translations are supported for loads, stores, shifts, compare-and-swap 21277atomics, and the 'clr' synthetic instruction. 21278 21279 If generating 32-bit code, 'as' will generate the 32-bit opcode. 21280Whereas if 64-bit code is being generated, the 64-bit opcode will be 21281emitted. For example 'ldn' will be transformed into 'ld' for 32-bit 21282code and 'ldx' for 64-bit code. 21283 21284 Here is an example meant to demonstrate all the supported opcode 21285translations: 21286 21287 ldn [%o0], %o1 21288 ldna [%o0] %asi, %o2 21289 stn %o1, [%o0] 21290 stna %o2, [%o0] %asi 21291 slln %o3, 3, %o3 21292 srln %o4, 8, %o4 21293 sran %o5, 12, %o5 21294 casn [%o0], %o1, %o2 21295 casna [%o0] %asi, %o1, %o2 21296 clrn %g1 21297 21298 In 32-bit mode 'as' will emit: 21299 21300 ld [%o0], %o1 21301 lda [%o0] %asi, %o2 21302 st %o1, [%o0] 21303 sta %o2, [%o0] %asi 21304 sll %o3, 3, %o3 21305 srl %o4, 8, %o4 21306 sra %o5, 12, %o5 21307 cas [%o0], %o1, %o2 21308 casa [%o0] %asi, %o1, %o2 21309 clr %g1 21310 21311 And in 64-bit mode 'as' will emit: 21312 21313 ldx [%o0], %o1 21314 ldxa [%o0] %asi, %o2 21315 stx %o1, [%o0] 21316 stxa %o2, [%o0] %asi 21317 sllx %o3, 3, %o3 21318 srlx %o4, 8, %o4 21319 srax %o5, 12, %o5 21320 casx [%o0], %o1, %o2 21321 casxa [%o0] %asi, %o1, %o2 21322 clrx %g1 21323 21324 Finally, the '.nword' translating directive is supported as well. It 21325is documented in the section on Sparc machine directives. 21326 21327 21328File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent 21329 213309.44.4 Floating Point 21331--------------------- 21332 21333The Sparc uses IEEE floating-point numbers. 21334 21335 21336File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 21337 213389.44.5 Sparc Machine Directives 21339------------------------------- 21340 21341The Sparc version of 'as' supports the following additional machine 21342directives: 21343 21344'.align' 21345 This must be followed by the desired alignment in bytes. 21346 21347'.common' 21348 This must be followed by a symbol name, a positive number, and 21349 '"bss"'. This behaves somewhat like '.comm', but the syntax is 21350 different. 21351 21352'.half' 21353 This is functionally identical to '.short'. 21354 21355'.nword' 21356 On the Sparc, the '.nword' directive produces native word sized 21357 value, ie. if assembling with -32 it is equivalent to '.word', if 21358 assembling with -64 it is equivalent to '.xword'. 21359 21360'.proc' 21361 This directive is ignored. Any text following it on the same line 21362 is also ignored. 21363 21364'.register' 21365 This directive declares use of a global application or system 21366 register. It must be followed by a register name %g2, %g3, %g6 or 21367 %g7, comma and the symbol name for that register. If symbol name 21368 is '#scratch', it is a scratch register, if it is '#ignore', it 21369 just suppresses any errors about using undeclared global register, 21370 but does not emit any information about it into the object file. 21371 This can be useful e.g. if you save the register before use and 21372 restore it after. 21373 21374'.reserve' 21375 This must be followed by a symbol name, a positive number, and 21376 '"bss"'. This behaves somewhat like '.lcomm', but the syntax is 21377 different. 21378 21379'.seg' 21380 This must be followed by '"text"', '"data"', or '"data1"'. It 21381 behaves like '.text', '.data', or '.data 1'. 21382 21383'.skip' 21384 This is functionally identical to the '.space' directive. 21385 21386'.word' 21387 On the Sparc, the '.word' directive produces 32 bit values, instead 21388 of the 16 bit values it produces on many other machines. 21389 21390'.xword' 21391 On the Sparc V9 processor, the '.xword' directive produces 64 bit 21392 values. 21393 21394 21395File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 21396 213979.45 TIC54X Dependent Features 21398============================== 21399 21400* Menu: 21401 21402* TIC54X-Opts:: Command-line Options 21403* TIC54X-Block:: Blocking 21404* TIC54X-Env:: Environment Settings 21405* TIC54X-Constants:: Constants Syntax 21406* TIC54X-Subsyms:: String Substitution 21407* TIC54X-Locals:: Local Label Syntax 21408* TIC54X-Builtins:: Builtin Assembler Math Functions 21409* TIC54X-Ext:: Extended Addressing Support 21410* TIC54X-Directives:: Directives 21411* TIC54X-Macros:: Macro Features 21412* TIC54X-MMRegs:: Memory-mapped Registers 21413* TIC54X-Syntax:: Syntax 21414 21415 21416File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 21417 214189.45.1 Options 21419-------------- 21420 21421The TMS320C54X version of 'as' has a few machine-dependent options. 21422 21423 You can use the '-mfar-mode' option to enable extended addressing 21424mode. All addresses will be assumed to be > 16 bits, and the 21425appropriate relocation types will be used. This option is equivalent to 21426using the '.far_mode' directive in the assembly code. If you do not use 21427the '-mfar-mode' option, all references will be assumed to be 16 bits. 21428This option may be abbreviated to '-mf'. 21429 21430 You can use the '-mcpu' option to specify a particular CPU. This 21431option is equivalent to using the '.version' directive in the assembly 21432code. For recognized CPU codes, see *Note '.version': 21433TIC54X-Directives. The default CPU version is '542'. 21434 21435 You can use the '-merrors-to-file' option to redirect error output to 21436a file (this provided for those deficient environments which don't 21437provide adequate output redirection). This option may be abbreviated to 21438'-me'. 21439 21440 21441File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 21442 214439.45.2 Blocking 21444--------------- 21445 21446A blocked section or memory block is guaranteed not to cross the 21447blocking boundary (usually a page, or 128 words) if it is smaller than 21448the blocking size, or to start on a page boundary if it is larger than 21449the blocking size. 21450 21451 21452File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 21453 214549.45.3 Environment Settings 21455--------------------------- 21456 21457'C54XDSP_DIR' and 'A_DIR' are semicolon-separated paths which are added 21458to the list of directories normally searched for source and include 21459files. 'C54XDSP_DIR' will override 'A_DIR'. 21460 21461 21462File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 21463 214649.45.4 Constants Syntax 21465----------------------- 21466 21467The TIC54X version of 'as' allows the following additional constant 21468formats, using a suffix to indicate the radix: 21469 21470 Binary 000000B, 011000b 21471 Octal 10Q, 224q 21472 Hexadecimal 45h, 0FH 21473 21474 21475 21476File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 21477 214789.45.5 String Substitution 21479-------------------------- 21480 21481A subset of allowable symbols (which we'll call subsyms) may be assigned 21482arbitrary string values. This is roughly equivalent to C preprocessor 21483#define macros. When 'as' encounters one of these symbols, the symbol 21484is replaced in the input stream by its string value. Subsym names 21485*must* begin with a letter. 21486 21487 Subsyms may be defined using the '.asg' and '.eval' directives (*Note 21488'.asg': TIC54X-Directives, *Note '.eval': TIC54X-Directives. 21489 21490 Expansion is recursive until a previously encountered symbol is seen, 21491at which point substitution stops. 21492 21493 In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, 21494and SYM1 is replaced with x. At this point, x has already been 21495encountered and the substitution stops. 21496 21497 .asg "x",SYM1 21498 .asg "SYM1",SYM2 21499 .asg "SYM2",x 21500 add x,a ; final code assembled is "add x, a" 21501 21502 Macro parameters are converted to subsyms; a side effect of this is 21503the normal 'as' '\ARG' dereferencing syntax is unnecessary. Subsyms 21504defined within a macro will have global scope, unless the '.var' 21505directive is used to identify the subsym as a local macro variable *note 21506'.var': TIC54X-Directives. 21507 21508 Substitution may be forced in situations where replacement might be 21509ambiguous by placing colons on either side of the subsym. The following 21510code: 21511 21512 .eval "10",x 21513 LAB:X: add #x, a 21514 21515 When assembled becomes: 21516 21517 LAB10 add #10, a 21518 21519 Smaller parts of the string assigned to a subsym may be accessed with 21520the following syntax: 21521 21522':SYMBOL(CHAR_INDEX):' 21523 Evaluates to a single-character string, the character at 21524 CHAR_INDEX. 21525':SYMBOL(START,LENGTH):' 21526 Evaluates to a substring of SYMBOL beginning at START with length 21527 LENGTH. 21528 21529 21530File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 21531 215329.45.6 Local Labels 21533------------------- 21534 21535Local labels may be defined in two ways: 21536 21537 * $N, where N is a decimal number between 0 and 9 21538 * LABEL?, where LABEL is any legal symbol name. 21539 21540 Local labels thus defined may be redefined or automatically 21541generated. The scope of a local label is based on when it may be 21542undefined or reset. This happens when one of the following situations 21543is encountered: 21544 21545 * .newblock directive *note '.newblock': TIC54X-Directives. 21546 * The current section is changed (.sect, .text, or .data) 21547 * Entering or leaving an included file 21548 * The macro scope where the label was defined is exited 21549 21550 21551File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 21552 215539.45.7 Math Builtins 21554-------------------- 21555 21556The following built-in functions may be used to generate a 21557floating-point value. All return a floating-point value except '$cvi', 21558'$int', and '$sgn', which return an integer value. 21559 21560'$acos(EXPR)' 21561 Returns the floating point arccosine of EXPR. 21562 21563'$asin(EXPR)' 21564 Returns the floating point arcsine of EXPR. 21565 21566'$atan(EXPR)' 21567 Returns the floating point arctangent of EXPR. 21568 21569'$atan2(EXPR1,EXPR2)' 21570 Returns the floating point arctangent of EXPR1 / EXPR2. 21571 21572'$ceil(EXPR)' 21573 Returns the smallest integer not less than EXPR as floating point. 21574 21575'$cosh(EXPR)' 21576 Returns the floating point hyperbolic cosine of EXPR. 21577 21578'$cos(EXPR)' 21579 Returns the floating point cosine of EXPR. 21580 21581'$cvf(EXPR)' 21582 Returns the integer value EXPR converted to floating-point. 21583 21584'$cvi(EXPR)' 21585 Returns the floating point value EXPR converted to integer. 21586 21587'$exp(EXPR)' 21588 Returns the floating point value e ^ EXPR. 21589 21590'$fabs(EXPR)' 21591 Returns the floating point absolute value of EXPR. 21592 21593'$floor(EXPR)' 21594 Returns the largest integer that is not greater than EXPR as 21595 floating point. 21596 21597'$fmod(EXPR1,EXPR2)' 21598 Returns the floating point remainder of EXPR1 / EXPR2. 21599 21600'$int(EXPR)' 21601 Returns 1 if EXPR evaluates to an integer, zero otherwise. 21602 21603'$ldexp(EXPR1,EXPR2)' 21604 Returns the floating point value EXPR1 * 2 ^ EXPR2. 21605 21606'$log10(EXPR)' 21607 Returns the base 10 logarithm of EXPR. 21608 21609'$log(EXPR)' 21610 Returns the natural logarithm of EXPR. 21611 21612'$max(EXPR1,EXPR2)' 21613 Returns the floating point maximum of EXPR1 and EXPR2. 21614 21615'$min(EXPR1,EXPR2)' 21616 Returns the floating point minimum of EXPR1 and EXPR2. 21617 21618'$pow(EXPR1,EXPR2)' 21619 Returns the floating point value EXPR1 ^ EXPR2. 21620 21621'$round(EXPR)' 21622 Returns the nearest integer to EXPR as a floating point number. 21623 21624'$sgn(EXPR)' 21625 Returns -1, 0, or 1 based on the sign of EXPR. 21626 21627'$sin(EXPR)' 21628 Returns the floating point sine of EXPR. 21629 21630'$sinh(EXPR)' 21631 Returns the floating point hyperbolic sine of EXPR. 21632 21633'$sqrt(EXPR)' 21634 Returns the floating point square root of EXPR. 21635 21636'$tan(EXPR)' 21637 Returns the floating point tangent of EXPR. 21638 21639'$tanh(EXPR)' 21640 Returns the floating point hyperbolic tangent of EXPR. 21641 21642'$trunc(EXPR)' 21643 Returns the integer value of EXPR truncated towards zero as 21644 floating point. 21645 21646 21647File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 21648 216499.45.8 Extended Addressing 21650-------------------------- 21651 21652The 'LDX' pseudo-op is provided for loading the extended addressing bits 21653of a label or address. For example, if an address '_label' resides in 21654extended program memory, the value of '_label' may be loaded as follows: 21655 ldx #_label,16,a ; loads extended bits of _label 21656 or #_label,a ; loads lower 16 bits of _label 21657 bacc a ; full address is in accumulator A 21658 21659 21660File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 21661 216629.45.9 Directives 21663----------------- 21664 21665'.align [SIZE]' 21666'.even' 21667 Align the section program counter on the next boundary, based on 21668 SIZE. SIZE may be any power of 2. '.even' is equivalent to 21669 '.align' with a SIZE of 2. 21670 '1' 21671 Align SPC to word boundary 21672 '2' 21673 Align SPC to longword boundary (same as .even) 21674 '128' 21675 Align SPC to page boundary 21676 21677'.asg STRING, NAME' 21678 Assign NAME the string STRING. String replacement is performed on 21679 STRING before assignment. 21680 21681'.eval STRING, NAME' 21682 Evaluate the contents of string STRING and assign the result as a 21683 string to the subsym NAME. String replacement is performed on 21684 STRING before assignment. 21685 21686'.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 21687 Reserve space for SYMBOL in the .bss section. SIZE is in words. 21688 If present, BLOCKING_FLAG indicates the allocated space should be 21689 aligned on a page boundary if it would otherwise cross a page 21690 boundary. If present, ALIGNMENT_FLAG causes the assembler to 21691 allocate SIZE on a long word boundary. 21692 21693'.byte VALUE [,...,VALUE_N]' 21694'.ubyte VALUE [,...,VALUE_N]' 21695'.char VALUE [,...,VALUE_N]' 21696'.uchar VALUE [,...,VALUE_N]' 21697 Place one or more bytes into consecutive words of the current 21698 section. The upper 8 bits of each word is zero-filled. If a label 21699 is used, it points to the word allocated for the first byte 21700 encountered. 21701 21702'.clink ["SECTION_NAME"]' 21703 Set STYP_CLINK flag for this section, which indicates to the linker 21704 that if no symbols from this section are referenced, the section 21705 should not be included in the link. If SECTION_NAME is omitted, 21706 the current section is used. 21707 21708'.c_mode' 21709 TBD. 21710 21711'.copy "FILENAME" | FILENAME' 21712'.include "FILENAME" | FILENAME' 21713 Read source statements from FILENAME. The normal include search 21714 path is used. Normally .copy will cause statements from the 21715 included file to be printed in the assembly listing and .include 21716 will not, but this distinction is not currently implemented. 21717 21718'.data' 21719 Begin assembling code into the .data section. 21720 21721'.double VALUE [,...,VALUE_N]' 21722'.ldouble VALUE [,...,VALUE_N]' 21723'.float VALUE [,...,VALUE_N]' 21724'.xfloat VALUE [,...,VALUE_N]' 21725 Place an IEEE single-precision floating-point representation of one 21726 or more floating-point values into the current section. All but 21727 '.xfloat' align the result on a longword boundary. Values are 21728 stored most-significant word first. 21729 21730'.drlist' 21731'.drnolist' 21732 Control printing of directives to the listing file. Ignored. 21733 21734'.emsg STRING' 21735'.mmsg STRING' 21736'.wmsg STRING' 21737 Emit a user-defined error, message, or warning, respectively. 21738 21739'.far_mode' 21740 Use extended addressing when assembling statements. This should 21741 appear only once per file, and is equivalent to the -mfar-mode 21742 option *note '-mfar-mode': TIC54X-Opts. 21743 21744'.fclist' 21745'.fcnolist' 21746 Control printing of false conditional blocks to the listing file. 21747 21748'.field VALUE [,SIZE]' 21749 Initialize a bitfield of SIZE bits in the current section. If 21750 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 21751 bits. If VALUE does not fit into SIZE bits, the value will be 21752 truncated. Successive '.field' directives will pack starting at 21753 the current word, filling the most significant bits first, and 21754 aligning to the start of the next word if the field size does not 21755 fit into the space remaining in the current word. A '.align' 21756 directive with an operand of 1 will force the next '.field' 21757 directive to begin packing into a new word. If a label is used, it 21758 points to the word that contains the specified field. 21759 21760'.global SYMBOL [,...,SYMBOL_N]' 21761'.def SYMBOL [,...,SYMBOL_N]' 21762'.ref SYMBOL [,...,SYMBOL_N]' 21763 '.def' nominally identifies a symbol defined in the current file 21764 and available to other files. '.ref' identifies a symbol used in 21765 the current file but defined elsewhere. Both map to the standard 21766 '.global' directive. 21767 21768'.half VALUE [,...,VALUE_N]' 21769'.uhalf VALUE [,...,VALUE_N]' 21770'.short VALUE [,...,VALUE_N]' 21771'.ushort VALUE [,...,VALUE_N]' 21772'.int VALUE [,...,VALUE_N]' 21773'.uint VALUE [,...,VALUE_N]' 21774'.word VALUE [,...,VALUE_N]' 21775'.uword VALUE [,...,VALUE_N]' 21776 Place one or more values into consecutive words of the current 21777 section. If a label is used, it points to the word allocated for 21778 the first value encountered. 21779 21780'.label SYMBOL' 21781 Define a special SYMBOL to refer to the load time address of the 21782 current section program counter. 21783 21784'.length' 21785'.width' 21786 Set the page length and width of the output listing file. Ignored. 21787 21788'.list' 21789'.nolist' 21790 Control whether the source listing is printed. Ignored. 21791 21792'.long VALUE [,...,VALUE_N]' 21793'.ulong VALUE [,...,VALUE_N]' 21794'.xlong VALUE [,...,VALUE_N]' 21795 Place one or more 32-bit values into consecutive words in the 21796 current section. The most significant word is stored first. 21797 '.long' and '.ulong' align the result on a longword boundary; 21798 'xlong' does not. 21799 21800'.loop [COUNT]' 21801'.break [CONDITION]' 21802'.endloop' 21803 Repeatedly assemble a block of code. '.loop' begins the block, and 21804 '.endloop' marks its termination. COUNT defaults to 1024, and 21805 indicates the number of times the block should be repeated. 21806 '.break' terminates the loop so that assembly begins after the 21807 '.endloop' directive. The optional CONDITION will cause the loop 21808 to terminate only if it evaluates to zero. 21809 21810'MACRO_NAME .macro [PARAM1][,...PARAM_N]' 21811'[.mexit]' 21812'.endm' 21813 See the section on macros for more explanation (*Note 21814 TIC54X-Macros::. 21815 21816'.mlib "FILENAME" | FILENAME' 21817 Load the macro library FILENAME. FILENAME must be an archived 21818 library (BFD ar-compatible) of text files, expected to contain only 21819 macro definitions. The standard include search path is used. 21820 21821'.mlist' 21822'.mnolist' 21823 Control whether to include macro and loop block expansions in the 21824 listing output. Ignored. 21825 21826'.mmregs' 21827 Define global symbolic names for the 'c54x registers. Supposedly 21828 equivalent to executing '.set' directives for each register with 21829 its memory-mapped value, but in reality is provided only for 21830 compatibility and does nothing. 21831 21832'.newblock' 21833 This directive resets any TIC54X local labels currently defined. 21834 Normal 'as' local labels are unaffected. 21835 21836'.option OPTION_LIST' 21837 Set listing options. Ignored. 21838 21839'.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' 21840 Designate SECTION_NAME for blocking. Blocking guarantees that a 21841 section will start on a page boundary (128 words) if it would 21842 otherwise cross a page boundary. Only initialized sections may be 21843 designated with this directive. See also *Note TIC54X-Block::. 21844 21845'.sect "SECTION_NAME"' 21846 Define a named initialized section and make it the current section. 21847 21848'SYMBOL .set "VALUE"' 21849'SYMBOL .equ "VALUE"' 21850 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 21851 table. SYMBOL may not be previously defined. 21852 21853'.space SIZE_IN_BITS' 21854'.bes SIZE_IN_BITS' 21855 Reserve the given number of bits in the current section and 21856 zero-fill them. If a label is used with '.space', it points to the 21857 *first* word reserved. With '.bes', the label points to the *last* 21858 word reserved. 21859 21860'.sslist' 21861'.ssnolist' 21862 Controls the inclusion of subsym replacement in the listing output. 21863 Ignored. 21864 21865'.string "STRING" [,...,"STRING_N"]' 21866'.pstring "STRING" [,...,"STRING_N"]' 21867 Place 8-bit characters from STRING into the current section. 21868 '.string' zero-fills the upper 8 bits of each word, while 21869 '.pstring' puts two characters into each word, filling the 21870 most-significant bits first. Unused space is zero-filled. If a 21871 label is used, it points to the first word initialized. 21872 21873'[STAG] .struct [OFFSET]' 21874'[NAME_1] element [COUNT_1]' 21875'[NAME_2] element [COUNT_2]' 21876'[TNAME] .tag STAGX [TCOUNT]' 21877'...' 21878'[NAME_N] element [COUNT_N]' 21879'[SSIZE] .endstruct' 21880'LABEL .tag [STAG]' 21881 Assign symbolic offsets to the elements of a structure. STAG 21882 defines a symbol to use to reference the structure. OFFSET 21883 indicates a starting value to use for the first element 21884 encountered; otherwise it defaults to zero. Each element can have 21885 a named offset, NAME, which is a symbol assigned the value of the 21886 element's offset into the structure. If STAG is missing, these 21887 become global symbols. COUNT adjusts the offset that many times, 21888 as if 'element' were an array. 'element' may be one of '.byte', 21889 '.word', '.long', '.float', or any equivalent of those, and the 21890 structure offset is adjusted accordingly. '.field' and '.string' 21891 are also allowed; the size of '.field' is one bit, and '.string' is 21892 considered to be one word in size. Only element descriptors, 21893 structure/union tags, '.align' and conditional assembly directives 21894 are allowed within '.struct'/'.endstruct'. '.align' aligns member 21895 offsets to word boundaries only. SSIZE, if provided, will always 21896 be assigned the size of the structure. 21897 21898 The '.tag' directive, in addition to being used to define a 21899 structure/union element within a structure, may be used to apply a 21900 structure to a symbol. Once applied to LABEL, the individual 21901 structure elements may be applied to LABEL to produce the desired 21902 offsets using LABEL as the structure base. 21903 21904'.tab' 21905 Set the tab size in the output listing. Ignored. 21906 21907'[UTAG] .union' 21908'[NAME_1] element [COUNT_1]' 21909'[NAME_2] element [COUNT_2]' 21910'[TNAME] .tag UTAGX[,TCOUNT]' 21911'...' 21912'[NAME_N] element [COUNT_N]' 21913'[USIZE] .endstruct' 21914'LABEL .tag [UTAG]' 21915 Similar to '.struct', but the offset after each element is reset to 21916 zero, and the USIZE is set to the maximum of all defined elements. 21917 Starting offset for the union is always zero. 21918 21919'[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 21920 Reserve space for variables in a named, uninitialized section 21921 (similar to .bss). '.usect' allows definitions sections 21922 independent of .bss. SYMBOL points to the first location reserved 21923 by this allocation. The symbol may be used as a variable name. 21924 SIZE is the allocated size in words. BLOCKING_FLAG indicates 21925 whether to block this section on a page boundary (128 words) (*note 21926 TIC54X-Block::). ALIGNMENT FLAG indicates whether the section 21927 should be longword-aligned. 21928 21929'.var SYM[,..., SYM_N]' 21930 Define a subsym to be a local variable within a macro. See *Note 21931 TIC54X-Macros::. 21932 21933'.version VERSION' 21934 Set which processor to build instructions for. Though the 21935 following values are accepted, the op is ignored. 21936 '541' 21937 '542' 21938 '543' 21939 '545' 21940 '545LP' 21941 '546LP' 21942 '548' 21943 '549' 21944 21945 21946File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 21947 219489.45.10 Macros 21949-------------- 21950 21951Macros do not require explicit dereferencing of arguments (i.e., \ARG). 21952 21953 During macro expansion, the macro parameters are converted to 21954subsyms. If the number of arguments passed the macro invocation exceeds 21955the number of parameters defined, the last parameter is assigned the 21956string equivalent of all remaining arguments. If fewer arguments are 21957given than parameters, the missing parameters are assigned empty 21958strings. To include a comma in an argument, you must enclose the 21959argument in quotes. 21960 21961 The following built-in subsym functions allow examination of the 21962string value of subsyms (or ordinary strings). The arguments are 21963strings unless otherwise indicated (subsyms passed as args will be 21964replaced by the strings they represent). 21965'$symlen(STR)' 21966 Returns the length of STR. 21967 21968'$symcmp(STR1,STR2)' 21969 Returns 0 if STR1 == STR2, non-zero otherwise. 21970 21971'$firstch(STR,CH)' 21972 Returns index of the first occurrence of character constant CH in 21973 STR. 21974 21975'$lastch(STR,CH)' 21976 Returns index of the last occurrence of character constant CH in 21977 STR. 21978 21979'$isdefed(SYMBOL)' 21980 Returns zero if the symbol SYMBOL is not in the symbol table, 21981 non-zero otherwise. 21982 21983'$ismember(SYMBOL,LIST)' 21984 Assign the first member of comma-separated string LIST to SYMBOL; 21985 LIST is reassigned the remainder of the list. Returns zero if LIST 21986 is a null string. Both arguments must be subsyms. 21987 21988'$iscons(EXPR)' 21989 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 4 21990 if a character, 5 if decimal, and zero if not an integer. 21991 21992'$isname(NAME)' 21993 Returns 1 if NAME is a valid symbol name, zero otherwise. 21994 21995'$isreg(REG)' 21996 Returns 1 if REG is a valid predefined register name (AR0-AR7 21997 only). 21998 21999'$structsz(STAG)' 22000 Returns the size of the structure or union represented by STAG. 22001 22002'$structacc(STAG)' 22003 Returns the reference point of the structure or union represented 22004 by STAG. Always returns zero. 22005 22006 22007File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent 22008 220099.45.11 Memory-mapped Registers 22010------------------------------- 22011 22012The following symbols are recognized as memory-mapped registers: 22013 22014 22015File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent 22016 220179.45.12 TIC54X Syntax 22018--------------------- 22019 22020* Menu: 22021 22022* TIC54X-Chars:: Special Characters 22023 22024 22025File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax 22026 220279.45.12.1 Special Characters 22028............................ 22029 22030The presence of a ';' appearing anywhere on a line indicates the start 22031of a comment that extends to the end of that line. 22032 22033 If a '#' appears as the first character of a line then the whole line 22034is treated as a comment, but in this case the line can also be a logical 22035line number directive (*note Comments::) or a preprocessor control 22036command (*note Preprocessing::). 22037 22038 The presence of an asterisk ('*') at the start of a line also 22039indicates a comment that extends to the end of that line. 22040 22041 The TIC54X assembler does not currently support a line separator 22042character. 22043 22044 22045File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 22046 220479.46 TIC6X Dependent Features 22048============================= 22049 22050* Menu: 22051 22052* TIC6X Options:: Options 22053* TIC6X Syntax:: Syntax 22054* TIC6X Directives:: Directives 22055 22056 22057File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 22058 220599.46.1 TIC6X Options 22060-------------------- 22061 22062'-march=ARCH' 22063 Enable (only) instructions from architecture ARCH. By default, all 22064 instructions are permitted. 22065 22066 The following values of ARCH are accepted: 'c62x', 'c64x', 'c64x+', 22067 'c67x', 'c67x+', 'c674x'. 22068 22069'-mdsbt' 22070'-mno-dsbt' 22071 The '-mdsbt' option causes the assembler to generate the 22072 'Tag_ABI_DSBT' attribute with a value of 1, indicating that the 22073 code is using DSBT addressing. The '-mno-dsbt' option, the 22074 default, causes the tag to have a value of 0, indicating that the 22075 code does not use DSBT addressing. The linker will emit a warning 22076 if objects of different type (DSBT and non-DSBT) are linked 22077 together. 22078 22079'-mpid=no' 22080'-mpid=near' 22081'-mpid=far' 22082 The '-mpid=' option causes the assembler to generate the 22083 'Tag_ABI_PID' attribute with a value indicating the form of data 22084 addressing used by the code. '-mpid=no', the default, indicates 22085 position-dependent data addressing, '-mpid=near' indicates 22086 position-independent addressing with GOT accesses using near DP 22087 addressing, and '-mpid=far' indicates position-independent 22088 addressing with GOT accesses using far DP addressing. The linker 22089 will emit a warning if objects built with different settings of 22090 this option are linked together. 22091 22092'-mpic' 22093'-mno-pic' 22094 The '-mpic' option causes the assembler to generate the 22095 'Tag_ABI_PIC' attribute with a value of 1, indicating that the code 22096 is using position-independent code addressing, The '-mno-pic' 22097 option, the default, causes the tag to have a value of 0, 22098 indicating position-dependent code addressing. The linker will 22099 emit a warning if objects of different type (position-dependent and 22100 position-independent) are linked together. 22101 22102'-mbig-endian' 22103'-mlittle-endian' 22104 Generate code for the specified endianness. The default is 22105 little-endian. 22106 22107 22108File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 22109 221109.46.2 TIC6X Syntax 22111------------------- 22112 22113The presence of a ';' on a line indicates the start of a comment that 22114extends to the end of the current line. If a '#' or '*' appears as the 22115first character of a line, the whole line is treated as a comment. Note 22116that if a line starts with a '#' character then it can also be a logical 22117line number directive (*note Comments::) or a preprocessor control 22118command (*note Preprocessing::). 22119 22120 The '@' character can be used instead of a newline to separate 22121statements. 22122 22123 Instruction, register and functional unit names are case-insensitive. 22124'as' requires fully-specified functional unit names, such as '.S1', 22125'.L1X' or '.D1T2', on all instructions using a functional unit. 22126 22127 For some instructions, there may be syntactic ambiguity between 22128register or functional unit names and the names of labels or other 22129symbols. To avoid this, enclose the ambiguous symbol name in 22130parentheses; register and functional unit names may not be enclosed in 22131parentheses. 22132 22133 22134File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent 22135 221369.46.3 TIC6X Directives 22137----------------------- 22138 22139Directives controlling the set of instructions accepted by the assembler 22140have effect for instructions between the directive and any subsequent 22141directive overriding it. 22142 22143'.arch ARCH' 22144 This has the same effect as '-march=ARCH'. 22145 22146'.cantunwind' 22147 Prevents unwinding through the current function. No personality 22148 routine or exception table data is required or permitted. 22149 22150 If this is not specified then frame unwinding information will be 22151 constructed from CFI directives. *note CFI directives::. 22152 22153'.c6xabi_attribute TAG, VALUE' 22154 Set the C6000 EABI build attribute TAG to VALUE. 22155 22156 The TAG is either an attribute number or one of 'Tag_ISA', 22157 'Tag_ABI_wchar_t', 'Tag_ABI_stack_align_needed', 22158 'Tag_ABI_stack_align_preserved', 'Tag_ABI_DSBT', 'Tag_ABI_PID', 22159 'Tag_ABI_PIC', 'TAG_ABI_array_object_alignment', 22160 'TAG_ABI_array_object_align_expected', 'Tag_ABI_compatibility' and 22161 'Tag_ABI_conformance'. The VALUE is either a 'number', '"string"', 22162 or 'number, "string"' depending on the tag. 22163 22164'.ehtype SYMBOL' 22165 Output an exception type table reference to SYMBOL. 22166 22167'.endp' 22168 Marks the end of and exception table or function. If preceded by a 22169 '.handlerdata' directive then this also switched back to the 22170 previous text section. 22171 22172'.handlerdata' 22173 Marks the end of the current function, and the start of the 22174 exception table entry for that function. Anything between this 22175 directive and the '.endp' directive will be added to the exception 22176 table entry. 22177 22178 Must be preceded by a CFI block containing a '.cfi_lsda' directive. 22179 22180'.nocmp' 22181 Disallow use of C64x+ compact instructions in the current text 22182 section. 22183 22184'.personalityindex INDEX' 22185 Sets the personality routine for the current function to the ABI 22186 specified compact routine number INDEX 22187 22188'.personality NAME' 22189 Sets the personality routine for the current function to NAME. 22190 22191'.scomm SYMBOL, SIZE, ALIGN' 22192 Like '.comm', creating a common symbol SYMBOL with size SIZE and 22193 alignment ALIGN, but unlike when using '.comm', this symbol will be 22194 placed into the small BSS section by the linker. 22195 22196 22197File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies 22198 221999.47 TILE-Gx Dependent Features 22200=============================== 22201 22202* Menu: 22203 22204* TILE-Gx Options:: TILE-Gx Options 22205* TILE-Gx Syntax:: TILE-Gx Syntax 22206* TILE-Gx Directives:: TILE-Gx Directives 22207 22208 22209File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent 22210 222119.47.1 Options 22212-------------- 22213 22214The following table lists all available TILE-Gx specific options: 22215 22216'-m32 | -m64' 22217 Select the word size, either 32 bits or 64 bits. 22218 22219'-EB | -EL' 22220 Select the endianness, either big-endian (-EB) or little-endian 22221 (-EL). 22222 22223 22224File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent 22225 222269.47.2 Syntax 22227------------- 22228 22229Block comments are delimited by '/*' and '*/'. End of line comments may 22230be introduced by '#'. 22231 22232 Instructions consist of a leading opcode or macro name followed by 22233whitespace and an optional comma-separated list of operands: 22234 22235 OPCODE [OPERAND, ...] 22236 22237 Instructions must be separated by a newline or semicolon. 22238 22239 There are two ways to write code: either write naked instructions, 22240which the assembler is free to combine into VLIW bundles, or specify the 22241VLIW bundles explicitly. 22242 22243 Bundles are specified using curly braces: 22244 22245 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 22246 22247 A bundle can span multiple lines. If you want to put multiple 22248instructions on a line, whether in a bundle or not, you need to separate 22249them with semicolons as in this example. 22250 22251 A bundle may contain one or more instructions, up to the limit 22252specified by the ISA (currently three). If fewer instructions are 22253specified than the hardware supports in a bundle, the assembler inserts 22254'fnop' instructions automatically. 22255 22256 The assembler will prefer to preserve the ordering of instructions 22257within the bundle, putting the first instruction in a lower-numbered 22258pipeline than the next one, etc. This fact, combined with the optional 22259use of explicit 'fnop' or 'nop' instructions, allows precise control 22260over which pipeline executes each instruction. 22261 22262 If the instructions cannot be bundled in the listed order, the 22263assembler will automatically try to find a valid pipeline assignment. 22264If there is no way to bundle the instructions together, the assembler 22265reports an error. 22266 22267 The assembler does not yet auto-bundle (automatically combine 22268multiple instructions into one bundle), but it reserves the right to do 22269so in the future. If you want to force an instruction to run by itself, 22270put it in a bundle explicitly with curly braces and use 'nop' 22271instructions (not 'fnop') to fill the remaining pipeline slots in that 22272bundle. 22273 22274* Menu: 22275 22276* TILE-Gx Opcodes:: Opcode Naming Conventions. 22277* TILE-Gx Registers:: Register Naming. 22278* TILE-Gx Modifiers:: Symbolic Operand Modifiers. 22279 22280 22281File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax 22282 222839.47.2.1 Opcode Names 22284..................... 22285 22286For a complete list of opcodes and descriptions of their semantics, see 22287'TILE-Gx Instruction Set Architecture', available upon request at 22288www.tilera.com. 22289 22290 22291File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax 22292 222939.47.2.2 Register Names 22294....................... 22295 22296General-purpose registers are represented by predefined symbols of the 22297form 'rN', where N represents a number between '0' and '63'. However, 22298the following registers have canonical names that must be used instead: 22299 22300'r54' 22301 sp 22302 22303'r55' 22304 lr 22305 22306'r56' 22307 sn 22308 22309'r57' 22310 idn0 22311 22312'r58' 22313 idn1 22314 22315'r59' 22316 udn0 22317 22318'r60' 22319 udn1 22320 22321'r61' 22322 udn2 22323 22324'r62' 22325 udn3 22326 22327'r63' 22328 zero 22329 22330 The assembler will emit a warning if a numeric name is used instead 22331of the non-numeric name. The '.no_require_canonical_reg_names' 22332assembler pseudo-op turns off this warning. 22333'.require_canonical_reg_names' turns it back on. 22334 22335 22336File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax 22337 223389.47.2.3 Symbolic Operand Modifiers 22339................................... 22340 22341The assembler supports several modifiers when using symbol addresses in 22342TILE-Gx instruction operands. The general syntax is the following: 22343 22344 modifier(symbol) 22345 22346 The following modifiers are supported: 22347 22348'hw0' 22349 22350 This modifier is used to load bits 0-15 of the symbol's address. 22351 22352'hw1' 22353 22354 This modifier is used to load bits 16-31 of the symbol's address. 22355 22356'hw2' 22357 22358 This modifier is used to load bits 32-47 of the symbol's address. 22359 22360'hw3' 22361 22362 This modifier is used to load bits 48-63 of the symbol's address. 22363 22364'hw0_last' 22365 22366 This modifier yields the same value as 'hw0', but it also checks 22367 that the value does not overflow. 22368 22369'hw1_last' 22370 22371 This modifier yields the same value as 'hw1', but it also checks 22372 that the value does not overflow. 22373 22374'hw2_last' 22375 22376 This modifier yields the same value as 'hw2', but it also checks 22377 that the value does not overflow. 22378 22379 A 48-bit symbolic value is constructed by using the following 22380 idiom: 22381 22382 moveli r0, hw2_last(sym) 22383 shl16insli r0, r0, hw1(sym) 22384 shl16insli r0, r0, hw0(sym) 22385 22386'hw0_got' 22387 22388 This modifier is used to load bits 0-15 of the symbol's offset in 22389 the GOT entry corresponding to the symbol. 22390 22391'hw0_last_got' 22392 22393 This modifier yields the same value as 'hw0_got', but it also 22394 checks that the value does not overflow. 22395 22396'hw1_last_got' 22397 22398 This modifier is used to load bits 16-31 of the symbol's offset in 22399 the GOT entry corresponding to the symbol, and it also checks that 22400 the value does not overflow. 22401 22402'plt' 22403 22404 This modifier is used for function symbols. It causes a _procedure 22405 linkage table_, an array of code stubs, to be created at the time 22406 the shared object is created or linked against, together with a 22407 global offset table entry. The value is a pc-relative offset to 22408 the corresponding stub code in the procedure linkage table. This 22409 arrangement causes the run-time symbol resolver to be called to 22410 look up and set the value of the symbol the first time the function 22411 is called (at latest; depending environment variables). It is only 22412 safe to leave the symbol unresolved this way if all references are 22413 function calls. 22414 22415'hw0_plt' 22416 22417 This modifier is used to load bits 0-15 of the pc-relative address 22418 of a plt entry. 22419 22420'hw1_plt' 22421 22422 This modifier is used to load bits 16-31 of the pc-relative address 22423 of a plt entry. 22424 22425'hw1_last_plt' 22426 22427 This modifier yields the same value as 'hw1_plt', but it also 22428 checks that the value does not overflow. 22429 22430'hw2_last_plt' 22431 22432 This modifier is used to load bits 32-47 of the pc-relative address 22433 of a plt entry, and it also checks that the value does not 22434 overflow. 22435 22436'hw0_tls_gd' 22437 22438 This modifier is used to load bits 0-15 of the offset of the GOT 22439 entry of the symbol's TLS descriptor, to be used for 22440 general-dynamic TLS accesses. 22441 22442'hw0_last_tls_gd' 22443 22444 This modifier yields the same value as 'hw0_tls_gd', but it also 22445 checks that the value does not overflow. 22446 22447'hw1_last_tls_gd' 22448 22449 This modifier is used to load bits 16-31 of the offset of the GOT 22450 entry of the symbol's TLS descriptor, to be used for 22451 general-dynamic TLS accesses. It also checks that the value does 22452 not overflow. 22453 22454'hw0_tls_ie' 22455 22456 This modifier is used to load bits 0-15 of the offset of the GOT 22457 entry containing the offset of the symbol's address from the TCB, 22458 to be used for initial-exec TLS accesses. 22459 22460'hw0_last_tls_ie' 22461 22462 This modifier yields the same value as 'hw0_tls_ie', but it also 22463 checks that the value does not overflow. 22464 22465'hw1_last_tls_ie' 22466 22467 This modifier is used to load bits 16-31 of the offset of the GOT 22468 entry containing the offset of the symbol's address from the TCB, 22469 to be used for initial-exec TLS accesses. It also checks that the 22470 value does not overflow. 22471 22472'hw0_tls_le' 22473 22474 This modifier is used to load bits 0-15 of the offset of the 22475 symbol's address from the TCB, to be used for local-exec TLS 22476 accesses. 22477 22478'hw0_last_tls_le' 22479 22480 This modifier yields the same value as 'hw0_tls_le', but it also 22481 checks that the value does not overflow. 22482 22483'hw1_last_tls_le' 22484 22485 This modifier is used to load bits 16-31 of the offset of the 22486 symbol's address from the TCB, to be used for local-exec TLS 22487 accesses. It also checks that the value does not overflow. 22488 22489'tls_gd_call' 22490 22491 This modifier is used to tag an instruction as the "call" part of a 22492 calling sequence for a TLS GD reference of its operand. 22493 22494'tls_gd_add' 22495 22496 This modifier is used to tag an instruction as the "add" part of a 22497 calling sequence for a TLS GD reference of its operand. 22498 22499'tls_ie_load' 22500 22501 This modifier is used to tag an instruction as the "load" part of a 22502 calling sequence for a TLS IE reference of its operand. 22503 22504 22505File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent 22506 225079.47.3 TILE-Gx Directives 22508------------------------- 22509 22510'.align EXPRESSION [, EXPRESSION]' 22511 This is the generic .ALIGN directive. The first argument is the 22512 requested alignment in bytes. 22513 22514'.allow_suspicious_bundles' 22515 Turns on error checking for combinations of instructions in a 22516 bundle that probably indicate a programming error. This is on by 22517 default. 22518 22519'.no_allow_suspicious_bundles' 22520 Turns off error checking for combinations of instructions in a 22521 bundle that probably indicate a programming error. 22522 22523'.require_canonical_reg_names' 22524 Require that canonical register names be used, and emit a warning 22525 if the numeric names are used. This is on by default. 22526 22527'.no_require_canonical_reg_names' 22528 Permit the use of numeric names for registers that have canonical 22529 names. 22530 22531 22532File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies 22533 225349.48 TILEPro Dependent Features 22535=============================== 22536 22537* Menu: 22538 22539* TILEPro Options:: TILEPro Options 22540* TILEPro Syntax:: TILEPro Syntax 22541* TILEPro Directives:: TILEPro Directives 22542 22543 22544File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent 22545 225469.48.1 Options 22547-------------- 22548 22549'as' has no machine-dependent command-line options for TILEPro. 22550 22551 22552File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent 22553 225549.48.2 Syntax 22555------------- 22556 22557Block comments are delimited by '/*' and '*/'. End of line comments may 22558be introduced by '#'. 22559 22560 Instructions consist of a leading opcode or macro name followed by 22561whitespace and an optional comma-separated list of operands: 22562 22563 OPCODE [OPERAND, ...] 22564 22565 Instructions must be separated by a newline or semicolon. 22566 22567 There are two ways to write code: either write naked instructions, 22568which the assembler is free to combine into VLIW bundles, or specify the 22569VLIW bundles explicitly. 22570 22571 Bundles are specified using curly braces: 22572 22573 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 22574 22575 A bundle can span multiple lines. If you want to put multiple 22576instructions on a line, whether in a bundle or not, you need to separate 22577them with semicolons as in this example. 22578 22579 A bundle may contain one or more instructions, up to the limit 22580specified by the ISA (currently three). If fewer instructions are 22581specified than the hardware supports in a bundle, the assembler inserts 22582'fnop' instructions automatically. 22583 22584 The assembler will prefer to preserve the ordering of instructions 22585within the bundle, putting the first instruction in a lower-numbered 22586pipeline than the next one, etc. This fact, combined with the optional 22587use of explicit 'fnop' or 'nop' instructions, allows precise control 22588over which pipeline executes each instruction. 22589 22590 If the instructions cannot be bundled in the listed order, the 22591assembler will automatically try to find a valid pipeline assignment. 22592If there is no way to bundle the instructions together, the assembler 22593reports an error. 22594 22595 The assembler does not yet auto-bundle (automatically combine 22596multiple instructions into one bundle), but it reserves the right to do 22597so in the future. If you want to force an instruction to run by itself, 22598put it in a bundle explicitly with curly braces and use 'nop' 22599instructions (not 'fnop') to fill the remaining pipeline slots in that 22600bundle. 22601 22602* Menu: 22603 22604* TILEPro Opcodes:: Opcode Naming Conventions. 22605* TILEPro Registers:: Register Naming. 22606* TILEPro Modifiers:: Symbolic Operand Modifiers. 22607 22608 22609File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax 22610 226119.48.2.1 Opcode Names 22612..................... 22613 22614For a complete list of opcodes and descriptions of their semantics, see 22615'TILE Processor User Architecture Manual', available upon request at 22616www.tilera.com. 22617 22618 22619File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax 22620 226219.48.2.2 Register Names 22622....................... 22623 22624General-purpose registers are represented by predefined symbols of the 22625form 'rN', where N represents a number between '0' and '63'. However, 22626the following registers have canonical names that must be used instead: 22627 22628'r54' 22629 sp 22630 22631'r55' 22632 lr 22633 22634'r56' 22635 sn 22636 22637'r57' 22638 idn0 22639 22640'r58' 22641 idn1 22642 22643'r59' 22644 udn0 22645 22646'r60' 22647 udn1 22648 22649'r61' 22650 udn2 22651 22652'r62' 22653 udn3 22654 22655'r63' 22656 zero 22657 22658 The assembler will emit a warning if a numeric name is used instead 22659of the canonical name. The '.no_require_canonical_reg_names' assembler 22660pseudo-op turns off this warning. '.require_canonical_reg_names' turns 22661it back on. 22662 22663 22664File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax 22665 226669.48.2.3 Symbolic Operand Modifiers 22667................................... 22668 22669The assembler supports several modifiers when using symbol addresses in 22670TILEPro instruction operands. The general syntax is the following: 22671 22672 modifier(symbol) 22673 22674 The following modifiers are supported: 22675 22676'lo16' 22677 22678 This modifier is used to load the low 16 bits of the symbol's 22679 address, sign-extended to a 32-bit value (sign-extension allows it 22680 to be range-checked against signed 16 bit immediate operands 22681 without complaint). 22682 22683'hi16' 22684 22685 This modifier is used to load the high 16 bits of the symbol's 22686 address, also sign-extended to a 32-bit value. 22687 22688'ha16' 22689 22690 'ha16(N)' is identical to 'hi16(N)', except if 'lo16(N)' is 22691 negative it adds one to the 'hi16(N)' value. This way 'lo16' and 22692 'ha16' can be added to create any 32-bit value using 'auli'. For 22693 example, here is how you move an arbitrary 32-bit address into r3: 22694 22695 moveli r3, lo16(sym) 22696 auli r3, r3, ha16(sym) 22697 22698'got' 22699 22700 This modifier is used to load the offset of the GOT entry 22701 corresponding to the symbol. 22702 22703'got_lo16' 22704 22705 This modifier is used to load the sign-extended low 16 bits of the 22706 offset of the GOT entry corresponding to the symbol. 22707 22708'got_hi16' 22709 22710 This modifier is used to load the sign-extended high 16 bits of the 22711 offset of the GOT entry corresponding to the symbol. 22712 22713'got_ha16' 22714 22715 This modifier is like 'got_hi16', but it adds one if 'got_lo16' of 22716 the input value is negative. 22717 22718'plt' 22719 22720 This modifier is used for function symbols. It causes a _procedure 22721 linkage table_, an array of code stubs, to be created at the time 22722 the shared object is created or linked against, together with a 22723 global offset table entry. The value is a pc-relative offset to 22724 the corresponding stub code in the procedure linkage table. This 22725 arrangement causes the run-time symbol resolver to be called to 22726 look up and set the value of the symbol the first time the function 22727 is called (at latest; depending environment variables). It is only 22728 safe to leave the symbol unresolved this way if all references are 22729 function calls. 22730 22731'tls_gd' 22732 22733 This modifier is used to load the offset of the GOT entry of the 22734 symbol's TLS descriptor, to be used for general-dynamic TLS 22735 accesses. 22736 22737'tls_gd_lo16' 22738 22739 This modifier is used to load the sign-extended low 16 bits of the 22740 offset of the GOT entry of the symbol's TLS descriptor, to be used 22741 for general dynamic TLS accesses. 22742 22743'tls_gd_hi16' 22744 22745 This modifier is used to load the sign-extended high 16 bits of the 22746 offset of the GOT entry of the symbol's TLS descriptor, to be used 22747 for general dynamic TLS accesses. 22748 22749'tls_gd_ha16' 22750 22751 This modifier is like 'tls_gd_hi16', but it adds one to the value 22752 if 'tls_gd_lo16' of the input value is negative. 22753 22754'tls_ie' 22755 22756 This modifier is used to load the offset of the GOT entry 22757 containing the offset of the symbol's address from the TCB, to be 22758 used for initial-exec TLS accesses. 22759 22760'tls_ie_lo16' 22761 22762 This modifier is used to load the low 16 bits of the offset of the 22763 GOT entry containing the offset of the symbol's address from the 22764 TCB, to be used for initial-exec TLS accesses. 22765 22766'tls_ie_hi16' 22767 22768 This modifier is used to load the high 16 bits of the offset of the 22769 GOT entry containing the offset of the symbol's address from the 22770 TCB, to be used for initial-exec TLS accesses. 22771 22772'tls_ie_ha16' 22773 22774 This modifier is like 'tls_ie_hi16', but it adds one to the value 22775 if 'tls_ie_lo16' of the input value is negative. 22776 22777'tls_le' 22778 22779 This modifier is used to load the offset of the symbol's address 22780 from the TCB, to be used for local-exec TLS accesses. 22781 22782'tls_le_lo16' 22783 22784 This modifier is used to load the low 16 bits of the offset of the 22785 symbol's address from the TCB, to be used for local-exec TLS 22786 accesses. 22787 22788'tls_le_hi16' 22789 22790 This modifier is used to load the high 16 bits of the offset of the 22791 symbol's address from the TCB, to be used for local-exec TLS 22792 accesses. 22793 22794'tls_le_ha16' 22795 22796 This modifier is like 'tls_le_hi16', but it adds one to the value 22797 if 'tls_le_lo16' of the input value is negative. 22798 22799'tls_gd_call' 22800 22801 This modifier is used to tag an instruction as the "call" part of a 22802 calling sequence for a TLS GD reference of its operand. 22803 22804'tls_gd_add' 22805 22806 This modifier is used to tag an instruction as the "add" part of a 22807 calling sequence for a TLS GD reference of its operand. 22808 22809'tls_ie_load' 22810 22811 This modifier is used to tag an instruction as the "load" part of a 22812 calling sequence for a TLS IE reference of its operand. 22813 22814 22815File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent 22816 228179.48.3 TILEPro Directives 22818------------------------- 22819 22820'.align EXPRESSION [, EXPRESSION]' 22821 This is the generic .ALIGN directive. The first argument is the 22822 requested alignment in bytes. 22823 22824'.allow_suspicious_bundles' 22825 Turns on error checking for combinations of instructions in a 22826 bundle that probably indicate a programming error. This is on by 22827 default. 22828 22829'.no_allow_suspicious_bundles' 22830 Turns off error checking for combinations of instructions in a 22831 bundle that probably indicate a programming error. 22832 22833'.require_canonical_reg_names' 22834 Require that canonical register names be used, and emit a warning 22835 if the numeric names are used. This is on by default. 22836 22837'.no_require_canonical_reg_names' 22838 Permit the use of numeric names for registers that have canonical 22839 names. 22840 22841 22842File: as.info, Node: V850-Dependent, Next: Vax-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies 22843 228449.49 v850 Dependent Features 22845============================ 22846 22847* Menu: 22848 22849* V850 Options:: Options 22850* V850 Syntax:: Syntax 22851* V850 Floating Point:: Floating Point 22852* V850 Directives:: V850 Machine Directives 22853* V850 Opcodes:: Opcodes 22854 22855 22856File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 22857 228589.49.1 Options 22859-------------- 22860 22861'as' supports the following additional command-line options for the V850 22862processor family: 22863 22864'-wsigned_overflow' 22865 Causes warnings to be produced when signed immediate values 22866 overflow the space available for then within their opcodes. By 22867 default this option is disabled as it is possible to receive 22868 spurious warnings due to using exact bit patterns as immediate 22869 constants. 22870 22871'-wunsigned_overflow' 22872 Causes warnings to be produced when unsigned immediate values 22873 overflow the space available for then within their opcodes. By 22874 default this option is disabled as it is possible to receive 22875 spurious warnings due to using exact bit patterns as immediate 22876 constants. 22877 22878'-mv850' 22879 Specifies that the assembled code should be marked as being 22880 targeted at the V850 processor. This allows the linker to detect 22881 attempts to link such code with code assembled for other 22882 processors. 22883 22884'-mv850e' 22885 Specifies that the assembled code should be marked as being 22886 targeted at the V850E processor. This allows the linker to detect 22887 attempts to link such code with code assembled for other 22888 processors. 22889 22890'-mv850e1' 22891 Specifies that the assembled code should be marked as being 22892 targeted at the V850E1 processor. This allows the linker to detect 22893 attempts to link such code with code assembled for other 22894 processors. 22895 22896'-mv850any' 22897 Specifies that the assembled code should be marked as being 22898 targeted at the V850 processor but support instructions that are 22899 specific to the extended variants of the process. This allows the 22900 production of binaries that contain target specific code, but which 22901 are also intended to be used in a generic fashion. For example 22902 libgcc.a contains generic routines used by the code produced by GCC 22903 for all versions of the v850 architecture, together with support 22904 routines only used by the V850E architecture. 22905 22906'-mv850e2' 22907 Specifies that the assembled code should be marked as being 22908 targeted at the V850E2 processor. This allows the linker to detect 22909 attempts to link such code with code assembled for other 22910 processors. 22911 22912'-mv850e2v3' 22913 Specifies that the assembled code should be marked as being 22914 targeted at the V850E2V3 processor. This allows the linker to 22915 detect attempts to link such code with code assembled for other 22916 processors. 22917 22918'-mv850e2v4' 22919 This is an alias for '-mv850e3v5'. 22920 22921'-mv850e3v5' 22922 Specifies that the assembled code should be marked as being 22923 targeted at the V850E3V5 processor. This allows the linker to 22924 detect attempts to link such code with code assembled for other 22925 processors. 22926 22927'-mrelax' 22928 Enables relaxation. This allows the .longcall and .longjump pseudo 22929 ops to be used in the assembler source code. These ops label 22930 sections of code which are either a long function call or a long 22931 branch. The assembler will then flag these sections of code and 22932 the linker will attempt to relax them. 22933 22934'-mgcc-abi' 22935 Marks the generated object file as supporting the old GCC ABI. 22936 22937'-mrh850-abi' 22938 Marks the generated object file as supporting the RH850 ABI. This 22939 is the default. 22940 22941'-m8byte-align' 22942 Marks the generated object file as supporting a maximum 64-bits of 22943 alignment for variables defined in the source code. 22944 22945'-m4byte-align' 22946 Marks the generated object file as supporting a maximum 32-bits of 22947 alignment for variables defined in the source code. This is the 22948 default. 22949 22950'-msoft-float' 22951 Marks the generated object file as not using any floating point 22952 instructions - and hence can be linked with other V850 binaries 22953 that do or do not use floating point. This is the default for 22954 binaries for architectures earlier than the 'e2v3'. 22955 22956'-mhard-float' 22957 Marks the generated object file as one that uses floating point 22958 instructions - and hence can only be linked with other V850 22959 binaries that use the same kind of floating point instructions, or 22960 with binaries that do not use floating point at all. This is the 22961 default for binaries the 'e2v3' and later architectures. 22962 22963 22964File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 22965 229669.49.2 Syntax 22967------------- 22968 22969* Menu: 22970 22971* V850-Chars:: Special Characters 22972* V850-Regs:: Register Names 22973 22974 22975File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 22976 229779.49.2.1 Special Characters 22978........................... 22979 22980'#' is the line comment character. If a '#' appears as the first 22981character of a line, the whole line is treated as a comment, but in this 22982case the line can also be a logical line number directive (*note 22983Comments::) or a preprocessor control command (*note Preprocessing::). 22984 22985 Two dashes ('--') can also be used to start a line comment. 22986 22987 The ';' character can be used to separate statements on the same 22988line. 22989 22990 22991File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 22992 229939.49.2.2 Register Names 22994....................... 22995 22996'as' supports the following names for registers: 22997'general register 0' 22998 r0, zero 22999'general register 1' 23000 r1 23001'general register 2' 23002 r2, hp 23003'general register 3' 23004 r3, sp 23005'general register 4' 23006 r4, gp 23007'general register 5' 23008 r5, tp 23009'general register 6' 23010 r6 23011'general register 7' 23012 r7 23013'general register 8' 23014 r8 23015'general register 9' 23016 r9 23017'general register 10' 23018 r10 23019'general register 11' 23020 r11 23021'general register 12' 23022 r12 23023'general register 13' 23024 r13 23025'general register 14' 23026 r14 23027'general register 15' 23028 r15 23029'general register 16' 23030 r16 23031'general register 17' 23032 r17 23033'general register 18' 23034 r18 23035'general register 19' 23036 r19 23037'general register 20' 23038 r20 23039'general register 21' 23040 r21 23041'general register 22' 23042 r22 23043'general register 23' 23044 r23 23045'general register 24' 23046 r24 23047'general register 25' 23048 r25 23049'general register 26' 23050 r26 23051'general register 27' 23052 r27 23053'general register 28' 23054 r28 23055'general register 29' 23056 r29 23057'general register 30' 23058 r30, ep 23059'general register 31' 23060 r31, lp 23061'system register 0' 23062 eipc 23063'system register 1' 23064 eipsw 23065'system register 2' 23066 fepc 23067'system register 3' 23068 fepsw 23069'system register 4' 23070 ecr 23071'system register 5' 23072 psw 23073'system register 16' 23074 ctpc 23075'system register 17' 23076 ctpsw 23077'system register 18' 23078 dbpc 23079'system register 19' 23080 dbpsw 23081'system register 20' 23082 ctbp 23083 23084 23085File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 23086 230879.49.3 Floating Point 23088--------------------- 23089 23090The V850 family uses IEEE floating-point numbers. 23091 23092 23093File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 23094 230959.49.4 V850 Machine Directives 23096------------------------------ 23097 23098'.offset <EXPRESSION>' 23099 Moves the offset into the current section to the specified amount. 23100 23101'.section "name", <type>' 23102 This is an extension to the standard .section directive. It sets 23103 the current section to be <type> and creates an alias for this 23104 section called "name". 23105 23106'.v850' 23107 Specifies that the assembled code should be marked as being 23108 targeted at the V850 processor. This allows the linker to detect 23109 attempts to link such code with code assembled for other 23110 processors. 23111 23112'.v850e' 23113 Specifies that the assembled code should be marked as being 23114 targeted at the V850E processor. This allows the linker to detect 23115 attempts to link such code with code assembled for other 23116 processors. 23117 23118'.v850e1' 23119 Specifies that the assembled code should be marked as being 23120 targeted at the V850E1 processor. This allows the linker to detect 23121 attempts to link such code with code assembled for other 23122 processors. 23123 23124'.v850e2' 23125 Specifies that the assembled code should be marked as being 23126 targeted at the V850E2 processor. This allows the linker to detect 23127 attempts to link such code with code assembled for other 23128 processors. 23129 23130'.v850e2v3' 23131 Specifies that the assembled code should be marked as being 23132 targeted at the V850E2V3 processor. This allows the linker to 23133 detect attempts to link such code with code assembled for other 23134 processors. 23135 23136'.v850e2v4' 23137 Specifies that the assembled code should be marked as being 23138 targeted at the V850E3V5 processor. This allows the linker to 23139 detect attempts to link such code with code assembled for other 23140 processors. 23141 23142'.v850e3v5' 23143 Specifies that the assembled code should be marked as being 23144 targeted at the V850E3V5 processor. This allows the linker to 23145 detect attempts to link such code with code assembled for other 23146 processors. 23147 23148 23149File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 23150 231519.49.5 Opcodes 23152-------------- 23153 23154'as' implements all the standard V850 opcodes. 23155 23156 'as' also implements the following pseudo ops: 23157 23158'hi0()' 23159 Computes the higher 16 bits of the given expression and stores it 23160 into the immediate operand field of the given instruction. For 23161 example: 23162 23163 'mulhi hi0(here - there), r5, r6' 23164 23165 computes the difference between the address of labels 'here' and 23166 'there', takes the upper 16 bits of this difference, shifts it down 23167 16 bits and then multiplies it by the lower 16 bits in register 5, 23168 putting the result into register 6. 23169 23170'lo()' 23171 Computes the lower 16 bits of the given expression and stores it 23172 into the immediate operand field of the given instruction. For 23173 example: 23174 23175 'addi lo(here - there), r5, r6' 23176 23177 computes the difference between the address of labels 'here' and 23178 'there', takes the lower 16 bits of this difference and adds it to 23179 register 5, putting the result into register 6. 23180 23181'hi()' 23182 Computes the higher 16 bits of the given expression and then adds 23183 the value of the most significant bit of the lower 16 bits of the 23184 expression and stores the result into the immediate operand field 23185 of the given instruction. For example the following code can be 23186 used to compute the address of the label 'here' and store it into 23187 register 6: 23188 23189 'movhi hi(here), r0, r6' 'movea lo(here), r6, r6' 23190 23191 The reason for this special behaviour is that movea performs a sign 23192 extension on its immediate operand. So for example if the address 23193 of 'here' was 0xFFFFFFFF then without the special behaviour of the 23194 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 23195 then the movea instruction would takes its immediate operand, 23196 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into 23197 r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With 23198 the hi() pseudo op adding in the top bit of the lo() pseudo op, the 23199 movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), 23200 so that the movea instruction stores 0xFFFFFFFF into r6 - the right 23201 value. 23202 23203'hilo()' 23204 Computes the 32 bit value of the given expression and stores it 23205 into the immediate operand field of the given instruction (which 23206 must be a mov instruction). For example: 23207 23208 'mov hilo(here), r6' 23209 23210 computes the absolute address of label 'here' and puts the result 23211 into register 6. 23212 23213'sdaoff()' 23214 Computes the offset of the named variable from the start of the 23215 Small Data Area (whose address is held in register 4, the GP 23216 register) and stores the result as a 16 bit signed value in the 23217 immediate operand field of the given instruction. For example: 23218 23219 'ld.w sdaoff(_a_variable)[gp],r6' 23220 23221 loads the contents of the location pointed to by the label 23222 '_a_variable' into register 6, provided that the label is located 23223 somewhere within +/- 32K of the address held in the GP register. 23224 [Note the linker assumes that the GP register contains a fixed 23225 address set to the address of the label called '__gp'. This can 23226 either be set up automatically by the linker, or specifically set 23227 by using the '--defsym __gp=<value>' command-line option]. 23228 23229'tdaoff()' 23230 Computes the offset of the named variable from the start of the 23231 Tiny Data Area (whose address is held in register 30, the EP 23232 register) and stores the result as a 4,5, 7 or 8 bit unsigned value 23233 in the immediate operand field of the given instruction. For 23234 example: 23235 23236 'sld.w tdaoff(_a_variable)[ep],r6' 23237 23238 loads the contents of the location pointed to by the label 23239 '_a_variable' into register 6, provided that the label is located 23240 somewhere within +256 bytes of the address held in the EP register. 23241 [Note the linker assumes that the EP register contains a fixed 23242 address set to the address of the label called '__ep'. This can 23243 either be set up automatically by the linker, or specifically set 23244 by using the '--defsym __ep=<value>' command-line option]. 23245 23246'zdaoff()' 23247 Computes the offset of the named variable from address 0 and stores 23248 the result as a 16 bit signed value in the immediate operand field 23249 of the given instruction. For example: 23250 23251 'movea zdaoff(_a_variable),zero,r6' 23252 23253 puts the address of the label '_a_variable' into register 6, 23254 assuming that the label is somewhere within the first 32K of 23255 memory. (Strictly speaking it also possible to access the last 32K 23256 of memory as well, as the offsets are signed). 23257 23258'ctoff()' 23259 Computes the offset of the named variable from the start of the 23260 Call Table Area (whose address is held in system register 20, the 23261 CTBP register) and stores the result a 6 or 16 bit unsigned value 23262 in the immediate field of then given instruction or piece of data. 23263 For example: 23264 23265 'callt ctoff(table_func1)' 23266 23267 will put the call the function whose address is held in the call 23268 table at the location labeled 'table_func1'. 23269 23270'.longcall name' 23271 Indicates that the following sequence of instructions is a long 23272 call to function 'name'. The linker will attempt to shorten this 23273 call sequence if 'name' is within a 22bit offset of the call. Only 23274 valid if the '-mrelax' command-line switch has been enabled. 23275 23276'.longjump name' 23277 Indicates that the following sequence of instructions is a long 23278 jump to label 'name'. The linker will attempt to shorten this code 23279 sequence if 'name' is within a 22bit offset of the jump. Only 23280 valid if the '-mrelax' command-line switch has been enabled. 23281 23282 For information on the V850 instruction set, see 'V850 Family 2328332-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. 23284Ltd. 23285 23286 23287File: as.info, Node: Vax-Dependent, Next: Visium-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 23288 232899.50 VAX Dependent Features 23290=========================== 23291 23292* Menu: 23293 23294* VAX-Opts:: VAX Command-Line Options 23295* VAX-float:: VAX Floating Point 23296* VAX-directives:: Vax Machine Directives 23297* VAX-opcodes:: VAX Opcodes 23298* VAX-branch:: VAX Branch Improvement 23299* VAX-operands:: VAX Operands 23300* VAX-no:: Not Supported on VAX 23301* VAX-Syntax:: VAX Syntax 23302 23303 23304File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 23305 233069.50.1 VAX Command-Line Options 23307------------------------------- 23308 23309The Vax version of 'as' accepts any of the following options, gives a 23310warning message that the option was ignored and proceeds. These options 23311are for compatibility with scripts designed for other people's 23312assemblers. 23313 23314'-D (Debug)' 23315'-S (Symbol Table)' 23316'-T (Token Trace)' 23317 These are obsolete options used to debug old assemblers. 23318 23319'-d (Displacement size for JUMPs)' 23320 This option expects a number following the '-d'. Like options that 23321 expect filenames, the number may immediately follow the '-d' (old 23322 standard) or constitute the whole of the command-line argument that 23323 follows '-d' (GNU standard). 23324 23325'-V (Virtualize Interpass Temporary File)' 23326 Some other assemblers use a temporary file. This option commanded 23327 them to keep the information in active memory rather than in a disk 23328 file. 'as' always does this, so this option is redundant. 23329 23330'-J (JUMPify Longer Branches)' 23331 Many 32-bit computers permit a variety of branch instructions to do 23332 the same job. Some of these instructions are short (and fast) but 23333 have a limited range; others are long (and slow) but can branch 23334 anywhere in virtual memory. Often there are 3 flavors of branch: 23335 short, medium and long. Some other assemblers would emit short and 23336 medium branches, unless told by this option to emit short and long 23337 branches. 23338 23339'-t (Temporary File Directory)' 23340 Some other assemblers may use a temporary file, and this option 23341 takes a filename being the directory to site the temporary file. 23342 Since 'as' does not use a temporary disk file, this option makes no 23343 difference. '-t' needs exactly one filename. 23344 23345 The Vax version of the assembler accepts additional options when 23346compiled for VMS: 23347 23348'-h N' 23349 External symbol or section (used for global variables) names are 23350 not case sensitive on VAX/VMS and always mapped to upper case. 23351 This is contrary to the C language definition which explicitly 23352 distinguishes upper and lower case. To implement a standard 23353 conforming C compiler, names must be changed (mapped) to preserve 23354 the case information. The default mapping is to convert all lower 23355 case characters to uppercase and adding an underscore followed by a 23356 6 digit hex value, representing a 24 digit binary value. The one 23357 digits in the binary value represent which characters are uppercase 23358 in the original symbol name. 23359 23360 The '-h N' option determines how we map names. This takes several 23361 values. No '-h' switch at all allows case hacking as described 23362 above. A value of zero ('-h0') implies names should be upper case, 23363 and inhibits the case hack. A value of 2 ('-h2') implies names 23364 should be all lower case, with no case hack. A value of 3 ('-h3') 23365 implies that case should be preserved. The value 1 is unused. The 23366 '-H' option directs 'as' to display every mapped symbol during 23367 assembly. 23368 23369 Symbols whose names include a dollar sign '$' are exceptions to the 23370 general name mapping. These symbols are normally only used to 23371 reference VMS library names. Such symbols are always mapped to 23372 upper case. 23373 23374'-+' 23375 The '-+' option causes 'as' to truncate any symbol name larger than 23376 31 characters. The '-+' option also prevents some code following 23377 the '_main' symbol normally added to make the object file 23378 compatible with Vax-11 "C". 23379 23380'-1' 23381 This option is ignored for backward compatibility with 'as' version 23382 1.x. 23383 23384'-H' 23385 The '-H' option causes 'as' to print every symbol which was changed 23386 by case mapping. 23387 23388 23389File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 23390 233919.50.2 VAX Floating Point 23392------------------------- 23393 23394Conversion of flonums to floating point is correct, and compatible with 23395previous assemblers. Rounding is towards zero if the remainder is 23396exactly half the least significant bit. 23397 23398 'D', 'F', 'G' and 'H' floating point formats are understood. 23399 23400 Immediate floating literals (_e.g._ 'S`$6.9') are rendered 23401correctly. Again, rounding is towards zero in the boundary case. 23402 23403 The '.float' directive produces 'f' format numbers. The '.double' 23404directive produces 'd' format numbers. 23405 23406 23407File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 23408 234099.50.3 Vax Machine Directives 23410----------------------------- 23411 23412The Vax version of the assembler supports four directives for generating 23413Vax floating point constants. They are described in the table below. 23414 23415'.dfloat' 23416 This expects zero or more flonums, separated by commas, and 23417 assembles Vax 'd' format 64-bit floating point constants. 23418 23419'.ffloat' 23420 This expects zero or more flonums, separated by commas, and 23421 assembles Vax 'f' format 32-bit floating point constants. 23422 23423'.gfloat' 23424 This expects zero or more flonums, separated by commas, and 23425 assembles Vax 'g' format 64-bit floating point constants. 23426 23427'.hfloat' 23428 This expects zero or more flonums, separated by commas, and 23429 assembles Vax 'h' format 128-bit floating point constants. 23430 23431 23432File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 23433 234349.50.4 VAX Opcodes 23435------------------ 23436 23437All DEC mnemonics are supported. Beware that 'case...' instructions 23438have exactly 3 operands. The dispatch table that follows the 'case...' 23439instruction should be made with '.word' statements. This is compatible 23440with all unix assemblers we know of. 23441 23442 23443File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 23444 234459.50.5 VAX Branch Improvement 23446----------------------------- 23447 23448Certain pseudo opcodes are permitted. They are for branch instructions. 23449They expand to the shortest branch instruction that reaches the target. 23450Generally these mnemonics are made by substituting 'j' for 'b' at the 23451start of a DEC mnemonic. This feature is included both for 23452compatibility and to help compilers. If you do not need this feature, 23453avoid these opcodes. Here are the mnemonics, and the code they can 23454expand into. 23455 23456'jbsb' 23457 'Jsb' is already an instruction mnemonic, so we chose 'jbsb'. 23458 (byte displacement) 23459 'bsbb ...' 23460 (word displacement) 23461 'bsbw ...' 23462 (long displacement) 23463 'jsb ...' 23464'jbr' 23465'jr' 23466 Unconditional branch. 23467 (byte displacement) 23468 'brb ...' 23469 (word displacement) 23470 'brw ...' 23471 (long displacement) 23472 'jmp ...' 23473'jCOND' 23474 COND may be any one of the conditional branches 'neq', 'nequ', 23475 'eql', 'eqlu', 'gtr', 'geq', 'lss', 'gtru', 'lequ', 'vc', 'vs', 23476 'gequ', 'cc', 'lssu', 'cs'. COND may also be one of the bit tests 23477 'bs', 'bc', 'bss', 'bcs', 'bsc', 'bcc', 'bssi', 'bcci', 'lbs', 23478 'lbc'. NOTCOND is the opposite condition to COND. 23479 (byte displacement) 23480 'bCOND ...' 23481 (word displacement) 23482 'bNOTCOND foo ; brw ... ; foo:' 23483 (long displacement) 23484 'bNOTCOND foo ; jmp ... ; foo:' 23485'jacbX' 23486 X may be one of 'b d f g h l w'. 23487 (word displacement) 23488 'OPCODE ...' 23489 (long displacement) 23490 OPCODE ..., foo ; 23491 brb bar ; 23492 foo: jmp ... ; 23493 bar: 23494'jaobYYY' 23495 YYY may be one of 'lss leq'. 23496'jsobZZZ' 23497 ZZZ may be one of 'geq gtr'. 23498 (byte displacement) 23499 'OPCODE ...' 23500 (word displacement) 23501 OPCODE ..., foo ; 23502 brb bar ; 23503 foo: brw DESTINATION ; 23504 bar: 23505 (long displacement) 23506 OPCODE ..., foo ; 23507 brb bar ; 23508 foo: jmp DESTINATION ; 23509 bar: 23510'aobleq' 23511'aoblss' 23512'sobgeq' 23513'sobgtr' 23514 (byte displacement) 23515 'OPCODE ...' 23516 (word displacement) 23517 OPCODE ..., foo ; 23518 brb bar ; 23519 foo: brw DESTINATION ; 23520 bar: 23521 (long displacement) 23522 OPCODE ..., foo ; 23523 brb bar ; 23524 foo: jmp DESTINATION ; 23525 bar: 23526 23527 23528File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 23529 235309.50.6 VAX Operands 23531------------------- 23532 23533The immediate character is '$' for Unix compatibility, not '#' as DEC 23534writes it. 23535 23536 The indirect character is '*' for Unix compatibility, not '@' as DEC 23537writes it. 23538 23539 The displacement sizing character is '`' (an accent grave) for Unix 23540compatibility, not '^' as DEC writes it. The letter preceding '`' may 23541have either case. 'G' is not understood, but all other letters ('b i l 23542s w') are understood. 23543 23544 Register names understood are 'r0 r1 r2 ... r15 ap fp sp pc'. Upper 23545and lower case letters are equivalent. 23546 23547 For instance 23548 tstb *w`$4(r5) 23549 23550 Any expression is permitted in an operand. Operands are comma 23551separated. 23552 23553 23554File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent 23555 235569.50.7 Not Supported on VAX 23557--------------------------- 23558 23559Vax bit fields can not be assembled with 'as'. Someone can add the 23560required code if they really need it. 23561 23562 23563File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent 23564 235659.50.8 VAX Syntax 23566----------------- 23567 23568* Menu: 23569 23570* VAX-Chars:: Special Characters 23571 23572 23573File: as.info, Node: VAX-Chars, Up: VAX-Syntax 23574 235759.50.8.1 Special Characters 23576........................... 23577 23578The presence of a '#' appearing anywhere on a line indicates the start 23579of a comment that extends to the end of that line. 23580 23581 If a '#' appears as the first character of a line then the whole line 23582is treated as a comment, but in this case the line can also be a logical 23583line number directive (*note Comments::) or a preprocessor control 23584command (*note Preprocessing::). 23585 23586 The ';' character can be used to separate statements on the same 23587line. 23588 23589 23590File: as.info, Node: Visium-Dependent, Next: WebAssembly-Dependent, Prev: Vax-Dependent, Up: Machine Dependencies 23591 235929.51 Visium Dependent Features 23593============================== 23594 23595* Menu: 23596 23597* Visium Options:: Options 23598* Visium Syntax:: Syntax 23599* Visium Opcodes:: Opcodes 23600 23601 23602File: as.info, Node: Visium Options, Next: Visium Syntax, Up: Visium-Dependent 23603 236049.51.1 Options 23605-------------- 23606 23607The Visium assembler implements one machine-specific option: 23608 23609'-mtune=ARCH' 23610 This option specifies the target architecture. If an attempt is 23611 made to assemble an instruction that will not execute on the target 23612 architecture, the assembler will issue an error message. 23613 23614 The following names are recognized: 'mcm24' 'mcm' 'gr5' 'gr6' 23615 23616 23617File: as.info, Node: Visium Syntax, Next: Visium Opcodes, Prev: Visium Options, Up: Visium-Dependent 23618 236199.51.2 Syntax 23620------------- 23621 23622* Menu: 23623 23624* Visium Characters:: Special Characters 23625* Visium Registers:: Register Names 23626 23627 23628File: as.info, Node: Visium Characters, Next: Visium Registers, Up: Visium Syntax 23629 236309.51.2.1 Special Characters 23631........................... 23632 23633Line comments are introduced either by the '!' character or by the ';' 23634character appearing anywhere on a line. 23635 23636 A hash character ('#') as the first character on a line also marks 23637the start of a line comment, but in this case it could also be a logical 23638line number directive (*note Comments::) or a preprocessor control 23639command (*note Preprocessing::). 23640 23641 The Visium assembler does not currently support a line separator 23642character. 23643 23644 23645File: as.info, Node: Visium Registers, Prev: Visium Characters, Up: Visium Syntax 23646 236479.51.2.2 Register Names 23648....................... 23649 23650Registers can be specified either by using their canonical mnemonic 23651names or by using their alias if they have one, for example 'sp'. 23652 23653 23654File: as.info, Node: Visium Opcodes, Prev: Visium Syntax, Up: Visium-Dependent 23655 236569.51.3 Opcodes 23657-------------- 23658 23659All the standard opcodes of the architecture are implemented, along with 23660the following three pseudo-instructions: 'cmp', 'cmpc', 'move'. 23661 23662 In addition, the following two illegal opcodes are implemented and 23663used by the simulation: 23664 23665 stop 5-bit immediate, SourceA 23666 trace 5-bit immediate, SourceA 23667 23668 23669File: as.info, Node: WebAssembly-Dependent, Next: XGATE-Dependent, Prev: Visium-Dependent, Up: Machine Dependencies 23670 236719.52 WebAssembly Dependent Features 23672=================================== 23673 23674* Menu: 23675 23676* WebAssembly-Notes:: Notes 23677* WebAssembly-Syntax:: Syntax 23678* WebAssembly-Floating-Point:: Floating Point 23679* WebAssembly-Opcodes:: Opcodes 23680* WebAssembly-module-layout:: Module Layout 23681 23682 23683File: as.info, Node: WebAssembly-Notes, Next: WebAssembly-Syntax, Up: WebAssembly-Dependent 23684 236859.52.1 Notes 23686------------ 23687 23688While WebAssembly provides its own module format for executables, this 23689documentation describes how to use 'as' to produce intermediate ELF 23690object format files. 23691 23692 23693File: as.info, Node: WebAssembly-Syntax, Next: WebAssembly-Floating-Point, Prev: WebAssembly-Notes, Up: WebAssembly-Dependent 23694 236959.52.2 Syntax 23696------------- 23697 23698The assembler syntax directly encodes sequences of opcodes as defined in 23699the WebAssembly binary encoding specification at 23700https://github.com/webassembly/spec/BinaryEncoding.md. Structured 23701sexp-style expressions are not supported as input. 23702 23703* Menu: 23704 23705* WebAssembly-Chars:: Special Characters 23706* WebAssembly-Relocs:: Relocations 23707* WebAssembly-Signatures:: Signatures 23708 23709 23710File: as.info, Node: WebAssembly-Chars, Next: WebAssembly-Relocs, Up: WebAssembly-Syntax 23711 237129.52.2.1 Special Characters 23713........................... 23714 23715'#' and ';' are the line comment characters. Note that if '#' is the 23716first character on a line then it can also be a logical line number 23717directive (*note Comments::) or a preprocessor control command (*note 23718Preprocessing::). 23719 23720 23721File: as.info, Node: WebAssembly-Relocs, Next: WebAssembly-Signatures, Prev: WebAssembly-Chars, Up: WebAssembly-Syntax 23722 237239.52.2.2 Relocations 23724.................... 23725 23726Special relocations are available by using the '@PLT', '@GOT', or '@GOT' 23727suffixes after a constant expression, which correspond to the 23728R_ASMJS_LEB128_PLT, R_ASMJS_LEB128_GOT, and R_ASMJS_LEB128_GOT_CODE 23729relocations, respectively. 23730 23731 The '@PLT' suffix is followed by a symbol name in braces; the symbol 23732value is used to determine the function signature for which a PLT stub 23733is generated. Currently, the symbol _name_ is parsed from its last 'F' 23734character to determine the argument count of the function, which is also 23735necessary for generating a PLT stub. 23736 23737 23738File: as.info, Node: WebAssembly-Signatures, Prev: WebAssembly-Relocs, Up: WebAssembly-Syntax 23739 237409.52.2.3 Signatures 23741................... 23742 23743Function signatures are specified with the 'signature' pseudo-opcode, 23744followed by a simple function signature imitating a C++-mangled function 23745type: 'F' followed by an optional 'v', then a sequence of 'i', 'l', 'f', 23746and 'd' characters to mark i32, i64, f32, and f64 parameters, 23747respectively; followed by a final 'E' to mark the end of the function 23748signature. 23749 23750 23751File: as.info, Node: WebAssembly-Floating-Point, Next: WebAssembly-Opcodes, Prev: WebAssembly-Syntax, Up: WebAssembly-Dependent 23752 237539.52.3 Floating Point 23754--------------------- 23755 23756WebAssembly uses little-endian IEEE floating-point numbers. 23757 23758 23759File: as.info, Node: WebAssembly-Opcodes, Next: WebAssembly-module-layout, Prev: WebAssembly-Floating-Point, Up: WebAssembly-Dependent 23760 237619.52.4 Regular Opcodes 23762---------------------- 23763 23764Ordinary instructions are encoded with the WebAssembly mnemonics as 23765listed at: 23766<https://github.com/WebAssembly/design/blob/master/BinaryEncoding.md>. 23767 23768 Opcodes are written directly in the order in which they are encoded, 23769without going through an intermediate sexp-style expression as in the 23770'was' format. 23771 23772 For "typed" opcodes (block, if, etc.), the type of the block is 23773specified in square brackets following the opcode: 'if[i]', 'if[]'. 23774 23775 23776File: as.info, Node: WebAssembly-module-layout, Prev: WebAssembly-Opcodes, Up: WebAssembly-Dependent 23777 237789.52.5 WebAssembly Module Layout 23779-------------------------------- 23780 23781'as' will only produce ELF output, not a valid WebAssembly module. It 23782is possible to make 'as' produce output in a single ELF section which 23783becomes a valid WebAssembly module, but a linker script to do so may be 23784preferable, as it doesn't require running the entire module through the 23785assembler at once. 23786 23787 23788File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: WebAssembly-Dependent, Up: Machine Dependencies 23789 237909.53 XGATE Dependent Features 23791============================= 23792 23793* Menu: 23794 23795* XGATE-Opts:: XGATE Options 23796* XGATE-Syntax:: Syntax 23797* XGATE-Directives:: Assembler Directives 23798* XGATE-Float:: Floating Point 23799* XGATE-opcodes:: Opcodes 23800 23801 23802File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent 23803 238049.53.1 XGATE Options 23805-------------------- 23806 23807The Freescale XGATE version of 'as' has a few machine dependent options. 23808 23809'-mshort' 23810 This option controls the ABI and indicates to use a 16-bit integer 23811 ABI. It has no effect on the assembled instructions. This is the 23812 default. 23813 23814'-mlong' 23815 This option controls the ABI and indicates to use a 32-bit integer 23816 ABI. 23817 23818'-mshort-double' 23819 This option controls the ABI and indicates to use a 32-bit float 23820 ABI. This is the default. 23821 23822'-mlong-double' 23823 This option controls the ABI and indicates to use a 64-bit float 23824 ABI. 23825 23826'--print-insn-syntax' 23827 You can use the '--print-insn-syntax' option to obtain the syntax 23828 description of the instruction when an error is detected. 23829 23830'--print-opcodes' 23831 The '--print-opcodes' option prints the list of all the 23832 instructions with their syntax. Once the list is printed 'as' 23833 exits. 23834 23835 23836File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent 23837 238389.53.2 Syntax 23839------------- 23840 23841In XGATE RISC syntax, the instruction name comes first and it may be 23842followed by up to three operands. Operands are separated by commas 23843(','). 'as' will complain if too many operands are specified for a 23844given instruction. The same will happen if you specified too few 23845operands. 23846 23847 nop 23848 ldl #23 23849 CMP R1, R2 23850 23851 The presence of a ';' character or a '!' character anywhere on a line 23852indicates the start of a comment that extends to the end of that line. 23853 23854 A '*' or a '#' character at the start of a line also introduces a 23855line comment, but these characters do not work elsewhere on the line. 23856If the first character of the line is a '#' then as well as starting a 23857comment, the line could also be logical line number directive (*note 23858Comments::) or a preprocessor control command (*note Preprocessing::). 23859 23860 The XGATE assembler does not currently support a line separator 23861character. 23862 23863 The following addressing modes are understood for XGATE: 23864"Inherent" 23865 '' 23866 23867"Immediate 3 Bit Wide" 23868 '#NUMBER' 23869 23870"Immediate 4 Bit Wide" 23871 '#NUMBER' 23872 23873"Immediate 8 Bit Wide" 23874 '#NUMBER' 23875 23876"Monadic Addressing" 23877 'REG' 23878 23879"Dyadic Addressing" 23880 'REG, REG' 23881 23882"Triadic Addressing" 23883 'REG, REG, REG' 23884 23885"Relative Addressing 9 Bit Wide" 23886 '*SYMBOL' 23887 23888"Relative Addressing 10 Bit Wide" 23889 '*SYMBOL' 23890 23891"Index Register plus Immediate Offset" 23892 'REG, (REG, #NUMBER)' 23893 23894"Index Register plus Register Offset" 23895 'REG, REG, REG' 23896 23897"Index Register plus Register Offset with Post-increment" 23898 'REG, REG, REG+' 23899 23900"Index Register plus Register Offset with Pre-decrement" 23901 'REG, REG, -REG' 23902 23903 The register can be either 'R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6' 23904 or 'R7'. 23905 23906 Convene macro opcodes to deal with 16-bit values have been added. 23907 23908"Immediate 16 Bit Wide" 23909 '#NUMBER', or '*SYMBOL' 23910 23911 For example: 23912 23913 ldw R1, #1024 23914 ldw R3, timer 23915 ldw R1, (R1, #0) 23916 COM R1 23917 stw R2, (R1, #0) 23918 23919 23920File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent 23921 239229.53.3 Assembler Directives 23923--------------------------- 23924 23925The XGATE version of 'as' have the following specific assembler 23926directives: 23927 23928 23929File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent 23930 239319.53.4 Floating Point 23932--------------------- 23933 23934Packed decimal (P) format floating literals are not supported(yet). 23935 23936 The floating point formats generated by directives are these. 23937 23938'.float' 23939 'Single' precision floating point constants. 23940 23941'.double' 23942 'Double' precision floating point constants. 23943 23944'.extend' 23945'.ldouble' 23946 'Extended' precision ('long double') floating point constants. 23947 23948 23949File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent 23950 239519.53.5 Opcodes 23952-------------- 23953 23954 23955File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies 23956 239579.54 XStormy16 Dependent Features 23958================================= 23959 23960* Menu: 23961 23962* XStormy16 Syntax:: Syntax 23963* XStormy16 Directives:: Machine Directives 23964* XStormy16 Opcodes:: Pseudo-Opcodes 23965 23966 23967File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent 23968 239699.54.1 Syntax 23970------------- 23971 23972* Menu: 23973 23974* XStormy16-Chars:: Special Characters 23975 23976 23977File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax 23978 239799.54.1.1 Special Characters 23980........................... 23981 23982'#' is the line comment character. If a '#' appears as the first 23983character of a line, the whole line is treated as a comment, but in this 23984case the line can also be a logical line number directive (*note 23985Comments::) or a preprocessor control command (*note Preprocessing::). 23986 23987 A semicolon (';') can be used to start a comment that extends from 23988wherever the character appears on the line up to the end of the line. 23989 23990 The '|' character can be used to separate statements on the same 23991line. 23992 23993 23994File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent 23995 239969.54.2 XStormy16 Machine Directives 23997----------------------------------- 23998 23999'.16bit_pointers' 24000 Like the '--16bit-pointers' command-line option this directive 24001 indicates that the assembly code makes use of 16-bit pointers. 24002 24003'.32bit_pointers' 24004 Like the '--32bit-pointers' command-line option this directive 24005 indicates that the assembly code makes use of 32-bit pointers. 24006 24007'.no_pointers' 24008 Like the '--no-pointers' command-line option this directive 24009 indicates that the assembly code does not makes use pointers. 24010 24011 24012File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent 24013 240149.54.3 XStormy16 Pseudo-Opcodes 24015------------------------------- 24016 24017'as' implements all the standard XStormy16 opcodes. 24018 24019 'as' also implements the following pseudo ops: 24020 24021'@lo()' 24022 Computes the lower 16 bits of the given expression and stores it 24023 into the immediate operand field of the given instruction. For 24024 example: 24025 24026 'add r6, @lo(here - there)' 24027 24028 computes the difference between the address of labels 'here' and 24029 'there', takes the lower 16 bits of this difference and adds it to 24030 register 6. 24031 24032'@hi()' 24033 Computes the higher 16 bits of the given expression and stores it 24034 into the immediate operand field of the given instruction. For 24035 example: 24036 24037 'addc r7, @hi(here - there)' 24038 24039 computes the difference between the address of labels 'here' and 24040 'there', takes the upper 16 bits of this difference, shifts it down 24041 16 bits and then adds it, along with the carry bit, to the value in 24042 register 7. 24043 24044 24045File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies 24046 240479.55 Xtensa Dependent Features 24048============================== 24049 24050This chapter covers features of the GNU assembler that are specific to 24051the Xtensa architecture. For details about the Xtensa instruction set, 24052please consult the 'Xtensa Instruction Set Architecture (ISA) Reference 24053Manual'. 24054 24055* Menu: 24056 24057* Xtensa Options:: Command-line Options. 24058* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 24059* Xtensa Optimizations:: Assembler Optimizations. 24060* Xtensa Relaxation:: Other Automatic Transformations. 24061* Xtensa Directives:: Directives for Xtensa Processors. 24062 24063 24064File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 24065 240669.55.1 Command-line Options 24067--------------------------- 24068 24069'--text-section-literals | --no-text-section-literals' 24070 Control the treatment of literal pools. The default is 24071 '--no-text-section-literals', which places literals in separate 24072 sections in the output file. This allows the literal pool to be 24073 placed in a data RAM/ROM. With '--text-section-literals', the 24074 literals are interspersed in the text section in order to keep them 24075 as close as possible to their references. This may be necessary 24076 for large assembly files, where the literals would otherwise be out 24077 of range of the 'L32R' instructions in the text section. Literals 24078 are grouped into pools following '.literal_position' directives or 24079 preceding 'ENTRY' instructions. These options only affect literals 24080 referenced via PC-relative 'L32R' instructions; literals for 24081 absolute mode 'L32R' instructions are handled separately. *Note 24082 literal: Literal Directive. 24083 24084'--auto-litpools | --no-auto-litpools' 24085 Control the treatment of literal pools. The default is 24086 '--no-auto-litpools', which in the absence of 24087 '--text-section-literals' places literals in separate sections in 24088 the output file. This allows the literal pool to be placed in a 24089 data RAM/ROM. With '--auto-litpools', the literals are interspersed 24090 in the text section in order to keep them as close as possible to 24091 their references, explicit '.literal_position' directives are not 24092 required. This may be necessary for very large functions, where 24093 single literal pool at the beginning of the function may not be 24094 reachable by 'L32R' instructions at the end. These options only 24095 affect literals referenced via PC-relative 'L32R' instructions; 24096 literals for absolute mode 'L32R' instructions are handled 24097 separately. When used together with '--text-section-literals', 24098 '--auto-litpools' takes precedence. *Note literal: Literal 24099 Directive. 24100 24101'--absolute-literals | --no-absolute-literals' 24102 Indicate to the assembler whether 'L32R' instructions use absolute 24103 or PC-relative addressing. If the processor includes the absolute 24104 addressing option, the default is to use absolute 'L32R' 24105 relocations. Otherwise, only the PC-relative 'L32R' relocations 24106 can be used. 24107 24108'--target-align | --no-target-align' 24109 Enable or disable automatic alignment to reduce branch penalties at 24110 some expense in code size. *Note Automatic Instruction Alignment: 24111 Xtensa Automatic Alignment. This optimization is enabled by 24112 default. Note that the assembler will always align instructions 24113 like 'LOOP' that have fixed alignment requirements. 24114 24115'--longcalls | --no-longcalls' 24116 Enable or disable transformation of call instructions to allow 24117 calls across a greater range of addresses. *Note Function Call 24118 Relaxation: Xtensa Call Relaxation. This option should be used 24119 when call targets can potentially be out of range. It may degrade 24120 both code size and performance, but the linker can generally 24121 optimize away the unnecessary overhead when a call ends up within 24122 range. The default is '--no-longcalls'. 24123 24124'--transform | --no-transform' 24125 Enable or disable all assembler transformations of Xtensa 24126 instructions, including both relaxation and optimization. The 24127 default is '--transform'; '--no-transform' should only be used in 24128 the rare cases when the instructions must be exactly as specified 24129 in the assembly source. Using '--no-transform' causes out of range 24130 instruction operands to be errors. 24131 24132'--rename-section OLDNAME=NEWNAME' 24133 Rename the OLDNAME section to NEWNAME. This option can be used 24134 multiple times to rename multiple sections. 24135 24136'--trampolines | --no-trampolines' 24137 Enable or disable transformation of jump instructions to allow 24138 jumps across a greater range of addresses. *Note Jump Trampolines: 24139 Xtensa Jump Relaxation. This option should be used when jump 24140 targets can potentially be out of range. In the absence of such 24141 jumps this option does not affect code size or performance. The 24142 default is '--trampolines'. 24143 24144'--abi-windowed | --abi-call0' 24145 Choose ABI tag written to the '.xtensa.info' section. ABI tag 24146 indicates ABI of the assembly code. A warning is issued by the 24147 linker on an attempt to link object files with inconsistent ABI 24148 tags. Default ABI is chosen by the Xtensa core configuration. 24149 24150 24151File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 24152 241539.55.2 Assembler Syntax 24154----------------------- 24155 24156Block comments are delimited by '/*' and '*/'. End of line comments may 24157be introduced with either '#' or '//'. 24158 24159 If a '#' appears as the first character of a line then the whole line 24160is treated as a comment, but in this case the line could also be a 24161logical line number directive (*note Comments::) or a preprocessor 24162control command (*note Preprocessing::). 24163 24164 Instructions consist of a leading opcode or macro name followed by 24165whitespace and an optional comma-separated list of operands: 24166 24167 OPCODE [OPERAND, ...] 24168 24169 Instructions must be separated by a newline or semicolon (';'). 24170 24171 FLIX instructions, which bundle multiple opcodes together in a single 24172instruction, are specified by enclosing the bundled opcodes inside 24173braces: 24174 24175 { 24176 [FORMAT] 24177 OPCODE0 [OPERANDS] 24178 OPCODE1 [OPERANDS] 24179 OPCODE2 [OPERANDS] 24180 ... 24181 } 24182 24183 The opcodes in a FLIX instruction are listed in the same order as the 24184corresponding instruction slots in the TIE format declaration. 24185Directives and labels are not allowed inside the braces of a FLIX 24186instruction. A particular TIE format name can optionally be specified 24187immediately after the opening brace, but this is usually unnecessary. 24188The assembler will automatically search for a format that can encode the 24189specified opcodes, so the format name need only be specified in rare 24190cases where there is more than one applicable format and where it 24191matters which of those formats is used. A FLIX instruction can also be 24192specified on a single line by separating the opcodes with semicolons: 24193 24194 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 24195 24196 If an opcode can only be encoded in a FLIX instruction but is not 24197specified as part of a FLIX bundle, the assembler will choose the 24198smallest format where the opcode can be encoded and will fill unused 24199instruction slots with no-ops. 24200 24201* Menu: 24202 24203* Xtensa Opcodes:: Opcode Naming Conventions. 24204* Xtensa Registers:: Register Naming. 24205 24206 24207File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 24208 242099.55.2.1 Opcode Names 24210..................... 24211 24212See the 'Xtensa Instruction Set Architecture (ISA) Reference Manual' for 24213a complete list of opcodes and descriptions of their semantics. 24214 24215 If an opcode name is prefixed with an underscore character ('_'), 24216'as' will not transform that instruction in any way. The underscore 24217prefix disables both optimization (*note Xtensa Optimizations: Xtensa 24218Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 24219Relaxation.) for that particular instruction. Only use the underscore 24220prefix when it is essential to select the exact opcode produced by the 24221assembler. Using this feature unnecessarily makes the code less 24222efficient by disabling assembler optimization and less flexible by 24223disabling relaxation. 24224 24225 Note that this special handling of underscore prefixes only applies 24226to Xtensa opcodes, not to either built-in macros or user-defined macros. 24227When an underscore prefix is used with a macro (e.g., '_MOV'), it refers 24228to a different macro. The assembler generally provides built-in macros 24229both with and without the underscore prefix, where the underscore 24230versions behave as if the underscore carries through to the instructions 24231in the macros. For example, '_MOV' may expand to '_MOV.N'. 24232 24233 The underscore prefix only applies to individual instructions, not to 24234series of instructions. For example, if a series of instructions have 24235underscore prefixes, the assembler will not transform the individual 24236instructions, but it may insert other instructions between them (e.g., 24237to align a 'LOOP' instruction). To prevent the assembler from modifying 24238a series of instructions as a whole, use the 'no-transform' directive. 24239*Note transform: Transform Directive. 24240 24241 24242File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 24243 242449.55.2.2 Register Names 24245....................... 24246 24247The assembly syntax for a register file entry is the "short" name for a 24248TIE register file followed by the index into that register file. For 24249example, the general-purpose 'AR' register file has a short name of 'a', 24250so these registers are named 'a0'...'a15'. As a special feature, 'sp' 24251is also supported as a synonym for 'a1'. Additional registers may be 24252added by processor configuration options and by designer-defined TIE 24253extensions. An initial '$' character is optional in all register names. 24254 24255 24256File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 24257 242589.55.3 Xtensa Optimizations 24259--------------------------- 24260 24261The optimizations currently supported by 'as' are generation of density 24262instructions where appropriate and automatic branch target alignment. 24263 24264* Menu: 24265 24266* Density Instructions:: Using Density Instructions. 24267* Xtensa Automatic Alignment:: Automatic Instruction Alignment. 24268 24269 24270File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 24271 242729.55.3.1 Using Density Instructions 24273................................... 24274 24275The Xtensa instruction set has a code density option that provides 2427616-bit versions of some of the most commonly used opcodes. Use of these 24277opcodes can significantly reduce code size. When possible, the 24278assembler automatically translates instructions from the core Xtensa 24279instruction set into equivalent instructions from the Xtensa code 24280density option. This translation can be disabled by using underscore 24281prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 24282'--no-transform' command-line option (*note Command Line Options: Xtensa 24283Options.), or by using the 'no-transform' directive (*note transform: 24284Transform Directive.). 24285 24286 It is a good idea _not_ to use the density instructions directly. 24287The assembler will automatically select dense instructions where 24288possible. If you later need to use an Xtensa processor without the code 24289density option, the same assembly code will then work without 24290modification. 24291 24292 24293File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 24294 242959.55.3.2 Automatic Instruction Alignment 24296........................................ 24297 24298The Xtensa assembler will automatically align certain instructions, both 24299to optimize performance and to satisfy architectural requirements. 24300 24301 As an optimization to improve performance, the assembler attempts to 24302align branch targets so they do not cross instruction fetch boundaries. 24303(Xtensa processors can be configured with either 32-bit or 64-bit 24304instruction fetch widths.) An instruction immediately following a call 24305is treated as a branch target in this context, because it will be the 24306target of a return from the call. This alignment has the potential to 24307reduce branch penalties at some expense in code size. This optimization 24308is enabled by default. You can disable it with the '--no-target-align' 24309command-line option (*note Command-line Options: Xtensa Options.). 24310 24311 The target alignment optimization is done without adding instructions 24312that could increase the execution time of the program. If there are 24313density instructions in the code preceding a target, the assembler can 24314change the target alignment by widening some of those instructions to 24315the equivalent 24-bit instructions. Extra bytes of padding can be 24316inserted immediately following unconditional jump and return 24317instructions. This approach is usually successful in aligning many, but 24318not all, branch targets. 24319 24320 The 'LOOP' family of instructions must be aligned such that the first 24321instruction in the loop body does not cross an instruction fetch 24322boundary (e.g., with a 32-bit fetch width, a 'LOOP' instruction must be 24323on either a 1 or 2 mod 4 byte boundary). The assembler knows about this 24324restriction and inserts the minimal number of 2 or 3 byte no-op 24325instructions to satisfy it. When no-op instructions are added, any 24326label immediately preceding the original loop will be moved in order to 24327refer to the loop instruction, not the newly generated no-op 24328instruction. To preserve binary compatibility across processors with 24329different fetch widths, the assembler conservatively assumes a 32-bit 24330fetch width when aligning 'LOOP' instructions (except if the first 24331instruction in the loop is a 64-bit instruction). 24332 24333 Previous versions of the assembler automatically aligned 'ENTRY' 24334instructions to 4-byte boundaries, but that alignment is now the 24335programmer's responsibility. 24336 24337 24338File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 24339 243409.55.4 Xtensa Relaxation 24341------------------------ 24342 24343When an instruction operand is outside the range allowed for that 24344particular instruction field, 'as' can transform the code to use a 24345functionally-equivalent instruction or sequence of instructions. This 24346process is known as "relaxation". This is typically done for branch 24347instructions because the distance of the branch targets is not known 24348until assembly-time. The Xtensa assembler offers branch relaxation and 24349also extends this concept to function calls, 'MOVI' instructions and 24350other instructions with immediate fields. 24351 24352* Menu: 24353 24354* Xtensa Branch Relaxation:: Relaxation of Branches. 24355* Xtensa Call Relaxation:: Relaxation of Function Calls. 24356* Xtensa Jump Relaxation:: Relaxation of Jumps. 24357* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 24358 24359 24360File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 24361 243629.55.4.1 Conditional Branch Relaxation 24363...................................... 24364 24365When the target of a branch is too far away from the branch itself, 24366i.e., when the offset from the branch to the target is too large to fit 24367in the immediate field of the branch instruction, it may be necessary to 24368replace the branch with a branch around a jump. For example, 24369 24370 beqz a2, L 24371 24372 may result in: 24373 24374 bnez.n a2, M 24375 j L 24376 M: 24377 24378 (The 'BNEZ.N' instruction would be used in this example only if the 24379density option is available. Otherwise, 'BNEZ' would be used.) 24380 24381 This relaxation works well because the unconditional jump instruction 24382has a much larger offset range than the various conditional branches. 24383However, an error will occur if a branch target is beyond the range of a 24384jump instruction. 'as' cannot relax unconditional jumps. Similarly, an 24385error will occur if the original input contains an unconditional jump to 24386a target that is out of range. 24387 24388 Branch relaxation is enabled by default. It can be disabled by using 24389underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 24390'--no-transform' command-line option (*note Command-line Options: Xtensa 24391Options.), or the 'no-transform' directive (*note transform: Transform 24392Directive.). 24393 24394 24395File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Jump Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 24396 243979.55.4.2 Function Call Relaxation 24398................................. 24399 24400Function calls may require relaxation because the Xtensa immediate call 24401instructions ('CALL0', 'CALL4', 'CALL8' and 'CALL12') provide a 24402PC-relative offset of only 512 Kbytes in either direction. For larger 24403programs, it may be necessary to use indirect calls ('CALLX0', 'CALLX4', 24404'CALLX8' and 'CALLX12') where the target address is specified in a 24405register. The Xtensa assembler can automatically relax immediate call 24406instructions into indirect call instructions. This relaxation is done 24407by loading the address of the called function into the callee's return 24408address register and then using a 'CALLX' instruction. So, for example: 24409 24410 call8 func 24411 24412 might be relaxed to: 24413 24414 .literal .L1, func 24415 l32r a8, .L1 24416 callx8 a8 24417 24418 Because the addresses of targets of function calls are not generally 24419known until link-time, the assembler must assume the worst and relax all 24420the calls to functions in other source files, not just those that really 24421will be out of range. The linker can recognize calls that were 24422unnecessarily relaxed, and it will remove the overhead introduced by the 24423assembler for those cases where direct calls are sufficient. 24424 24425 Call relaxation is disabled by default because it can have a negative 24426effect on both code size and performance, although the linker can 24427usually eliminate the unnecessary overhead. If a program is too large 24428and some of the calls are out of range, function call relaxation can be 24429enabled using the '--longcalls' command-line option or the 'longcalls' 24430directive (*note longcalls: Longcalls Directive.). 24431 24432 24433File: as.info, Node: Xtensa Jump Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 24434 244359.55.4.3 Jump Relaxation 24436........................ 24437 24438Jump instruction may require relaxation because the Xtensa jump 24439instruction ('J') provide a PC-relative offset of only 128 Kbytes in 24440either direction. One option is to use jump long ('J.L') instruction, 24441which depending on jump distance may be assembled as jump ('J') or 24442indirect jump ('JX'). However it needs a free register. When there's 24443no spare register it is possible to plant intermediate jump sites 24444(trampolines) between the jump instruction and its target. These sites 24445may be located in areas unreachable by normal code execution flow, in 24446that case they only contain intermediate jumps, or they may be inserted 24447in the middle of code block, in which case there's an additional jump 24448from the beginning of the trampoline to the instruction past its end. 24449So, for example: 24450 24451 j 1f 24452 ... 24453 retw 24454 ... 24455 mov a10, a2 24456 call8 func 24457 ... 24458 1: 24459 ... 24460 24461 might be relaxed to: 24462 24463 j .L0_TR_1 24464 ... 24465 retw 24466 .L0_TR_1: 24467 j 1f 24468 ... 24469 mov a10, a2 24470 call8 func 24471 ... 24472 1: 24473 ... 24474 24475 or to: 24476 24477 j .L0_TR_1 24478 ... 24479 retw 24480 ... 24481 mov a10, a2 24482 j .L0_TR_0 24483 .L0_TR_1: 24484 j 1f 24485 .L0_TR_0: 24486 call8 func 24487 ... 24488 1: 24489 ... 24490 24491 The Xtensa assembler uses trampolines with jump around only when it 24492cannot find suitable unreachable trampoline. There may be multiple 24493trampolines between the jump instruction and its target. 24494 24495 This relaxation does not apply to jumps to undefined symbols, 24496assuming they will reach their targets once resolved. 24497 24498 Jump relaxation is enabled by default because it does not affect code 24499size or performance while the code itself is small. This relaxation may 24500be disabled completely with '--no-trampolines' or '--no-transform' 24501command-line options (*note Command-line Options: Xtensa Options.). 24502 24503 24504File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Jump Relaxation, Up: Xtensa Relaxation 24505 245069.55.4.4 Other Immediate Field Relaxation 24507......................................... 24508 24509The assembler normally performs the following other relaxations. They 24510can be disabled by using underscore prefixes (*note Opcode Names: Xtensa 24511Opcodes.), the '--no-transform' command-line option (*note Command-line 24512Options: Xtensa Options.), or the 'no-transform' directive (*note 24513transform: Transform Directive.). 24514 24515 The 'MOVI' machine instruction can only materialize values in the 24516range from -2048 to 2047. Values outside this range are best 24517materialized with 'L32R' instructions. Thus: 24518 24519 movi a0, 100000 24520 24521 is assembled into the following machine code: 24522 24523 .literal .L1, 100000 24524 l32r a0, .L1 24525 24526 The 'L8UI' machine instruction can only be used with immediate 24527offsets in the range from 0 to 255. The 'L16SI' and 'L16UI' machine 24528instructions can only be used with offsets from 0 to 510. The 'L32I' 24529machine instruction can only be used with offsets from 0 to 1020. A 24530load offset outside these ranges can be materialized with an 'L32R' 24531instruction if the destination register of the load is different than 24532the source address register. For example: 24533 24534 l32i a1, a0, 2040 24535 24536 is translated to: 24537 24538 .literal .L1, 2040 24539 l32r a1, .L1 24540 add a1, a0, a1 24541 l32i a1, a1, 0 24542 24543If the load destination and source address register are the same, an 24544out-of-range offset causes an error. 24545 24546 The Xtensa 'ADDI' instruction only allows immediate operands in the 24547range from -128 to 127. There are a number of alternate instruction 24548sequences for the 'ADDI' operation. First, if the immediate is 0, the 24549'ADDI' will be turned into a 'MOV.N' instruction (or the equivalent 'OR' 24550instruction if the code density option is not available). If the 'ADDI' 24551immediate is outside of the range -128 to 127, but inside the range 24552-32896 to 32639, an 'ADDMI' instruction or 'ADDMI'/'ADDI' sequence will 24553be used. Finally, if the immediate is outside of this range and a free 24554register is available, an 'L32R'/'ADD' sequence will be used with a 24555literal allocated from the literal pool. 24556 24557 For example: 24558 24559 addi a5, a6, 0 24560 addi a5, a6, 512 24561 addi a5, a6, 513 24562 addi a5, a6, 50000 24563 24564 is assembled into the following: 24565 24566 .literal .L1, 50000 24567 mov.n a5, a6 24568 addmi a5, a6, 0x200 24569 addmi a5, a6, 0x200 24570 addi a5, a5, 1 24571 l32r a5, .L1 24572 add a5, a6, a5 24573 24574 24575File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 24576 245779.55.5 Directives 24578----------------- 24579 24580The Xtensa assembler supports a region-based directive syntax: 24581 24582 .begin DIRECTIVE [OPTIONS] 24583 ... 24584 .end DIRECTIVE 24585 24586 All the Xtensa-specific directives that apply to a region of code use 24587this syntax. 24588 24589 The directive applies to code between the '.begin' and the '.end'. 24590The state of the option after the '.end' reverts to what it was before 24591the '.begin'. A nested '.begin'/'.end' region can further change the 24592state of the directive without having to be aware of its outer state. 24593For example, consider: 24594 24595 .begin no-transform 24596 L: add a0, a1, a2 24597 .begin transform 24598 M: add a0, a1, a2 24599 .end transform 24600 N: add a0, a1, a2 24601 .end no-transform 24602 24603 The 'ADD' opcodes at 'L' and 'N' in the outer 'no-transform' region 24604both result in 'ADD' machine instructions, but the assembler selects an 24605'ADD.N' instruction for the 'ADD' at 'M' in the inner 'transform' 24606region. 24607 24608 The advantage of this style is that it works well inside macros which 24609can preserve the context of their callers. 24610 24611 The following directives are available: 24612* Menu: 24613 24614* Schedule Directive:: Enable instruction scheduling. 24615* Longcalls Directive:: Use Indirect Calls for Greater Range. 24616* Transform Directive:: Disable All Assembler Transformations. 24617* Literal Directive:: Intermix Literals with Instructions. 24618* Literal Position Directive:: Specify Inline Literal Pool Locations. 24619* Literal Prefix Directive:: Specify Literal Section Name Prefix. 24620* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 24621 24622 24623File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 24624 246259.55.5.1 schedule 24626................. 24627 24628The 'schedule' directive is recognized only for compatibility with 24629Tensilica's assembler. 24630 24631 .begin [no-]schedule 24632 .end [no-]schedule 24633 24634 This directive is ignored and has no effect on 'as'. 24635 24636 24637File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 24638 246399.55.5.2 longcalls 24640.................. 24641 24642The 'longcalls' directive enables or disables function call relaxation. 24643*Note Function Call Relaxation: Xtensa Call Relaxation. 24644 24645 .begin [no-]longcalls 24646 .end [no-]longcalls 24647 24648 Call relaxation is disabled by default unless the '--longcalls' 24649command-line option is specified. The 'longcalls' directive overrides 24650the default determined by the command-line options. 24651 24652 24653File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 24654 246559.55.5.3 transform 24656.................. 24657 24658This directive enables or disables all assembler transformation, 24659including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 24660optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 24661 24662 .begin [no-]transform 24663 .end [no-]transform 24664 24665 Transformations are enabled by default unless the '--no-transform' 24666option is used. The 'transform' directive overrides the default 24667determined by the command-line options. An underscore opcode prefix, 24668disabling transformation of that opcode, always takes precedence over 24669both directives and command-line flags. 24670 24671 24672File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 24673 246749.55.5.4 literal 24675................ 24676 24677The '.literal' directive is used to define literal pool data, i.e., 24678read-only 32-bit data accessed via 'L32R' instructions. 24679 24680 .literal LABEL, VALUE[, VALUE...] 24681 24682 This directive is similar to the standard '.word' directive, except 24683that the actual location of the literal data is determined by the 24684assembler and linker, not by the position of the '.literal' directive. 24685Using this directive gives the assembler freedom to locate the literal 24686data in the most appropriate place and possibly to combine identical 24687literals. For example, the code: 24688 24689 entry sp, 40 24690 .literal .L1, sym 24691 l32r a4, .L1 24692 24693 can be used to load a pointer to the symbol 'sym' into register 'a4'. 24694The value of 'sym' will not be placed between the 'ENTRY' and 'L32R' 24695instructions; instead, the assembler puts the data in a literal pool. 24696 24697 Literal pools are placed by default in separate literal sections; 24698however, when using the '--text-section-literals' option (*note 24699Command-line Options: Xtensa Options.), the literal pools for 24700PC-relative mode 'L32R' instructions are placed in the current 24701section.(1) These text section literal pools are created automatically 24702before 'ENTRY' instructions and manually after '.literal_position' 24703directives (*note literal_position: Literal Position Directive.). If 24704there are no preceding 'ENTRY' instructions, explicit 24705'.literal_position' directives must be used to place the text section 24706literal pools; otherwise, 'as' will report an error. 24707 24708 When literals are placed in separate sections, the literal section 24709names are derived from the names of the sections where the literals are 24710defined. The base literal section names are '.literal' for PC-relative 24711mode 'L32R' instructions and '.lit4' for absolute mode 'L32R' 24712instructions (*note absolute-literals: Absolute Literals Directive.). 24713These base names are used for literals defined in the default '.text' 24714section. For literals defined in other sections or within the scope of 24715a 'literal_prefix' directive (*note literal_prefix: Literal Prefix 24716Directive.), the following rules determine the literal section name: 24717 24718 1. If the current section is a member of a section group, the literal 24719 section name includes the group name as a suffix to the base 24720 '.literal' or '.lit4' name, with a period to separate the base name 24721 and group name. The literal section is also made a member of the 24722 group. 24723 24724 2. If the current section name (or 'literal_prefix' value) begins with 24725 "'.gnu.linkonce.KIND.'", the literal section name is formed by 24726 replacing "'.KIND'" with the base '.literal' or '.lit4' name. For 24727 example, for literals defined in a section named 24728 '.gnu.linkonce.t.func', the literal section will be 24729 '.gnu.linkonce.literal.func' or '.gnu.linkonce.lit4.func'. 24730 24731 3. If the current section name (or 'literal_prefix' value) ends with 24732 '.text', the literal section name is formed by replacing that 24733 suffix with the base '.literal' or '.lit4' name. For example, for 24734 literals defined in a section named '.iram0.text', the literal 24735 section will be '.iram0.literal' or '.iram0.lit4'. 24736 24737 4. If none of the preceding conditions apply, the literal section name 24738 is formed by adding the base '.literal' or '.lit4' name as a suffix 24739 to the current section name (or 'literal_prefix' value). 24740 24741 ---------- Footnotes ---------- 24742 24743 (1) Literals for the '.init' and '.fini' sections are always placed 24744in separate sections, even when '--text-section-literals' is enabled. 24745 24746 24747File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 24748 247499.55.5.5 literal_position 24750......................... 24751 24752When using '--text-section-literals' to place literals inline in the 24753section being assembled, the '.literal_position' directive can be used 24754to mark a potential location for a literal pool. 24755 24756 .literal_position 24757 24758 The '.literal_position' directive is ignored when the 24759'--text-section-literals' option is not used or when 'L32R' instructions 24760use the absolute addressing mode. 24761 24762 The assembler will automatically place text section literal pools 24763before 'ENTRY' instructions, so the '.literal_position' directive is 24764only needed to specify some other location for a literal pool. You may 24765need to add an explicit jump instruction to skip over an inline literal 24766pool. 24767 24768 For example, an interrupt vector does not begin with an 'ENTRY' 24769instruction so the assembler will be unable to automatically find a good 24770place to put a literal pool. Moreover, the code for the interrupt 24771vector must be at a specific starting address, so the literal pool 24772cannot come before the start of the code. The literal pool for the 24773vector must be explicitly positioned in the middle of the vector (before 24774any uses of the literals, due to the negative offsets used by 24775PC-relative 'L32R' instructions). The '.literal_position' directive can 24776be used to do this. In the following code, the literal for 'M' will 24777automatically be aligned correctly and is placed after the unconditional 24778jump. 24779 24780 .global M 24781 code_start: 24782 j continue 24783 .literal_position 24784 .align 4 24785 continue: 24786 movi a4, M 24787 24788 24789File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 24790 247919.55.5.6 literal_prefix 24792....................... 24793 24794The 'literal_prefix' directive allows you to override the default 24795literal section names, which are derived from the names of the sections 24796where the literals are defined. 24797 24798 .begin literal_prefix [NAME] 24799 .end literal_prefix 24800 24801 For literals defined within the delimited region, the literal section 24802names are derived from the NAME argument instead of the name of the 24803current section. The rules used to derive the literal section names do 24804not change. *Note literal: Literal Directive. If the NAME argument is 24805omitted, the literal sections revert to the defaults. This directive 24806has no effect when using the '--text-section-literals' option (*note 24807Command-line Options: Xtensa Options.). 24808 24809 24810File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 24811 248129.55.5.7 absolute-literals 24813.......................... 24814 24815The 'absolute-literals' and 'no-absolute-literals' directives control 24816the absolute vs. PC-relative mode for 'L32R' instructions. These are 24817relevant only for Xtensa configurations that include the absolute 24818addressing option for 'L32R' instructions. 24819 24820 .begin [no-]absolute-literals 24821 .end [no-]absolute-literals 24822 24823 These directives do not change the 'L32R' mode--they only cause the 24824assembler to emit the appropriate kind of relocation for 'L32R' 24825instructions and to place the literal values in the appropriate section. 24826To change the 'L32R' mode, the program must write the 'LITBASE' special 24827register. It is the programmer's responsibility to keep track of the 24828mode and indicate to the assembler which mode is used in each region of 24829code. 24830 24831 If the Xtensa configuration includes the absolute 'L32R' addressing 24832option, the default is to assume absolute 'L32R' addressing unless the 24833'--no-absolute-literals' command-line option is specified. Otherwise, 24834the default is to assume PC-relative 'L32R' addressing. The 24835'absolute-literals' directive can then be used to override the default 24836determined by the command-line options. 24837 24838 24839File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 24840 248419.56 Z80 Dependent Features 24842=========================== 24843 24844* Menu: 24845 24846* Z80 Options:: Options 24847* Z80 Syntax:: Syntax 24848* Z80 Floating Point:: Floating Point 24849* Z80 Directives:: Z80 Machine Directives 24850* Z80 Opcodes:: Opcodes 24851 24852 24853File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 24854 248559.56.1 Command-line Options 24856--------------------------- 24857 24858'-march=CPU[-EXT...][+EXT...]' 24859 This option specifies the target processor. The assembler will 24860 issue an error message if an attempt is made to assemble an 24861 instruction which will not execute on the target processor. The 24862 following processor names are recognized: 'z80', 'z180', 'ez80', 24863 'gbz80', 'z80n', 'r800'. In addition to the basic instruction set, 24864 the assembler can be told to accept some extention mnemonics. For 24865 example, '-march=z180+sli+infc' extends Z180 with SLI instructions 24866 and IN F,(C). The following extentions are currently supported: 24867 'full' (all known instructions), 'adl' (ADL CPU mode by default, 24868 eZ80 only), 'sli' (instruction known as SLI, SLL or SL1), 'xyhl' 24869 (instructions with halves of index registers: IXL, IXH, IYL, IYH), 24870 'xdcb' (instructions like ROTOP (II+D),R and BITOP N,(II+D),R), 24871 'infc' (instruction IN F,(C) or IN (C)), 'outc0' (instruction OUT 24872 (C),0). Note that rather than extending a basic instruction set, 24873 the extention mnemonics starting with '-' revoke the respective 24874 functionality: '-march=z80-full+xyhl' first removes all default 24875 extentions and adds support for index registers halves only. 24876 24877 If this option is not specified then '-march=z80+xyhl+infc' is 24878 assumed. 24879 24880'-local-prefix=PREFIX' 24881 Mark all labels with specified prefix as local. But such label can 24882 be marked global explicitly in the code. This option do not change 24883 default local label prefix '.L', it is just adds new one. 24884 24885'-colonless' 24886 Accept colonless labels. All symbols at line begin are treated as 24887 labels. 24888 24889'-sdcc' 24890 Accept assembler code produced by SDCC. 24891 24892'-fp-s=FORMAT' 24893 Single precision floating point numbers format. Default: ieee754 24894 (32 bit). 24895 24896'-fp-d=FORMAT' 24897 Double precision floating point numbers format. Default: ieee754 24898 (64 bit). 24899 24900 Floating point numbers formats. 24901'ieee754' 24902 Single or double precision IEEE754 compatible format. 24903 24904'half' 24905 Half precision IEEE754 compatible format (16 bits). 24906 24907'single' 24908 Single precision IEEE754 compatible format (32 bits). 24909 24910'double' 24911 Double precision IEEE754 compatible format (64 bits). 24912 24913'zeda32' 24914 32 bit floating point format from z80float library by Zeda. 24915 24916'math48' 24917 48 bit floating point format from Math48 package by Anders 24918 Hejlsberg. 24919 24920 24921File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent 24922 249239.56.2 Syntax 24924------------- 24925 24926The assembler syntax closely follows the 'Z80 family CPU User Manual' by 24927Zilog. In expressions a single '=' may be used as "is equal to" 24928comparison operator. 24929 24930 Suffices can be used to indicate the radix of integer constants; 'H' 24931or 'h' for hexadecimal, 'D' or 'd' for decimal, 'Q', 'O', 'q' or 'o' for 24932octal, and 'B' for binary. 24933 24934 The suffix 'b' denotes a backreference to local label. 24935 24936* Menu: 24937 24938* Z80-Chars:: Special Characters 24939* Z80-Regs:: Register Names 24940* Z80-Case:: Case Sensitivity 24941* Z80-Labels:: Labels 24942 24943 24944File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 24945 249469.56.2.1 Special Characters 24947........................... 24948 24949The semicolon ';' is the line comment character; 24950 24951 If a '#' appears as the first character of a line then the whole line 24952is treated as a comment, but in this case the line could also be a 24953logical line number directive (*note Comments::) or a preprocessor 24954control command (*note Preprocessing::). 24955 24956 The Z80 assembler does not support a line separator character. 24957 24958 The dollar sign '$' can be used as a prefix for hexadecimal numbers 24959and as a symbol denoting the current location counter. 24960 24961 A backslash '\' is an ordinary character for the Z80 assembler. 24962 24963 The single quote ''' must be followed by a closing quote. If there 24964is one character in between, it is a character constant, otherwise it is 24965a string constant. 24966 24967 24968File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax 24969 249709.56.2.2 Register Names 24971....................... 24972 24973The registers are referred to with the letters assigned to them by 24974Zilog. In addition 'as' recognizes 'ixl' and 'ixh' as the least and 24975most significant octet in 'ix', and similarly 'iyl' and 'iyh' as parts 24976of 'iy'. 24977 24978 24979File: as.info, Node: Z80-Case, Next: Z80-Labels, Prev: Z80-Regs, Up: Z80 Syntax 24980 249819.56.2.3 Case Sensitivity 24982......................... 24983 24984Upper and lower case are equivalent in register names, opcodes, 24985condition codes and assembler directives. The case of letters is 24986significant in labels and symbol names. The case is also important to 24987distinguish the suffix 'b' for a backward reference to a local label 24988from the suffix 'B' for a number in binary notation. 24989 24990 24991File: as.info, Node: Z80-Labels, Prev: Z80-Case, Up: Z80 Syntax 24992 249939.56.2.4 Labels 24994............... 24995 24996Labels started by '.L' acts as local labels. You may specify custom 24997local label prefix by '-local-prefix' command-line option. Dollar, 24998forward and backward local labels are supported. By default, all labels 24999are followed by colon. Legacy code with colonless labels can be built 25000with '-colonless' command-line option specified. In this case all 25001tokens at line begin are treated as labels. 25002 25003 25004File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent 25005 250069.56.3 Floating Point 25007--------------------- 25008 25009Floating-point numbers of following types are supported: 25010 25011'ieee754' 25012 Supported half, single and double precision IEEE754 compatible 25013 numbers. 25014 25015'zeda32' 25016 32 bit floating point numbers from z80float library by Zeda. 25017 25018'math48' 25019 48 bit floating point numbers from Math48 package by Anders 25020 Hejlsberg. 25021 25022 25023File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent 25024 250259.56.4 Z80 Assembler Directives 25026------------------------------- 25027 25028'as' for the Z80 supports some additional directives for compatibility 25029with other assemblers. 25030 25031 These are the additional directives in 'as' for the Z80: 25032 25033'.assume ADL = EXPRESSION' 25034 Set ADL status for eZ80. Non-zero value enable compilation in ADL 25035 mode else used Z80 mode. ADL and Z80 mode produces incompatible 25036 object code. Mixing both of them within one binary may lead 25037 problems with disassembler. 25038 25039'db EXPRESSION|STRING[,EXPRESSION|STRING...]' 25040'defb EXPRESSION|STRING[,EXPRESSION|STRING...]' 25041'defm STRING[,STRING...]' 25042 For each STRING the characters are copied to the object file, for 25043 each other EXPRESSION the value is stored in one byte. A warning 25044 is issued in case of an overflow. Backslash symbol in the strings 25045 is generic symbol, it cannot be used as escape character. *Note 25046 '.ascii': Ascii. 25047 25048'dw EXPRESSION[,EXPRESSION...]' 25049'defw EXPRESSION[,EXPRESSION...]' 25050 For each EXPRESSION the value is stored in two bytes, ignoring 25051 overflow. 25052 25053'd24 EXPRESSION[,EXPRESSION...]' 25054'def24 EXPRESSION[,EXPRESSION...]' 25055 For each EXPRESSION the value is stored in three bytes, ignoring 25056 overflow. 25057 25058'd32 EXPRESSION[,EXPRESSION...]' 25059'def32 EXPRESSION[,EXPRESSION...]' 25060 For each EXPRESSION the value is stored in four bytes, ignoring 25061 overflow. 25062 25063'ds COUNT[, VALUE]' 25064'defs COUNT[, VALUE]' 25065 Fill COUNT bytes in the object file with VALUE, if VALUE is omitted 25066 it defaults to zero. 25067 25068'SYMBOL defl EXPRESSION' 25069 The 'defl' directive is like '.set' but with different syntax. 25070 *Note '.set': Set. It set the value of SYMBOL to EXPRESSION. 25071 Symbols defined with 'defl' are not protected from redefinition. 25072 25073'SYMBOL equ EXPRESSION' 25074 The 'equ' directive is like '.equiv' but with different syntax. 25075 *Note '.equiv': Equiv. It set the value of SYMBOL to EXPRESSION. 25076 It is an error if SYMBOL is already defined. Symbols defined with 25077 'equ' are not protected from redefinition. 25078 25079'psect NAME' 25080 A synonym for '.section', no second argument should be given. 25081 *Note '.section': Section. 25082 25083'xdef SYMBOL' 25084 A synonym for '.global', make SYMBOL is visible to linker. *Note 25085 '.global': Global. 25086 25087'xref NAME' 25088 A synonym for '.extern' (*note '.extern': Extern.). 25089 25090 25091File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent 25092 250939.56.5 Opcodes 25094-------------- 25095 25096In line with common practice, Z80 mnemonics are used for the Z80, Z80N, 25097Z180, eZ80, Ascii R800 and the GameBoy Z80. 25098 25099 In many instructions it is possible to use one of the half index 25100registers ('ixl','ixh','iyl','iyh') in stead of an 8-bit general purpose 25101register. This yields instructions that are documented on the eZ80 and 25102the R800, undocumented on the Z80 and unsupported on the Z180. 25103Similarly 'in f,(c)' is documented on the R800, undocumented on the Z80 25104and unsupported on the Z180 and the eZ80. 25105 25106 The assembler also supports the following undocumented 25107Z80-instructions, that have not been adopted in any other instruction 25108set: 25109'out (c),0' 25110 Sends zero to the port pointed to by register 'C'. 25111 25112'sli M' 25113 Equivalent to 'M = (M<<1)+1', the operand M can be any operand that 25114 is valid for 'sla'. One can use 'sll' as a synonym for 'sli'. 25115 25116'OP (ix+D), R' 25117 This is equivalent to 25118 25119 ld R, (ix+D) 25120 OP R 25121 ld (ix+D), R 25122 25123 The operation 'OP' may be any of 'res B,', 'set B,', 'rl', 'rlc', 25124 'rr', 'rrc', 'sla', 'sli', 'sra' and 'srl', and the register 'R' 25125 may be any of 'a', 'b', 'c', 'd', 'e', 'h' and 'l'. 25126 25127'OP (iy+D), R' 25128 As above, but with 'iy' instead of 'ix'. 25129 25130 The web site at <http://www.z80.info> is a good starting place to 25131find more information on programming the Z80. 25132 25133 You may enable or disable any of these instructions for any target 25134CPU even this instruction is not supported by any real CPU of this type. 25135Useful for custom CPU cores. 25136 25137 25138File: as.info, Node: Z8000-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies 25139 251409.57 Z8000 Dependent Features 25141============================= 25142 25143The Z8000 as supports both members of the Z8000 family: the unsegmented 25144Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit 25145addresses. 25146 25147 When the assembler is in unsegmented mode (specified with the 25148'unsegm' directive), an address takes up one word (16 bit) sized 25149register. When the assembler is in segmented mode (specified with the 25150'segm' directive), a 24-bit address takes up a long (32 bit) register. 25151*Note Assembler Directives for the Z8000: Z8000 Directives, for a list 25152of other Z8000 specific assembler directives. 25153 25154* Menu: 25155 25156* Z8000 Options:: Command-line options for the Z8000 25157* Z8000 Syntax:: Assembler syntax for the Z8000 25158* Z8000 Directives:: Special directives for the Z8000 25159* Z8000 Opcodes:: Opcodes 25160 25161 25162File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 25163 251649.57.1 Options 25165-------------- 25166 25167'-z8001' 25168 Generate segmented code by default. 25169 25170'-z8002' 25171 Generate unsegmented code by default. 25172 25173 25174File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 25175 251769.57.2 Syntax 25177------------- 25178 25179* Menu: 25180 25181* Z8000-Chars:: Special Characters 25182* Z8000-Regs:: Register Names 25183* Z8000-Addressing:: Addressing Modes 25184 25185 25186File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 25187 251889.57.2.1 Special Characters 25189........................... 25190 25191'!' is the line comment character. 25192 25193 If a '#' appears as the first character of a line then the whole line 25194is treated as a comment, but in this case the line could also be a 25195logical line number directive (*note Comments::) or a preprocessor 25196control command (*note Preprocessing::). 25197 25198 You can use ';' instead of a newline to separate statements. 25199 25200 25201File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 25202 252039.57.2.2 Register Names 25204....................... 25205 25206The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 25207to different sized groups of registers by register number, with the 25208prefix 'r' for 16 bit registers, 'rr' for 32 bit registers and 'rq' for 2520964 bit registers. You can also refer to the contents of the first eight 25210(of the sixteen 16 bit registers) by bytes. They are named 'rlN' and 25211'rhN'. 25212 25213_byte registers_ 25214 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 25215 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 25216 25217_word registers_ 25218 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 25219 25220_long word registers_ 25221 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 25222 25223_quad word registers_ 25224 rq0 rq4 rq8 rq12 25225 25226 25227File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 25228 252299.57.2.3 Addressing Modes 25230......................... 25231 25232as understands the following addressing modes for the Z8000: 25233 25234'rlN' 25235'rhN' 25236'rN' 25237'rrN' 25238'rqN' 25239 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 25240 25241'@rN' 25242'@rrN' 25243 Indirect register: @rrN in segmented mode, @rN in unsegmented mode. 25244 25245'ADDR' 25246 Direct: the 16 bit or 24 bit address (depending on whether the 25247 assembler is in segmented or unsegmented mode) of the operand is in 25248 the instruction. 25249 25250'address(rN)' 25251 Indexed: the 16 or 24 bit address is added to the 16 bit register 25252 to produce the final address in memory of the operand. 25253 25254'rN(#IMM)' 25255'rrN(#IMM)' 25256 Base Address: the 16 or 24 bit register is added to the 16 bit sign 25257 extended immediate displacement to produce the final address in 25258 memory of the operand. 25259 25260'rN(rM)' 25261'rrN(rM)' 25262 Base Index: the 16 or 24 bit register rN or rrN is added to the 25263 sign extended 16 bit index register rM to produce the final address 25264 in memory of the operand. 25265 25266'#XX' 25267 Immediate data XX. 25268 25269 25270File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 25271 252729.57.3 Assembler Directives for the Z8000 25273----------------------------------------- 25274 25275The Z8000 port of as includes additional assembler directives, for 25276compatibility with other Z8000 assemblers. These do not begin with '.' 25277(unlike the ordinary as directives). 25278 25279'segm' 25280'.z8001' 25281 Generate code for the segmented Z8001. 25282 25283'unsegm' 25284'.z8002' 25285 Generate code for the unsegmented Z8002. 25286 25287'name' 25288 Synonym for '.file' 25289 25290'global' 25291 Synonym for '.global' 25292 25293'wval' 25294 Synonym for '.word' 25295 25296'lval' 25297 Synonym for '.long' 25298 25299'bval' 25300 Synonym for '.byte' 25301 25302'sval' 25303 Assemble a string. 'sval' expects one string literal, delimited by 25304 single quotes. It assembles each byte of the string into 25305 consecutive addresses. You can use the escape sequence '%XX' 25306 (where XX represents a two-digit hexadecimal number) to represent 25307 the character whose ASCII value is XX. Use this feature to 25308 describe single quote and other characters that may not appear in 25309 string literals as themselves. For example, the C statement 25310 'char *a = "he said \"it's 50% off\"";' is represented in Z8000 25311 assembly language (shown with the assembler output in hex at the 25312 left) as 25313 25314 68652073 sval 'he said %22it%27s 50%25 off%22%00' 25315 61696420 25316 22697427 25317 73203530 25318 25206F66 25319 662200 25320 25321'rsect' 25322 synonym for '.section' 25323 25324'block' 25325 synonym for '.space' 25326 25327'even' 25328 special case of '.align'; aligns output to even byte boundary. 25329 25330 25331File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 25332 253339.57.4 Opcodes 25334-------------- 25335 25336For detailed information on the Z8000 machine instruction set, see 25337'Z8000 Technical Manual'. 25338 25339 The following table summarizes the opcodes and their arguments: 25340 25341 rs 16 bit source register 25342 rd 16 bit destination register 25343 rbs 8 bit source register 25344 rbd 8 bit destination register 25345 rrs 32 bit source register 25346 rrd 32 bit destination register 25347 rqs 64 bit source register 25348 rqd 64 bit destination register 25349 addr 16/24 bit address 25350 imm immediate data 25351 25352 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 25353 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 25354 add rd,@rs clrb rbd dab rbd 25355 add rd,addr com @rd dbjnz rbd,disp7 25356 add rd,addr(rs) com addr dec @rd,imm4m1 25357 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 25358 add rd,rs com rd dec addr,imm4m1 25359 addb rbd,@rs comb @rd dec rd,imm4m1 25360 addb rbd,addr comb addr decb @rd,imm4m1 25361 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 25362 addb rbd,imm8 comb rbd decb addr,imm4m1 25363 addb rbd,rbs comflg flags decb rbd,imm4m1 25364 addl rrd,@rs cp @rd,imm16 di i2 25365 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 25366 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 25367 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 25368 addl rrd,rrs cp rd,addr div rrd,imm16 25369 and rd,@rs cp rd,addr(rs) div rrd,rs 25370 and rd,addr cp rd,imm16 divl rqd,@rs 25371 and rd,addr(rs) cp rd,rs divl rqd,addr 25372 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 25373 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 25374 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 25375 andb rbd,addr cpb rbd,@rs djnz rd,disp7 25376 andb rbd,addr(rs) cpb rbd,addr ei i2 25377 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 25378 andb rbd,rbs cpb rbd,imm8 ex rd,addr 25379 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 25380 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 25381 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 25382 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 25383 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 25384 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 25385 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 25386 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 25387 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 25388 bitb rbd,rs cpl rrd,@rs ext8f imm8 25389 bpt cpl rrd,addr exts rrd 25390 call @rd cpl rrd,addr(rs) extsb rd 25391 call addr cpl rrd,imm32 extsl rqd 25392 call addr(rd) cpl rrd,rrs halt 25393 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 25394 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 25395 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 25396 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 25397 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 25398 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 25399 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 25400 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 25401 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 25402 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 25403 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 25404 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 25405 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 25406 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 25407 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 25408 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 25409 iret ldib @rd,@rs,rr neg addr(rd) 25410 jp cc,@rd ldir @rd,@rs,rr neg rd 25411 jp cc,addr ldirb @rd,@rs,rr negb @rd 25412 jp cc,addr(rd) ldk rd,imm4 negb addr 25413 jr cc,disp8 ldl @rd,rrs negb addr(rd) 25414 ld @rd,imm16 ldl addr(rd),rrs negb rbd 25415 ld @rd,rs ldl addr,rrs nop 25416 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 25417 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 25418 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 25419 ld addr,rs ldl rrd,addr or rd,imm16 25420 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 25421 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 25422 ld rd,@rs ldl rrd,rrs orb rbd,addr 25423 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 25424 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 25425 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 25426 ld rd,rs ldm addr(rd),rs,n out @rd,rs 25427 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 25428 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 25429 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 25430 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 25431 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 25432 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 25433 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 25434 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 25435 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 25436 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 25437 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 25438 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 25439 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 25440 ldb rbd,@rs mbit popl addr,@rs 25441 ldb rbd,addr mreq rd popl rrd,@rs 25442 ldb rbd,addr(rs) mres push @rd,@rs 25443 ldb rbd,imm8 mset push @rd,addr 25444 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 25445 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 25446 push @rd,rs set addr,imm4 subl rrd,imm32 25447 pushl @rd,@rs set rd,imm4 subl rrd,rrs 25448 pushl @rd,addr set rd,rs tcc cc,rd 25449 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 25450 pushl @rd,rrs setb addr(rd),imm4 test @rd 25451 res @rd,imm4 setb addr,imm4 test addr 25452 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 25453 res addr,imm4 setb rbd,rs test rd 25454 res rd,imm4 setflg imm4 testb @rd 25455 res rd,rs sinb rbd,imm16 testb addr 25456 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 25457 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 25458 resb addr,imm4 sindb @rd,@rs,rba testl @rd 25459 resb rbd,imm4 sinib @rd,@rs,ra testl addr 25460 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 25461 resflg imm4 sla rd,imm8 testl rrd 25462 ret cc slab rbd,imm8 trdb @rd,@rs,rba 25463 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 25464 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 25465 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 25466 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 25467 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 25468 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 25469 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 25470 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 25471 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 25472 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 25473 rsvd36 sra rd,imm8 tset rd 25474 rsvd38 srab rbd,imm8 tsetb @rd 25475 rsvd78 sral rrd,imm8 tsetb addr 25476 rsvd7e srl rd,imm8 tsetb addr(rd) 25477 rsvd9d srlb rbd,imm8 tsetb rbd 25478 rsvd9f srll rrd,imm8 xor rd,@rs 25479 rsvdb9 sub rd,@rs xor rd,addr 25480 rsvdbf sub rd,addr xor rd,addr(rs) 25481 sbc rd,rs sub rd,addr(rs) xor rd,imm16 25482 sbcb rbd,rbs sub rd,imm16 xor rd,rs 25483 sc imm8 sub rd,rs xorb rbd,@rs 25484 sda rd,rs subb rbd,@rs xorb rbd,addr 25485 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 25486 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 25487 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 25488 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 25489 sdll rrd,rs subl rrd,@rs 25490 set @rd,imm4 subl rrd,addr 25491 set addr(rd),imm4 subl rrd,addr(rs) 25492 25493 25494File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 25495 2549610 Reporting Bugs 25497***************** 25498 25499Your bug reports play an essential role in making 'as' reliable. 25500 25501 Reporting a bug may help you by bringing a solution to your problem, 25502or it may not. But in any case the principal function of a bug report 25503is to help the entire community by making the next version of 'as' work 25504better. Bug reports are your contribution to the maintenance of 'as'. 25505 25506 In order for a bug report to serve its purpose, you must include the 25507information that enables us to fix the bug. 25508 25509* Menu: 25510 25511* Bug Criteria:: Have you found a bug? 25512* Bug Reporting:: How to report bugs 25513 25514 25515File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 25516 2551710.1 Have You Found a Bug? 25518========================== 25519 25520If you are not sure whether you have found a bug, here are some 25521guidelines: 25522 25523 * If the assembler gets a fatal signal, for any input whatever, that 25524 is a 'as' bug. Reliable assemblers never crash. 25525 25526 * If 'as' produces an error message for valid input, that is a bug. 25527 25528 * If 'as' does not produce an error message for invalid input, that 25529 is a bug. However, you should note that your idea of "invalid 25530 input" might be our idea of "an extension" or "support for 25531 traditional practice". 25532 25533 * If you are an experienced user of assemblers, your suggestions for 25534 improvement of 'as' are welcome in any case. 25535 25536 25537File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 25538 2553910.2 How to Report Bugs 25540======================= 25541 25542A number of companies and individuals offer support for GNU products. 25543If you obtained 'as' from a support organization, we recommend you 25544contact that organization first. 25545 25546 You can find contact information for many support companies and 25547individuals in the file 'etc/SERVICE' in the GNU Emacs distribution. 25548 25549 In any event, we also recommend that you send bug reports for 'as' to 25550<https://www.sourceware.org/bugzilla/>. 25551 25552 The fundamental principle of reporting bugs usefully is this: *report 25553all the facts*. If you are not sure whether to state a fact or leave it 25554out, state it! 25555 25556 Often people omit facts because they think they know what causes the 25557problem and assume that some details do not matter. Thus, you might 25558assume that the name of a symbol you use in an example does not matter. 25559Well, probably it does not, but one cannot be sure. Perhaps the bug is 25560a stray memory reference which happens to fetch from the location where 25561that name is stored in memory; perhaps, if the name were different, the 25562contents of that location would fool the assembler into doing the right 25563thing despite the bug. Play it safe and give a specific, complete 25564example. That is the easiest thing for you to do, and the most helpful. 25565 25566 Keep in mind that the purpose of a bug report is to enable us to fix 25567the bug if it is new to us. Therefore, always write your bug reports on 25568the assumption that the bug has not been reported previously. 25569 25570 Sometimes people give a few sketchy facts and ask, "Does this ring a 25571bell?" This cannot help us fix a bug, so it is basically useless. We 25572respond by asking for enough details to enable us to investigate. You 25573might as well expedite matters by sending them to begin with. 25574 25575 To enable us to fix the bug, you should include all these things: 25576 25577 * The version of 'as'. 'as' announces it if you start it with the 25578 '--version' argument. 25579 25580 Without this, we will not know whether there is any point in 25581 looking for the bug in the current version of 'as'. 25582 25583 * Any patches you may have applied to the 'as' source. 25584 25585 * The type of machine you are using, and the operating system name 25586 and version number. 25587 25588 * What compiler (and its version) was used to compile 'as'--e.g. 25589 "'gcc-2.7'". 25590 25591 * The command arguments you gave the assembler to assemble your 25592 example and observe the bug. To guarantee you will not omit 25593 something important, list them all. A copy of the Makefile (or the 25594 output from make) is sufficient. 25595 25596 If we were to try to guess the arguments, we would probably guess 25597 wrong and then we might not encounter the bug. 25598 25599 * A complete input file that will reproduce the bug. If the bug is 25600 observed when the assembler is invoked via a compiler, send the 25601 assembler source, not the high level language source. Most 25602 compilers will produce the assembler source when run with the '-S' 25603 option. If you are using 'gcc', use the options '-v --save-temps'; 25604 this will save the assembler source in a file with an extension of 25605 '.s', and also show you exactly how 'as' is being run. 25606 25607 * A description of what behavior you observe that you believe is 25608 incorrect. For example, "It gets a fatal signal." 25609 25610 Of course, if the bug is that 'as' gets a fatal signal, then we 25611 will certainly notice it. But if the bug is incorrect output, we 25612 might not notice unless it is glaringly wrong. You might as well 25613 not give us a chance to make a mistake. 25614 25615 Even if the problem you experience is a fatal signal, you should 25616 still say so explicitly. Suppose something strange is going on, 25617 such as, your copy of 'as' is out of sync, or you have encountered 25618 a bug in the C library on your system. (This has happened!) Your 25619 copy might crash and ours would not. If you told us to expect a 25620 crash, then when ours fails to crash, we would know that the bug 25621 was not happening for us. If you had not told us to expect a 25622 crash, then we would not be able to draw any conclusion from our 25623 observations. 25624 25625 * If you wish to suggest changes to the 'as' source, send us context 25626 diffs, as generated by 'diff' with the '-u', '-c', or '-p' option. 25627 Always send diffs from the old file to the new file. If you even 25628 discuss something in the 'as' source, refer to it by context, not 25629 by line number. 25630 25631 The line numbers in our development sources will not match those in 25632 your sources. Your line numbers would convey no useful information 25633 to us. 25634 25635 Here are some things that are not necessary: 25636 25637 * A description of the envelope of the bug. 25638 25639 Often people who encounter a bug spend a lot of time investigating 25640 which changes to the input file will make the bug go away and which 25641 changes will not affect it. 25642 25643 This is often time consuming and not very useful, because the way 25644 we will find the bug is by running a single example under the 25645 debugger with breakpoints, not by pure deduction from a series of 25646 examples. We recommend that you save your time for something else. 25647 25648 Of course, if you can find a simpler example to report _instead_ of 25649 the original one, that is a convenience for us. Errors in the 25650 output will be easier to spot, running under the debugger will take 25651 less time, and so on. 25652 25653 However, simplification is not vital; if you do not want to do 25654 this, report the bug anyway and send us the entire test case you 25655 used. 25656 25657 * A patch for the bug. 25658 25659 A patch for the bug does help us if it is a good one. But do not 25660 omit the necessary information, such as the test case, on the 25661 assumption that a patch is all we need. We might see problems with 25662 your patch and decide to fix the problem another way, or we might 25663 not understand it at all. 25664 25665 Sometimes with a program as complicated as 'as' it is very hard to 25666 construct an example that will make the program follow a certain 25667 path through the code. If you do not send us the example, we will 25668 not be able to construct one, so we will not be able to verify that 25669 the bug is fixed. 25670 25671 And if we cannot understand what bug you are trying to fix, or why 25672 your patch should be an improvement, we will not install it. A 25673 test case will help us to understand. 25674 25675 * A guess about what the bug is or what it depends on. 25676 25677 Such guesses are usually wrong. Even we cannot guess right about 25678 such things without first using the debugger to find the facts. 25679 25680 25681File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 25682 2568311 Acknowledgements 25684******************* 25685 25686If you have contributed to GAS and your name isn't listed here, it is 25687not meant as a slight. We just don't know about it. Send mail to the 25688maintainer, and we'll correct the situation. Currently the maintainer 25689is Nick Clifton (email address 'nickc@redhat.com'). 25690 25691 Dean Elsner wrote the original GNU assembler for the VAX.(1) 25692 25693 Jay Fenlason maintained GAS for a while, adding support for 25694GDB-specific debug information and the 68k series machines, most of the 25695preprocessing pass, and extensive changes in 'messages.c', 25696'input-file.c', 'write.c'. 25697 25698 K. Richard Pixley maintained GAS for a while, adding various 25699enhancements and many bug fixes, including merging support for several 25700processors, breaking GAS up to handle multiple object file format back 25701ends (including heavy rewrite, testing, an integration of the coff and 25702b.out back ends), adding configuration including heavy testing and 25703verification of cross assemblers and file splits and renaming, converted 25704GAS to strictly ANSI C including full prototypes, added support for 25705m680[34]0 and cpu32, did considerable work on i960 including a COFF port 25706(including considerable amounts of reverse engineering), a SPARC opcode 25707file rewrite, DECstation, rs6000, and hp300hpux host ports, updated 25708"know" assertions and made them work, much other reorganization, 25709cleanup, and lint. 25710 25711 Ken Raeburn wrote the high-level BFD interface code to replace most 25712of the code in format-specific I/O modules. 25713 25714 The original VMS support was contributed by David L. Kashtan. Eric 25715Youngdale has done much work with it since. 25716 25717 The Intel 80386 machine description was written by Eliot Dresselhaus. 25718 25719 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 25720 25721 The Motorola 88k machine description was contributed by Devon Bowen 25722of Buffalo University and Torbjorn Granlund of the Swedish Institute of 25723Computer Science. 25724 25725 Keith Knowles at the Open Software Foundation wrote the original MIPS 25726back end ('tc-mips.c', 'tc-mips.h'), and contributed Rose format support 25727(which hasn't been merged in yet). Ralph Campbell worked with the MIPS 25728code to support a.out format. 25729 25730 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, 25731tc-h8300), and IEEE 695 object file format (obj-ieee), was written by 25732Steve Chamberlain of Cygnus Support. Steve also modified the COFF back 25733end to use BFD for some low-level operations, for use with the H8/300 25734and AMD 29k targets. 25735 25736 John Gilmore built the AMD 29000 support, added '.include' support, 25737and simplified the configuration of which versions accept which 25738directives. He updated the 68k machine description so that Motorola's 25739opcodes always produced fixed-size instructions (e.g., 'jsr'), while 25740synthetic instructions remained shrinkable ('jbsr'). John fixed many 25741bugs, including true tested cross-compilation support, and one bug in 25742relaxation that took a week and required the proverbial one-bit fix. 25743 25744 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax 25745for the 68k, completed support for some COFF targets (68k, i386 SVR3, 25746and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the 25747initial RS/6000 and PowerPC assembler, and made a few other minor 25748patches. 25749 25750 Steve Chamberlain made GAS able to generate listings. 25751 25752 Hewlett-Packard contributed support for the HP9000/300. 25753 25754 Jeff Law wrote GAS and BFD support for the native HPPA object format 25755(SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF 25756object formats). This work was supported by both the Center for 25757Software Science at the University of Utah and Cygnus Support. 25758 25759 Support for ELF format files has been worked on by Mark Eichin of 25760Cygnus Support (original, incomplete implementation for SPARC), Pete 25761Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael 25762Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn 25763of Cygnus Support (sparc, and some initial 64-bit support). 25764 25765 Linas Vepstas added GAS support for the ESA/390 "IBM 370" 25766architecture. 25767 25768 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 25769GAS and BFD support for openVMS/Alpha. 25770 25771 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 25772various tic* flavors. 25773 25774 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 25775Tensilica, Inc. added support for Xtensa processors. 25776 25777 Several engineers at Cygnus Support have also provided many small bug 25778fixes and configuration enhancements. 25779 25780 Jon Beniston added support for the Lattice Mico32 architecture. 25781 25782 Many others have contributed large or small bugfixes and 25783enhancements. If you have contributed significant work and are not 25784mentioned on this list, and want to be, let us know. Some of the 25785history has been lost; we are not intentionally leaving anyone out. 25786 25787 ---------- Footnotes ---------- 25788 25789 (1) Any more details? 25790 25791 25792File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top 25793 25794Appendix A GNU Free Documentation License 25795***************************************** 25796 25797 Version 1.3, 3 November 2008 25798 25799 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. 25800 <http://fsf.org/> 25801 25802 Everyone is permitted to copy and distribute verbatim copies 25803 of this license document, but changing it is not allowed. 25804 25805 0. PREAMBLE 25806 25807 The purpose of this License is to make a manual, textbook, or other 25808 functional and useful document "free" in the sense of freedom: to 25809 assure everyone the effective freedom to copy and redistribute it, 25810 with or without modifying it, either commercially or 25811 noncommercially. Secondarily, this License preserves for the 25812 author and publisher a way to get credit for their work, while not 25813 being considered responsible for modifications made by others. 25814 25815 This License is a kind of "copyleft", which means that derivative 25816 works of the document must themselves be free in the same sense. 25817 It complements the GNU General Public License, which is a copyleft 25818 license designed for free software. 25819 25820 We have designed this License in order to use it for manuals for 25821 free software, because free software needs free documentation: a 25822 free program should come with manuals providing the same freedoms 25823 that the software does. But this License is not limited to 25824 software manuals; it can be used for any textual work, regardless 25825 of subject matter or whether it is published as a printed book. We 25826 recommend this License principally for works whose purpose is 25827 instruction or reference. 25828 25829 1. APPLICABILITY AND DEFINITIONS 25830 25831 This License applies to any manual or other work, in any medium, 25832 that contains a notice placed by the copyright holder saying it can 25833 be distributed under the terms of this License. Such a notice 25834 grants a world-wide, royalty-free license, unlimited in duration, 25835 to use that work under the conditions stated herein. The 25836 "Document", below, refers to any such manual or work. Any member 25837 of the public is a licensee, and is addressed as "you". You accept 25838 the license if you copy, modify or distribute the work in a way 25839 requiring permission under copyright law. 25840 25841 A "Modified Version" of the Document means any work containing the 25842 Document or a portion of it, either copied verbatim, or with 25843 modifications and/or translated into another language. 25844 25845 A "Secondary Section" is a named appendix or a front-matter section 25846 of the Document that deals exclusively with the relationship of the 25847 publishers or authors of the Document to the Document's overall 25848 subject (or to related matters) and contains nothing that could 25849 fall directly within that overall subject. (Thus, if the Document 25850 is in part a textbook of mathematics, a Secondary Section may not 25851 explain any mathematics.) The relationship could be a matter of 25852 historical connection with the subject or with related matters, or 25853 of legal, commercial, philosophical, ethical or political position 25854 regarding them. 25855 25856 The "Invariant Sections" are certain Secondary Sections whose 25857 titles are designated, as being those of Invariant Sections, in the 25858 notice that says that the Document is released under this License. 25859 If a section does not fit the above definition of Secondary then it 25860 is not allowed to be designated as Invariant. The Document may 25861 contain zero Invariant Sections. If the Document does not identify 25862 any Invariant Sections then there are none. 25863 25864 The "Cover Texts" are certain short passages of text that are 25865 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 25866 that says that the Document is released under this License. A 25867 Front-Cover Text may be at most 5 words, and a Back-Cover Text may 25868 be at most 25 words. 25869 25870 A "Transparent" copy of the Document means a machine-readable copy, 25871 represented in a format whose specification is available to the 25872 general public, that is suitable for revising the document 25873 straightforwardly with generic text editors or (for images composed 25874 of pixels) generic paint programs or (for drawings) some widely 25875 available drawing editor, and that is suitable for input to text 25876 formatters or for automatic translation to a variety of formats 25877 suitable for input to text formatters. A copy made in an otherwise 25878 Transparent file format whose markup, or absence of markup, has 25879 been arranged to thwart or discourage subsequent modification by 25880 readers is not Transparent. An image format is not Transparent if 25881 used for any substantial amount of text. A copy that is not 25882 "Transparent" is called "Opaque". 25883 25884 Examples of suitable formats for Transparent copies include plain 25885 ASCII without markup, Texinfo input format, LaTeX input format, 25886 SGML or XML using a publicly available DTD, and standard-conforming 25887 simple HTML, PostScript or PDF designed for human modification. 25888 Examples of transparent image formats include PNG, XCF and JPG. 25889 Opaque formats include proprietary formats that can be read and 25890 edited only by proprietary word processors, SGML or XML for which 25891 the DTD and/or processing tools are not generally available, and 25892 the machine-generated HTML, PostScript or PDF produced by some word 25893 processors for output purposes only. 25894 25895 The "Title Page" means, for a printed book, the title page itself, 25896 plus such following pages as are needed to hold, legibly, the 25897 material this License requires to appear in the title page. For 25898 works in formats which do not have any title page as such, "Title 25899 Page" means the text near the most prominent appearance of the 25900 work's title, preceding the beginning of the body of the text. 25901 25902 The "publisher" means any person or entity that distributes copies 25903 of the Document to the public. 25904 25905 A section "Entitled XYZ" means a named subunit of the Document 25906 whose title either is precisely XYZ or contains XYZ in parentheses 25907 following text that translates XYZ in another language. (Here XYZ 25908 stands for a specific section name mentioned below, such as 25909 "Acknowledgements", "Dedications", "Endorsements", or "History".) 25910 To "Preserve the Title" of such a section when you modify the 25911 Document means that it remains a section "Entitled XYZ" according 25912 to this definition. 25913 25914 The Document may include Warranty Disclaimers next to the notice 25915 which states that this License applies to the Document. These 25916 Warranty Disclaimers are considered to be included by reference in 25917 this License, but only as regards disclaiming warranties: any other 25918 implication that these Warranty Disclaimers may have is void and 25919 has no effect on the meaning of this License. 25920 25921 2. VERBATIM COPYING 25922 25923 You may copy and distribute the Document in any medium, either 25924 commercially or noncommercially, provided that this License, the 25925 copyright notices, and the license notice saying this License 25926 applies to the Document are reproduced in all copies, and that you 25927 add no other conditions whatsoever to those of this License. You 25928 may not use technical measures to obstruct or control the reading 25929 or further copying of the copies you make or distribute. However, 25930 you may accept compensation in exchange for copies. If you 25931 distribute a large enough number of copies you must also follow the 25932 conditions in section 3. 25933 25934 You may also lend copies, under the same conditions stated above, 25935 and you may publicly display copies. 25936 25937 3. COPYING IN QUANTITY 25938 25939 If you publish printed copies (or copies in media that commonly 25940 have printed covers) of the Document, numbering more than 100, and 25941 the Document's license notice requires Cover Texts, you must 25942 enclose the copies in covers that carry, clearly and legibly, all 25943 these Cover Texts: Front-Cover Texts on the front cover, and 25944 Back-Cover Texts on the back cover. Both covers must also clearly 25945 and legibly identify you as the publisher of these copies. The 25946 front cover must present the full title with all words of the title 25947 equally prominent and visible. You may add other material on the 25948 covers in addition. Copying with changes limited to the covers, as 25949 long as they preserve the title of the Document and satisfy these 25950 conditions, can be treated as verbatim copying in other respects. 25951 25952 If the required texts for either cover are too voluminous to fit 25953 legibly, you should put the first ones listed (as many as fit 25954 reasonably) on the actual cover, and continue the rest onto 25955 adjacent pages. 25956 25957 If you publish or distribute Opaque copies of the Document 25958 numbering more than 100, you must either include a machine-readable 25959 Transparent copy along with each Opaque copy, or state in or with 25960 each Opaque copy a computer-network location from which the general 25961 network-using public has access to download using public-standard 25962 network protocols a complete Transparent copy of the Document, free 25963 of added material. If you use the latter option, you must take 25964 reasonably prudent steps, when you begin distribution of Opaque 25965 copies in quantity, to ensure that this Transparent copy will 25966 remain thus accessible at the stated location until at least one 25967 year after the last time you distribute an Opaque copy (directly or 25968 through your agents or retailers) of that edition to the public. 25969 25970 It is requested, but not required, that you contact the authors of 25971 the Document well before redistributing any large number of copies, 25972 to give them a chance to provide you with an updated version of the 25973 Document. 25974 25975 4. MODIFICATIONS 25976 25977 You may copy and distribute a Modified Version of the Document 25978 under the conditions of sections 2 and 3 above, provided that you 25979 release the Modified Version under precisely this License, with the 25980 Modified Version filling the role of the Document, thus licensing 25981 distribution and modification of the Modified Version to whoever 25982 possesses a copy of it. In addition, you must do these things in 25983 the Modified Version: 25984 25985 A. Use in the Title Page (and on the covers, if any) a title 25986 distinct from that of the Document, and from those of previous 25987 versions (which should, if there were any, be listed in the 25988 History section of the Document). You may use the same title 25989 as a previous version if the original publisher of that 25990 version gives permission. 25991 25992 B. List on the Title Page, as authors, one or more persons or 25993 entities responsible for authorship of the modifications in 25994 the Modified Version, together with at least five of the 25995 principal authors of the Document (all of its principal 25996 authors, if it has fewer than five), unless they release you 25997 from this requirement. 25998 25999 C. State on the Title page the name of the publisher of the 26000 Modified Version, as the publisher. 26001 26002 D. Preserve all the copyright notices of the Document. 26003 26004 E. Add an appropriate copyright notice for your modifications 26005 adjacent to the other copyright notices. 26006 26007 F. Include, immediately after the copyright notices, a license 26008 notice giving the public permission to use the Modified 26009 Version under the terms of this License, in the form shown in 26010 the Addendum below. 26011 26012 G. Preserve in that license notice the full lists of Invariant 26013 Sections and required Cover Texts given in the Document's 26014 license notice. 26015 26016 H. Include an unaltered copy of this License. 26017 26018 I. Preserve the section Entitled "History", Preserve its Title, 26019 and add to it an item stating at least the title, year, new 26020 authors, and publisher of the Modified Version as given on the 26021 Title Page. If there is no section Entitled "History" in the 26022 Document, create one stating the title, year, authors, and 26023 publisher of the Document as given on its Title Page, then add 26024 an item describing the Modified Version as stated in the 26025 previous sentence. 26026 26027 J. Preserve the network location, if any, given in the Document 26028 for public access to a Transparent copy of the Document, and 26029 likewise the network locations given in the Document for 26030 previous versions it was based on. These may be placed in the 26031 "History" section. You may omit a network location for a work 26032 that was published at least four years before the Document 26033 itself, or if the original publisher of the version it refers 26034 to gives permission. 26035 26036 K. For any section Entitled "Acknowledgements" or "Dedications", 26037 Preserve the Title of the section, and preserve in the section 26038 all the substance and tone of each of the contributor 26039 acknowledgements and/or dedications given therein. 26040 26041 L. Preserve all the Invariant Sections of the Document, unaltered 26042 in their text and in their titles. Section numbers or the 26043 equivalent are not considered part of the section titles. 26044 26045 M. Delete any section Entitled "Endorsements". Such a section 26046 may not be included in the Modified Version. 26047 26048 N. Do not retitle any existing section to be Entitled 26049 "Endorsements" or to conflict in title with any Invariant 26050 Section. 26051 26052 O. Preserve any Warranty Disclaimers. 26053 26054 If the Modified Version includes new front-matter sections or 26055 appendices that qualify as Secondary Sections and contain no 26056 material copied from the Document, you may at your option designate 26057 some or all of these sections as invariant. To do this, add their 26058 titles to the list of Invariant Sections in the Modified Version's 26059 license notice. These titles must be distinct from any other 26060 section titles. 26061 26062 You may add a section Entitled "Endorsements", provided it contains 26063 nothing but endorsements of your Modified Version by various 26064 parties--for example, statements of peer review or that the text 26065 has been approved by an organization as the authoritative 26066 definition of a standard. 26067 26068 You may add a passage of up to five words as a Front-Cover Text, 26069 and a passage of up to 25 words as a Back-Cover Text, to the end of 26070 the list of Cover Texts in the Modified Version. Only one passage 26071 of Front-Cover Text and one of Back-Cover Text may be added by (or 26072 through arrangements made by) any one entity. If the Document 26073 already includes a cover text for the same cover, previously added 26074 by you or by arrangement made by the same entity you are acting on 26075 behalf of, you may not add another; but you may replace the old 26076 one, on explicit permission from the previous publisher that added 26077 the old one. 26078 26079 The author(s) and publisher(s) of the Document do not by this 26080 License give permission to use their names for publicity for or to 26081 assert or imply endorsement of any Modified Version. 26082 26083 5. COMBINING DOCUMENTS 26084 26085 You may combine the Document with other documents released under 26086 this License, under the terms defined in section 4 above for 26087 modified versions, provided that you include in the combination all 26088 of the Invariant Sections of all of the original documents, 26089 unmodified, and list them all as Invariant Sections of your 26090 combined work in its license notice, and that you preserve all 26091 their Warranty Disclaimers. 26092 26093 The combined work need only contain one copy of this License, and 26094 multiple identical Invariant Sections may be replaced with a single 26095 copy. If there are multiple Invariant Sections with the same name 26096 but different contents, make the title of each such section unique 26097 by adding at the end of it, in parentheses, the name of the 26098 original author or publisher of that section if known, or else a 26099 unique number. Make the same adjustment to the section titles in 26100 the list of Invariant Sections in the license notice of the 26101 combined work. 26102 26103 In the combination, you must combine any sections Entitled 26104 "History" in the various original documents, forming one section 26105 Entitled "History"; likewise combine any sections Entitled 26106 "Acknowledgements", and any sections Entitled "Dedications". You 26107 must delete all sections Entitled "Endorsements." 26108 26109 6. COLLECTIONS OF DOCUMENTS 26110 26111 You may make a collection consisting of the Document and other 26112 documents released under this License, and replace the individual 26113 copies of this License in the various documents with a single copy 26114 that is included in the collection, provided that you follow the 26115 rules of this License for verbatim copying of each of the documents 26116 in all other respects. 26117 26118 You may extract a single document from such a collection, and 26119 distribute it individually under this License, provided you insert 26120 a copy of this License into the extracted document, and follow this 26121 License in all other respects regarding verbatim copying of that 26122 document. 26123 26124 7. AGGREGATION WITH INDEPENDENT WORKS 26125 26126 A compilation of the Document or its derivatives with other 26127 separate and independent documents or works, in or on a volume of a 26128 storage or distribution medium, is called an "aggregate" if the 26129 copyright resulting from the compilation is not used to limit the 26130 legal rights of the compilation's users beyond what the individual 26131 works permit. When the Document is included in an aggregate, this 26132 License does not apply to the other works in the aggregate which 26133 are not themselves derivative works of the Document. 26134 26135 If the Cover Text requirement of section 3 is applicable to these 26136 copies of the Document, then if the Document is less than one half 26137 of the entire aggregate, the Document's Cover Texts may be placed 26138 on covers that bracket the Document within the aggregate, or the 26139 electronic equivalent of covers if the Document is in electronic 26140 form. Otherwise they must appear on printed covers that bracket 26141 the whole aggregate. 26142 26143 8. TRANSLATION 26144 26145 Translation is considered a kind of modification, so you may 26146 distribute translations of the Document under the terms of section 26147 4. Replacing Invariant Sections with translations requires special 26148 permission from their copyright holders, but you may include 26149 translations of some or all Invariant Sections in addition to the 26150 original versions of these Invariant Sections. You may include a 26151 translation of this License, and all the license notices in the 26152 Document, and any Warranty Disclaimers, provided that you also 26153 include the original English version of this License and the 26154 original versions of those notices and disclaimers. In case of a 26155 disagreement between the translation and the original version of 26156 this License or a notice or disclaimer, the original version will 26157 prevail. 26158 26159 If a section in the Document is Entitled "Acknowledgements", 26160 "Dedications", or "History", the requirement (section 4) to 26161 Preserve its Title (section 1) will typically require changing the 26162 actual title. 26163 26164 9. TERMINATION 26165 26166 You may not copy, modify, sublicense, or distribute the Document 26167 except as expressly provided under this License. Any attempt 26168 otherwise to copy, modify, sublicense, or distribute it is void, 26169 and will automatically terminate your rights under this License. 26170 26171 However, if you cease all violation of this License, then your 26172 license from a particular copyright holder is reinstated (a) 26173 provisionally, unless and until the copyright holder explicitly and 26174 finally terminates your license, and (b) permanently, if the 26175 copyright holder fails to notify you of the violation by some 26176 reasonable means prior to 60 days after the cessation. 26177 26178 Moreover, your license from a particular copyright holder is 26179 reinstated permanently if the copyright holder notifies you of the 26180 violation by some reasonable means, this is the first time you have 26181 received notice of violation of this License (for any work) from 26182 that copyright holder, and you cure the violation prior to 30 days 26183 after your receipt of the notice. 26184 26185 Termination of your rights under this section does not terminate 26186 the licenses of parties who have received copies or rights from you 26187 under this License. If your rights have been terminated and not 26188 permanently reinstated, receipt of a copy of some or all of the 26189 same material does not give you any rights to use it. 26190 26191 10. FUTURE REVISIONS OF THIS LICENSE 26192 26193 The Free Software Foundation may publish new, revised versions of 26194 the GNU Free Documentation License from time to time. Such new 26195 versions will be similar in spirit to the present version, but may 26196 differ in detail to address new problems or concerns. See 26197 <http://www.gnu.org/copyleft/>. 26198 26199 Each version of the License is given a distinguishing version 26200 number. If the Document specifies that a particular numbered 26201 version of this License "or any later version" applies to it, you 26202 have the option of following the terms and conditions either of 26203 that specified version or of any later version that has been 26204 published (not as a draft) by the Free Software Foundation. If the 26205 Document does not specify a version number of this License, you may 26206 choose any version ever published (not as a draft) by the Free 26207 Software Foundation. If the Document specifies that a proxy can 26208 decide which future versions of this License can be used, that 26209 proxy's public statement of acceptance of a version permanently 26210 authorizes you to choose that version for the Document. 26211 26212 11. RELICENSING 26213 26214 "Massive Multiauthor Collaboration Site" (or "MMC Site") means any 26215 World Wide Web server that publishes copyrightable works and also 26216 provides prominent facilities for anybody to edit those works. A 26217 public wiki that anybody can edit is an example of such a server. 26218 A "Massive Multiauthor Collaboration" (or "MMC") contained in the 26219 site means any set of copyrightable works thus published on the MMC 26220 site. 26221 26222 "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0 26223 license published by Creative Commons Corporation, a not-for-profit 26224 corporation with a principal place of business in San Francisco, 26225 California, as well as future copyleft versions of that license 26226 published by that same organization. 26227 26228 "Incorporate" means to publish or republish a Document, in whole or 26229 in part, as part of another Document. 26230 26231 An MMC is "eligible for relicensing" if it is licensed under this 26232 License, and if all works that were first published under this 26233 License somewhere other than this MMC, and subsequently 26234 incorporated in whole or in part into the MMC, (1) had no cover 26235 texts or invariant sections, and (2) were thus incorporated prior 26236 to November 1, 2008. 26237 26238 The operator of an MMC Site may republish an MMC contained in the 26239 site under CC-BY-SA on the same site at any time before August 1, 26240 2009, provided the MMC is eligible for relicensing. 26241 26242ADDENDUM: How to use this License for your documents 26243==================================================== 26244 26245To use this License in a document you have written, include a copy of 26246the License in the document and put the following copyright and license 26247notices just after the title page: 26248 26249 Copyright (C) YEAR YOUR NAME. 26250 Permission is granted to copy, distribute and/or modify this document 26251 under the terms of the GNU Free Documentation License, Version 1.3 26252 or any later version published by the Free Software Foundation; 26253 with no Invariant Sections, no Front-Cover Texts, and no Back-Cover 26254 Texts. A copy of the license is included in the section entitled ``GNU 26255 Free Documentation License''. 26256 26257 If you have Invariant Sections, Front-Cover Texts and Back-Cover 26258Texts, replace the "with...Texts." line with this: 26259 26260 with the Invariant Sections being LIST THEIR TITLES, with 26261 the Front-Cover Texts being LIST, and with the Back-Cover Texts 26262 being LIST. 26263 26264 If you have Invariant Sections without Cover Texts, or some other 26265combination of the three, merge those two alternatives to suit the 26266situation. 26267 26268 If your document contains nontrivial examples of program code, we 26269recommend releasing these examples in parallel under your choice of free 26270software license, such as the GNU General Public License, to permit 26271their use in free software. 26272 26273 26274File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top 26275 26276AS Index 26277******** 26278 26279[index] 26280* Menu: 26281 26282* \" (doublequote character): Strings. (line 43) 26283* \b (backspace character): Strings. (line 15) 26284* \DDD (octal character code): Strings. (line 30) 26285* \f (formfeed character): Strings. (line 18) 26286* \n (newline character): Strings. (line 21) 26287* \r (carriage return character): Strings. (line 24) 26288* \t (tab): Strings. (line 27) 26289* \XD... (hex character code): Strings. (line 36) 26290* \\ (\ character): Strings. (line 40) 26291* #: Comments. (line 33) 26292* #APP: Preprocessing. (line 28) 26293* #NO_APP: Preprocessing. (line 28) 26294* $ in symbol names: D10V-Chars. (line 46) 26295* $ in symbol names <1>: D30V-Chars. (line 70) 26296* $ in symbol names <2>: Meta-Chars. (line 10) 26297* $ in symbol names <3>: SH-Chars. (line 15) 26298* $a: ARM Mapping Symbols. 26299 (line 9) 26300* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) 26301* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) 26302* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) 26303* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) 26304* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) 26305* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) 26306* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) 26307* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) 26308* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) 26309* $d: AArch64 Mapping Symbols. 26310 (line 12) 26311* $d <1>: ARM Mapping Symbols. 26312 (line 15) 26313* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) 26314* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) 26315* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) 26316* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) 26317* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) 26318* $int math builtin, TIC54X: TIC54X-Builtins. (line 50) 26319* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) 26320* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) 26321* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) 26322* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) 26323* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) 26324* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) 26325* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) 26326* $log math builtin, TIC54X: TIC54X-Builtins. (line 59) 26327* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) 26328* $max math builtin, TIC54X: TIC54X-Builtins. (line 62) 26329* $min math builtin, TIC54X: TIC54X-Builtins. (line 65) 26330* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) 26331* $round math builtin, TIC54X: TIC54X-Builtins. (line 71) 26332* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) 26333* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) 26334* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) 26335* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) 26336* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) 26337* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) 26338* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) 26339* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) 26340* $t: ARM Mapping Symbols. 26341 (line 12) 26342* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) 26343* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) 26344* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) 26345* $x: AArch64 Mapping Symbols. 26346 (line 9) 26347* %gp: RX-Modifiers. (line 6) 26348* %gpreg: RX-Modifiers. (line 22) 26349* %pidreg: RX-Modifiers. (line 25) 26350* -+ option, VAX/VMS: VAX-Opts. (line 71) 26351* --: Command Line. (line 10) 26352* --32 option, i386: i386-Options. (line 8) 26353* --32 option, x86-64: i386-Options. (line 8) 26354* --64 option, i386: i386-Options. (line 8) 26355* --64 option, x86-64: i386-Options. (line 8) 26356* --abi-call0: Xtensa Options. (line 82) 26357* --abi-windowed: Xtensa Options. (line 82) 26358* --absolute-literals: Xtensa Options. (line 39) 26359* --allow-reg-prefix: SH Options. (line 9) 26360* --alternate: alternate. (line 6) 26361* --auto-litpools: Xtensa Options. (line 22) 26362* --base-size-default-16: M68K-Opts. (line 66) 26363* --base-size-default-32: M68K-Opts. (line 66) 26364* --big: SH Options. (line 9) 26365* --bitwise-or option, M680x0: M68K-Opts. (line 59) 26366* --compress-debug-sections= option: Overview. (line 378) 26367* --disp-size-default-16: M68K-Opts. (line 75) 26368* --disp-size-default-32: M68K-Opts. (line 75) 26369* --divide option, i386: i386-Options. (line 25) 26370* --dsp: SH Options. (line 9) 26371* --emulation=crisaout command-line option, CRIS: CRIS-Opts. (line 9) 26372* --emulation=criself command-line option, CRIS: CRIS-Opts. (line 9) 26373* --enforce-aligned-data: Sparc-Aligned-Data. (line 11) 26374* --fatal-warnings: W. (line 16) 26375* --fdpic: SH Options. (line 31) 26376* --fix-v4bx command-line option, ARM: ARM Options. (line 380) 26377* --fixed-special-register-names command-line option, MMIX: MMIX-Opts. 26378 (line 8) 26379* --force-long-branches: M68HC11-Opts. (line 81) 26380* --generate-example: M68HC11-Opts. (line 98) 26381* --globalize-symbols command-line option, MMIX: MMIX-Opts. (line 12) 26382* --gnu-syntax command-line option, MMIX: MMIX-Opts. (line 16) 26383* --linker-allocated-gregs command-line option, MMIX: MMIX-Opts. 26384 (line 67) 26385* --listing-cont-lines: listing. (line 34) 26386* --listing-lhs-width: listing. (line 16) 26387* --listing-lhs-width2: listing. (line 21) 26388* --listing-rhs-width: listing. (line 28) 26389* --little: SH Options. (line 9) 26390* --longcalls: Xtensa Options. (line 53) 26391* --march=ARCHITECTURE command-line option, CRIS: CRIS-Opts. (line 34) 26392* --MD: MD. (line 6) 26393* --mul-bug-abort command-line option, CRIS: CRIS-Opts. (line 63) 26394* --no-absolute-literals: Xtensa Options. (line 39) 26395* --no-auto-litpools: Xtensa Options. (line 22) 26396* --no-expand command-line option, MMIX: MMIX-Opts. (line 31) 26397* --no-longcalls: Xtensa Options. (line 53) 26398* --no-merge-gregs command-line option, MMIX: MMIX-Opts. (line 36) 26399* --no-mul-bug-abort command-line option, CRIS: CRIS-Opts. (line 63) 26400* --no-pad-sections: no-pad-sections. (line 6) 26401* --no-predefined-syms command-line option, MMIX: MMIX-Opts. (line 22) 26402* --no-pushj-stubs command-line option, MMIX: MMIX-Opts. (line 54) 26403* --no-stubs command-line option, MMIX: MMIX-Opts. (line 54) 26404* --no-target-align: Xtensa Options. (line 46) 26405* --no-text-section-literals: Xtensa Options. (line 7) 26406* --no-trampolines: Xtensa Options. (line 74) 26407* --no-transform: Xtensa Options. (line 62) 26408* --no-underscore command-line option, CRIS: CRIS-Opts. (line 15) 26409* --no-warn: W. (line 11) 26410* --pcrel: M68K-Opts. (line 87) 26411* --pic command-line option, CRIS: CRIS-Opts. (line 27) 26412* --print-insn-syntax: M68HC11-Opts. (line 87) 26413* --print-insn-syntax <1>: XGATE-Opts. (line 25) 26414* --print-opcodes: M68HC11-Opts. (line 91) 26415* --print-opcodes <1>: XGATE-Opts. (line 29) 26416* --register-prefix-optional option, M680x0: M68K-Opts. (line 46) 26417* --relax: SH Options. (line 9) 26418* --relax command-line option, MMIX: MMIX-Opts. (line 19) 26419* --rename-section: Xtensa Options. (line 70) 26420* --renesas: SH Options. (line 9) 26421* --sectname-subst: Section. (line 71) 26422* --short-branches: M68HC11-Opts. (line 67) 26423* --small: SH Options. (line 9) 26424* --statistics: statistics. (line 6) 26425* --strict-direct-mode: M68HC11-Opts. (line 57) 26426* --target-align: Xtensa Options. (line 46) 26427* --text-section-literals: Xtensa Options. (line 7) 26428* --traditional-format: traditional-format. (line 6) 26429* --trampolines: Xtensa Options. (line 74) 26430* --transform: Xtensa Options. (line 62) 26431* --underscore command-line option, CRIS: CRIS-Opts. (line 15) 26432* --warn: W. (line 19) 26433* --x32 option, i386: i386-Options. (line 8) 26434* --x32 option, x86-64: i386-Options. (line 8) 26435* --xgate-ramoffset: M68HC11-Opts. (line 36) 26436* -1 option, VAX/VMS: VAX-Opts. (line 77) 26437* -32addr command-line option, Alpha: Alpha Options. (line 57) 26438* -a: a. (line 6) 26439* -ac: a. (line 6) 26440* -ad: a. (line 6) 26441* -ag: a. (line 6) 26442* -ah: a. (line 6) 26443* -al: a. (line 6) 26444* -Aleon: Sparc-Opts. (line 25) 26445* -an: a. (line 6) 26446* -as: a. (line 6) 26447* -Asparc: Sparc-Opts. (line 25) 26448* -Asparcfmaf: Sparc-Opts. (line 25) 26449* -Asparcima: Sparc-Opts. (line 25) 26450* -Asparclet: Sparc-Opts. (line 25) 26451* -Asparclite: Sparc-Opts. (line 25) 26452* -Asparcvis: Sparc-Opts. (line 25) 26453* -Asparcvis2: Sparc-Opts. (line 25) 26454* -Asparcvis3: Sparc-Opts. (line 25) 26455* -Asparcvis3r: Sparc-Opts. (line 25) 26456* -Av6: Sparc-Opts. (line 25) 26457* -Av7: Sparc-Opts. (line 25) 26458* -Av8: Sparc-Opts. (line 25) 26459* -Av9: Sparc-Opts. (line 25) 26460* -Av9a: Sparc-Opts. (line 25) 26461* -Av9b: Sparc-Opts. (line 25) 26462* -Av9c: Sparc-Opts. (line 25) 26463* -Av9d: Sparc-Opts. (line 25) 26464* -Av9e: Sparc-Opts. (line 25) 26465* -Av9m: Sparc-Opts. (line 25) 26466* -Av9v: Sparc-Opts. (line 25) 26467* -big option, M32R: M32R-Opts. (line 35) 26468* -colonless command-line option, Z80: Z80 Options. (line 33) 26469* -D: D. (line 6) 26470* -D, ignored on VAX: VAX-Opts. (line 11) 26471* -d, VAX option: VAX-Opts. (line 16) 26472* -eabi= command-line option, ARM: ARM Options. (line 356) 26473* -EB command-line option, AArch64: AArch64 Options. (line 6) 26474* -EB command-line option, ARC: ARC Options. (line 84) 26475* -EB command-line option, ARM: ARM Options. (line 361) 26476* -EB command-line option, BPF: BPF Options. (line 6) 26477* -EB option (MIPS): MIPS Options. (line 13) 26478* -EB option, M32R: M32R-Opts. (line 39) 26479* -EB option, TILE-Gx: TILE-Gx Options. (line 11) 26480* -EL command-line option, AArch64: AArch64 Options. (line 10) 26481* -EL command-line option, ARC: ARC Options. (line 88) 26482* -EL command-line option, ARM: ARM Options. (line 372) 26483* -EL command-line option, BPF: BPF Options. (line 10) 26484* -EL option (MIPS): MIPS Options. (line 13) 26485* -EL option, M32R: M32R-Opts. (line 32) 26486* -EL option, TILE-Gx: TILE-Gx Options. (line 11) 26487* -f: f. (line 6) 26488* -F command-line option, Alpha: Alpha Options. (line 57) 26489* -fno-pic option, RISC-V: RISC-V-Options. (line 12) 26490* -fp-d command-line option, Z80: Z80 Options. (line 44) 26491* -fp-s command-line option, Z80: Z80 Options. (line 40) 26492* -fpic option, RISC-V: RISC-V-Options. (line 8) 26493* -g command-line option, Alpha: Alpha Options. (line 47) 26494* -G command-line option, Alpha: Alpha Options. (line 53) 26495* -G option (MIPS): MIPS Options. (line 8) 26496* -h option, VAX/VMS: VAX-Opts. (line 45) 26497* -H option, VAX/VMS: VAX-Opts. (line 81) 26498* -I PATH: I. (line 6) 26499* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 26500* -Ip option, M32RX: M32R-Opts. (line 97) 26501* -J, ignored on VAX: VAX-Opts. (line 27) 26502* -K: K. (line 6) 26503* -k command-line option, ARM: ARM Options. (line 376) 26504* -KPIC option, M32R: M32R-Opts. (line 42) 26505* -KPIC option, MIPS: MIPS Options. (line 21) 26506* -L: L. (line 6) 26507* -l option, M680x0: M68K-Opts. (line 34) 26508* -little option, M32R: M32R-Opts. (line 27) 26509* -local-prefix command-line option, Z80: Z80 Options. (line 28) 26510* -M: M. (line 6) 26511* -m11/03: PDP-11-Options. (line 140) 26512* -m11/04: PDP-11-Options. (line 143) 26513* -m11/05: PDP-11-Options. (line 146) 26514* -m11/10: PDP-11-Options. (line 146) 26515* -m11/15: PDP-11-Options. (line 149) 26516* -m11/20: PDP-11-Options. (line 149) 26517* -m11/21: PDP-11-Options. (line 152) 26518* -m11/23: PDP-11-Options. (line 155) 26519* -m11/24: PDP-11-Options. (line 155) 26520* -m11/34: PDP-11-Options. (line 158) 26521* -m11/34a: PDP-11-Options. (line 161) 26522* -m11/35: PDP-11-Options. (line 164) 26523* -m11/40: PDP-11-Options. (line 164) 26524* -m11/44: PDP-11-Options. (line 167) 26525* -m11/45: PDP-11-Options. (line 170) 26526* -m11/50: PDP-11-Options. (line 170) 26527* -m11/53: PDP-11-Options. (line 173) 26528* -m11/55: PDP-11-Options. (line 170) 26529* -m11/60: PDP-11-Options. (line 176) 26530* -m11/70: PDP-11-Options. (line 170) 26531* -m11/73: PDP-11-Options. (line 173) 26532* -m11/83: PDP-11-Options. (line 173) 26533* -m11/84: PDP-11-Options. (line 173) 26534* -m11/93: PDP-11-Options. (line 173) 26535* -m11/94: PDP-11-Options. (line 173) 26536* -m16c option, M16C: M32C-Opts. (line 12) 26537* -m31 option, s390: s390 Options. (line 8) 26538* -m32 option, TILE-Gx: TILE-Gx Options. (line 8) 26539* -m32bit-doubles: RX-Opts. (line 9) 26540* -m32c option, M32C: M32C-Opts. (line 9) 26541* -m32r option, M32R: M32R-Opts. (line 21) 26542* -m32rx option, M32R2: M32R-Opts. (line 17) 26543* -m32rx option, M32RX: M32R-Opts. (line 9) 26544* -m4byte-align command-line option, V850: V850 Options. (line 90) 26545* -m64 option, s390: s390 Options. (line 8) 26546* -m64 option, TILE-Gx: TILE-Gx Options. (line 8) 26547* -m64bit-doubles: RX-Opts. (line 15) 26548* -m68000 and related options: M68K-Opts. (line 99) 26549* -m68hc11: M68HC11-Opts. (line 9) 26550* -m68hc12: M68HC11-Opts. (line 14) 26551* -m68hcs12: M68HC11-Opts. (line 21) 26552* -m8byte-align command-line option, V850: V850 Options. (line 86) 26553* -mabi= command-line option, AArch64: AArch64 Options. (line 14) 26554* -mabi=ABI option, RISC-V: RISC-V-Options. (line 33) 26555* -madd-bnd-prefix option, i386: i386-Options. (line 159) 26556* -madd-bnd-prefix option, x86-64: i386-Options. (line 159) 26557* -malign-branch-boundary= option, i386: i386-Options. (line 205) 26558* -malign-branch-boundary= option, x86-64: i386-Options. (line 205) 26559* -malign-branch-prefix-size= option, i386: i386-Options. (line 220) 26560* -malign-branch-prefix-size= option, x86-64: i386-Options. (line 220) 26561* -malign-branch= option, i386: i386-Options. (line 212) 26562* -malign-branch= option, x86-64: i386-Options. (line 212) 26563* -mall: PDP-11-Options. (line 26) 26564* -mall-enabled command-line option, LM32: LM32 Options. (line 30) 26565* -mall-extensions: PDP-11-Options. (line 26) 26566* -mall-opcodes command-line option, AVR: AVR Options. (line 111) 26567* -mamd64 option, x86-64: i386-Options. (line 290) 26568* -mapcs-26 command-line option, ARM: ARM Options. (line 328) 26569* -mapcs-32 command-line option, ARM: ARM Options. (line 328) 26570* -mapcs-float command-line option, ARM: ARM Options. (line 342) 26571* -mapcs-reentrant command-line option, ARM: ARM Options. (line 347) 26572* -march-attr option, RISC-V: RISC-V-Options. (line 48) 26573* -march= command-line option, AArch64: AArch64 Options. (line 43) 26574* -march= command-line option, ARM: ARM Options. (line 85) 26575* -march= command-line option, M680x0: M68K-Opts. (line 8) 26576* -march= command-line option, TIC6X: TIC6X Options. (line 6) 26577* -march= command-line option, Z80: Z80 Options. (line 6) 26578* -march= option, i386: i386-Options. (line 32) 26579* -march= option, s390: s390 Options. (line 25) 26580* -march= option, x86-64: i386-Options. (line 32) 26581* -march=ISA option, RISC-V: RISC-V-Options. (line 15) 26582* -matpcs command-line option, ARM: ARM Options. (line 334) 26583* -mavxscalar= option, i386: i386-Options. (line 104) 26584* -mavxscalar= option, x86-64: i386-Options. (line 104) 26585* -mbarrel-shift-enabled command-line option, LM32: LM32 Options. 26586 (line 12) 26587* -mbig-endian: RX-Opts. (line 20) 26588* -mbig-endian option, RISC-V: RISC-V-Options. (line 71) 26589* -mbig-obj option, i386: i386-Options. (line 173) 26590* -mbig-obj option, x86-64: i386-Options. (line 173) 26591* -mbranches-within-32B-boundaries option, i386: i386-Options. 26592 (line 225) 26593* -mbranches-within-32B-boundaries option, x86-64: i386-Options. 26594 (line 225) 26595* -mbreak-enabled command-line option, LM32: LM32 Options. (line 27) 26596* -mccs command-line option, ARM: ARM Options. (line 389) 26597* -mcis: PDP-11-Options. (line 32) 26598* -mcode-density command-line option, ARC: ARC Options. (line 93) 26599* -mconstant-gp command-line option, IA-64: IA-64 Options. (line 6) 26600* -mCPU command-line option, Alpha: Alpha Options. (line 6) 26601* -mcpu option, cpu: TIC54X-Opts. (line 15) 26602* -mcpu=: RX-Opts. (line 75) 26603* -mcpu= command-line option, AArch64: AArch64 Options. (line 19) 26604* -mcpu= command-line option, ARM: ARM Options. (line 6) 26605* -mcpu= command-line option, Blackfin: Blackfin Options. (line 6) 26606* -mcpu= command-line option, M680x0: M68K-Opts. (line 14) 26607* -mcpu=CPU command-line option, ARC: ARC Options. (line 10) 26608* -mcsm: PDP-11-Options. (line 43) 26609* -mcsr-check option, RISC-V: RISC-V-Options. (line 60) 26610* -mdcache-enabled command-line option, LM32: LM32 Options. (line 24) 26611* -mdebug command-line option, Alpha: Alpha Options. (line 25) 26612* -mdivide-enabled command-line option, LM32: LM32 Options. (line 9) 26613* -mdollar-hex option, dollar-hex: S12Z Options. (line 17) 26614* -mdpfp command-line option, ARC: ARC Options. (line 108) 26615* -mdsbt command-line option, TIC6X: TIC6X Options. (line 13) 26616* -me option, stderr redirect: TIC54X-Opts. (line 20) 26617* -meis: PDP-11-Options. (line 46) 26618* -mepiphany command-line option, Epiphany: Epiphany Options. 26619 (line 9) 26620* -mepiphany16 command-line option, Epiphany: Epiphany Options. 26621 (line 13) 26622* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) 26623* -mesa option, s390: s390 Options. (line 17) 26624* -mevexlig= option, i386: i386-Options. (line 125) 26625* -mevexlig= option, x86-64: i386-Options. (line 125) 26626* -mevexrcig= option, i386: i386-Options. (line 280) 26627* -mevexrcig= option, x86-64: i386-Options. (line 280) 26628* -mevexwig= option, i386: i386-Options. (line 135) 26629* -mevexwig= option, x86-64: i386-Options. (line 135) 26630* -mf option, far-mode: TIC54X-Opts. (line 8) 26631* -mf11: PDP-11-Options. (line 122) 26632* -mfar-mode option, far-mode: TIC54X-Opts. (line 8) 26633* -mfdpic command-line option, Blackfin: Blackfin Options. (line 19) 26634* -mfence-as-lock-add= option, i386: i386-Options. (line 186) 26635* -mfence-as-lock-add= option, x86-64: i386-Options. (line 186) 26636* -mfis: PDP-11-Options. (line 51) 26637* -mfloat-abi= command-line option, ARM: ARM Options. (line 351) 26638* -mfp-11: PDP-11-Options. (line 56) 26639* -mfp16-format= command-line option: ARM Options. (line 289) 26640* -mfpp: PDP-11-Options. (line 56) 26641* -mfpu: PDP-11-Options. (line 56) 26642* -mfpu= command-line option, ARM: ARM Options. (line 265) 26643* -mfpuda command-line option, ARC: ARC Options. (line 111) 26644* -mgcc-abi: RX-Opts. (line 63) 26645* -mgcc-abi command-line option, V850: V850 Options. (line 79) 26646* -mgcc-isr command-line option, AVR: AVR Options. (line 132) 26647* -mhard-float command-line option, V850: V850 Options. (line 101) 26648* -micache-enabled command-line option, LM32: LM32 Options. (line 21) 26649* -mimplicit-it command-line option, ARM: ARM Options. (line 312) 26650* -mint-register: RX-Opts. (line 57) 26651* -mintel64 option, x86-64: i386-Options. (line 290) 26652* -mip2022 option, IP2K: IP2K-Opts. (line 14) 26653* -mip2022ext option, IP2022: IP2K-Opts. (line 9) 26654* -misa-spec=ISAspec option, RISC-V: RISC-V-Options. (line 21) 26655* -mj11: PDP-11-Options. (line 126) 26656* -mka11: PDP-11-Options. (line 92) 26657* -mkb11: PDP-11-Options. (line 95) 26658* -mkd11a: PDP-11-Options. (line 98) 26659* -mkd11b: PDP-11-Options. (line 101) 26660* -mkd11d: PDP-11-Options. (line 104) 26661* -mkd11e: PDP-11-Options. (line 107) 26662* -mkd11f: PDP-11-Options. (line 110) 26663* -mkd11h: PDP-11-Options. (line 110) 26664* -mkd11k: PDP-11-Options. (line 114) 26665* -mkd11q: PDP-11-Options. (line 110) 26666* -mkd11z: PDP-11-Options. (line 118) 26667* -mkev11: PDP-11-Options. (line 51) 26668* -mkev11 <1>: PDP-11-Options. (line 51) 26669* -mlfence-after-load= option, i386: i386-Options. (line 233) 26670* -mlfence-after-load= option, x86-64: i386-Options. (line 233) 26671* -mlfence-before-indirect-branch= option, i386: i386-Options. 26672 (line 240) 26673* -mlfence-before-indirect-branch= option, x86-64: i386-Options. 26674 (line 240) 26675* -mlfence-before-ret= option, i386: i386-Options. (line 260) 26676* -mlfence-before-ret= option, x86-64: i386-Options. (line 260) 26677* -mlimited-eis: PDP-11-Options. (line 64) 26678* -mlink-relax command-line option, AVR: AVR Options. (line 123) 26679* -mlittle-endian: RX-Opts. (line 26) 26680* -mlittle-endian option, RISC-V: RISC-V-Options. (line 68) 26681* -mlong: M68HC11-Opts. (line 45) 26682* -mlong <1>: XGATE-Opts. (line 13) 26683* -mlong-double: M68HC11-Opts. (line 53) 26684* -mlong-double <1>: XGATE-Opts. (line 21) 26685* -mm9s12x: M68HC11-Opts. (line 27) 26686* -mm9s12xg: M68HC11-Opts. (line 32) 26687* -mmcu= command-line option, AVR: AVR Options. (line 6) 26688* -mmfpt: PDP-11-Options. (line 70) 26689* -mmicrocode: PDP-11-Options. (line 83) 26690* -mmnemonic= option, i386: i386-Options. (line 142) 26691* -mmnemonic= option, x86-64: i386-Options. (line 142) 26692* -mmultiply-enabled command-line option, LM32: LM32 Options. 26693 (line 6) 26694* -mmutiproc: PDP-11-Options. (line 73) 26695* -mmxps: PDP-11-Options. (line 77) 26696* -mnaked-reg option, i386: i386-Options. (line 154) 26697* -mnaked-reg option, x86-64: i386-Options. (line 154) 26698* -mnan= command-line option, MIPS: MIPS Options. (line 439) 26699* -mno-allow-string-insns: RX-Opts. (line 82) 26700* -mno-arch-attr option, RISC-V: RISC-V-Options. (line 56) 26701* -mno-cis: PDP-11-Options. (line 32) 26702* -mno-csm: PDP-11-Options. (line 43) 26703* -mno-csr-check option, RISC-V: RISC-V-Options. (line 65) 26704* -mno-dsbt command-line option, TIC6X: TIC6X Options. (line 13) 26705* -mno-eis: PDP-11-Options. (line 46) 26706* -mno-extensions: PDP-11-Options. (line 29) 26707* -mno-fdpic command-line option, Blackfin: Blackfin Options. 26708 (line 22) 26709* -mno-fis: PDP-11-Options. (line 51) 26710* -mno-fp-11: PDP-11-Options. (line 56) 26711* -mno-fpp: PDP-11-Options. (line 56) 26712* -mno-fpu: PDP-11-Options. (line 56) 26713* -mno-kev11: PDP-11-Options. (line 51) 26714* -mno-limited-eis: PDP-11-Options. (line 64) 26715* -mno-link-relax command-line option, AVR: AVR Options. (line 127) 26716* -mno-mfpt: PDP-11-Options. (line 70) 26717* -mno-microcode: PDP-11-Options. (line 83) 26718* -mno-mutiproc: PDP-11-Options. (line 73) 26719* -mno-mxps: PDP-11-Options. (line 77) 26720* -mno-pic: PDP-11-Options. (line 11) 26721* -mno-pic command-line option, TIC6X: TIC6X Options. (line 36) 26722* -mno-regnames option, s390: s390 Options. (line 51) 26723* -mno-relax option, RISC-V: RISC-V-Options. (line 45) 26724* -mno-skip-bug command-line option, AVR: AVR Options. (line 114) 26725* -mno-spl: PDP-11-Options. (line 80) 26726* -mno-sym32: MIPS Options. (line 348) 26727* -mno-verbose-error command-line option, AArch64: AArch64 Options. 26728 (line 64) 26729* -mno-wrap command-line option, AVR: AVR Options. (line 117) 26730* -mnopic command-line option, Blackfin: Blackfin Options. (line 22) 26731* -mnps400 command-line option, ARC: ARC Options. (line 102) 26732* -momit-lock-prefix= option, i386: i386-Options. (line 177) 26733* -momit-lock-prefix= option, x86-64: i386-Options. (line 177) 26734* -mpic: PDP-11-Options. (line 11) 26735* -mpic command-line option, TIC6X: TIC6X Options. (line 36) 26736* -mpid: RX-Opts. (line 50) 26737* -mpid= command-line option, TIC6X: TIC6X Options. (line 23) 26738* -mpriv-spec=PRIVspec option, RISC-V: RISC-V-Options. (line 27) 26739* -mreg-prefix=PREFIX option, reg-prefix: S12Z Options. (line 9) 26740* -mregnames option, s390: s390 Options. (line 48) 26741* -mrelax command-line option, ARC: ARC Options. (line 97) 26742* -mrelax command-line option, V850: V850 Options. (line 72) 26743* -mrelax option, RISC-V: RISC-V-Options. (line 41) 26744* -mrelax-relocations= option, i386: i386-Options. (line 195) 26745* -mrelax-relocations= option, x86-64: i386-Options. (line 195) 26746* -mrh850-abi command-line option, V850: V850 Options. (line 82) 26747* -mrmw command-line option, AVR: AVR Options. (line 120) 26748* -mrx-abi: RX-Opts. (line 69) 26749* -mshared option, i386: i386-Options. (line 164) 26750* -mshared option, x86-64: i386-Options. (line 164) 26751* -mshort: M68HC11-Opts. (line 40) 26752* -mshort <1>: XGATE-Opts. (line 8) 26753* -mshort-double: M68HC11-Opts. (line 49) 26754* -mshort-double <1>: XGATE-Opts. (line 17) 26755* -msign-extend-enabled command-line option, LM32: LM32 Options. 26756 (line 15) 26757* -msmall-data-limit: RX-Opts. (line 42) 26758* -msoft-float command-line option, V850: V850 Options. (line 95) 26759* -mspfp command-line option, ARC: ARC Options. (line 105) 26760* -mspl: PDP-11-Options. (line 80) 26761* -msse-check= option, i386: i386-Options. (line 94) 26762* -msse-check= option, x86-64: i386-Options. (line 94) 26763* -msse2avx option, i386: i386-Options. (line 90) 26764* -msse2avx option, x86-64: i386-Options. (line 90) 26765* -msym32: MIPS Options. (line 348) 26766* -msyntax= option, i386: i386-Options. (line 148) 26767* -msyntax= option, x86-64: i386-Options. (line 148) 26768* -mt11: PDP-11-Options. (line 130) 26769* -mthumb command-line option, ARM: ARM Options. (line 302) 26770* -mthumb-interwork command-line option, ARM: ARM Options. (line 307) 26771* -mtune= option, i386: i386-Options. (line 82) 26772* -mtune= option, x86-64: i386-Options. (line 82) 26773* -mtune=ARCH command-line option, Visium: Visium Options. (line 8) 26774* -muse-conventional-section-names: RX-Opts. (line 33) 26775* -muse-renesas-section-names: RX-Opts. (line 37) 26776* -muser-enabled command-line option, LM32: LM32 Options. (line 18) 26777* -mv850 command-line option, V850: V850 Options. (line 23) 26778* -mv850any command-line option, V850: V850 Options. (line 41) 26779* -mv850e command-line option, V850: V850 Options. (line 29) 26780* -mv850e1 command-line option, V850: V850 Options. (line 35) 26781* -mv850e2 command-line option, V850: V850 Options. (line 51) 26782* -mv850e2v3 command-line option, V850: V850 Options. (line 57) 26783* -mv850e2v4 command-line option, V850: V850 Options. (line 63) 26784* -mv850e3v5 command-line option, V850: V850 Options. (line 66) 26785* -mverbose-error command-line option, AArch64: AArch64 Options. 26786 (line 60) 26787* -mvexwig= option, i386: i386-Options. (line 115) 26788* -mvexwig= option, x86-64: i386-Options. (line 115) 26789* -mvxworks-pic option, MIPS: MIPS Options. (line 26) 26790* -mwarn-areg-zero option, s390: s390 Options. (line 54) 26791* -mwarn-deprecated command-line option, ARM: ARM Options. (line 384) 26792* -mwarn-syms command-line option, ARM: ARM Options. (line 392) 26793* -mx86-used-note= option, i386: i386-Options. (line 273) 26794* -mx86-used-note= option, x86-64: i386-Options. (line 273) 26795* -mzarch option, s390: s390 Options. (line 17) 26796* -m[no-]68851 command-line option, M680x0: M68K-Opts. (line 21) 26797* -m[no-]68881 command-line option, M680x0: M68K-Opts. (line 21) 26798* -m[no-]div command-line option, M680x0: M68K-Opts. (line 21) 26799* -m[no-]emac command-line option, M680x0: M68K-Opts. (line 21) 26800* -m[no-]float command-line option, M680x0: M68K-Opts. (line 21) 26801* -m[no-]mac command-line option, M680x0: M68K-Opts. (line 21) 26802* -m[no-]usp command-line option, M680x0: M68K-Opts. (line 21) 26803* -N command-line option, CRIS: CRIS-Opts. (line 59) 26804* -nIp option, M32RX: M32R-Opts. (line 101) 26805* -no-bitinst, M32R2: M32R-Opts. (line 54) 26806* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) 26807* -no-mdebug command-line option, Alpha: Alpha Options. (line 25) 26808* -no-parallel option, M32RX: M32R-Opts. (line 51) 26809* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 26810 (line 79) 26811* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) 26812* -nocpp ignored (MIPS): MIPS Options. (line 351) 26813* -noreplace command-line option, Alpha: Alpha Options. (line 40) 26814* -o: o. (line 6) 26815* -O option, i386: i386-Options. (line 296) 26816* -O option, M32RX: M32R-Opts. (line 59) 26817* -O option, x86-64: i386-Options. (line 296) 26818* -O0 option, i386: i386-Options. (line 296) 26819* -O0 option, x86-64: i386-Options. (line 296) 26820* -O1 option, i386: i386-Options. (line 296) 26821* -O1 option, x86-64: i386-Options. (line 296) 26822* -O2 option, i386: i386-Options. (line 296) 26823* -O2 option, x86-64: i386-Options. (line 296) 26824* -Os option, i386: i386-Options. (line 296) 26825* -Os option, x86-64: i386-Options. (line 296) 26826* -parallel option, M32RX: M32R-Opts. (line 46) 26827* -R: R. (line 6) 26828* -relax command-line option, Alpha: Alpha Options. (line 32) 26829* -replace command-line option, Alpha: Alpha Options. (line 40) 26830* -S, ignored on VAX: VAX-Opts. (line 11) 26831* -sdcc command-line option, Z80: Z80 Options. (line 37) 26832* -T, ignored on VAX: VAX-Opts. (line 11) 26833* -t, ignored on VAX: VAX-Opts. (line 36) 26834* -v: v. (line 6) 26835* -V, redundant on VAX: VAX-Opts. (line 22) 26836* -version: v. (line 6) 26837* -W: W. (line 11) 26838* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 26839 (line 65) 26840* -warn-unmatched-high option, M32R: M32R-Opts. (line 105) 26841* -Wnp option, M32RX: M32R-Opts. (line 83) 26842* -Wnuh option, M32RX: M32R-Opts. (line 117) 26843* -Wp option, M32RX: M32R-Opts. (line 75) 26844* -wsigned_overflow command-line option, V850: V850 Options. (line 9) 26845* -Wuh option, M32RX: M32R-Opts. (line 114) 26846* -wunsigned_overflow command-line option, V850: V850 Options. 26847 (line 16) 26848* -x command-line option, MMIX: MMIX-Opts. (line 44) 26849* -z8001 command-line option, Z8000: Z8000 Options. (line 6) 26850* -z8002 command-line option, Z8000: Z8000 Options. (line 9) 26851* . (symbol): Dot. (line 6) 26852* .align directive, ARM: ARM Directives. (line 6) 26853* .align directive, TILE-Gx: TILE-Gx Directives. (line 6) 26854* .align directive, TILEPro: TILEPro Directives. (line 6) 26855* .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives. 26856 (line 10) 26857* .allow_suspicious_bundles directive, TILEPro: TILEPro Directives. 26858 (line 10) 26859* .arch directive, AArch64: AArch64 Directives. (line 6) 26860* .arch directive, ARM: ARM Directives. (line 13) 26861* .arch directive, TIC6X: TIC6X Directives. (line 10) 26862* .arch_extension directive, AArch64: AArch64 Directives. (line 13) 26863* .arch_extension directive, ARM: ARM Directives. (line 21) 26864* .arc_attribute directive, ARC: ARC Directives. (line 240) 26865* .arm directive, ARM: ARM Directives. (line 30) 26866* .assume directive, Z80: Z80 Directives. (line 12) 26867* .attribute directive, RISC-V: RISC-V-Directives. (line 100) 26868* .big directive, M32RX: M32R-Directives. (line 88) 26869* .bss directive, AArch64: AArch64 Directives. (line 21) 26870* .bss directive, ARM: ARM Directives. (line 33) 26871* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20) 26872* .cantunwind directive, ARM: ARM Directives. (line 36) 26873* .cantunwind directive, TIC6X: TIC6X Directives. (line 13) 26874* .cfi_b_key_frame directive, AArch64: AArch64 Directives. (line 99) 26875* .code directive, ARM: ARM Directives. (line 40) 26876* .cpu directive, AArch64: AArch64 Directives. (line 24) 26877* .cpu directive, ARM: ARM Directives. (line 44) 26878* .dn and .qn directives, ARM: ARM Directives. (line 52) 26879* .dword directive, AArch64: AArch64 Directives. (line 28) 26880* .eabi_attribute directive, ARM: ARM Directives. (line 76) 26881* .ehtype directive, TIC6X: TIC6X Directives. (line 31) 26882* .endp directive, TIC6X: TIC6X Directives. (line 34) 26883* .even directive, AArch64: AArch64 Directives. (line 31) 26884* .even directive, ARM: ARM Directives. (line 105) 26885* .extend directive, ARM: ARM Directives. (line 108) 26886* .float16 directive, AArch64: AArch64 Directives. (line 35) 26887* .float16 directive, ARM: ARM Directives. (line 114) 26888* .float16_format directive, ARM: ARM Directives. (line 122) 26889* .fnend directive, ARM: ARM Directives. (line 129) 26890* .fnstart directive, ARM: ARM Directives. (line 137) 26891* .force_thumb directive, ARM: ARM Directives. (line 140) 26892* .fpu directive, ARM: ARM Directives. (line 144) 26893* .global: MIPS insn. (line 12) 26894* .gnu_attribute 4, N directive, MIPS: MIPS FP ABI History. 26895 (line 6) 26896* .gnu_attribute Tag_GNU_MIPS_ABI_FP, N directive, MIPS: MIPS FP ABI History. 26897 (line 6) 26898* .handlerdata directive, ARM: ARM Directives. (line 148) 26899* .handlerdata directive, TIC6X: TIC6X Directives. (line 39) 26900* .insn: MIPS insn. (line 6) 26901* .insn directive, s390: s390 Directives. (line 11) 26902* .inst directive, AArch64: AArch64 Directives. (line 41) 26903* .inst directive, ARM: ARM Directives. (line 157) 26904* .ldouble directive, ARM: ARM Directives. (line 108) 26905* .little directive, M32RX: M32R-Directives. (line 82) 26906* .long directive, s390: s390 Directives. (line 16) 26907* .ltorg directive, AArch64: AArch64 Directives. (line 45) 26908* .ltorg directive, ARM: ARM Directives. (line 167) 26909* .ltorg directive, s390: s390 Directives. (line 79) 26910* .m32r directive, M32R: M32R-Directives. (line 66) 26911* .m32r2 directive, M32R2: M32R-Directives. (line 77) 26912* .m32rx directive, M32RX: M32R-Directives. (line 72) 26913* .machine directive, s390: s390 Directives. (line 84) 26914* .machinemode directive, s390: s390 Directives. (line 101) 26915* .module: MIPS assembly options. 26916 (line 6) 26917* .module fp=NN directive, MIPS: MIPS FP ABI Selection. 26918 (line 6) 26919* .movsp directive, ARM: ARM Directives. (line 181) 26920* .nan directive, MIPS: MIPS NaN Encodings. (line 6) 26921* .nocmp directive, TIC6X: TIC6X Directives. (line 47) 26922* .no_pointers directive, XStormy16: XStormy16 Directives. 26923 (line 14) 26924* .o: Object. (line 6) 26925* .object_arch directive, ARM: ARM Directives. (line 186) 26926* .packed directive, ARM: ARM Directives. (line 192) 26927* .pad directive, ARM: ARM Directives. (line 197) 26928* .param on HPPA: HPPA Directives. (line 19) 26929* .personality directive, ARM: ARM Directives. (line 202) 26930* .personality directive, TIC6X: TIC6X Directives. (line 55) 26931* .personalityindex directive, ARM: ARM Directives. (line 205) 26932* .personalityindex directive, TIC6X: TIC6X Directives. (line 51) 26933* .pool directive, AArch64: AArch64 Directives. (line 59) 26934* .pool directive, ARM: ARM Directives. (line 209) 26935* .quad directive, s390: s390 Directives. (line 16) 26936* .req directive, AArch64: AArch64 Directives. (line 62) 26937* .req directive, ARM: ARM Directives. (line 212) 26938* .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives. 26939 (line 19) 26940* .require_canonical_reg_names directive, TILEPro: TILEPro Directives. 26941 (line 19) 26942* .save directive, ARM: ARM Directives. (line 217) 26943* .scomm directive, TIC6X: TIC6X Directives. (line 58) 26944* .secrel32 directive, ARM: ARM Directives. (line 255) 26945* .set arch=CPU: MIPS ISA. (line 18) 26946* .set at: MIPS Macros. (line 41) 26947* .set at=REG: MIPS Macros. (line 35) 26948* .set autoextend: MIPS autoextend. (line 6) 26949* .set crc: MIPS ASE Instruction Generation Overrides. 26950 (line 68) 26951* .set doublefloat: MIPS Floating-Point. 26952 (line 12) 26953* .set dsp: MIPS ASE Instruction Generation Overrides. 26954 (line 21) 26955* .set dspr2: MIPS ASE Instruction Generation Overrides. 26956 (line 26) 26957* .set dspr3: MIPS ASE Instruction Generation Overrides. 26958 (line 31) 26959* .set ginv: MIPS ASE Instruction Generation Overrides. 26960 (line 72) 26961* .set hardfloat: MIPS Floating-Point. 26962 (line 6) 26963* .set insn32: MIPS assembly options. 26964 (line 18) 26965* .set loongson-cam: MIPS ASE Instruction Generation Overrides. 26966 (line 81) 26967* .set loongson-ext: MIPS ASE Instruction Generation Overrides. 26968 (line 86) 26969* .set loongson-ext2: MIPS ASE Instruction Generation Overrides. 26970 (line 91) 26971* .set loongson-mmi: MIPS ASE Instruction Generation Overrides. 26972 (line 76) 26973* .set macro: MIPS Macros. (line 30) 26974* .set mcu: MIPS ASE Instruction Generation Overrides. 26975 (line 42) 26976* .set mdmx: MIPS ASE Instruction Generation Overrides. 26977 (line 16) 26978* .set mips16e2: MIPS ASE Instruction Generation Overrides. 26979 (line 61) 26980* .set mips3d: MIPS ASE Instruction Generation Overrides. 26981 (line 6) 26982* .set mipsN: MIPS ISA. (line 6) 26983* .set msa: MIPS ASE Instruction Generation Overrides. 26984 (line 47) 26985* .set mt: MIPS ASE Instruction Generation Overrides. 26986 (line 37) 26987* .set noat: MIPS Macros. (line 41) 26988* .set noautoextend: MIPS autoextend. (line 6) 26989* .set nocrc: MIPS ASE Instruction Generation Overrides. 26990 (line 68) 26991* .set nodsp: MIPS ASE Instruction Generation Overrides. 26992 (line 21) 26993* .set nodspr2: MIPS ASE Instruction Generation Overrides. 26994 (line 26) 26995* .set nodspr3: MIPS ASE Instruction Generation Overrides. 26996 (line 31) 26997* .set noginv: MIPS ASE Instruction Generation Overrides. 26998 (line 72) 26999* .set noinsn32: MIPS assembly options. 27000 (line 18) 27001* .set noloongson-cam: MIPS ASE Instruction Generation Overrides. 27002 (line 81) 27003* .set noloongson-ext: MIPS ASE Instruction Generation Overrides. 27004 (line 86) 27005* .set noloongson-ext2: MIPS ASE Instruction Generation Overrides. 27006 (line 91) 27007* .set noloongson-mmi: MIPS ASE Instruction Generation Overrides. 27008 (line 76) 27009* .set nomacro: MIPS Macros. (line 30) 27010* .set nomcu: MIPS ASE Instruction Generation Overrides. 27011 (line 42) 27012* .set nomdmx: MIPS ASE Instruction Generation Overrides. 27013 (line 16) 27014* .set nomips16e2: MIPS ASE Instruction Generation Overrides. 27015 (line 61) 27016* .set nomips3d: MIPS ASE Instruction Generation Overrides. 27017 (line 6) 27018* .set nomsa: MIPS ASE Instruction Generation Overrides. 27019 (line 47) 27020* .set nomt: MIPS ASE Instruction Generation Overrides. 27021 (line 37) 27022* .set nosmartmips: MIPS ASE Instruction Generation Overrides. 27023 (line 11) 27024* .set nosym32: MIPS Symbol Sizes. (line 6) 27025* .set novirt: MIPS ASE Instruction Generation Overrides. 27026 (line 52) 27027* .set noxpa: MIPS ASE Instruction Generation Overrides. 27028 (line 57) 27029* .set pop: MIPS Option Stack. (line 6) 27030* .set push: MIPS Option Stack. (line 6) 27031* .set singlefloat: MIPS Floating-Point. 27032 (line 12) 27033* .set smartmips: MIPS ASE Instruction Generation Overrides. 27034 (line 11) 27035* .set softfloat: MIPS Floating-Point. 27036 (line 6) 27037* .set sym32: MIPS Symbol Sizes. (line 6) 27038* .set virt: MIPS ASE Instruction Generation Overrides. 27039 (line 52) 27040* .set xpa: MIPS ASE Instruction Generation Overrides. 27041 (line 57) 27042* .setfp directive, ARM: ARM Directives. (line 241) 27043* .short directive, s390: s390 Directives. (line 16) 27044* .syntax directive, ARM: ARM Directives. (line 260) 27045* .thumb directive, ARM: ARM Directives. (line 264) 27046* .thumb_func directive, ARM: ARM Directives. (line 267) 27047* .thumb_set directive, ARM: ARM Directives. (line 278) 27048* .tlsdescadd directive, AArch64: AArch64 Directives. (line 70) 27049* .tlsdesccall directive, AArch64: AArch64 Directives. (line 73) 27050* .tlsdescldr directive, AArch64: AArch64 Directives. (line 76) 27051* .tlsdescseq directive, ARM: ARM Directives. (line 285) 27052* .unreq directive, AArch64: AArch64 Directives. (line 79) 27053* .unreq directive, ARM: ARM Directives. (line 290) 27054* .unwind_raw directive, ARM: ARM Directives. (line 301) 27055* .v850 directive, V850: V850 Directives. (line 14) 27056* .v850e directive, V850: V850 Directives. (line 20) 27057* .v850e1 directive, V850: V850 Directives. (line 26) 27058* .v850e2 directive, V850: V850 Directives. (line 32) 27059* .v850e2v3 directive, V850: V850 Directives. (line 38) 27060* .v850e2v4 directive, V850: V850 Directives. (line 44) 27061* .v850e3v5 directive, V850: V850 Directives. (line 50) 27062* .variant_pcs directive, AArch64: AArch64 Directives. (line 90) 27063* .vsave directive, ARM: ARM Directives. (line 308) 27064* .xword directive, AArch64: AArch64 Directives. (line 95) 27065* .z8001: Z8000 Directives. (line 11) 27066* .z8002: Z8000 Directives. (line 15) 27067* 16-bit code, i386: i386-16bit. (line 6) 27068* 16bit_pointers directive, XStormy16: XStormy16 Directives. 27069 (line 6) 27070* 16byte directive, Nios II: Nios II Directives. (line 28) 27071* 16byte directive, PRU: PRU Directives. (line 25) 27072* 2byte directive: 2byte. (line 6) 27073* 2byte directive, Nios II: Nios II Directives. (line 19) 27074* 2byte directive, PRU: PRU Directives. (line 16) 27075* 32bit_pointers directive, XStormy16: XStormy16 Directives. 27076 (line 10) 27077* 3DNow!, i386: i386-SIMD. (line 6) 27078* 3DNow!, x86-64: i386-SIMD. (line 6) 27079* 430 support: MSP430-Dependent. (line 6) 27080* 4byte directive: 4byte. (line 6) 27081* 4byte directive, Nios II: Nios II Directives. (line 22) 27082* 4byte directive, PRU: PRU Directives. (line 19) 27083* 8byte directive: 8byte. (line 6) 27084* 8byte directive, Nios II: Nios II Directives. (line 25) 27085* 8byte directive, PRU: PRU Directives. (line 22) 27086* : (label): Statements. (line 31) 27087* @gotoff(SYMBOL), ARC modifier: ARC Modifiers. (line 20) 27088* @gotpc(SYMBOL), ARC modifier: ARC Modifiers. (line 16) 27089* @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21) 27090* @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10) 27091* @pcl(SYMBOL), ARC modifier: ARC Modifiers. (line 12) 27092* @plt(SYMBOL), ARC modifier: ARC Modifiers. (line 23) 27093* @sda(SYMBOL), ARC modifier: ARC Modifiers. (line 28) 27094* @word modifier, D10V: D10V-Word. (line 6) 27095* _ opcode prefix: Xtensa Opcodes. (line 9) 27096* __DYNAMIC__, ARC pre-defined symbol: ARC Symbols. (line 14) 27097* __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol: ARC Symbols. 27098 (line 11) 27099* a.out: Object. (line 6) 27100* a.out symbol attributes: a.out Symbols. (line 6) 27101* AArch64 floating point (IEEE): AArch64 Floating Point. 27102 (line 6) 27103* AArch64 immediate character: AArch64-Chars. (line 13) 27104* AArch64 line comment character: AArch64-Chars. (line 6) 27105* AArch64 line separator: AArch64-Chars. (line 10) 27106* AArch64 machine directives: AArch64 Directives. (line 6) 27107* AArch64 opcodes: AArch64 Opcodes. (line 6) 27108* AArch64 options (none): AArch64 Options. (line 6) 27109* AArch64 register names: AArch64-Regs. (line 6) 27110* AArch64 relocations: AArch64-Relocations. 27111 (line 6) 27112* AArch64 support: AArch64-Dependent. (line 6) 27113* abort directive: Abort. (line 6) 27114* ABORT directive: ABORT (COFF). (line 6) 27115* absolute section: Ld Sections. (line 29) 27116* absolute-literals directive: Absolute Literals Directive. 27117 (line 6) 27118* ADDI instructions, relaxation: Xtensa Immediate Relaxation. 27119 (line 43) 27120* addition, permitted arguments: Infix Ops. (line 45) 27121* addresses: Expressions. (line 6) 27122* addresses, format of: Secs Background. (line 65) 27123* addressing modes, D10V: D10V-Addressing. (line 6) 27124* addressing modes, D30V: D30V-Addressing. (line 6) 27125* addressing modes, H8/300: H8/300-Addressing. (line 6) 27126* addressing modes, M680x0: M68K-Syntax. (line 21) 27127* addressing modes, M68HC11: M68HC11-Syntax. (line 29) 27128* addressing modes, S12Z: S12Z Addressing Modes. 27129 (line 6) 27130* addressing modes, SH: SH-Addressing. (line 6) 27131* addressing modes, XGATE: XGATE-Syntax. (line 28) 27132* addressing modes, Z8000: Z8000-Addressing. (line 6) 27133* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) 27134* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 43) 27135* ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations. 27136 (line 14) 27137* advancing location counter: Org. (line 6) 27138* align directive: Align. (line 6) 27139* align directive <1>: RISC-V-Directives. (line 8) 27140* align directive, Nios II: Nios II Directives. (line 6) 27141* align directive, OpenRISC: OpenRISC-Directives. 27142 (line 9) 27143* align directive, PRU: PRU Directives. (line 6) 27144* align directive, SPARC: Sparc-Directives. (line 9) 27145* align directive, TIC54X: TIC54X-Directives. (line 6) 27146* aligned instruction bundle: Bundle directives. (line 9) 27147* alignment for NEON instructions: ARM-Neon-Alignment. (line 6) 27148* alignment of branch targets: Xtensa Automatic Alignment. 27149 (line 6) 27150* alignment of LOOP instructions: Xtensa Automatic Alignment. 27151 (line 6) 27152* Alpha floating point (IEEE): Alpha Floating Point. 27153 (line 6) 27154* Alpha line comment character: Alpha-Chars. (line 6) 27155* Alpha line separator: Alpha-Chars. (line 11) 27156* Alpha notes: Alpha Notes. (line 6) 27157* Alpha options: Alpha Options. (line 6) 27158* Alpha registers: Alpha-Regs. (line 6) 27159* Alpha relocations: Alpha-Relocs. (line 6) 27160* Alpha support: Alpha-Dependent. (line 6) 27161* Alpha Syntax: Alpha Options. (line 60) 27162* Alpha-only directives: Alpha Directives. (line 9) 27163* Altera Nios II support: NiosII-Dependent. (line 6) 27164* altered difference tables: Word. (line 12) 27165* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) 27166* ARC Branch Target Address: ARC-Regs. (line 60) 27167* ARC BTA saved on exception entry: ARC-Regs. (line 79) 27168* ARC Build configuration for: BTA Registers: ARC-Regs. (line 89) 27169* ARC Build configuration for: Core Registers: ARC-Regs. (line 97) 27170* ARC Build configuration for: Interrupts: ARC-Regs. (line 93) 27171* ARC Build Configuration Registers Version: ARC-Regs. (line 85) 27172* ARC C preprocessor macro separator: ARC-Chars. (line 31) 27173* ARC core general registers: ARC-Regs. (line 10) 27174* ARC DCCM RAM Configuration Register: ARC-Regs. (line 101) 27175* ARC Exception Cause Register: ARC-Regs. (line 63) 27176* ARC Exception Return Address: ARC-Regs. (line 76) 27177* ARC extension core registers: ARC-Regs. (line 38) 27178* ARC frame pointer: ARC-Regs. (line 17) 27179* ARC global pointer: ARC-Regs. (line 14) 27180* ARC interrupt link register: ARC-Regs. (line 27) 27181* ARC Interrupt Vector Base address: ARC-Regs. (line 66) 27182* ARC level 1 interrupt link register: ARC-Regs. (line 23) 27183* ARC level 2 interrupt link register: ARC-Regs. (line 31) 27184* ARC line comment character: ARC-Chars. (line 11) 27185* ARC line separator: ARC-Chars. (line 27) 27186* ARC link register: ARC-Regs. (line 35) 27187* ARC loop counter: ARC-Regs. (line 41) 27188* ARC machine directives: ARC Directives. (line 6) 27189* ARC opcodes: ARC Opcodes. (line 6) 27190* ARC options: ARC Options. (line 6) 27191* ARC Processor Identification register: ARC-Regs. (line 51) 27192* ARC Program Counter: ARC-Regs. (line 54) 27193* ARC register name prefix character: ARC-Chars. (line 7) 27194* ARC register names: ARC-Regs. (line 6) 27195* ARC Saved User Stack Pointer: ARC-Regs. (line 73) 27196* ARC stack pointer: ARC-Regs. (line 20) 27197* ARC Status register: ARC-Regs. (line 57) 27198* ARC STATUS32 saved on exception: ARC-Regs. (line 82) 27199* ARC Stored STATUS32 register on entry to level P0 interrupts: ARC-Regs. 27200 (line 69) 27201* ARC support: ARC-Dependent. (line 6) 27202* ARC symbol prefix character: ARC-Chars. (line 20) 27203* ARC word aligned program counter: ARC-Regs. (line 44) 27204* arch directive, i386: i386-Arch. (line 6) 27205* arch directive, M680x0: M68K-Directives. (line 22) 27206* arch directive, MSP 430: MSP430 Directives. (line 18) 27207* arch directive, x86-64: i386-Arch. (line 6) 27208* architecture options, IP2022: IP2K-Opts. (line 9) 27209* architecture options, IP2K: IP2K-Opts. (line 14) 27210* architecture options, M16C: M32C-Opts. (line 12) 27211* architecture options, M32C: M32C-Opts. (line 9) 27212* architecture options, M32R: M32R-Opts. (line 21) 27213* architecture options, M32R2: M32R-Opts. (line 17) 27214* architecture options, M32RX: M32R-Opts. (line 9) 27215* architecture options, M680x0: M68K-Opts. (line 99) 27216* Architecture variant option, CRIS: CRIS-Opts. (line 34) 27217* architectures, Meta: Meta Options. (line 6) 27218* architectures, PowerPC: PowerPC-Opts. (line 6) 27219* architectures, SCORE: SCORE-Opts. (line 6) 27220* architectures, SPARC: Sparc-Opts. (line 6) 27221* arguments for addition: Infix Ops. (line 45) 27222* arguments for subtraction: Infix Ops. (line 50) 27223* arguments in expressions: Arguments. (line 6) 27224* arithmetic functions: Operators. (line 6) 27225* arithmetic operands: Arguments. (line 6) 27226* ARM data relocations: ARM-Relocations. (line 6) 27227* ARM floating point (IEEE): ARM Floating Point. (line 6) 27228* ARM identifiers: ARM-Chars. (line 19) 27229* ARM immediate character: ARM-Chars. (line 17) 27230* ARM line comment character: ARM-Chars. (line 6) 27231* ARM line separator: ARM-Chars. (line 14) 27232* ARM machine directives: ARM Directives. (line 6) 27233* ARM opcodes: ARM Opcodes. (line 6) 27234* ARM options (none): ARM Options. (line 6) 27235* ARM register names: ARM-Regs. (line 6) 27236* ARM support: ARM-Dependent. (line 6) 27237* ascii directive: Ascii. (line 6) 27238* asciz directive: Asciz. (line 6) 27239* asg directive, TIC54X: TIC54X-Directives. (line 18) 27240* assembler bugs, reporting: Bug Reporting. (line 6) 27241* assembler crash: Bug Criteria. (line 9) 27242* assembler directive .3byte, RX: RX-Directives. (line 9) 27243* assembler directive .arch, CRIS: CRIS-Pseudos. (line 50) 27244* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) 27245* assembler directive .far, M68HC11: M68HC11-Directives. (line 20) 27246* assembler directive .fetchalign, RX: RX-Directives. (line 13) 27247* assembler directive .interrupt, M68HC11: M68HC11-Directives. 27248 (line 26) 27249* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) 27250* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) 27251* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 18) 27252* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) 27253* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 137) 27254* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 101) 27255* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 137) 27256* assembler directive GREG, MMIX: MMIX-Pseudos. (line 53) 27257* assembler directive IS, MMIX: MMIX-Pseudos. (line 44) 27258* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) 27259* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 29) 27260* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 113) 27261* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 125) 27262* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 113) 27263* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 113) 27264* assembler directives, CRIS: CRIS-Pseudos. (line 6) 27265* assembler directives, M68HC11: M68HC11-Directives. (line 6) 27266* assembler directives, M68HC12: M68HC11-Directives. (line 6) 27267* assembler directives, MMIX: MMIX-Pseudos. (line 6) 27268* assembler directives, RL78: RL78-Directives. (line 6) 27269* assembler directives, RX: RX-Directives. (line 6) 27270* assembler directives, XGATE: XGATE-Directives. (line 6) 27271* assembler internal logic error: As Sections. (line 13) 27272* assembler version: v. (line 6) 27273* assembler, and linker: Secs Background. (line 10) 27274* assembly listings, enabling: a. (line 6) 27275* assigning values to symbols: Setting Symbols. (line 6) 27276* assigning values to symbols <1>: Equ. (line 6) 27277* at register, MIPS: MIPS Macros. (line 35) 27278* attributes, symbol: Symbol Attributes. (line 6) 27279* att_syntax pseudo op, i386: i386-Variations. (line 6) 27280* att_syntax pseudo op, x86-64: i386-Variations. (line 6) 27281* auxiliary attributes, COFF symbols: COFF Symbols. (line 19) 27282* auxiliary symbol information, COFF: Dim. (line 6) 27283* AVR line comment character: AVR-Chars. (line 6) 27284* AVR line separator: AVR-Chars. (line 14) 27285* AVR modifiers: AVR-Modifiers. (line 6) 27286* AVR opcode summary: AVR Opcodes. (line 6) 27287* AVR options (none): AVR Options. (line 6) 27288* AVR register names: AVR-Regs. (line 6) 27289* AVR support: AVR-Dependent. (line 6) 27290* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 27291* backslash (\\): Strings. (line 40) 27292* backspace (\b): Strings. (line 15) 27293* balign directive: Balign. (line 6) 27294* balignl directive: Balign. (line 29) 27295* balignw directive: Balign. (line 29) 27296* bes directive, TIC54X: TIC54X-Directives. (line 194) 27297* big endian output, MIPS: Overview. (line 856) 27298* big endian output, PJ: Overview. (line 760) 27299* big-endian output, MIPS: MIPS Options. (line 13) 27300* big-endian output, TIC6X: TIC6X Options. (line 46) 27301* bignums: Bignums. (line 6) 27302* binary constants, TIC54X: TIC54X-Constants. (line 8) 27303* binary files, including: Incbin. (line 6) 27304* binary integers: Integers. (line 6) 27305* bit names, IA-64: IA-64-Bits. (line 6) 27306* bitfields, not supported on VAX: VAX-no. (line 6) 27307* Blackfin directives: Blackfin Directives. 27308 (line 6) 27309* Blackfin options (none): Blackfin Options. (line 6) 27310* Blackfin support: Blackfin-Dependent. (line 6) 27311* Blackfin syntax: Blackfin Syntax. (line 6) 27312* block: Z8000 Directives. (line 55) 27313* BMI, i386: i386-BMI. (line 6) 27314* BMI, x86-64: i386-BMI. (line 6) 27315* BPF line comment character: BPF-Chars. (line 6) 27316* BPF opcodes: BPF Opcodes. (line 6) 27317* BPF options (none): BPF Options. (line 6) 27318* BPF register names: BPF-Regs. (line 6) 27319* BPF support: BPF-Dependent. (line 6) 27320* branch improvement, M680x0: M68K-Branch. (line 6) 27321* branch improvement, M68HC11: M68HC11-Branch. (line 6) 27322* branch improvement, VAX: VAX-branch. (line 6) 27323* branch instructions, relaxation: Xtensa Branch Relaxation. 27324 (line 6) 27325* Branch Target Address, ARC: ARC-Regs. (line 60) 27326* branch target alignment: Xtensa Automatic Alignment. 27327 (line 6) 27328* break directive, TIC54X: TIC54X-Directives. (line 141) 27329* BSD syntax: PDP-11-Syntax. (line 6) 27330* bss directive: Bss. (line 6) 27331* BSS directive: RISC-V-Directives. (line 24) 27332* bss directive, TIC54X: TIC54X-Directives. (line 27) 27333* bss section: Ld Sections. (line 20) 27334* bss section <1>: bss. (line 6) 27335* BTA saved on exception entry, ARC: ARC-Regs. (line 79) 27336* bug criteria: Bug Criteria. (line 6) 27337* bug reports: Bug Reporting. (line 6) 27338* bugs in assembler: Reporting Bugs. (line 6) 27339* Build configuration for: BTA Registers, ARC: ARC-Regs. (line 89) 27340* Build configuration for: Core Registers, ARC: ARC-Regs. (line 97) 27341* Build configuration for: Interrupts, ARC: ARC-Regs. (line 93) 27342* Build Configuration Registers Version, ARC: ARC-Regs. (line 85) 27343* Built-in symbols, CRIS: CRIS-Symbols. (line 6) 27344* builtin math functions, TIC54X: TIC54X-Builtins. (line 6) 27345* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) 27346* bundle: Bundle directives. (line 9) 27347* bundle-locked: Bundle directives. (line 39) 27348* bundle_align_mode directive: Bundle directives. (line 9) 27349* bundle_lock directive: Bundle directives. (line 31) 27350* bundle_unlock directive: Bundle directives. (line 31) 27351* bus lock prefixes, i386: i386-Prefixes. (line 36) 27352* bval: Z8000 Directives. (line 30) 27353* byte directive: Byte. (line 6) 27354* byte directive, TIC54X: TIC54X-Directives. (line 34) 27355* C preprocessor macro separator, ARC: ARC-Chars. (line 31) 27356* C-SKY options: C-SKY Options. (line 6) 27357* C-SKY support: C-SKY-Dependent. (line 6) 27358* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 27359* call directive, Nios II: Nios II Relocations. 27360 (line 38) 27361* call instructions, i386: i386-Mnemonics. (line 115) 27362* call instructions, relaxation: Xtensa Call Relaxation. 27363 (line 6) 27364* call instructions, x86-64: i386-Mnemonics. (line 115) 27365* call_hiadj directive, Nios II: Nios II Relocations. 27366 (line 38) 27367* call_lo directive, Nios II: Nios II Relocations. 27368 (line 38) 27369* carriage return (backslash-r): Strings. (line 24) 27370* case sensitivity, Z80: Z80-Case. (line 6) 27371* cfi_endproc directive: CFI directives. (line 40) 27372* cfi_fde_data directive: CFI directives. (line 66) 27373* cfi_personality directive: CFI directives. (line 47) 27374* cfi_personality_id directive: CFI directives. (line 59) 27375* cfi_sections directive: CFI directives. (line 9) 27376* cfi_startproc directive: CFI directives. (line 30) 27377* char directive, TIC54X: TIC54X-Directives. (line 34) 27378* character constant, Z80: Z80-Chars. (line 20) 27379* character constants: Characters. (line 6) 27380* character escape codes: Strings. (line 15) 27381* character escapes, Z80: Z80-Chars. (line 18) 27382* character, single: Chars. (line 6) 27383* characters used in symbols: Symbol Intro. (line 6) 27384* clink directive, TIC54X: TIC54X-Directives. (line 43) 27385* code16 directive, i386: i386-16bit. (line 6) 27386* code16gcc directive, i386: i386-16bit. (line 6) 27387* code32 directive, i386: i386-16bit. (line 6) 27388* code64 directive, i386: i386-16bit. (line 6) 27389* code64 directive, x86-64: i386-16bit. (line 6) 27390* COFF auxiliary symbol information: Dim. (line 6) 27391* COFF structure debugging: Tag. (line 6) 27392* COFF symbol attributes: COFF Symbols. (line 6) 27393* COFF symbol descriptor: Desc. (line 6) 27394* COFF symbol storage class: Scl. (line 6) 27395* COFF symbol type: Type. (line 11) 27396* COFF symbols, debugging: Def. (line 6) 27397* COFF value attribute: Val. (line 6) 27398* COMDAT: Linkonce. (line 6) 27399* comm directive: Comm. (line 6) 27400* command line conventions: Command Line. (line 6) 27401* command-line options ignored, VAX: VAX-Opts. (line 6) 27402* command-line options, V850: V850 Options. (line 9) 27403* comment character, XStormy16: XStormy16-Chars. (line 11) 27404* comments: Comments. (line 6) 27405* comments, M680x0: M68K-Chars. (line 6) 27406* comments, removed by preprocessor: Preprocessing. (line 11) 27407* common directive, SPARC: Sparc-Directives. (line 12) 27408* common sections: Linkonce. (line 6) 27409* common variable storage: bss. (line 6) 27410* comparison expressions: Infix Ops. (line 56) 27411* conditional assembly: If. (line 6) 27412* constant, single character: Chars. (line 6) 27413* constants: Constants. (line 6) 27414* constants, bignum: Bignums. (line 6) 27415* constants, character: Characters. (line 6) 27416* constants, converted by preprocessor: Preprocessing. (line 14) 27417* constants, floating point: Flonums. (line 6) 27418* constants, integer: Integers. (line 6) 27419* constants, number: Numbers. (line 6) 27420* constants, Sparc: Sparc-Constants. (line 6) 27421* constants, string: Strings. (line 6) 27422* constants, TIC54X: TIC54X-Constants. (line 6) 27423* conversion instructions, i386: i386-Mnemonics. (line 66) 27424* conversion instructions, x86-64: i386-Mnemonics. (line 66) 27425* coprocessor wait, i386: i386-Prefixes. (line 40) 27426* copy directive, TIC54X: TIC54X-Directives. (line 52) 27427* core general registers, ARC: ARC-Regs. (line 10) 27428* cpu directive, ARC: ARC Directives. (line 27) 27429* cpu directive, M680x0: M68K-Directives. (line 30) 27430* cpu directive, MSP 430: MSP430 Directives. (line 22) 27431* CR16 line comment character: CR16-Chars. (line 6) 27432* CR16 line separator: CR16-Chars. (line 12) 27433* CR16 Operand Qualifiers: CR16 Operand Qualifiers. 27434 (line 6) 27435* CR16 support: CR16-Dependent. (line 6) 27436* crash of assembler: Bug Criteria. (line 9) 27437* CRIS --emulation=crisaout command-line option: CRIS-Opts. (line 9) 27438* CRIS --emulation=criself command-line option: CRIS-Opts. (line 9) 27439* CRIS --march=ARCHITECTURE command-line option: CRIS-Opts. (line 34) 27440* CRIS --mul-bug-abort command-line option: CRIS-Opts. (line 63) 27441* CRIS --no-mul-bug-abort command-line option: CRIS-Opts. (line 63) 27442* CRIS --no-underscore command-line option: CRIS-Opts. (line 15) 27443* CRIS --pic command-line option: CRIS-Opts. (line 27) 27444* CRIS --underscore command-line option: CRIS-Opts. (line 15) 27445* CRIS -N command-line option: CRIS-Opts. (line 59) 27446* CRIS architecture variant option: CRIS-Opts. (line 34) 27447* CRIS assembler directive .arch: CRIS-Pseudos. (line 50) 27448* CRIS assembler directive .dword: CRIS-Pseudos. (line 12) 27449* CRIS assembler directive .syntax: CRIS-Pseudos. (line 18) 27450* CRIS assembler directives: CRIS-Pseudos. (line 6) 27451* CRIS built-in symbols: CRIS-Symbols. (line 6) 27452* CRIS instruction expansion: CRIS-Expand. (line 6) 27453* CRIS line comment characters: CRIS-Chars. (line 6) 27454* CRIS options: CRIS-Opts. (line 6) 27455* CRIS position-independent code: CRIS-Opts. (line 27) 27456* CRIS pseudo-op .arch: CRIS-Pseudos. (line 50) 27457* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) 27458* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 18) 27459* CRIS pseudo-ops: CRIS-Pseudos. (line 6) 27460* CRIS register names: CRIS-Regs. (line 6) 27461* CRIS support: CRIS-Dependent. (line 6) 27462* CRIS symbols in position-independent code: CRIS-Pic. (line 6) 27463* ctbp register, V850: V850-Regs. (line 90) 27464* ctoff pseudo-op, V850: V850 Opcodes. (line 110) 27465* ctpc register, V850: V850-Regs. (line 82) 27466* ctpsw register, V850: V850-Regs. (line 84) 27467* current address: Dot. (line 6) 27468* current address, advancing: Org. (line 6) 27469* c_mode directive, TIC54X: TIC54X-Directives. (line 49) 27470* D10V @word modifier: D10V-Word. (line 6) 27471* D10V addressing modes: D10V-Addressing. (line 6) 27472* D10V floating point: D10V-Float. (line 6) 27473* D10V line comment character: D10V-Chars. (line 6) 27474* D10V opcode summary: D10V-Opcodes. (line 6) 27475* D10V optimization: Overview. (line 639) 27476* D10V options: D10V-Opts. (line 6) 27477* D10V registers: D10V-Regs. (line 6) 27478* D10V size modifiers: D10V-Size. (line 6) 27479* D10V sub-instruction ordering: D10V-Chars. (line 14) 27480* D10V sub-instructions: D10V-Subs. (line 6) 27481* D10V support: D10V-Dependent. (line 6) 27482* D10V syntax: D10V-Syntax. (line 6) 27483* d24 directive, Z80: Z80 Directives. (line 32) 27484* D30V addressing modes: D30V-Addressing. (line 6) 27485* D30V floating point: D30V-Float. (line 6) 27486* D30V Guarded Execution: D30V-Guarded. (line 6) 27487* D30V line comment character: D30V-Chars. (line 6) 27488* D30V nops: Overview. (line 647) 27489* D30V nops after 32-bit multiply: Overview. (line 650) 27490* D30V opcode summary: D30V-Opcodes. (line 6) 27491* D30V optimization: Overview. (line 644) 27492* D30V options: D30V-Opts. (line 6) 27493* D30V registers: D30V-Regs. (line 6) 27494* D30V size modifiers: D30V-Size. (line 6) 27495* D30V sub-instruction ordering: D30V-Chars. (line 14) 27496* D30V sub-instructions: D30V-Subs. (line 6) 27497* D30V support: D30V-Dependent. (line 6) 27498* D30V syntax: D30V-Syntax. (line 6) 27499* d32 directive, Z80: Z80 Directives. (line 37) 27500* data alignment on SPARC: Sparc-Aligned-Data. (line 6) 27501* data and text sections, joining: R. (line 6) 27502* data directive: Data. (line 6) 27503* data directive, TIC54X: TIC54X-Directives. (line 59) 27504* Data directives: RISC-V-Directives. (line 12) 27505* data relocations, ARM: ARM-Relocations. (line 6) 27506* data section: Ld Sections. (line 9) 27507* data1 directive, M680x0: M68K-Directives. (line 9) 27508* data2 directive, M680x0: M68K-Directives. (line 12) 27509* db directive, Z80: Z80 Directives. (line 18) 27510* dbpc register, V850: V850-Regs. (line 86) 27511* dbpsw register, V850: V850-Regs. (line 88) 27512* dc directive: Dc. (line 6) 27513* dcb directive: Dcb. (line 6) 27514* DCCM RAM Configuration Register, ARC: ARC-Regs. (line 101) 27515* debuggers, and symbol order: Symbols. (line 10) 27516* debugging COFF symbols: Def. (line 6) 27517* DEC syntax: PDP-11-Syntax. (line 6) 27518* decimal integers: Integers. (line 12) 27519* def directive: Def. (line 6) 27520* def directive, TIC54X: TIC54X-Directives. (line 101) 27521* def24 directive, Z80: Z80 Directives. (line 33) 27522* def32 directive, Z80: Z80 Directives. (line 38) 27523* defb directive, Z80: Z80 Directives. (line 19) 27524* defl directive, Z80: Z80 Directives. (line 47) 27525* defm directive, Z80: Z80 Directives. (line 20) 27526* defs directive, Z80: Z80 Directives. (line 43) 27527* defw directive, Z80: Z80 Directives. (line 28) 27528* density instructions: Density Instructions. 27529 (line 6) 27530* dependency tracking: MD. (line 6) 27531* deprecated directives: Deprecated. (line 6) 27532* desc directive: Desc. (line 6) 27533* descriptor, of a.out symbol: Symbol Desc. (line 6) 27534* dfloat directive, VAX: VAX-directives. (line 9) 27535* difference tables altered: Word. (line 12) 27536* difference tables, warning: K. (line 6) 27537* differences, mmixal: MMIX-mmixal. (line 6) 27538* dim directive: Dim. (line 6) 27539* directives and instructions: Statements. (line 20) 27540* directives for PowerPC: PowerPC-Pseudo. (line 6) 27541* directives for SCORE: SCORE-Pseudo. (line 6) 27542* directives, Blackfin: Blackfin Directives. 27543 (line 6) 27544* directives, M32R: M32R-Directives. (line 6) 27545* directives, M680x0: M68K-Directives. (line 6) 27546* directives, machine independent: Pseudo Ops. (line 6) 27547* directives, Xtensa: Xtensa Directives. (line 6) 27548* directives, Z8000: Z8000 Directives. (line 6) 27549* Disable floating-point instructions: MIPS Floating-Point. 27550 (line 6) 27551* Disable single-precision floating-point operations: MIPS Floating-Point. 27552 (line 12) 27553* displacement sizing character, VAX: VAX-operands. (line 12) 27554* dollar local symbols: Symbol Names. (line 113) 27555* dot (symbol): Dot. (line 6) 27556* double directive: Double. (line 6) 27557* double directive, i386: i386-Float. (line 14) 27558* double directive, M680x0: M68K-Float. (line 14) 27559* double directive, M68HC11: M68HC11-Float. (line 14) 27560* double directive, RX: RX-Float. (line 11) 27561* double directive, TIC54X: TIC54X-Directives. (line 62) 27562* double directive, VAX: VAX-float. (line 15) 27563* double directive, x86-64: i386-Float. (line 14) 27564* double directive, XGATE: XGATE-Float. (line 13) 27565* doublequote (\"): Strings. (line 43) 27566* drlist directive, TIC54X: TIC54X-Directives. (line 71) 27567* drnolist directive, TIC54X: TIC54X-Directives. (line 71) 27568* ds directive: Ds. (line 6) 27569* ds directive, Z80: Z80 Directives. (line 42) 27570* DTP-relative data directives: RISC-V-Directives. (line 18) 27571* dw directive, Z80: Z80 Directives. (line 27) 27572* dword directive, BPF: BPF Directives. (line 15) 27573* dword directive, Nios II: Nios II Directives. (line 16) 27574* dword directive, PRU: PRU Directives. (line 13) 27575* EB command-line option, C-SKY: C-SKY Options. (line 18) 27576* EB command-line option, Nios II: Nios II Options. (line 22) 27577* ecr register, V850: V850-Regs. (line 78) 27578* eight-byte integer: Quad. (line 9) 27579* eight-byte integer <1>: 8byte. (line 6) 27580* eipc register, V850: V850-Regs. (line 70) 27581* eipsw register, V850: V850-Regs. (line 72) 27582* eject directive: Eject. (line 6) 27583* EL command-line option, C-SKY: C-SKY Options. (line 14) 27584* EL command-line option, Nios II: Nios II Options. (line 25) 27585* ELF symbol type: Type. (line 22) 27586* else directive: Else. (line 6) 27587* elseif directive: Elseif. (line 6) 27588* empty expressions: Empty Exprs. (line 6) 27589* emsg directive, TIC54X: TIC54X-Directives. (line 75) 27590* emulation: Overview. (line 1110) 27591* encoding options, i386: i386-Mnemonics. (line 38) 27592* encoding options, x86-64: i386-Mnemonics. (line 38) 27593* end directive: End. (line 6) 27594* endef directive: Endef. (line 6) 27595* endfunc directive: Endfunc. (line 6) 27596* endianness, MIPS: Overview. (line 856) 27597* endianness, PJ: Overview. (line 760) 27598* endif directive: Endif. (line 6) 27599* endloop directive, TIC54X: TIC54X-Directives. (line 141) 27600* endm directive: Macro. (line 137) 27601* endm directive, TIC54X: TIC54X-Directives. (line 151) 27602* endproc directive, OpenRISC: OpenRISC-Directives. 27603 (line 24) 27604* endstruct directive, TIC54X: TIC54X-Directives. (line 214) 27605* endunion directive, TIC54X: TIC54X-Directives. (line 248) 27606* environment settings, TIC54X: TIC54X-Env. (line 6) 27607* EOF, newline must precede: Statements. (line 14) 27608* ep register, V850: V850-Regs. (line 66) 27609* Epiphany line comment character: Epiphany-Chars. (line 6) 27610* Epiphany line separator: Epiphany-Chars. (line 14) 27611* Epiphany options: Epiphany Options. (line 6) 27612* Epiphany support: Epiphany-Dependent. (line 6) 27613* equ directive: Equ. (line 6) 27614* equ directive, TIC54X: TIC54X-Directives. (line 189) 27615* equ directive, Z80: Z80 Directives. (line 52) 27616* equiv directive: Equiv. (line 6) 27617* eqv directive: Eqv. (line 6) 27618* err directive: Err. (line 6) 27619* error directive: Error. (line 6) 27620* error messages: Errors. (line 6) 27621* error on valid input: Bug Criteria. (line 12) 27622* errors, caused by warnings: W. (line 16) 27623* errors, continuing after: Z. (line 6) 27624* escape codes, character: Strings. (line 15) 27625* eval directive, TIC54X: TIC54X-Directives. (line 22) 27626* even: Z8000 Directives. (line 58) 27627* even directive, M680x0: M68K-Directives. (line 15) 27628* even directive, TIC54X: TIC54X-Directives. (line 6) 27629* Exception Cause Register, ARC: ARC-Regs. (line 63) 27630* Exception Return Address, ARC: ARC-Regs. (line 76) 27631* exitm directive: Macro. (line 140) 27632* expr (internal section): As Sections. (line 17) 27633* expression arguments: Arguments. (line 6) 27634* expressions: Expressions. (line 6) 27635* expressions, comparison: Infix Ops. (line 56) 27636* expressions, empty: Empty Exprs. (line 6) 27637* expressions, integer: Integer Exprs. (line 6) 27638* extAuxRegister directive, ARC: ARC Directives. (line 105) 27639* extCondCode directive, ARC: ARC Directives. (line 126) 27640* extCoreRegister directive, ARC: ARC Directives. (line 137) 27641* extend directive M680x0: M68K-Float. (line 17) 27642* extend directive M68HC11: M68HC11-Float. (line 17) 27643* extend directive XGATE: XGATE-Float. (line 16) 27644* extension core registers, ARC: ARC-Regs. (line 38) 27645* extension instructions, i386: i386-Mnemonics. (line 85) 27646* extension instructions, x86-64: i386-Mnemonics. (line 85) 27647* extern directive: Extern. (line 6) 27648* extInstruction directive, ARC: ARC Directives. (line 164) 27649* fail directive: Fail. (line 6) 27650* far_mode directive, TIC54X: TIC54X-Directives. (line 80) 27651* faster processing (-f): f. (line 6) 27652* fatal signal: Bug Criteria. (line 9) 27653* fclist directive, TIC54X: TIC54X-Directives. (line 85) 27654* fcnolist directive, TIC54X: TIC54X-Directives. (line 85) 27655* fepc register, V850: V850-Regs. (line 74) 27656* fepsw register, V850: V850-Regs. (line 76) 27657* ffloat directive, VAX: VAX-directives. (line 13) 27658* field directive, TIC54X: TIC54X-Directives. (line 89) 27659* file directive: File. (line 6) 27660* file directive, MSP 430: MSP430 Directives. (line 6) 27661* file name, logical: File. (line 13) 27662* file names and line numbers, in warnings/errors: Errors. (line 16) 27663* files, including: Include. (line 6) 27664* files, input: Input Files. (line 6) 27665* fill directive: Fill. (line 6) 27666* filling memory: Skip. (line 6) 27667* filling memory <1>: Space. (line 6) 27668* filling memory with no-op instructions: Nop. (line 6) 27669* filling memory with no-op instructions <1>: Nops. (line 6) 27670* filling memory with zero bytes: Zero. (line 6) 27671* FLIX syntax: Xtensa Syntax. (line 6) 27672* float directive: Float. (line 6) 27673* float directive, i386: i386-Float. (line 14) 27674* float directive, M680x0: M68K-Float. (line 11) 27675* float directive, M68HC11: M68HC11-Float. (line 11) 27676* float directive, RX: RX-Float. (line 8) 27677* float directive, TIC54X: TIC54X-Directives. (line 62) 27678* float directive, VAX: VAX-float. (line 15) 27679* float directive, x86-64: i386-Float. (line 14) 27680* float directive, XGATE: XGATE-Float. (line 10) 27681* floating point numbers: Flonums. (line 6) 27682* floating point numbers (double): Double. (line 6) 27683* floating point numbers (single): Float. (line 6) 27684* floating point numbers (single) <1>: Single. (line 6) 27685* floating point, AArch64 (IEEE): AArch64 Floating Point. 27686 (line 6) 27687* floating point, Alpha (IEEE): Alpha Floating Point. 27688 (line 6) 27689* floating point, ARM (IEEE): ARM Floating Point. (line 6) 27690* floating point, D10V: D10V-Float. (line 6) 27691* floating point, D30V: D30V-Float. (line 6) 27692* floating point, H8/300 (IEEE): H8/300 Floating Point. 27693 (line 6) 27694* floating point, HPPA (IEEE): HPPA Floating Point. 27695 (line 6) 27696* floating point, i386: i386-Float. (line 6) 27697* floating point, M680x0: M68K-Float. (line 6) 27698* floating point, M68HC11: M68HC11-Float. (line 6) 27699* floating point, MSP 430 (IEEE): MSP430 Floating Point. 27700 (line 6) 27701* floating point, OPENRISC (IEEE): OpenRISC-Float. (line 6) 27702* floating point, RX: RX-Float. (line 6) 27703* floating point, s390: s390 Floating Point. 27704 (line 6) 27705* floating point, SH (IEEE): SH Floating Point. (line 6) 27706* floating point, SPARC (IEEE): Sparc-Float. (line 6) 27707* floating point, V850 (IEEE): V850 Floating Point. 27708 (line 6) 27709* floating point, VAX: VAX-float. (line 6) 27710* floating point, WebAssembly (IEEE): WebAssembly-Floating-Point. 27711 (line 6) 27712* floating point, x86-64: i386-Float. (line 6) 27713* floating point, XGATE: XGATE-Float. (line 6) 27714* floating point, Z80: Z80 Floating Point. (line 6) 27715* flonums: Flonums. (line 6) 27716* force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 27717* format of error messages: Errors. (line 38) 27718* format of warning messages: Errors. (line 12) 27719* formfeed (\f): Strings. (line 18) 27720* four-byte integer: 4byte. (line 6) 27721* fpic command-line option, C-SKY: C-SKY Options. (line 22) 27722* frame pointer, ARC: ARC-Regs. (line 17) 27723* func directive: Func. (line 6) 27724* functions, in expressions: Operators. (line 6) 27725* gfloat directive, VAX: VAX-directives. (line 17) 27726* global: Z8000 Directives. (line 21) 27727* global directive: Global. (line 6) 27728* global directive, TIC54X: TIC54X-Directives. (line 101) 27729* global pointer, ARC: ARC-Regs. (line 14) 27730* got directive, Nios II: Nios II Relocations. 27731 (line 38) 27732* gotoff directive, Nios II: Nios II Relocations. 27733 (line 38) 27734* gotoff_hiadj directive, Nios II: Nios II Relocations. 27735 (line 38) 27736* gotoff_lo directive, Nios II: Nios II Relocations. 27737 (line 38) 27738* got_hiadj directive, Nios II: Nios II Relocations. 27739 (line 38) 27740* got_lo directive, Nios II: Nios II Relocations. 27741 (line 38) 27742* gp register, MIPS: MIPS Small Data. (line 6) 27743* gp register, V850: V850-Regs. (line 14) 27744* gprel directive, Nios II: Nios II Relocations. 27745 (line 26) 27746* grouping data: Sub-Sections. (line 6) 27747* H8/300 addressing modes: H8/300-Addressing. (line 6) 27748* H8/300 floating point (IEEE): H8/300 Floating Point. 27749 (line 6) 27750* H8/300 line comment character: H8/300-Chars. (line 6) 27751* H8/300 line separator: H8/300-Chars. (line 8) 27752* H8/300 machine directives (none): H8/300 Directives. (line 6) 27753* H8/300 opcode summary: H8/300 Opcodes. (line 6) 27754* H8/300 options: H8/300 Options. (line 6) 27755* H8/300 registers: H8/300-Regs. (line 6) 27756* H8/300 size suffixes: H8/300 Opcodes. (line 160) 27757* H8/300 support: H8/300-Dependent. (line 6) 27758* H8/300H, assembling for: H8/300 Directives. (line 8) 27759* half directive, BPF: BPF Directives. (line 9) 27760* half directive, Nios II: Nios II Directives. (line 10) 27761* half directive, SPARC: Sparc-Directives. (line 17) 27762* half directive, TIC54X: TIC54X-Directives. (line 109) 27763* hex character code (\XD...): Strings. (line 36) 27764* hexadecimal integers: Integers. (line 15) 27765* hexadecimal prefix, S12Z: S12Z Options. (line 17) 27766* hexadecimal prefix, Z80: Z80-Chars. (line 15) 27767* hfloat directive, VAX: VAX-directives. (line 21) 27768* hi directive, Nios II: Nios II Relocations. 27769 (line 20) 27770* hi pseudo-op, V850: V850 Opcodes. (line 33) 27771* hi0 pseudo-op, V850: V850 Opcodes. (line 10) 27772* hiadj directive, Nios II: Nios II Relocations. 27773 (line 6) 27774* hidden directive: Hidden. (line 6) 27775* high directive, M32R: M32R-Directives. (line 18) 27776* hilo pseudo-op, V850: V850 Opcodes. (line 55) 27777* HPPA directives not supported: HPPA Directives. (line 11) 27778* HPPA floating point (IEEE): HPPA Floating Point. 27779 (line 6) 27780* HPPA Syntax: HPPA Options. (line 7) 27781* HPPA-only directives: HPPA Directives. (line 24) 27782* hword directive: hword. (line 6) 27783* i386 16-bit code: i386-16bit. (line 6) 27784* i386 arch directive: i386-Arch. (line 6) 27785* i386 att_syntax pseudo op: i386-Variations. (line 6) 27786* i386 conversion instructions: i386-Mnemonics. (line 66) 27787* i386 extension instructions: i386-Mnemonics. (line 85) 27788* i386 floating point: i386-Float. (line 6) 27789* i386 immediate operands: i386-Variations. (line 15) 27790* i386 instruction naming: i386-Mnemonics. (line 9) 27791* i386 instruction prefixes: i386-Prefixes. (line 6) 27792* i386 intel_syntax pseudo op: i386-Variations. (line 6) 27793* i386 jump optimization: i386-Jumps. (line 6) 27794* i386 jump, call, return: i386-Variations. (line 45) 27795* i386 jump/call operands: i386-Variations. (line 15) 27796* i386 line comment character: i386-Chars. (line 6) 27797* i386 line separator: i386-Chars. (line 18) 27798* i386 memory references: i386-Memory. (line 6) 27799* i386 mnemonic compatibility: i386-Mnemonics. (line 121) 27800* i386 mul, imul instructions: i386-Notes. (line 6) 27801* i386 options: i386-Options. (line 6) 27802* i386 register operands: i386-Variations. (line 15) 27803* i386 registers: i386-Regs. (line 6) 27804* i386 sections: i386-Variations. (line 51) 27805* i386 size suffixes: i386-Variations. (line 28) 27806* i386 source, destination operands: i386-Variations. (line 21) 27807* i386 support: i386-Dependent. (line 6) 27808* i386 syntax compatibility: i386-Variations. (line 6) 27809* i80386 support: i386-Dependent. (line 6) 27810* IA-64 line comment character: IA-64-Chars. (line 6) 27811* IA-64 line separator: IA-64-Chars. (line 8) 27812* IA-64 options: IA-64 Options. (line 6) 27813* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6) 27814* IA-64 registers: IA-64-Regs. (line 6) 27815* IA-64 relocations: IA-64-Relocs. (line 6) 27816* IA-64 support: IA-64-Dependent. (line 6) 27817* IA-64 Syntax: IA-64 Options. (line 85) 27818* ident directive: Ident. (line 6) 27819* identifiers, ARM: ARM-Chars. (line 19) 27820* identifiers, MSP 430: MSP430-Chars. (line 17) 27821* if directive: If. (line 6) 27822* ifb directive: If. (line 21) 27823* ifc directive: If. (line 25) 27824* ifdef directive: If. (line 16) 27825* ifeq directive: If. (line 33) 27826* ifeqs directive: If. (line 36) 27827* ifge directive: If. (line 40) 27828* ifgt directive: If. (line 44) 27829* ifle directive: If. (line 48) 27830* iflt directive: If. (line 52) 27831* ifnb directive: If. (line 56) 27832* ifnc directive: If. (line 61) 27833* ifndef directive: If. (line 65) 27834* ifne directive: If. (line 72) 27835* ifnes directive: If. (line 76) 27836* ifnotdef directive: If. (line 65) 27837* immediate character, AArch64: AArch64-Chars. (line 13) 27838* immediate character, ARM: ARM-Chars. (line 17) 27839* immediate character, M680x0: M68K-Chars. (line 13) 27840* immediate character, VAX: VAX-operands. (line 6) 27841* immediate fields, relaxation: Xtensa Immediate Relaxation. 27842 (line 6) 27843* immediate operands, i386: i386-Variations. (line 15) 27844* immediate operands, x86-64: i386-Variations. (line 15) 27845* imul instruction, i386: i386-Notes. (line 6) 27846* imul instruction, x86-64: i386-Notes. (line 6) 27847* incbin directive: Incbin. (line 6) 27848* include directive: Include. (line 6) 27849* include directive search path: I. (line 6) 27850* indirect character, VAX: VAX-operands. (line 9) 27851* infix operators: Infix Ops. (line 6) 27852* inhibiting interrupts, i386: i386-Prefixes. (line 36) 27853* input: Input Files. (line 6) 27854* input file linenumbers: Input Files. (line 35) 27855* INSN directives: RISC-V-Directives. (line 92) 27856* instruction aliases, s390: s390 Aliases. (line 6) 27857* instruction bundle: Bundle directives. (line 9) 27858* instruction expansion, CRIS: CRIS-Expand. (line 6) 27859* instruction expansion, MMIX: MMIX-Expand. (line 6) 27860* instruction formats, risc-v: RISC-V-Formats. (line 6) 27861* instruction formats, s390: s390 Formats. (line 6) 27862* instruction marker, s390: s390 Instruction Marker. 27863 (line 6) 27864* instruction mnemonics, s390: s390 Mnemonics. (line 6) 27865* instruction naming, i386: i386-Mnemonics. (line 9) 27866* instruction naming, x86-64: i386-Mnemonics. (line 9) 27867* instruction operand modifier, s390: s390 Operand Modifier. 27868 (line 6) 27869* instruction operands, s390: s390 Operands. (line 6) 27870* instruction prefixes, i386: i386-Prefixes. (line 6) 27871* instruction set, M680x0: M68K-opcodes. (line 6) 27872* instruction set, M68HC11: M68HC11-opcodes. (line 6) 27873* instruction set, XGATE: XGATE-opcodes. (line 5) 27874* instruction summary, AVR: AVR Opcodes. (line 6) 27875* instruction summary, D10V: D10V-Opcodes. (line 6) 27876* instruction summary, D30V: D30V-Opcodes. (line 6) 27877* instruction summary, H8/300: H8/300 Opcodes. (line 6) 27878* instruction summary, LM32: LM32 Opcodes. (line 6) 27879* instruction summary, LM32 <1>: OpenRISC-Opcodes. (line 6) 27880* instruction summary, SH: SH Opcodes. (line 6) 27881* instruction summary, Z8000: Z8000 Opcodes. (line 6) 27882* instruction syntax, s390: s390 Syntax. (line 6) 27883* instructions and directives: Statements. (line 20) 27884* int directive: Int. (line 6) 27885* int directive, H8/300: H8/300 Directives. (line 6) 27886* int directive, i386: i386-Float. (line 21) 27887* int directive, TIC54X: TIC54X-Directives. (line 109) 27888* int directive, x86-64: i386-Float. (line 21) 27889* integer expressions: Integer Exprs. (line 6) 27890* integer, 16-byte: Octa. (line 6) 27891* integer, 2-byte: 2byte. (line 6) 27892* integer, 4-byte: 4byte. (line 6) 27893* integer, 8-byte: Quad. (line 9) 27894* integer, 8-byte <1>: 8byte. (line 6) 27895* integers: Integers. (line 6) 27896* integers, 16-bit: hword. (line 6) 27897* integers, 32-bit: Int. (line 6) 27898* integers, binary: Integers. (line 6) 27899* integers, decimal: Integers. (line 12) 27900* integers, hexadecimal: Integers. (line 15) 27901* integers, octal: Integers. (line 9) 27902* integers, one byte: Byte. (line 6) 27903* intel_syntax pseudo op, i386: i386-Variations. (line 6) 27904* intel_syntax pseudo op, x86-64: i386-Variations. (line 6) 27905* internal assembler sections: As Sections. (line 6) 27906* internal directive: Internal. (line 6) 27907* interrupt link register, ARC: ARC-Regs. (line 27) 27908* Interrupt Vector Base address, ARC: ARC-Regs. (line 66) 27909* invalid input: Bug Criteria. (line 14) 27910* invocation summary: Overview. (line 6) 27911* IP2K architecture options: IP2K-Opts. (line 9) 27912* IP2K architecture options <1>: IP2K-Opts. (line 14) 27913* IP2K line comment character: IP2K-Chars. (line 6) 27914* IP2K line separator: IP2K-Chars. (line 14) 27915* IP2K options: IP2K-Opts. (line 6) 27916* IP2K support: IP2K-Dependent. (line 6) 27917* irp directive: Irp. (line 6) 27918* irpc directive: Irpc. (line 6) 27919* joining text and data sections: R. (line 6) 27920* jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 27921* jump instructions, i386: i386-Mnemonics. (line 115) 27922* jump instructions, relaxation: Xtensa Jump Relaxation. 27923 (line 6) 27924* jump instructions, x86-64: i386-Mnemonics. (line 115) 27925* jump optimization, i386: i386-Jumps. (line 6) 27926* jump optimization, x86-64: i386-Jumps. (line 6) 27927* jump/call operands, i386: i386-Variations. (line 15) 27928* jump/call operands, x86-64: i386-Variations. (line 15) 27929* L16SI instructions, relaxation: Xtensa Immediate Relaxation. 27930 (line 23) 27931* L16UI instructions, relaxation: Xtensa Immediate Relaxation. 27932 (line 23) 27933* L32I instructions, relaxation: Xtensa Immediate Relaxation. 27934 (line 23) 27935* L8UI instructions, relaxation: Xtensa Immediate Relaxation. 27936 (line 23) 27937* label (:): Statements. (line 31) 27938* label directive, TIC54X: TIC54X-Directives. (line 121) 27939* labels: Labels. (line 6) 27940* labels, Z80: Z80-Labels. (line 6) 27941* largecomm directive, ELF: i386-Directives. (line 17) 27942* lcomm directive: Lcomm. (line 6) 27943* lcomm directive <1>: ARC Directives. (line 9) 27944* lcomm directive, COFF: i386-Directives. (line 6) 27945* lcommon directive, ARC: ARC Directives. (line 24) 27946* ld: Object. (line 15) 27947* ldouble directive M680x0: M68K-Float. (line 17) 27948* ldouble directive M68HC11: M68HC11-Float. (line 17) 27949* ldouble directive XGATE: XGATE-Float. (line 16) 27950* ldouble directive, TIC54X: TIC54X-Directives. (line 62) 27951* LDR reg,=<expr> pseudo op, AArch64: AArch64 Opcodes. (line 9) 27952* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) 27953* LEB128 directives: RISC-V-Directives. (line 27) 27954* length directive, TIC54X: TIC54X-Directives. (line 125) 27955* length of symbols: Symbol Intro. (line 19) 27956* level 1 interrupt link register, ARC: ARC-Regs. (line 23) 27957* level 2 interrupt link register, ARC: ARC-Regs. (line 31) 27958* lflags directive (ignored): Lflags. (line 6) 27959* line: ARC-Chars. (line 30) 27960* line comment character: Comments. (line 19) 27961* line comment character, AArch64: AArch64-Chars. (line 6) 27962* line comment character, Alpha: Alpha-Chars. (line 6) 27963* line comment character, ARC: ARC-Chars. (line 11) 27964* line comment character, ARM: ARM-Chars. (line 6) 27965* line comment character, AVR: AVR-Chars. (line 6) 27966* line comment character, BPF: BPF-Chars. (line 6) 27967* line comment character, CR16: CR16-Chars. (line 6) 27968* line comment character, D10V: D10V-Chars. (line 6) 27969* line comment character, D30V: D30V-Chars. (line 6) 27970* line comment character, Epiphany: Epiphany-Chars. (line 6) 27971* line comment character, H8/300: H8/300-Chars. (line 6) 27972* line comment character, i386: i386-Chars. (line 6) 27973* line comment character, IA-64: IA-64-Chars. (line 6) 27974* line comment character, IP2K: IP2K-Chars. (line 6) 27975* line comment character, LM32: LM32-Chars. (line 6) 27976* line comment character, M32C: M32C-Chars. (line 6) 27977* line comment character, M680x0: M68K-Chars. (line 6) 27978* line comment character, M68HC11: M68HC11-Syntax. (line 17) 27979* line comment character, Meta: Meta-Chars. (line 6) 27980* line comment character, MicroBlaze: MicroBlaze-Chars. (line 6) 27981* line comment character, MIPS: MIPS-Chars. (line 6) 27982* line comment character, MSP 430: MSP430-Chars. (line 6) 27983* line comment character, Nios II: Nios II Chars. (line 6) 27984* line comment character, NS32K: NS32K-Chars. (line 6) 27985* line comment character, OpenRISC: OpenRISC-Chars. (line 6) 27986* line comment character, PJ: PJ-Chars. (line 6) 27987* line comment character, PowerPC: PowerPC-Chars. (line 6) 27988* line comment character, PRU: PRU Chars. (line 6) 27989* line comment character, RL78: RL78-Chars. (line 6) 27990* line comment character, RX: RX-Chars. (line 6) 27991* line comment character, S12Z: S12Z Syntax Overview. 27992 (line 32) 27993* line comment character, s390: s390 Characters. (line 6) 27994* line comment character, SCORE: SCORE-Chars. (line 6) 27995* line comment character, SH: SH-Chars. (line 6) 27996* line comment character, Sparc: Sparc-Chars. (line 6) 27997* line comment character, TIC54X: TIC54X-Chars. (line 6) 27998* line comment character, TIC6X: TIC6X Syntax. (line 6) 27999* line comment character, V850: V850-Chars. (line 6) 28000* line comment character, VAX: VAX-Chars. (line 6) 28001* line comment character, Visium: Visium Characters. (line 6) 28002* line comment character, WebAssembly: WebAssembly-Chars. (line 6) 28003* line comment character, XGATE: XGATE-Syntax. (line 16) 28004* line comment character, XStormy16: XStormy16-Chars. (line 6) 28005* line comment character, Z80: Z80-Chars. (line 6) 28006* line comment character, Z8000: Z8000-Chars. (line 6) 28007* line comment characters, CRIS: CRIS-Chars. (line 6) 28008* line comment characters, MMIX: MMIX-Chars. (line 6) 28009* line directive: Line. (line 6) 28010* line directive, MSP 430: MSP430 Directives. (line 14) 28011* line numbers, in input files: Input Files. (line 35) 28012* line separator character: Statements. (line 6) 28013* line separator character, Nios II: Nios II Chars. (line 6) 28014* line separator, AArch64: AArch64-Chars. (line 10) 28015* line separator, Alpha: Alpha-Chars. (line 11) 28016* line separator, ARC: ARC-Chars. (line 27) 28017* line separator, ARM: ARM-Chars. (line 14) 28018* line separator, AVR: AVR-Chars. (line 14) 28019* line separator, CR16: CR16-Chars. (line 12) 28020* line separator, Epiphany: Epiphany-Chars. (line 14) 28021* line separator, H8/300: H8/300-Chars. (line 8) 28022* line separator, i386: i386-Chars. (line 18) 28023* line separator, IA-64: IA-64-Chars. (line 8) 28024* line separator, IP2K: IP2K-Chars. (line 14) 28025* line separator, LM32: LM32-Chars. (line 12) 28026* line separator, M32C: M32C-Chars. (line 14) 28027* line separator, M680x0: M68K-Chars. (line 20) 28028* line separator, M68HC11: M68HC11-Syntax. (line 26) 28029* line separator, Meta: Meta-Chars. (line 8) 28030* line separator, MicroBlaze: MicroBlaze-Chars. (line 14) 28031* line separator, MIPS: MIPS-Chars. (line 14) 28032* line separator, MSP 430: MSP430-Chars. (line 14) 28033* line separator, NS32K: NS32K-Chars. (line 18) 28034* line separator, OpenRISC: OpenRISC-Chars. (line 9) 28035* line separator, PJ: PJ-Chars. (line 14) 28036* line separator, PowerPC: PowerPC-Chars. (line 18) 28037* line separator, RL78: RL78-Chars. (line 14) 28038* line separator, RX: RX-Chars. (line 14) 28039* line separator, S12Z: S12Z Syntax Overview. 28040 (line 41) 28041* line separator, s390: s390 Characters. (line 13) 28042* line separator, SCORE: SCORE-Chars. (line 14) 28043* line separator, SH: SH-Chars. (line 8) 28044* line separator, Sparc: Sparc-Chars. (line 14) 28045* line separator, TIC54X: TIC54X-Chars. (line 17) 28046* line separator, TIC6X: TIC6X Syntax. (line 13) 28047* line separator, V850: V850-Chars. (line 13) 28048* line separator, VAX: VAX-Chars. (line 14) 28049* line separator, Visium: Visium Characters. (line 14) 28050* line separator, XGATE: XGATE-Syntax. (line 25) 28051* line separator, XStormy16: XStormy16-Chars. (line 14) 28052* line separator, Z80: Z80-Chars. (line 13) 28053* line separator, Z8000: Z8000-Chars. (line 13) 28054* lines starting with #: Comments. (line 33) 28055* link register, ARC: ARC-Regs. (line 35) 28056* linker: Object. (line 15) 28057* linker, and assembler: Secs Background. (line 10) 28058* linkonce directive: Linkonce. (line 6) 28059* list directive: List. (line 6) 28060* list directive, TIC54X: TIC54X-Directives. (line 129) 28061* listing control, turning off: Nolist. (line 6) 28062* listing control, turning on: List. (line 6) 28063* listing control: new page: Eject. (line 6) 28064* listing control: paper size: Psize. (line 6) 28065* listing control: subtitle: Sbttl. (line 6) 28066* listing control: title line: Title. (line 6) 28067* listings, enabling: a. (line 6) 28068* literal directive: Literal Directive. (line 6) 28069* literal pool entries, s390: s390 Literal Pool Entries. 28070 (line 6) 28071* literal_position directive: Literal Position Directive. 28072 (line 6) 28073* literal_prefix directive: Literal Prefix Directive. 28074 (line 6) 28075* little endian output, MIPS: Overview. (line 859) 28076* little endian output, PJ: Overview. (line 763) 28077* little-endian output, MIPS: MIPS Options. (line 13) 28078* little-endian output, TIC6X: TIC6X Options. (line 46) 28079* LM32 line comment character: LM32-Chars. (line 6) 28080* LM32 line separator: LM32-Chars. (line 12) 28081* LM32 modifiers: LM32-Modifiers. (line 6) 28082* LM32 opcode summary: LM32 Opcodes. (line 6) 28083* LM32 options (none): LM32 Options. (line 6) 28084* LM32 register names: LM32-Regs. (line 6) 28085* LM32 support: LM32-Dependent. (line 6) 28086* ln directive: Ln. (line 6) 28087* lo directive, Nios II: Nios II Relocations. 28088 (line 23) 28089* lo pseudo-op, V850: V850 Opcodes. (line 22) 28090* loc directive: Loc. (line 6) 28091* local common symbols: Lcomm. (line 6) 28092* local directive: Local. (line 6) 28093* local labels: Symbol Names. (line 43) 28094* local symbol names: Symbol Names. (line 30) 28095* local symbols, retaining in output: L. (line 6) 28096* location counter: Dot. (line 6) 28097* location counter, advancing: Org. (line 6) 28098* location counter, Z80: Z80-Chars. (line 15) 28099* loc_mark_labels directive: Loc_mark_labels. (line 6) 28100* logical file name: File. (line 13) 28101* logical line number: Line. (line 6) 28102* logical line numbers: Comments. (line 33) 28103* long directive: Long. (line 6) 28104* long directive, i386: i386-Float. (line 21) 28105* long directive, TIC54X: TIC54X-Directives. (line 133) 28106* long directive, x86-64: i386-Float. (line 21) 28107* longcall pseudo-op, V850: V850 Opcodes. (line 122) 28108* longcalls directive: Longcalls Directive. 28109 (line 6) 28110* longjump pseudo-op, V850: V850 Opcodes. (line 128) 28111* Loongson Content Address Memory (CAM) generation override: MIPS ASE Instruction Generation Overrides. 28112 (line 81) 28113* Loongson EXTensions (EXT) instructions generation override: MIPS ASE Instruction Generation Overrides. 28114 (line 86) 28115* Loongson EXTensions R2 (EXT2) instructions generation override: MIPS ASE Instruction Generation Overrides. 28116 (line 91) 28117* Loongson MultiMedia extensions Instructions (MMI) generation override: MIPS ASE Instruction Generation Overrides. 28118 (line 76) 28119* loop counter, ARC: ARC-Regs. (line 41) 28120* loop directive, TIC54X: TIC54X-Directives. (line 141) 28121* LOOP instructions, alignment: Xtensa Automatic Alignment. 28122 (line 6) 28123* low directive, M32R: M32R-Directives. (line 9) 28124* lp register, V850: V850-Regs. (line 68) 28125* lval: Z8000 Directives. (line 27) 28126* LWP, i386: i386-LWP. (line 6) 28127* LWP, x86-64: i386-LWP. (line 6) 28128* M16C architecture option: M32C-Opts. (line 12) 28129* M32C architecture option: M32C-Opts. (line 9) 28130* M32C line comment character: M32C-Chars. (line 6) 28131* M32C line separator: M32C-Chars. (line 14) 28132* M32C modifiers: M32C-Modifiers. (line 6) 28133* M32C options: M32C-Opts. (line 6) 28134* M32C support: M32C-Dependent. (line 6) 28135* M32R architecture options: M32R-Opts. (line 9) 28136* M32R architecture options <1>: M32R-Opts. (line 17) 28137* M32R architecture options <2>: M32R-Opts. (line 21) 28138* M32R directives: M32R-Directives. (line 6) 28139* M32R options: M32R-Opts. (line 6) 28140* M32R support: M32R-Dependent. (line 6) 28141* M32R warnings: M32R-Warnings. (line 6) 28142* M680x0 addressing modes: M68K-Syntax. (line 21) 28143* M680x0 architecture options: M68K-Opts. (line 99) 28144* M680x0 branch improvement: M68K-Branch. (line 6) 28145* M680x0 directives: M68K-Directives. (line 6) 28146* M680x0 floating point: M68K-Float. (line 6) 28147* M680x0 immediate character: M68K-Chars. (line 13) 28148* M680x0 line comment character: M68K-Chars. (line 6) 28149* M680x0 line separator: M68K-Chars. (line 20) 28150* M680x0 opcodes: M68K-opcodes. (line 6) 28151* M680x0 options: M68K-Opts. (line 6) 28152* M680x0 pseudo-opcodes: M68K-Branch. (line 6) 28153* M680x0 size modifiers: M68K-Syntax. (line 8) 28154* M680x0 support: M68K-Dependent. (line 6) 28155* M680x0 syntax: M68K-Syntax. (line 8) 28156* M68HC11 addressing modes: M68HC11-Syntax. (line 29) 28157* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) 28158* M68HC11 assembler directive .far: M68HC11-Directives. (line 20) 28159* M68HC11 assembler directive .interrupt: M68HC11-Directives. 28160 (line 26) 28161* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16) 28162* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10) 28163* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31) 28164* M68HC11 assembler directives: M68HC11-Directives. (line 6) 28165* M68HC11 branch improvement: M68HC11-Branch. (line 6) 28166* M68HC11 floating point: M68HC11-Float. (line 6) 28167* M68HC11 line comment character: M68HC11-Syntax. (line 17) 28168* M68HC11 line separator: M68HC11-Syntax. (line 26) 28169* M68HC11 modifiers: M68HC11-Modifiers. (line 6) 28170* M68HC11 opcodes: M68HC11-opcodes. (line 6) 28171* M68HC11 options: M68HC11-Opts. (line 6) 28172* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6) 28173* M68HC11 syntax: M68HC11-Syntax. (line 6) 28174* M68HC12 assembler directives: M68HC11-Directives. (line 6) 28175* mA6 command-line option, ARC: ARC Options. (line 14) 28176* mA7 command-line option, ARC: ARC Options. (line 39) 28177* machine dependencies: Machine Dependencies. 28178 (line 6) 28179* machine directives, AArch64: AArch64 Directives. (line 6) 28180* machine directives, ARC: ARC Directives. (line 6) 28181* machine directives, ARM: ARM Directives. (line 6) 28182* machine directives, BPF: BPF Directives. (line 6) 28183* machine directives, H8/300 (none): H8/300 Directives. (line 6) 28184* machine directives, MSP 430: MSP430 Directives. (line 6) 28185* machine directives, Nios II: Nios II Directives. (line 6) 28186* machine directives, OPENRISC: OpenRISC-Directives. 28187 (line 6) 28188* machine directives, PRU: PRU Directives. (line 6) 28189* machine directives, RISC-V: RISC-V-Directives. (line 6) 28190* machine directives, SH: SH Directives. (line 6) 28191* machine directives, SPARC: Sparc-Directives. (line 6) 28192* machine directives, TIC54X: TIC54X-Directives. (line 6) 28193* machine directives, TIC6X: TIC6X Directives. (line 6) 28194* machine directives, TILE-Gx: TILE-Gx Directives. (line 6) 28195* machine directives, TILEPro: TILEPro Directives. (line 6) 28196* machine directives, V850: V850 Directives. (line 6) 28197* machine directives, VAX: VAX-directives. (line 6) 28198* machine directives, x86: i386-Directives. (line 6) 28199* machine directives, XStormy16: XStormy16 Directives. 28200 (line 6) 28201* machine independent directives: Pseudo Ops. (line 6) 28202* machine instructions (not covered): Manual. (line 14) 28203* machine relocations, Nios II: Nios II Relocations. 28204 (line 6) 28205* machine relocations, PRU: PRU Relocations. (line 6) 28206* machine-independent syntax: Syntax. (line 6) 28207* macro directive: Macro. (line 28) 28208* macro directive, TIC54X: TIC54X-Directives. (line 151) 28209* macros: Macro. (line 6) 28210* macros, count executed: Macro. (line 142) 28211* Macros, MSP 430: MSP430-Macros. (line 6) 28212* macros, TIC54X: TIC54X-Macros. (line 6) 28213* make rules: MD. (line 6) 28214* manual, structure and purpose: Manual. (line 6) 28215* marc600 command-line option, ARC: ARC Options. (line 14) 28216* mARC601 command-line option, ARC: ARC Options. (line 27) 28217* mARC700 command-line option, ARC: ARC Options. (line 39) 28218* march command-line option, C-SKY: C-SKY Options. (line 6) 28219* march command-line option, Nios II: Nios II Options. (line 28) 28220* math builtins, TIC54X: TIC54X-Builtins. (line 6) 28221* Maximum number of continuation lines: listing. (line 34) 28222* mbig-endian command-line option, C-SKY: C-SKY Options. (line 18) 28223* mbranch-stub command-line option, C-SKY: C-SKY Options. (line 34) 28224* mcache command-line option, C-SKY: C-SKY Options. (line 100) 28225* mcp command-line option, C-SKY: C-SKY Options. (line 97) 28226* mcpu command-line option, C-SKY: C-SKY Options. (line 10) 28227* mdsp command-line option, C-SKY: C-SKY Options. (line 109) 28228* medsp command-line option, C-SKY: C-SKY Options. (line 112) 28229* melrw command-line option, C-SKY: C-SKY Options. (line 64) 28230* mEM command-line option, ARC: ARC Options. (line 42) 28231* memory references, i386: i386-Memory. (line 6) 28232* memory references, x86-64: i386-Memory. (line 6) 28233* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6) 28234* merging text and data sections: R. (line 6) 28235* messages from assembler: Errors. (line 6) 28236* Meta architectures: Meta Options. (line 6) 28237* Meta line comment character: Meta-Chars. (line 6) 28238* Meta line separator: Meta-Chars. (line 8) 28239* Meta options: Meta Options. (line 6) 28240* Meta registers: Meta-Regs. (line 6) 28241* Meta support: Meta-Dependent. (line 6) 28242* mforce2bsr command-line option, C-SKY: C-SKY Options. (line 43) 28243* mhard-float command-line option, C-SKY: C-SKY Options. (line 91) 28244* mHS command-line option, ARC: ARC Options. (line 64) 28245* MicroBlaze architectures: MicroBlaze-Dependent. 28246 (line 6) 28247* MicroBlaze directives: MicroBlaze Directives. 28248 (line 6) 28249* MicroBlaze line comment character: MicroBlaze-Chars. (line 6) 28250* MicroBlaze line separator: MicroBlaze-Chars. (line 14) 28251* MicroBlaze support: MicroBlaze-Dependent. 28252 (line 12) 28253* minus, permitted arguments: Infix Ops. (line 50) 28254* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options. 28255 (line 18) 28256* MIPS architecture options: MIPS Options. (line 29) 28257* MIPS big-endian output: MIPS Options. (line 13) 28258* MIPS CPU override: MIPS ISA. (line 18) 28259* MIPS cyclic redundancy check (CRC) instruction generation override: MIPS ASE Instruction Generation Overrides. 28260 (line 68) 28261* MIPS directives to override command-line options: MIPS assembly options. 28262 (line 6) 28263* MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides. 28264 (line 21) 28265* MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides. 28266 (line 26) 28267* MIPS DSP Release 3 instruction generation override: MIPS ASE Instruction Generation Overrides. 28268 (line 31) 28269* MIPS endianness: Overview. (line 856) 28270* MIPS eXtended Physical Address (XPA) instruction generation override: MIPS ASE Instruction Generation Overrides. 28271 (line 57) 28272* MIPS Global INValidate (GINV) instruction generation override: MIPS ASE Instruction Generation Overrides. 28273 (line 72) 28274* MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings. 28275 (line 6) 28276* MIPS ISA: Overview. (line 862) 28277* MIPS ISA override: MIPS ISA. (line 6) 28278* MIPS line comment character: MIPS-Chars. (line 6) 28279* MIPS line separator: MIPS-Chars. (line 14) 28280* MIPS little-endian output: MIPS Options. (line 13) 28281* MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides. 28282 (line 42) 28283* MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides. 28284 (line 16) 28285* MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides. 28286 (line 6) 28287* MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides. 28288 (line 37) 28289* MIPS option stack: MIPS Option Stack. (line 6) 28290* MIPS processor: MIPS-Dependent. (line 6) 28291* MIPS SIMD Architecture instruction generation override: MIPS ASE Instruction Generation Overrides. 28292 (line 47) 28293* MIPS16e2 instruction generation override: MIPS ASE Instruction Generation Overrides. 28294 (line 61) 28295* mistack command-line option, C-SKY: C-SKY Options. (line 82) 28296* MIT: M68K-Syntax. (line 6) 28297* mjsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 28298* mlabr command-line option, C-SKY: C-SKY Options. (line 75) 28299* mlaf command-line option, C-SKY: C-SKY Options. (line 69) 28300* mlib directive, TIC54X: TIC54X-Directives. (line 157) 28301* mlink-relax command-line option, PRU: PRU Options. (line 6) 28302* mlist directive, TIC54X: TIC54X-Directives. (line 162) 28303* mliterals-after-br command-line option, C-SKY: C-SKY Options. 28304 (line 75) 28305* mliterals-after-func command-line option, C-SKY: C-SKY Options. 28306 (line 69) 28307* mlittle-endian command-line option, C-SKY: C-SKY Options. (line 14) 28308* mljump command-line option, C-SKY: C-SKY Options. (line 26) 28309* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 137) 28310* MMIX assembler directive BYTE: MMIX-Pseudos. (line 101) 28311* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 137) 28312* MMIX assembler directive GREG: MMIX-Pseudos. (line 53) 28313* MMIX assembler directive IS: MMIX-Pseudos. (line 44) 28314* MMIX assembler directive LOC: MMIX-Pseudos. (line 7) 28315* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 29) 28316* MMIX assembler directive OCTA: MMIX-Pseudos. (line 113) 28317* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 125) 28318* MMIX assembler directive TETRA: MMIX-Pseudos. (line 113) 28319* MMIX assembler directive WYDE: MMIX-Pseudos. (line 113) 28320* MMIX assembler directives: MMIX-Pseudos. (line 6) 28321* MMIX line comment characters: MMIX-Chars. (line 6) 28322* MMIX options: MMIX-Opts. (line 6) 28323* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 137) 28324* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 101) 28325* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 137) 28326* MMIX pseudo-op GREG: MMIX-Pseudos. (line 53) 28327* MMIX pseudo-op IS: MMIX-Pseudos. (line 44) 28328* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) 28329* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 29) 28330* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 113) 28331* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 125) 28332* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 113) 28333* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 113) 28334* MMIX pseudo-ops: MMIX-Pseudos. (line 6) 28335* MMIX register names: MMIX-Regs. (line 6) 28336* MMIX support: MMIX-Dependent. (line 6) 28337* mmixal differences: MMIX-mmixal. (line 6) 28338* mmp command-line option, C-SKY: C-SKY Options. (line 94) 28339* mmregs directive, TIC54X: TIC54X-Directives. (line 167) 28340* mmsg directive, TIC54X: TIC54X-Directives. (line 75) 28341* MMX, i386: i386-SIMD. (line 6) 28342* MMX, x86-64: i386-SIMD. (line 6) 28343* mnemonic compatibility, i386: i386-Mnemonics. (line 121) 28344* mnemonic suffixes, i386: i386-Variations. (line 28) 28345* mnemonic suffixes, x86-64: i386-Variations. (line 28) 28346* mnemonics for opcodes, VAX: VAX-opcodes. (line 6) 28347* mnemonics, AVR: AVR Opcodes. (line 6) 28348* mnemonics, D10V: D10V-Opcodes. (line 6) 28349* mnemonics, D30V: D30V-Opcodes. (line 6) 28350* mnemonics, H8/300: H8/300 Opcodes. (line 6) 28351* mnemonics, LM32: LM32 Opcodes. (line 6) 28352* mnemonics, OpenRISC: OpenRISC-Opcodes. (line 6) 28353* mnemonics, SH: SH Opcodes. (line 6) 28354* mnemonics, Z8000: Z8000 Opcodes. (line 6) 28355* mno-branch-stub command-line option, C-SKY: C-SKY Options. (line 34) 28356* mno-elrw command-line option, C-SKY: C-SKY Options. (line 64) 28357* mno-force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 28358* mno-istack command-line option, C-SKY: C-SKY Options. (line 82) 28359* mno-jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 28360* mno-labr command-line option, C-SKY: C-SKY Options. (line 75) 28361* mno-laf command-line option, C-SKY: C-SKY Options. (line 69) 28362* mno-link-relax command-line option, PRU: PRU Options. (line 12) 28363* mno-literals-after-func command-line option, C-SKY: C-SKY Options. 28364 (line 69) 28365* mno-ljump command-line option, C-SKY: C-SKY Options. (line 26) 28366* mno-lrw command-line option, C-SKY: C-SKY Options. (line 59) 28367* mno-warn-regname-label command-line option, PRU: PRU Options. 28368 (line 16) 28369* mnolist directive, TIC54X: TIC54X-Directives. (line 162) 28370* mnoliterals-after-br command-line option, C-SKY: C-SKY Options. 28371 (line 75) 28372* mnolrw command-line option, C-SKY: C-SKY Options. (line 59) 28373* mnps400 command-line option, ARC: ARC Options. (line 79) 28374* modifiers, M32C: M32C-Modifiers. (line 6) 28375* module layout, WebAssembly: WebAssembly-module-layout. 28376 (line 6) 28377* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) 28378* MOVI instructions, relaxation: Xtensa Immediate Relaxation. 28379 (line 12) 28380* MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations. 28381 (line 6) 28382* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21) 28383* MRI compatibility mode: M. (line 6) 28384* mri directive: MRI. (line 6) 28385* MRI mode, temporarily: MRI. (line 6) 28386* msecurity command-line option, C-SKY: C-SKY Options. (line 103) 28387* MSP 430 floating point (IEEE): MSP430 Floating Point. 28388 (line 6) 28389* MSP 430 identifiers: MSP430-Chars. (line 17) 28390* MSP 430 line comment character: MSP430-Chars. (line 6) 28391* MSP 430 line separator: MSP430-Chars. (line 14) 28392* MSP 430 machine directives: MSP430 Directives. (line 6) 28393* MSP 430 macros: MSP430-Macros. (line 6) 28394* MSP 430 opcodes: MSP430 Opcodes. (line 6) 28395* MSP 430 options (none): MSP430 Options. (line 6) 28396* MSP 430 profiling capability: MSP430 Profiling Capability. 28397 (line 6) 28398* MSP 430 register names: MSP430-Regs. (line 6) 28399* MSP 430 support: MSP430-Dependent. (line 6) 28400* MSP430 Assembler Extensions: MSP430-Ext. (line 6) 28401* mspabi_attribute directive, MSP430: MSP430 Directives. (line 38) 28402* mtrust command-line option, C-SKY: C-SKY Options. (line 106) 28403* mul instruction, i386: i386-Notes. (line 6) 28404* mul instruction, x86-64: i386-Notes. (line 6) 28405* mvdsp command-line option, C-SKY: C-SKY Options. (line 115) 28406* N32K support: NS32K-Dependent. (line 6) 28407* name: Z8000 Directives. (line 18) 28408* named section: Section. (line 6) 28409* named sections: Ld Sections. (line 8) 28410* names, symbol: Symbol Names. (line 6) 28411* naming object file: o. (line 6) 28412* NDS32 options: NDS32 Options. (line 6) 28413* NDS32 processor: NDS32-Dependent. (line 6) 28414* new page, in listings: Eject. (line 6) 28415* newblock directive, TIC54X: TIC54X-Directives. (line 173) 28416* newline (\n): Strings. (line 21) 28417* newline, required at file end: Statements. (line 14) 28418* Nios II line comment character: Nios II Chars. (line 6) 28419* Nios II line separator character: Nios II Chars. (line 6) 28420* Nios II machine directives: Nios II Directives. (line 6) 28421* Nios II machine relocations: Nios II Relocations. 28422 (line 6) 28423* Nios II opcodes: Nios II Opcodes. (line 6) 28424* Nios II options: Nios II Options. (line 6) 28425* Nios II support: NiosII-Dependent. (line 6) 28426* Nios support: NiosII-Dependent. (line 6) 28427* no-absolute-literals directive: Absolute Literals Directive. 28428 (line 6) 28429* no-force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 28430* no-jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 28431* no-longcalls directive: Longcalls Directive. 28432 (line 6) 28433* no-relax command-line option, Nios II: Nios II Options. (line 19) 28434* no-schedule directive: Schedule Directive. (line 6) 28435* no-transform directive: Transform Directive. 28436 (line 6) 28437* nodelay directive, OpenRISC: OpenRISC-Directives. 28438 (line 15) 28439* nolist directive: Nolist. (line 6) 28440* nolist directive, TIC54X: TIC54X-Directives. (line 129) 28441* nop directive: Nop. (line 6) 28442* NOP pseudo op, ARM: ARM Opcodes. (line 9) 28443* nops directive: Nops. (line 6) 28444* notes for Alpha: Alpha Notes. (line 6) 28445* notes for WebAssembly: WebAssembly-Notes. (line 6) 28446* NS32K line comment character: NS32K-Chars. (line 6) 28447* NS32K line separator: NS32K-Chars. (line 18) 28448* null-terminated strings: Asciz. (line 6) 28449* number constants: Numbers. (line 6) 28450* number of macros executed: Macro. (line 142) 28451* numbered subsections: Sub-Sections. (line 6) 28452* numbers, 16-bit: hword. (line 6) 28453* numeric values: Expressions. (line 6) 28454* nword directive, SPARC: Sparc-Directives. (line 20) 28455* Object Attribute, RISC-V: RISC-V-ATTRIBUTE. (line 6) 28456* object attributes: Object Attributes. (line 6) 28457* object file: Object. (line 6) 28458* object file format: Object Formats. (line 6) 28459* object file name: o. (line 6) 28460* object file, after errors: Z. (line 6) 28461* obsolescent directives: Deprecated. (line 6) 28462* octa directive: Octa. (line 6) 28463* octal character code (\DDD): Strings. (line 30) 28464* octal integers: Integers. (line 9) 28465* offset directive: Offset. (line 6) 28466* offset directive, V850: V850 Directives. (line 6) 28467* opcode mnemonics, VAX: VAX-opcodes. (line 6) 28468* opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6) 28469* opcode names, TILEPro: TILEPro Opcodes. (line 6) 28470* opcode names, Xtensa: Xtensa Opcodes. (line 6) 28471* opcode summary, AVR: AVR Opcodes. (line 6) 28472* opcode summary, D10V: D10V-Opcodes. (line 6) 28473* opcode summary, D30V: D30V-Opcodes. (line 6) 28474* opcode summary, H8/300: H8/300 Opcodes. (line 6) 28475* opcode summary, LM32: LM32 Opcodes. (line 6) 28476* opcode summary, OpenRISC: OpenRISC-Opcodes. (line 6) 28477* opcode summary, SH: SH Opcodes. (line 6) 28478* opcode summary, Z8000: Z8000 Opcodes. (line 6) 28479* opcodes for AArch64: AArch64 Opcodes. (line 6) 28480* opcodes for ARC: ARC Opcodes. (line 6) 28481* opcodes for ARM: ARM Opcodes. (line 6) 28482* opcodes for BPF: BPF Opcodes. (line 6) 28483* opcodes for MSP 430: MSP430 Opcodes. (line 6) 28484* opcodes for Nios II: Nios II Opcodes. (line 6) 28485* opcodes for PRU: PRU Opcodes. (line 6) 28486* opcodes for V850: V850 Opcodes. (line 6) 28487* opcodes, M680x0: M68K-opcodes. (line 6) 28488* opcodes, M68HC11: M68HC11-opcodes. (line 6) 28489* opcodes, WebAssembly: WebAssembly-Opcodes. 28490 (line 6) 28491* OPENRISC floating point (IEEE): OpenRISC-Float. (line 6) 28492* OpenRISC line comment character: OpenRISC-Chars. (line 6) 28493* OpenRISC line separator: OpenRISC-Chars. (line 9) 28494* OPENRISC machine directives: OpenRISC-Directives. 28495 (line 6) 28496* OpenRISC opcode summary: OpenRISC-Opcodes. (line 6) 28497* OpenRISC registers: OpenRISC-Regs. (line 6) 28498* OpenRISC relocations: OpenRISC-Relocs. (line 6) 28499* OPENRISC support: OpenRISC-Dependent. (line 6) 28500* OPENRISC syntax: OpenRISC-Dependent. (line 13) 28501* operand delimiters, i386: i386-Variations. (line 15) 28502* operand delimiters, x86-64: i386-Variations. (line 15) 28503* operand notation, VAX: VAX-operands. (line 6) 28504* operands in expressions: Arguments. (line 6) 28505* operator precedence: Infix Ops. (line 11) 28506* operators, in expressions: Operators. (line 6) 28507* operators, permitted arguments: Infix Ops. (line 6) 28508* optimization, D10V: Overview. (line 639) 28509* optimization, D30V: Overview. (line 644) 28510* optimizations: Xtensa Optimizations. 28511 (line 6) 28512* Option directive: RISC-V-Directives. (line 34) 28513* option directive: RISC-V-Directives. (line 34) 28514* option directive, TIC54X: TIC54X-Directives. (line 177) 28515* option summary: Overview. (line 6) 28516* options for AArch64 (none): AArch64 Options. (line 6) 28517* options for Alpha: Alpha Options. (line 6) 28518* options for ARC: ARC Options. (line 6) 28519* options for ARM (none): ARM Options. (line 6) 28520* options for AVR (none): AVR Options. (line 6) 28521* options for Blackfin (none): Blackfin Options. (line 6) 28522* options for BPF (none): BPF Options. (line 6) 28523* options for C-SKY: C-SKY Options. (line 6) 28524* options for i386: i386-Options. (line 6) 28525* options for IA-64: IA-64 Options. (line 6) 28526* options for LM32 (none): LM32 Options. (line 6) 28527* options for Meta: Meta Options. (line 6) 28528* options for MSP430 (none): MSP430 Options. (line 6) 28529* options for NDS32: NDS32 Options. (line 6) 28530* options for Nios II: Nios II Options. (line 6) 28531* options for PDP-11: PDP-11-Options. (line 6) 28532* options for PowerPC: PowerPC-Opts. (line 6) 28533* options for PRU: PRU Options. (line 6) 28534* options for s390: s390 Options. (line 6) 28535* options for SCORE: SCORE-Opts. (line 6) 28536* options for SPARC: Sparc-Opts. (line 6) 28537* options for TIC6X: TIC6X Options. (line 6) 28538* options for V850 (none): V850 Options. (line 6) 28539* options for VAX/VMS: VAX-Opts. (line 42) 28540* options for Visium: Visium Options. (line 6) 28541* options for x86-64: i386-Options. (line 6) 28542* options for Z80: Z80 Options. (line 6) 28543* options, all versions of assembler: Invoking. (line 6) 28544* options, command line: Command Line. (line 13) 28545* options, CRIS: CRIS-Opts. (line 6) 28546* options, D10V: D10V-Opts. (line 6) 28547* options, D30V: D30V-Opts. (line 6) 28548* options, Epiphany: Epiphany Options. (line 6) 28549* options, H8/300: H8/300 Options. (line 6) 28550* options, IP2K: IP2K-Opts. (line 6) 28551* options, M32C: M32C-Opts. (line 6) 28552* options, M32R: M32R-Opts. (line 6) 28553* options, M680x0: M68K-Opts. (line 6) 28554* options, M68HC11: M68HC11-Opts. (line 6) 28555* options, MMIX: MMIX-Opts. (line 6) 28556* options, PJ: PJ Options. (line 6) 28557* options, RL78: RL78-Opts. (line 6) 28558* options, RX: RX-Opts. (line 6) 28559* options, S12Z: S12Z Options. (line 6) 28560* options, SH: SH Options. (line 6) 28561* options, TIC54X: TIC54X-Opts. (line 6) 28562* options, XGATE: XGATE-Opts. (line 6) 28563* options, Z8000: Z8000 Options. (line 6) 28564* org directive: Org. (line 6) 28565* other attribute, of a.out symbol: Symbol Other. (line 6) 28566* output file: Object. (line 6) 28567* output section padding: no-pad-sections. (line 6) 28568* p2align directive: P2align. (line 6) 28569* p2alignl directive: P2align. (line 30) 28570* p2alignw directive: P2align. (line 30) 28571* padding the location counter: Align. (line 6) 28572* padding the location counter given a power of two: P2align. 28573 (line 6) 28574* padding the location counter given number of bytes: Balign. 28575 (line 6) 28576* page, in listings: Eject. (line 6) 28577* paper size, for listings: Psize. (line 6) 28578* paths for .include: I. (line 6) 28579* patterns, writing in memory: Fill. (line 6) 28580* PDP-11 comments: PDP-11-Syntax. (line 16) 28581* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) 28582* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10) 28583* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6) 28584* PDP-11 line separator: PDP-11-Syntax. (line 19) 28585* PDP-11 support: PDP-11-Dependent. (line 6) 28586* PDP-11 syntax: PDP-11-Syntax. (line 6) 28587* PIC code generation for ARM: ARM Options. (line 376) 28588* PIC code generation for M32R: M32R-Opts. (line 42) 28589* pic command-line option, C-SKY: C-SKY Options. (line 22) 28590* PIC selection, MIPS: MIPS Options. (line 21) 28591* PJ endianness: Overview. (line 760) 28592* PJ line comment character: PJ-Chars. (line 6) 28593* PJ line separator: PJ-Chars. (line 14) 28594* PJ options: PJ Options. (line 6) 28595* PJ support: PJ-Dependent. (line 6) 28596* plus, permitted arguments: Infix Ops. (line 45) 28597* pmem directive, PRU: PRU Relocations. (line 6) 28598* popsection directive: PopSection. (line 6) 28599* Position-independent code, CRIS: CRIS-Opts. (line 27) 28600* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) 28601* PowerPC architectures: PowerPC-Opts. (line 6) 28602* PowerPC directives: PowerPC-Pseudo. (line 6) 28603* PowerPC line comment character: PowerPC-Chars. (line 6) 28604* PowerPC line separator: PowerPC-Chars. (line 18) 28605* PowerPC options: PowerPC-Opts. (line 6) 28606* PowerPC support: PPC-Dependent. (line 6) 28607* precedence of operators: Infix Ops. (line 11) 28608* precision, floating point: Flonums. (line 6) 28609* prefix operators: Prefix Ops. (line 6) 28610* prefixes, i386: i386-Prefixes. (line 6) 28611* preprocessing: Preprocessing. (line 6) 28612* preprocessing, turning on and off: Preprocessing. (line 28) 28613* previous directive: Previous. (line 6) 28614* primary attributes, COFF symbols: COFF Symbols. (line 13) 28615* print directive: Print. (line 6) 28616* proc directive, OpenRISC: OpenRISC-Directives. 28617 (line 20) 28618* proc directive, SPARC: Sparc-Directives. (line 25) 28619* Processor Identification register, ARC: ARC-Regs. (line 51) 28620* profiler directive, MSP 430: MSP430 Directives. (line 26) 28621* profiling capability for MSP 430: MSP430 Profiling Capability. 28622 (line 6) 28623* Program Counter, ARC: ARC-Regs. (line 54) 28624* protected directive: Protected. (line 6) 28625* PRU line comment character: PRU Chars. (line 6) 28626* PRU machine directives: PRU Directives. (line 6) 28627* PRU machine relocations: PRU Relocations. (line 6) 28628* PRU opcodes: PRU Opcodes. (line 6) 28629* PRU options: PRU Options. (line 6) 28630* PRU support: PRU-Dependent. (line 6) 28631* psect directive, Z80: Z80 Directives. (line 58) 28632* pseudo map fd, BPF: BPF-Pseudo-Maps. (line 6) 28633* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 50) 28634* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) 28635* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 18) 28636* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 137) 28637* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 101) 28638* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 137) 28639* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 53) 28640* pseudo-op IS, MMIX: MMIX-Pseudos. (line 44) 28641* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) 28642* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 29) 28643* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 113) 28644* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 125) 28645* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 113) 28646* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 113) 28647* pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6) 28648* pseudo-opcodes, M680x0: M68K-Branch. (line 6) 28649* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) 28650* pseudo-ops for branch, VAX: VAX-branch. (line 6) 28651* pseudo-ops, CRIS: CRIS-Pseudos. (line 6) 28652* pseudo-ops, machine independent: Pseudo Ops. (line 6) 28653* pseudo-ops, MMIX: MMIX-Pseudos. (line 6) 28654* psize directive: Psize. (line 6) 28655* PSR bits: IA-64-Bits. (line 6) 28656* pstring directive, TIC54X: TIC54X-Directives. (line 206) 28657* psw register, V850: V850-Regs. (line 80) 28658* purgem directive: Purgem. (line 6) 28659* purpose of GNU assembler: GNU Assembler. (line 12) 28660* pushsection directive: PushSection. (line 6) 28661* quad directive: Quad. (line 6) 28662* quad directive, i386: i386-Float. (line 21) 28663* quad directive, x86-64: i386-Float. (line 21) 28664* real-mode code, i386: i386-16bit. (line 6) 28665* ref directive, TIC54X: TIC54X-Directives. (line 101) 28666* refsym directive, MSP 430: MSP430 Directives. (line 30) 28667* register directive, SPARC: Sparc-Directives. (line 29) 28668* register name prefix character, ARC: ARC-Chars. (line 7) 28669* register names, AArch64: AArch64-Regs. (line 6) 28670* register names, Alpha: Alpha-Regs. (line 6) 28671* register names, ARC: ARC-Regs. (line 6) 28672* register names, ARM: ARM-Regs. (line 6) 28673* register names, AVR: AVR-Regs. (line 6) 28674* register names, BPF: BPF-Regs. (line 6) 28675* register names, CRIS: CRIS-Regs. (line 6) 28676* register names, H8/300: H8/300-Regs. (line 6) 28677* register names, IA-64: IA-64-Regs. (line 6) 28678* register names, LM32: LM32-Regs. (line 6) 28679* register names, MMIX: MMIX-Regs. (line 6) 28680* register names, MSP 430: MSP430-Regs. (line 6) 28681* register names, OpenRISC: OpenRISC-Regs. (line 6) 28682* register names, S12Z: S12Z Addressing Modes. 28683 (line 28) 28684* register names, Sparc: Sparc-Regs. (line 6) 28685* register names, TILE-Gx: TILE-Gx Registers. (line 6) 28686* register names, TILEPro: TILEPro Registers. (line 6) 28687* register names, V850: V850-Regs. (line 6) 28688* register names, VAX: VAX-operands. (line 17) 28689* register names, Visium: Visium Registers. (line 6) 28690* register names, Xtensa: Xtensa Registers. (line 6) 28691* register names, Z80: Z80-Regs. (line 6) 28692* register naming, s390: s390 Register. (line 6) 28693* register notation, S12Z: S12Z Register Notation. 28694 (line 6) 28695* register operands, i386: i386-Variations. (line 15) 28696* register operands, x86-64: i386-Variations. (line 15) 28697* registers, D10V: D10V-Regs. (line 6) 28698* registers, D30V: D30V-Regs. (line 6) 28699* registers, i386: i386-Regs. (line 6) 28700* registers, Meta: Meta-Regs. (line 6) 28701* registers, SH: SH-Regs. (line 6) 28702* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) 28703* registers, x86-64: i386-Regs. (line 6) 28704* registers, Z8000: Z8000-Regs. (line 6) 28705* relax-all command-line option, Nios II: Nios II Options. (line 13) 28706* relax-section command-line option, Nios II: Nios II Options. 28707 (line 6) 28708* relaxation: Xtensa Relaxation. (line 6) 28709* relaxation of ADDI instructions: Xtensa Immediate Relaxation. 28710 (line 43) 28711* relaxation of branch instructions: Xtensa Branch Relaxation. 28712 (line 6) 28713* relaxation of call instructions: Xtensa Call Relaxation. 28714 (line 6) 28715* relaxation of immediate fields: Xtensa Immediate Relaxation. 28716 (line 6) 28717* relaxation of jump instructions: Xtensa Jump Relaxation. 28718 (line 6) 28719* relaxation of L16SI instructions: Xtensa Immediate Relaxation. 28720 (line 23) 28721* relaxation of L16UI instructions: Xtensa Immediate Relaxation. 28722 (line 23) 28723* relaxation of L32I instructions: Xtensa Immediate Relaxation. 28724 (line 23) 28725* relaxation of L8UI instructions: Xtensa Immediate Relaxation. 28726 (line 23) 28727* relaxation of MOVI instructions: Xtensa Immediate Relaxation. 28728 (line 12) 28729* reloc directive: Reloc. (line 6) 28730* relocation: Sections. (line 6) 28731* relocation example: Ld Sections. (line 40) 28732* relocations, AArch64: AArch64-Relocations. 28733 (line 6) 28734* relocations, Alpha: Alpha-Relocs. (line 6) 28735* relocations, OpenRISC: OpenRISC-Relocs. (line 6) 28736* relocations, Sparc: Sparc-Relocs. (line 6) 28737* relocations, WebAssembly: WebAssembly-Relocs. (line 6) 28738* repeat prefixes, i386: i386-Prefixes. (line 44) 28739* reporting bugs in assembler: Reporting Bugs. (line 6) 28740* rept directive: Rept. (line 6) 28741* reserve directive, SPARC: Sparc-Directives. (line 39) 28742* return instructions, i386: i386-Variations. (line 45) 28743* return instructions, x86-64: i386-Variations. (line 45) 28744* REX prefixes, i386: i386-Prefixes. (line 46) 28745* RISC-V instruction formats: RISC-V-Formats. (line 6) 28746* RISC-V machine directives: RISC-V-Directives. (line 6) 28747* RISC-V support: RISC-V-Dependent. (line 6) 28748* RL78 assembler directives: RL78-Directives. (line 6) 28749* RL78 line comment character: RL78-Chars. (line 6) 28750* RL78 line separator: RL78-Chars. (line 14) 28751* RL78 modifiers: RL78-Modifiers. (line 6) 28752* RL78 options: RL78-Opts. (line 6) 28753* RL78 support: RL78-Dependent. (line 6) 28754* rsect: Z8000 Directives. (line 52) 28755* RX assembler directive .3byte: RX-Directives. (line 9) 28756* RX assembler directive .fetchalign: RX-Directives. (line 13) 28757* RX assembler directives: RX-Directives. (line 6) 28758* RX floating point: RX-Float. (line 6) 28759* RX line comment character: RX-Chars. (line 6) 28760* RX line separator: RX-Chars. (line 14) 28761* RX modifiers: RX-Modifiers. (line 6) 28762* RX options: RX-Opts. (line 6) 28763* RX support: RX-Dependent. (line 6) 28764* S12Z addressing modes: S12Z Addressing Modes. 28765 (line 6) 28766* S12Z line separator: S12Z Syntax Overview. 28767 (line 41) 28768* S12Z options: S12Z Options. (line 6) 28769* S12Z support: S12Z-Dependent. (line 8) 28770* S12Z syntax: S12Z Syntax. (line 12) 28771* s390 floating point: s390 Floating Point. 28772 (line 6) 28773* s390 instruction aliases: s390 Aliases. (line 6) 28774* s390 instruction formats: s390 Formats. (line 6) 28775* s390 instruction marker: s390 Instruction Marker. 28776 (line 6) 28777* s390 instruction mnemonics: s390 Mnemonics. (line 6) 28778* s390 instruction operand modifier: s390 Operand Modifier. 28779 (line 6) 28780* s390 instruction operands: s390 Operands. (line 6) 28781* s390 instruction syntax: s390 Syntax. (line 6) 28782* s390 line comment character: s390 Characters. (line 6) 28783* s390 line separator: s390 Characters. (line 13) 28784* s390 literal pool entries: s390 Literal Pool Entries. 28785 (line 6) 28786* s390 options: s390 Options. (line 6) 28787* s390 register naming: s390 Register. (line 6) 28788* s390 support: S/390-Dependent. (line 6) 28789* Saved User Stack Pointer, ARC: ARC-Regs. (line 73) 28790* sblock directive, TIC54X: TIC54X-Directives. (line 180) 28791* sbttl directive: Sbttl. (line 6) 28792* schedule directive: Schedule Directive. (line 6) 28793* scl directive: Scl. (line 6) 28794* SCORE architectures: SCORE-Opts. (line 6) 28795* SCORE directives: SCORE-Pseudo. (line 6) 28796* SCORE line comment character: SCORE-Chars. (line 6) 28797* SCORE line separator: SCORE-Chars. (line 14) 28798* SCORE options: SCORE-Opts. (line 6) 28799* SCORE processor: SCORE-Dependent. (line 6) 28800* sdaoff pseudo-op, V850: V850 Opcodes. (line 65) 28801* search path for .include: I. (line 6) 28802* sect directive, TIC54X: TIC54X-Directives. (line 186) 28803* section directive (COFF version): Section. (line 16) 28804* section directive (ELF version): Section. (line 67) 28805* section directive, V850: V850 Directives. (line 9) 28806* section name substitution: Section. (line 71) 28807* section override prefixes, i386: i386-Prefixes. (line 23) 28808* Section Stack: PopSection. (line 6) 28809* Section Stack <1>: Previous. (line 6) 28810* Section Stack <2>: PushSection. (line 6) 28811* Section Stack <3>: Section. (line 62) 28812* Section Stack <4>: SubSection. (line 6) 28813* section-relative addressing: Secs Background. (line 65) 28814* sections: Sections. (line 6) 28815* sections in messages, internal: As Sections. (line 6) 28816* sections, i386: i386-Variations. (line 51) 28817* sections, named: Ld Sections. (line 8) 28818* sections, x86-64: i386-Variations. (line 51) 28819* seg directive, SPARC: Sparc-Directives. (line 44) 28820* segm: Z8000 Directives. (line 10) 28821* set at directive, Nios II: Nios II Directives. (line 35) 28822* set break directive, Nios II: Nios II Directives. (line 43) 28823* set directive: Set. (line 6) 28824* set directive, Nios II: Nios II Directives. (line 57) 28825* set directive, TIC54X: TIC54X-Directives. (line 189) 28826* set noat directive, Nios II: Nios II Directives. (line 31) 28827* set nobreak directive, Nios II: Nios II Directives. (line 39) 28828* set norelax directive, Nios II: Nios II Directives. (line 46) 28829* set no_warn_regname_label directive, PRU: PRU Directives. (line 28) 28830* set relaxall directive, Nios II: Nios II Directives. (line 53) 28831* set relaxsection directive, Nios II: Nios II Directives. (line 49) 28832* SH addressing modes: SH-Addressing. (line 6) 28833* SH floating point (IEEE): SH Floating Point. (line 6) 28834* SH line comment character: SH-Chars. (line 6) 28835* SH line separator: SH-Chars. (line 8) 28836* SH machine directives: SH Directives. (line 6) 28837* SH opcode summary: SH Opcodes. (line 6) 28838* SH options: SH Options. (line 6) 28839* SH registers: SH-Regs. (line 6) 28840* SH support: SH-Dependent. (line 6) 28841* shigh directive, M32R: M32R-Directives. (line 26) 28842* short directive: Short. (line 6) 28843* short directive, TIC54X: TIC54X-Directives. (line 109) 28844* signatures, WebAssembly: WebAssembly-Signatures. 28845 (line 6) 28846* SIMD, i386: i386-SIMD. (line 6) 28847* SIMD, x86-64: i386-SIMD. (line 6) 28848* single character constant: Chars. (line 6) 28849* single directive: Single. (line 6) 28850* single directive, i386: i386-Float. (line 14) 28851* single directive, x86-64: i386-Float. (line 14) 28852* single quote, Z80: Z80-Chars. (line 20) 28853* sixteen bit integers: hword. (line 6) 28854* sixteen byte integer: Octa. (line 6) 28855* size directive (COFF version): Size. (line 11) 28856* size directive (ELF version): Size. (line 19) 28857* size modifiers, D10V: D10V-Size. (line 6) 28858* size modifiers, D30V: D30V-Size. (line 6) 28859* size modifiers, M680x0: M68K-Syntax. (line 8) 28860* size prefixes, i386: i386-Prefixes. (line 27) 28861* size suffixes, H8/300: H8/300 Opcodes. (line 160) 28862* size, translations, Sparc: Sparc-Size-Translations. 28863 (line 6) 28864* sizes operands, i386: i386-Variations. (line 28) 28865* sizes operands, x86-64: i386-Variations. (line 28) 28866* skip directive: Skip. (line 6) 28867* skip directive, M680x0: M68K-Directives. (line 19) 28868* skip directive, SPARC: Sparc-Directives. (line 48) 28869* sleb128 directive: Sleb128. (line 6) 28870* small data, MIPS: MIPS Small Data. (line 6) 28871* SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides. 28872 (line 11) 28873* SOM symbol attributes: SOM Symbols. (line 6) 28874* source program: Input Files. (line 6) 28875* source, destination operands; i386: i386-Variations. (line 21) 28876* source, destination operands; x86-64: i386-Variations. (line 21) 28877* sp register: Xtensa Registers. (line 6) 28878* sp register, V850: V850-Regs. (line 12) 28879* space directive: Space. (line 6) 28880* space directive, TIC54X: TIC54X-Directives. (line 194) 28881* space used, maximum for assembly: statistics. (line 6) 28882* SPARC architectures: Sparc-Opts. (line 6) 28883* Sparc constants: Sparc-Constants. (line 6) 28884* SPARC data alignment: Sparc-Aligned-Data. (line 6) 28885* SPARC floating point (IEEE): Sparc-Float. (line 6) 28886* Sparc line comment character: Sparc-Chars. (line 6) 28887* Sparc line separator: Sparc-Chars. (line 14) 28888* SPARC machine directives: Sparc-Directives. (line 6) 28889* SPARC options: Sparc-Opts. (line 6) 28890* Sparc registers: Sparc-Regs. (line 6) 28891* Sparc relocations: Sparc-Relocs. (line 6) 28892* Sparc size translations: Sparc-Size-Translations. 28893 (line 6) 28894* SPARC support: Sparc-Dependent. (line 6) 28895* SPARC syntax: Sparc-Aligned-Data. (line 21) 28896* special characters, M680x0: M68K-Chars. (line 6) 28897* special purpose registers, MSP 430: MSP430-Regs. (line 11) 28898* sslist directive, TIC54X: TIC54X-Directives. (line 201) 28899* ssnolist directive, TIC54X: TIC54X-Directives. (line 201) 28900* stabd directive: Stab. (line 38) 28901* stabn directive: Stab. (line 49) 28902* stabs directive: Stab. (line 52) 28903* stabX directives: Stab. (line 6) 28904* stack pointer, ARC: ARC-Regs. (line 20) 28905* standard assembler sections: Secs Background. (line 27) 28906* standard input, as input file: Command Line. (line 10) 28907* statement separator character: Statements. (line 6) 28908* statement separator, AArch64: AArch64-Chars. (line 10) 28909* statement separator, Alpha: Alpha-Chars. (line 11) 28910* statement separator, ARC: ARC-Chars. (line 27) 28911* statement separator, ARM: ARM-Chars. (line 14) 28912* statement separator, AVR: AVR-Chars. (line 14) 28913* statement separator, BPF: BPF-Chars. (line 10) 28914* statement separator, CR16: CR16-Chars. (line 12) 28915* statement separator, Epiphany: Epiphany-Chars. (line 14) 28916* statement separator, H8/300: H8/300-Chars. (line 8) 28917* statement separator, i386: i386-Chars. (line 18) 28918* statement separator, IA-64: IA-64-Chars. (line 8) 28919* statement separator, IP2K: IP2K-Chars. (line 14) 28920* statement separator, LM32: LM32-Chars. (line 12) 28921* statement separator, M32C: M32C-Chars. (line 14) 28922* statement separator, M68HC11: M68HC11-Syntax. (line 26) 28923* statement separator, Meta: Meta-Chars. (line 8) 28924* statement separator, MicroBlaze: MicroBlaze-Chars. (line 14) 28925* statement separator, MIPS: MIPS-Chars. (line 14) 28926* statement separator, MSP 430: MSP430-Chars. (line 14) 28927* statement separator, NS32K: NS32K-Chars. (line 18) 28928* statement separator, OpenRISC: OpenRISC-Chars. (line 9) 28929* statement separator, PJ: PJ-Chars. (line 14) 28930* statement separator, PowerPC: PowerPC-Chars. (line 18) 28931* statement separator, RL78: RL78-Chars. (line 14) 28932* statement separator, RX: RX-Chars. (line 14) 28933* statement separator, S12Z: S12Z Syntax Overview. 28934 (line 41) 28935* statement separator, s390: s390 Characters. (line 13) 28936* statement separator, SCORE: SCORE-Chars. (line 14) 28937* statement separator, SH: SH-Chars. (line 8) 28938* statement separator, Sparc: Sparc-Chars. (line 14) 28939* statement separator, TIC54X: TIC54X-Chars. (line 17) 28940* statement separator, TIC6X: TIC6X Syntax. (line 13) 28941* statement separator, V850: V850-Chars. (line 13) 28942* statement separator, VAX: VAX-Chars. (line 14) 28943* statement separator, Visium: Visium Characters. (line 14) 28944* statement separator, XGATE: XGATE-Syntax. (line 25) 28945* statement separator, XStormy16: XStormy16-Chars. (line 14) 28946* statement separator, Z80: Z80-Chars. (line 13) 28947* statement separator, Z8000: Z8000-Chars. (line 13) 28948* statements, structure of: Statements. (line 6) 28949* statistics, about assembly: statistics. (line 6) 28950* Status register, ARC: ARC-Regs. (line 57) 28951* STATUS32 saved on exception, ARC: ARC-Regs. (line 82) 28952* stopping the assembly: Abort. (line 6) 28953* Stored STATUS32 register on entry to level P0 interrupts, ARC: ARC-Regs. 28954 (line 69) 28955* string constants: Strings. (line 6) 28956* string directive: String. (line 8) 28957* string directive on HPPA: HPPA Directives. (line 137) 28958* string directive, TIC54X: TIC54X-Directives. (line 206) 28959* string literals: Ascii. (line 6) 28960* string, copying to object file: String. (line 8) 28961* string16 directive: String. (line 8) 28962* string16, copying to object file: String. (line 8) 28963* string32 directive: String. (line 8) 28964* string32, copying to object file: String. (line 8) 28965* string64 directive: String. (line 8) 28966* string64, copying to object file: String. (line 8) 28967* string8 directive: String. (line 8) 28968* string8, copying to object file: String. (line 8) 28969* struct directive: Struct. (line 6) 28970* struct directive, TIC54X: TIC54X-Directives. (line 214) 28971* structure debugging, COFF: Tag. (line 6) 28972* sub-instruction ordering, D10V: D10V-Chars. (line 14) 28973* sub-instruction ordering, D30V: D30V-Chars. (line 14) 28974* sub-instructions, D10V: D10V-Subs. (line 6) 28975* sub-instructions, D30V: D30V-Subs. (line 6) 28976* subexpressions: Arguments. (line 24) 28977* subsection directive: SubSection. (line 6) 28978* subsym builtins, TIC54X: TIC54X-Macros. (line 16) 28979* subtitles for listings: Sbttl. (line 6) 28980* subtraction, permitted arguments: Infix Ops. (line 50) 28981* summary of options: Overview. (line 6) 28982* support: HPPA-Dependent. (line 6) 28983* supporting files, including: Include. (line 6) 28984* suppressing warnings: W. (line 11) 28985* sval: Z8000 Directives. (line 33) 28986* symbol attributes: Symbol Attributes. (line 6) 28987* symbol attributes, a.out: a.out Symbols. (line 6) 28988* symbol attributes, COFF: COFF Symbols. (line 6) 28989* symbol attributes, SOM: SOM Symbols. (line 6) 28990* symbol descriptor, COFF: Desc. (line 6) 28991* symbol modifiers: AVR-Modifiers. (line 12) 28992* symbol modifiers <1>: LM32-Modifiers. (line 12) 28993* symbol modifiers <2>: M32C-Modifiers. (line 11) 28994* symbol modifiers <3>: M68HC11-Modifiers. (line 12) 28995* symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6) 28996* symbol modifiers, TILEPro: TILEPro Modifiers. (line 6) 28997* symbol names: Symbol Names. (line 6) 28998* symbol names, $ in: D10V-Chars. (line 46) 28999* symbol names, $ in <1>: D30V-Chars. (line 70) 29000* symbol names, $ in <2>: Meta-Chars. (line 10) 29001* symbol names, $ in <3>: SH-Chars. (line 15) 29002* symbol names, local: Symbol Names. (line 30) 29003* symbol names, temporary: Symbol Names. (line 43) 29004* symbol prefix character, ARC: ARC-Chars. (line 20) 29005* symbol storage class (COFF): Scl. (line 6) 29006* symbol type: Symbol Type. (line 6) 29007* symbol type, COFF: Type. (line 11) 29008* symbol type, ELF: Type. (line 22) 29009* symbol value: Symbol Value. (line 6) 29010* symbol value, setting: Set. (line 6) 29011* symbol values, assigning: Setting Symbols. (line 6) 29012* symbol versioning: Symver. (line 6) 29013* symbol, common: Comm. (line 6) 29014* symbol, making visible to linker: Global. (line 6) 29015* symbolic debuggers, information for: Stab. (line 6) 29016* symbols: Symbols. (line 6) 29017* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6) 29018* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42) 29019* symbols, assigning values to: Equ. (line 6) 29020* Symbols, built-in, CRIS: CRIS-Symbols. (line 6) 29021* Symbols, CRIS, built-in: CRIS-Symbols. (line 6) 29022* symbols, local common: Lcomm. (line 6) 29023* symver directive: Symver. (line 6) 29024* syntax compatibility, i386: i386-Variations. (line 6) 29025* syntax compatibility, x86-64: i386-Variations. (line 6) 29026* syntax, AVR: AVR-Modifiers. (line 6) 29027* syntax, Blackfin: Blackfin Syntax. (line 6) 29028* syntax, D10V: D10V-Syntax. (line 6) 29029* syntax, D30V: D30V-Syntax. (line 6) 29030* syntax, LM32: LM32-Modifiers. (line 6) 29031* syntax, M680x0: M68K-Syntax. (line 8) 29032* syntax, M68HC11: M68HC11-Syntax. (line 6) 29033* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6) 29034* syntax, machine-independent: Syntax. (line 6) 29035* syntax, OPENRISC: OpenRISC-Dependent. (line 12) 29036* syntax, RL78: RL78-Modifiers. (line 6) 29037* syntax, RX: RX-Modifiers. (line 6) 29038* syntax, S12Z: S12Z Syntax. (line 11) 29039* syntax, SPARC: Sparc-Aligned-Data. (line 20) 29040* syntax, TILE-Gx: TILE-Gx Syntax. (line 6) 29041* syntax, TILEPro: TILEPro Syntax. (line 6) 29042* syntax, XGATE: XGATE-Syntax. (line 6) 29043* syntax, Xtensa assembler: Xtensa Syntax. (line 6) 29044* tab (\t): Strings. (line 27) 29045* tab directive, TIC54X: TIC54X-Directives. (line 245) 29046* tag directive: Tag. (line 6) 29047* tag directive, TIC54X: TIC54X-Directives. (line 214) 29048* tag directive, TIC54X <1>: TIC54X-Directives. (line 248) 29049* TBM, i386: i386-TBM. (line 6) 29050* TBM, x86-64: i386-TBM. (line 6) 29051* tdaoff pseudo-op, V850: V850 Opcodes. (line 81) 29052* temporary symbol names: Symbol Names. (line 43) 29053* text and data sections, joining: R. (line 6) 29054* text directive: Text. (line 6) 29055* text section: Ld Sections. (line 9) 29056* tfloat directive, i386: i386-Float. (line 14) 29057* tfloat directive, x86-64: i386-Float. (line 14) 29058* Thumb support: ARM-Dependent. (line 6) 29059* TIC54X builtin math functions: TIC54X-Builtins. (line 6) 29060* TIC54X line comment character: TIC54X-Chars. (line 6) 29061* TIC54X line separator: TIC54X-Chars. (line 17) 29062* TIC54X machine directives: TIC54X-Directives. (line 6) 29063* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6) 29064* TIC54X options: TIC54X-Opts. (line 6) 29065* TIC54X subsym builtins: TIC54X-Macros. (line 16) 29066* TIC54X support: TIC54X-Dependent. (line 6) 29067* TIC54X-specific macros: TIC54X-Macros. (line 6) 29068* TIC6X big-endian output: TIC6X Options. (line 46) 29069* TIC6X line comment character: TIC6X Syntax. (line 6) 29070* TIC6X line separator: TIC6X Syntax. (line 13) 29071* TIC6X little-endian output: TIC6X Options. (line 46) 29072* TIC6X machine directives: TIC6X Directives. (line 6) 29073* TIC6X options: TIC6X Options. (line 6) 29074* TIC6X support: TIC6X-Dependent. (line 6) 29075* TILE-Gx machine directives: TILE-Gx Directives. (line 6) 29076* TILE-Gx modifiers: TILE-Gx Modifiers. (line 6) 29077* TILE-Gx opcode names: TILE-Gx Opcodes. (line 6) 29078* TILE-Gx register names: TILE-Gx Registers. (line 6) 29079* TILE-Gx support: TILE-Gx-Dependent. (line 6) 29080* TILE-Gx syntax: TILE-Gx Syntax. (line 6) 29081* TILEPro machine directives: TILEPro Directives. (line 6) 29082* TILEPro modifiers: TILEPro Modifiers. (line 6) 29083* TILEPro opcode names: TILEPro Opcodes. (line 6) 29084* TILEPro register names: TILEPro Registers. (line 6) 29085* TILEPro support: TILEPro-Dependent. (line 6) 29086* TILEPro syntax: TILEPro Syntax. (line 6) 29087* time, total for assembly: statistics. (line 6) 29088* title directive: Title. (line 6) 29089* tls_common directive: Tls_common. (line 6) 29090* tls_gd directive, Nios II: Nios II Relocations. 29091 (line 38) 29092* tls_ie directive, Nios II: Nios II Relocations. 29093 (line 38) 29094* tls_ldm directive, Nios II: Nios II Relocations. 29095 (line 38) 29096* tls_ldo directive, Nios II: Nios II Relocations. 29097 (line 38) 29098* tls_le directive, Nios II: Nios II Relocations. 29099 (line 38) 29100* TMS320C6X support: TIC6X-Dependent. (line 6) 29101* tp register, V850: V850-Regs. (line 16) 29102* transform directive: Transform Directive. 29103 (line 6) 29104* trusted compiler: f. (line 6) 29105* turning preprocessing on and off: Preprocessing. (line 28) 29106* two-byte integer: 2byte. (line 6) 29107* type directive (COFF version): Type. (line 11) 29108* type directive (ELF version): Type. (line 22) 29109* type of a symbol: Symbol Type. (line 6) 29110* ualong directive, SH: SH Directives. (line 6) 29111* uaquad directive, SH: SH Directives. (line 6) 29112* uaword directive, SH: SH Directives. (line 6) 29113* ubyte directive, TIC54X: TIC54X-Directives. (line 34) 29114* uchar directive, TIC54X: TIC54X-Directives. (line 34) 29115* uhalf directive, TIC54X: TIC54X-Directives. (line 109) 29116* uint directive, TIC54X: TIC54X-Directives. (line 109) 29117* uleb128 directive: Uleb128. (line 6) 29118* ulong directive, TIC54X: TIC54X-Directives. (line 133) 29119* undefined section: Ld Sections. (line 36) 29120* union directive, TIC54X: TIC54X-Directives. (line 248) 29121* unsegm: Z8000 Directives. (line 14) 29122* usect directive, TIC54X: TIC54X-Directives. (line 260) 29123* ushort directive, TIC54X: TIC54X-Directives. (line 109) 29124* uword directive, TIC54X: TIC54X-Directives. (line 109) 29125* V850 command-line options: V850 Options. (line 9) 29126* V850 floating point (IEEE): V850 Floating Point. 29127 (line 6) 29128* V850 line comment character: V850-Chars. (line 6) 29129* V850 line separator: V850-Chars. (line 13) 29130* V850 machine directives: V850 Directives. (line 6) 29131* V850 opcodes: V850 Opcodes. (line 6) 29132* V850 options (none): V850 Options. (line 6) 29133* V850 register names: V850-Regs. (line 6) 29134* V850 support: V850-Dependent. (line 6) 29135* val directive: Val. (line 6) 29136* value attribute, COFF: Val. (line 6) 29137* value directive: i386-Directives. (line 26) 29138* value of a symbol: Symbol Value. (line 6) 29139* var directive, TIC54X: TIC54X-Directives. (line 270) 29140* VAX bitfields not supported: VAX-no. (line 6) 29141* VAX branch improvement: VAX-branch. (line 6) 29142* VAX command-line options ignored: VAX-Opts. (line 6) 29143* VAX displacement sizing character: VAX-operands. (line 12) 29144* VAX floating point: VAX-float. (line 6) 29145* VAX immediate character: VAX-operands. (line 6) 29146* VAX indirect character: VAX-operands. (line 9) 29147* VAX line comment character: VAX-Chars. (line 6) 29148* VAX line separator: VAX-Chars. (line 14) 29149* VAX machine directives: VAX-directives. (line 6) 29150* VAX opcode mnemonics: VAX-opcodes. (line 6) 29151* VAX operand notation: VAX-operands. (line 6) 29152* VAX register names: VAX-operands. (line 17) 29153* VAX support: Vax-Dependent. (line 6) 29154* Vax-11 C compatibility: VAX-Opts. (line 42) 29155* VAX/VMS options: VAX-Opts. (line 42) 29156* version directive: Version. (line 6) 29157* version directive, TIC54X: TIC54X-Directives. (line 274) 29158* version of assembler: v. (line 6) 29159* versions of symbols: Symver. (line 6) 29160* Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides. 29161 (line 52) 29162* visibility: Hidden. (line 6) 29163* visibility <1>: Internal. (line 6) 29164* visibility <2>: Protected. (line 6) 29165* Visium line comment character: Visium Characters. (line 6) 29166* Visium line separator: Visium Characters. (line 14) 29167* Visium options: Visium Options. (line 6) 29168* Visium registers: Visium Registers. (line 6) 29169* Visium support: Visium-Dependent. (line 6) 29170* VMS (VAX) options: VAX-Opts. (line 42) 29171* vtable_entry directive: VTableEntry. (line 6) 29172* vtable_inherit directive: VTableInherit. (line 6) 29173* warning directive: Warning. (line 6) 29174* warning for altered difference tables: K. (line 6) 29175* warning messages: Errors. (line 6) 29176* warnings, causing error: W. (line 16) 29177* warnings, M32R: M32R-Warnings. (line 6) 29178* warnings, suppressing: W. (line 11) 29179* warnings, switching on: W. (line 19) 29180* weak directive: Weak. (line 6) 29181* weakref directive: Weakref. (line 6) 29182* WebAssembly floating point (IEEE): WebAssembly-Floating-Point. 29183 (line 6) 29184* WebAssembly line comment character: WebAssembly-Chars. (line 6) 29185* WebAssembly module layout: WebAssembly-module-layout. 29186 (line 6) 29187* WebAssembly notes: WebAssembly-Notes. (line 6) 29188* WebAssembly opcodes: WebAssembly-Opcodes. 29189 (line 6) 29190* WebAssembly relocations: WebAssembly-Relocs. (line 6) 29191* WebAssembly signatures: WebAssembly-Signatures. 29192 (line 6) 29193* WebAssembly support: WebAssembly-Dependent. 29194 (line 6) 29195* WebAssembly Syntax: WebAssembly-Syntax. (line 6) 29196* whitespace: Whitespace. (line 6) 29197* whitespace, removed by preprocessor: Preprocessing. (line 7) 29198* wide floating point directives, VAX: VAX-directives. (line 9) 29199* width directive, TIC54X: TIC54X-Directives. (line 125) 29200* Width of continuation lines of disassembly output: listing. 29201 (line 21) 29202* Width of first line disassembly output: listing. (line 16) 29203* Width of source line output: listing. (line 28) 29204* wmsg directive, TIC54X: TIC54X-Directives. (line 75) 29205* word aligned program counter, ARC: ARC-Regs. (line 44) 29206* word directive: Word. (line 6) 29207* word directive, BPF: BPF Directives. (line 12) 29208* word directive, H8/300: H8/300 Directives. (line 6) 29209* word directive, i386: i386-Float. (line 21) 29210* word directive, Nios II: Nios II Directives. (line 13) 29211* word directive, OpenRISC: OpenRISC-Directives. 29212 (line 12) 29213* word directive, PRU: PRU Directives. (line 10) 29214* word directive, SPARC: Sparc-Directives. (line 51) 29215* word directive, TIC54X: TIC54X-Directives. (line 109) 29216* word directive, x86-64: i386-Float. (line 21) 29217* writing patterns in memory: Fill. (line 6) 29218* wval: Z8000 Directives. (line 24) 29219* x86 machine directives: i386-Directives. (line 6) 29220* x86-64 arch directive: i386-Arch. (line 6) 29221* x86-64 att_syntax pseudo op: i386-Variations. (line 6) 29222* x86-64 conversion instructions: i386-Mnemonics. (line 66) 29223* x86-64 extension instructions: i386-Mnemonics. (line 85) 29224* x86-64 floating point: i386-Float. (line 6) 29225* x86-64 immediate operands: i386-Variations. (line 15) 29226* x86-64 instruction naming: i386-Mnemonics. (line 9) 29227* x86-64 intel_syntax pseudo op: i386-Variations. (line 6) 29228* x86-64 jump optimization: i386-Jumps. (line 6) 29229* x86-64 jump, call, return: i386-Variations. (line 45) 29230* x86-64 jump/call operands: i386-Variations. (line 15) 29231* x86-64 memory references: i386-Memory. (line 6) 29232* x86-64 options: i386-Options. (line 6) 29233* x86-64 register operands: i386-Variations. (line 15) 29234* x86-64 registers: i386-Regs. (line 6) 29235* x86-64 sections: i386-Variations. (line 51) 29236* x86-64 size suffixes: i386-Variations. (line 28) 29237* x86-64 source, destination operands: i386-Variations. (line 21) 29238* x86-64 support: i386-Dependent. (line 6) 29239* x86-64 syntax compatibility: i386-Variations. (line 6) 29240* xdef directive, Z80: Z80 Directives. (line 62) 29241* xfloat directive, TIC54X: TIC54X-Directives. (line 62) 29242* XGATE addressing modes: XGATE-Syntax. (line 28) 29243* XGATE assembler directives: XGATE-Directives. (line 6) 29244* XGATE floating point: XGATE-Float. (line 6) 29245* XGATE line comment character: XGATE-Syntax. (line 16) 29246* XGATE line separator: XGATE-Syntax. (line 25) 29247* XGATE opcodes: XGATE-opcodes. (line 6) 29248* XGATE options: XGATE-Opts. (line 6) 29249* XGATE support: XGATE-Dependent. (line 6) 29250* XGATE syntax: XGATE-Syntax. (line 6) 29251* xlong directive, TIC54X: TIC54X-Directives. (line 133) 29252* xref directive, Z80: Z80 Directives. (line 66) 29253* XStormy16 comment character: XStormy16-Chars. (line 11) 29254* XStormy16 line comment character: XStormy16-Chars. (line 6) 29255* XStormy16 line separator: XStormy16-Chars. (line 14) 29256* XStormy16 machine directives: XStormy16 Directives. 29257 (line 6) 29258* XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6) 29259* XStormy16 support: XSTORMY16-Dependent. 29260 (line 6) 29261* Xtensa architecture: Xtensa-Dependent. (line 6) 29262* Xtensa assembler syntax: Xtensa Syntax. (line 6) 29263* Xtensa directives: Xtensa Directives. (line 6) 29264* Xtensa opcode names: Xtensa Opcodes. (line 6) 29265* Xtensa register names: Xtensa Registers. (line 6) 29266* xword directive, SPARC: Sparc-Directives. (line 55) 29267* Z80 $: Z80-Chars. (line 15) 29268* Z80 ': Z80-Chars. (line 20) 29269* Z80 floating point: Z80 Floating Point. (line 6) 29270* Z80 labels: Z80-Labels. (line 6) 29271* Z80 line comment character: Z80-Chars. (line 6) 29272* Z80 line separator: Z80-Chars. (line 13) 29273* Z80 options: Z80 Options. (line 6) 29274* Z80 registers: Z80-Regs. (line 6) 29275* Z80 support: Z80-Dependent. (line 6) 29276* Z80 Syntax: Z80 Options. (line 67) 29277* Z80, case sensitivity: Z80-Case. (line 6) 29278* Z80, \: Z80-Chars. (line 18) 29279* Z80-only directives: Z80 Directives. (line 6) 29280* Z800 addressing modes: Z8000-Addressing. (line 6) 29281* Z8000 directives: Z8000 Directives. (line 6) 29282* Z8000 line comment character: Z8000-Chars. (line 6) 29283* Z8000 line separator: Z8000-Chars. (line 13) 29284* Z8000 opcode summary: Z8000 Opcodes. (line 6) 29285* Z8000 options: Z8000 Options. (line 6) 29286* Z8000 registers: Z8000-Regs. (line 6) 29287* Z8000 support: Z8000-Dependent. (line 6) 29288* zdaoff pseudo-op, V850: V850 Opcodes. (line 98) 29289* zero directive: Zero. (line 6) 29290* zero register, V850: V850-Regs. (line 7) 29291* zero-terminated strings: Asciz. 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