1 #as: -mlfence-after-load=yes 2 #objdump: -dw 3 #warning_output: lfence-load.e 4 #name: x86-64 -mlfence-after-load=yes 5 6 .*: +file format .* 7 8 9 Disassembly of section .text: 10 11 0+ <_start>: 12 +[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%rbp\) 13 +[a-f0-9]+: 0f ae e8 lfence 14 +[a-f0-9]+: 0f 01 55 00 lgdt 0x0\(%rbp\) 15 +[a-f0-9]+: 0f ae e8 lfence 16 +[a-f0-9]+: 0f c7 75 00 vmptrld 0x0\(%rbp\) 17 +[a-f0-9]+: 0f ae e8 lfence 18 +[a-f0-9]+: 66 0f c7 75 00 vmclear 0x0\(%rbp\) 19 +[a-f0-9]+: 66 0f 38 82 55 00 invpcid 0x0\(%rbp\),%rdx 20 +[a-f0-9]+: 0f ae e8 lfence 21 +[a-f0-9]+: 67 0f 01 38 invlpg \(%eax\) 22 +[a-f0-9]+: 0f ae 7d 00 clflush 0x0\(%rbp\) 23 +[a-f0-9]+: 66 0f ae 7d 00 clflushopt 0x0\(%rbp\) 24 +[a-f0-9]+: 66 0f ae 75 00 clwb 0x0\(%rbp\) 25 +[a-f0-9]+: 0f 1c 45 00 cldemote 0x0\(%rbp\) 26 +[a-f0-9]+: f3 0f 1b 4d 00 bndmk 0x0\(%rbp\),%bnd1 27 +[a-f0-9]+: f3 0f 1a 4d 00 bndcl 0x0\(%rbp\),%bnd1 28 +[a-f0-9]+: f2 0f 1a 4d 00 bndcu 0x0\(%rbp\),%bnd1 29 +[a-f0-9]+: f2 0f 1b 4d 00 bndcn 0x0\(%rbp\),%bnd1 30 +[a-f0-9]+: 0f 1b 4d 00 bndstx %bnd1,0x0\(%rbp\) 31 +[a-f0-9]+: 0f 1a 4d 00 bndldx 0x0\(%rbp\),%bnd1 32 +[a-f0-9]+: 0f 18 4d 00 prefetcht0 0x0\(%rbp\) 33 +[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\) 34 +[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\) 35 +[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\) 36 +[a-f0-9]+: 0f a1 pop %fs 37 +[a-f0-9]+: 0f ae e8 lfence 38 +[a-f0-9]+: 9d popf * 39 +[a-f0-9]+: 0f ae e8 lfence 40 +[a-f0-9]+: d7 xlat %ds:\(%rbx\) 41 +[a-f0-9]+: 0f ae e8 lfence 42 +[a-f0-9]+: d9 55 00 fsts 0x0\(%rbp\) 43 +[a-f0-9]+: d9 45 00 flds 0x0\(%rbp\) 44 +[a-f0-9]+: 0f ae e8 lfence 45 +[a-f0-9]+: db 55 00 fistl 0x0\(%rbp\) 46 +[a-f0-9]+: df 55 00 fists 0x0\(%rbp\) 47 +[a-f0-9]+: db 45 00 fildl 0x0\(%rbp\) 48 +[a-f0-9]+: 0f ae e8 lfence 49 +[a-f0-9]+: df 45 00 filds 0x0\(%rbp\) 50 +[a-f0-9]+: 0f ae e8 lfence 51 +[a-f0-9]+: 9b dd 75 00 fsave 0x0\(%rbp\) 52 +[a-f0-9]+: dd 65 00 frstor 0x0\(%rbp\) 53 +[a-f0-9]+: 0f ae e8 lfence 54 +[a-f0-9]+: df 45 00 filds 0x0\(%rbp\) 55 +[a-f0-9]+: 0f ae e8 lfence 56 +[a-f0-9]+: df 4d 00 fisttps 0x0\(%rbp\) 57 +[a-f0-9]+: d9 65 00 fldenv 0x0\(%rbp\) 58 +[a-f0-9]+: 0f ae e8 lfence 59 +[a-f0-9]+: 9b d9 75 00 fstenv 0x0\(%rbp\) 60 +[a-f0-9]+: d8 45 00 fadds 0x0\(%rbp\) 61 +[a-f0-9]+: 0f ae e8 lfence 62 +[a-f0-9]+: d8 04 24 fadds \(%rsp\) 63 +[a-f0-9]+: 0f ae e8 lfence 64 +[a-f0-9]+: d8 c3 fadd %st\(3\),%st 65 +[a-f0-9]+: d8 01 fadds \(%rcx\) 66 +[a-f0-9]+: 0f ae e8 lfence 67 +[a-f0-9]+: df 01 filds \(%rcx\) 68 +[a-f0-9]+: 0f ae e8 lfence 69 +[a-f0-9]+: df 11 fists \(%rcx\) 70 +[a-f0-9]+: 0f ae 29 xrstor \(%rcx\) 71 +[a-f0-9]+: 0f ae e8 lfence 72 +[a-f0-9]+: 0f 18 01 prefetchnta \(%rcx\) 73 +[a-f0-9]+: 0f c7 09 cmpxchg8b \(%rcx\) 74 +[a-f0-9]+: 0f ae e8 lfence 75 +[a-f0-9]+: 48 0f c7 09 cmpxchg16b \(%rcx\) 76 +[a-f0-9]+: 0f ae e8 lfence 77 +[a-f0-9]+: ff c1 inc %ecx 78 +[a-f0-9]+: 0f 01 10 lgdt \(%rax\) 79 +[a-f0-9]+: 0f ae e8 lfence 80 +[a-f0-9]+: 0f 0f 66 02 b0 pfcmpeq 0x2\(%rsi\),%mm4 81 +[a-f0-9]+: 0f ae e8 lfence 82 +[a-f0-9]+: 8f 00 pop \(%rax\) 83 +[a-f0-9]+: 0f ae e8 lfence 84 +[a-f0-9]+: 58 pop %rax 85 +[a-f0-9]+: 0f ae e8 lfence 86 +[a-f0-9]+: 66 d1 11 rclw \(%rcx\) 87 +[a-f0-9]+: 0f ae e8 lfence 88 +[a-f0-9]+: f7 01 01 00 00 00 testl \$0x1,\(%rcx\) 89 +[a-f0-9]+: 0f ae e8 lfence 90 +[a-f0-9]+: ff 01 incl \(%rcx\) 91 +[a-f0-9]+: 0f ae e8 lfence 92 +[a-f0-9]+: f7 11 notl \(%rcx\) 93 +[a-f0-9]+: 0f ae e8 lfence 94 +[a-f0-9]+: f7 31 divl \(%rcx\) 95 +[a-f0-9]+: 0f ae e8 lfence 96 +[a-f0-9]+: f7 21 mull \(%rcx\) 97 +[a-f0-9]+: 0f ae e8 lfence 98 +[a-f0-9]+: f7 39 idivl \(%rcx\) 99 +[a-f0-9]+: 0f ae e8 lfence 100 +[a-f0-9]+: f7 29 imull \(%rcx\) 101 +[a-f0-9]+: 0f ae e8 lfence 102 +[a-f0-9]+: 48 8d 04 40 lea \(%rax,%rax,2\),%rax 103 +[a-f0-9]+: c9 leave * 104 +[a-f0-9]+: 6e outsb %ds:\(%rsi\),\(%dx\) 105 +[a-f0-9]+: 0f ae e8 lfence 106 +[a-f0-9]+: ac lods %ds:\(%rsi\),%al 107 +[a-f0-9]+: 0f ae e8 lfence 108 +[a-f0-9]+: f3 a5 rep movsl %ds:\(%rsi\),%es:\(%rdi\) 109 +[a-f0-9]+: 0f ae e8 lfence 110 +[a-f0-9]+: f3 af repz scas %es:\(%rdi\),%eax 111 +[a-f0-9]+: 0f ae e8 lfence 112 +[a-f0-9]+: f3 a7 repz cmpsl %es:\(%rdi\),%ds:\(%rsi\) 113 +[a-f0-9]+: 0f ae e8 lfence 114 +[a-f0-9]+: f3 ad rep lods %ds:\(%rsi\),%eax 115 +[a-f0-9]+: 0f ae e8 lfence 116 +[a-f0-9]+: 41 83 03 01 addl \$0x1,\(%r11\) 117 +[a-f0-9]+: 0f ae e8 lfence 118 +[a-f0-9]+: 41 0f ba 23 01 btl \$0x1,\(%r11\) 119 +[a-f0-9]+: 0f ae e8 lfence 120 +[a-f0-9]+: 48 0f c1 03 xadd %rax,\(%rbx\) 121 +[a-f0-9]+: 0f ae e8 lfence 122 +[a-f0-9]+: 48 0f c1 c3 xadd %rax,%rbx 123 +[a-f0-9]+: 48 87 03 xchg %rax,\(%rbx\) 124 +[a-f0-9]+: 0f ae e8 lfence 125 +[a-f0-9]+: 48 93 xchg %rax,%rbx 126 +[a-f0-9]+: 48 39 45 40 cmp %rax,0x40\(%rbp\) 127 +[a-f0-9]+: 0f ae e8 lfence 128 +[a-f0-9]+: 48 3b 45 40 cmp 0x40\(%rbp\),%rax 129 +[a-f0-9]+: 0f ae e8 lfence 130 +[a-f0-9]+: 48 01 45 40 add %rax,0x40\(%rbp\) 131 +[a-f0-9]+: 0f ae e8 lfence 132 +[a-f0-9]+: 48 03 00 add \(%rax\),%rax 133 +[a-f0-9]+: 0f ae e8 lfence 134 +[a-f0-9]+: 48 85 45 40 test %rax,0x40\(%rbp\) 135 +[a-f0-9]+: 0f ae e8 lfence 136 +[a-f0-9]+: 48 85 45 40 test %rax,0x40\(%rbp\) 137 +[a-f0-9]+: 0f ae e8 lfence 138 #pass 139