1 #objdump: -dw -Mintel 2 #name: x86-64 prefetch (Intel disassembly) 3 #source: prefetch.s 4 5 .*: +file format .* 6 7 Disassembly of section .text: 8 9 0+ <amd_prefetch>: 10 \s*[a-f0-9]+: 0f 0d 00 prefetch BYTE PTR \[rax\] 11 \s*[a-f0-9]+: 0f 0d 08 prefetchw BYTE PTR \[rax\] 12 \s*[a-f0-9]+: 0f 0d 10 prefetchwt1 BYTE PTR \[rax\] 13 \s*[a-f0-9]+: 0f 0d 18 prefetch BYTE PTR \[rax\] 14 \s*[a-f0-9]+: 0f 0d 20 prefetch BYTE PTR \[rax\] 15 \s*[a-f0-9]+: 0f 0d 28 prefetch BYTE PTR \[rax\] 16 \s*[a-f0-9]+: 0f 0d 30 prefetch BYTE PTR \[rax\] 17 \s*[a-f0-9]+: 0f 0d 38 prefetch BYTE PTR \[rax\] 18 19 0+[0-9a-f]+ <intel_prefetch>: 20 \s*[a-f0-9]+: 0f 18 00 prefetchnta BYTE PTR \[rax\] 21 \s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[rax\] 22 \s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[rax\] 23 \s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[rax\] 24 \s*[a-f0-9]+: 0f 18 20 nop DWORD PTR \[rax\] 25 \s*[a-f0-9]+: 0f 18 28 nop DWORD PTR \[rax\] 26 \s*[a-f0-9]+: 0f 18 30 nop DWORD PTR \[rax\] 27 \s*[a-f0-9]+: 0f 18 38 nop DWORD PTR \[rax\] 28