1// ICEDEV=hx8k-ct256 bash ../icecube.sh sb_ram40.v
2// ../../icebox/icebox_vlog.py -P sb_ram40.psb sb_ram40.txt
3// ../../icebox/icebox_explain.py -t '7 21' sb_ram40.txt
4
5module top (
6	input  [10:0] WADDR,
7	input  [10:0] RADDR,
8	input  [15:0] MASK,
9	input  [15:0] WDATA,
10	output [15:0] RDATA_0,
11	output [ 7:0] RDATA_1,
12	output [ 1:0] RDATA_3,
13	input         WE, WCLKE, WCLK,
14	input         RE, RCLKE, RCLK,
15	output        X
16);
17	// Write Mode 0:  8 Bit ADDR, 16 Bit DATA, MASK
18	// Write Mode 1:  9 Bit ADDR,  8 Bit DATA, NO MASK
19	// Write Mode 2: 10 Bit ADDR,  4 Bit DATA, NO MASK
20	// Write Mode 3: 11 Bit ADDR,  2 Bit DATA, NO MASK
21
22	SB_RAM40_4K #(
23		.READ_MODE(0),
24		.WRITE_MODE(0)
25	) ram40_00 (
26		.WADDR(WADDR[7:0]),
27		.RADDR(RADDR[7:0]),
28		.MASK(MASK),
29		.WDATA(WDATA),
30		.RDATA(RDATA_0),
31		.WE(WE),
32		.WCLKE(WCLKE),
33		.WCLK(WCLK),
34		.RE(RE),
35		.RCLKE(RCLKE),
36		.RCLK(RCLK)
37	);
38
39	SB_RAM40_4K #(
40		.READ_MODE(1),
41		.WRITE_MODE(2)
42	) ram40_12 (
43		.WADDR(WADDR[9:0]),
44		.RADDR(RADDR[8:0]),
45		.WDATA(WDATA[3:0]),
46		.RDATA(RDATA_1),
47		.WE(WE),
48		.WCLKE(WCLKE),
49		.WCLK(WCLK),
50		.RE(RE),
51		.RCLKE(RCLKE),
52		.RCLK(RCLK)
53	);
54
55	SB_RAM40_4K #(
56		.READ_MODE(3),
57		.WRITE_MODE(3)
58	) ram40_33 (
59		.WADDR(WADDR),
60		.RADDR(RADDR),
61		.WDATA(WDATA[1:0]),
62		.RDATA(RDATA_3),
63		.WE(WE),
64		.WCLKE(WCLKE),
65		.WCLK(WCLK),
66		.RE(RE),
67		.RCLKE(RCLKE),
68		.RCLK(RCLK)
69	);
70
71	SB_LUT4 #(
72		.LUT_INIT(16'b 1000_0000_0000_0000)
73	) lut (
74		.O(X),
75		.I0(RDATA_0[0]),
76		.I1(RDATA_0[6]),
77		.I2(RDATA_0[8]),
78		.I3(RDATA_0[14])
79	);
80endmodule
81