1 /*========================== begin_copyright_notice ============================ 2 3 Copyright (C) 2017-2021 Intel Corporation 4 5 SPDX-License-Identifier: MIT 6 7 ============================= end_copyright_notice ===========================*/ 8 9 //==== G4Instruction.h - info about G4 instructions ====// 10 // 11 // This file contains descriptions of all G4 instructions (real or pseudo). 12 // It is the single place to enumerate description for each instruction. 13 // Adding, subtracting, commenting instructions shall happen in this file. 14 15 // HANDLE_INST: describe each instruction 16 // HANDLE_NAME_INST: a variant of HANDLE_INST, using given instruction name 17 // instead of opcode as name. 18 19 // 20 // 1. none of those two macros are defined, this file should be empty 21 // 2. If both macros are the same, users of this file need to define 22 // HANDLE_INST only, no need to define both. 23 // 24 #ifndef HANDLE_INST 25 #define HANDLE_INST(op, nsrc, ndst, type, plat, attr) 26 #endif 27 #ifndef HANDLE_NAME_INST 28 #define HANDLE_NAME_INST(op, name, nsrc, ndst, type, plat, attr) \ 29 HANDLE_INST(op, nsrc, ndst, type, plat, attr) 30 #endif 31 32 // 33 // First one is illegal instruction 34 // 35 HANDLE_INST(illegal, 0, 0, InstTypeMisc, GENX_BDW, ATTR_NONE) 36 37 // 38 // InstTypeMov 39 // 40 HANDLE_INST(mov, 1, 1, InstTypeMov, GENX_BDW, ATTR_COMMUTATIVE) 41 HANDLE_INST(sel, 2, 1, InstTypeMov, GENX_BDW, ATTR_NONE) 42 HANDLE_INST(movi, 1, 1, InstTypeMov, GENX_BDW, ATTR_NONE) 43 HANDLE_INST(smov, 2, 1, InstTypeMov, GENX_BDW, ATTR_NONE) 44 HANDLE_INST(csel, 3, 1, InstTypeMov, GENX_SKL, ATTR_FLOAT_SRC_ONLY) 45 // 46 // fcvt: special pseudo instruction for converting b/w a standard float type 47 // and bf8/tf32, which are denoted by Type_UB/Type_UD, respectively. 48 // 49 HANDLE_INST(fcvt, 1, 1, InstTypeMov, GENX_PVCXT, ATTR_PSEUDO) 50 51 // 52 // InstTypeLogic 53 // 54 HANDLE_INST(not, 1, 1, InstTypeLogic, GENX_BDW, ATTR_NONE) 55 HANDLE_INST(and, 2, 1, InstTypeLogic, GENX_BDW, ATTR_COMMUTATIVE) 56 HANDLE_INST(or, 2, 1, InstTypeLogic, GENX_BDW, ATTR_COMMUTATIVE) 57 HANDLE_INST(xor, 2, 1, InstTypeLogic, GENX_BDW, ATTR_COMMUTATIVE) 58 HANDLE_INST(bfrev, 1, 1, InstTypeLogic, GENX_BDW, ATTR_NONE) 59 HANDLE_INST(bfe, 3, 1, InstTypeLogic, GENX_BDW, ATTR_NONE) 60 HANDLE_INST(bfi1, 2, 1, InstTypeLogic, GENX_BDW, ATTR_NONE) 61 HANDLE_INST(bfi2, 3, 1, InstTypeLogic, GENX_BDW, ATTR_NONE) 62 HANDLE_INST(fbh, 1, 1, InstTypeLogic, GENX_BDW, ATTR_NONE) 63 HANDLE_INST(fbl, 1, 1, InstTypeLogic, GENX_BDW, ATTR_NONE) 64 HANDLE_INST(cbit, 1, 1, InstTypeLogic, GENX_BDW, ATTR_NONE) 65 HANDLE_INST(bfn, 3, 1, InstTypeLogic, XeHP_SDV, ATTR_NONE) 66 67 // 68 // InstTypeArith 69 // 70 HANDLE_INST(shr, 2, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 71 HANDLE_INST(shl, 2, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 72 HANDLE_INST(asr, 2, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 73 74 HANDLE_INST(ror, 2, 1, InstTypeArith, GENX_ICLLP, ATTR_NONE) 75 HANDLE_INST(rol, 2, 1, InstTypeArith, GENX_ICLLP, ATTR_NONE) 76 77 HANDLE_INST(math, 2, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 78 HANDLE_INST(add, 2, 1, InstTypeArith, GENX_BDW, ATTR_COMMUTATIVE) 79 HANDLE_INST(mul, 2, 1, InstTypeArith, GENX_BDW, ATTR_COMMUTATIVE) 80 HANDLE_INST(avg, 2, 1, InstTypeArith, GENX_BDW, ATTR_COMMUTATIVE) 81 HANDLE_INST(frc, 1, 1, InstTypeArith, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 82 HANDLE_INST(rndu, 1, 1, InstTypeArith, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 83 HANDLE_INST(rndd, 1, 1, InstTypeArith, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 84 HANDLE_INST(rnde, 1, 1, InstTypeArith, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 85 HANDLE_INST(rndz, 1, 1, InstTypeArith, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 86 HANDLE_INST(mac, 2, 1, InstTypeArith, GENX_BDW, ATTR_COMMUTATIVE) 87 HANDLE_INST(mach, 2, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 88 HANDLE_INST(lzd, 1, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 89 HANDLE_INST(addc, 2, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 90 HANDLE_INST(subb, 2, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 91 92 HANDLE_INST(dp4a, 3, 1, InstTypeArith, GENX_TGLLP, ATTR_NONE) 93 HANDLE_INST(dpas, 3, 1, InstTypeArith, XeHP_SDV, ATTR_NONE) 94 HANDLE_INST(dpasw, 3, 1, InstTypeArith, XeHP_SDV, ATTR_NONE) 95 HANDLE_INST(add3, 3, 1, InstTypeArith, XeHP_SDV, ATTR_COMMUTATIVE) 96 97 98 HANDLE_INST(madm, 3, 1, InstTypeArith, GENX_BDW, ATTR_NONE) 99 // 100 // Following are pseudo instructions 101 // 102 HANDLE_INST(mulh, 2, 1, InstTypeArith, GENX_BDW, ATTR_COMMUTATIVE) 103 HANDLE_INST(srnd, 2, 1, InstTypeArith, GENX_PVCXT, ATTR_PSEUDO) 104 HANDLE_INST(madw, 3, 1, InstTypeArith, GENX_BDW, ATTR_WIDE_DST) 105 106 // 107 // InstTypeCompare 108 // 109 HANDLE_INST(cmp, 2, 1, InstTypeCompare, GENX_BDW, ATTR_NONE) 110 HANDLE_INST(cmpn, 2, 1, InstTypeCompare, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 111 112 // 113 // InstTypeFlow 114 // 115 HANDLE_INST(jmpi, 1, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 116 HANDLE_INST(brd, 1, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 117 HANDLE_INST(if, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 118 HANDLE_INST(brc, 2, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 119 HANDLE_INST(else, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 120 HANDLE_INST(endif, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 121 HANDLE_INST(while, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 122 HANDLE_INST(break, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 123 HANDLE_INST(cont, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 124 HANDLE_INST(halt, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 125 HANDLE_INST(call, 1, 1, InstTypeFlow, GENX_BDW, ATTR_NONE) 126 HANDLE_INST(return, 1, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 127 HANDLE_INST(goto, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 128 HANDLE_INST(join, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 129 // 130 // Following are pseudo instructions 131 // 132 HANDLE_INST(do, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 133 HANDLE_INST(pseudo_fcall, 1, 1, InstTypeFlow, GENX_BDW, ATTR_NONE) 134 HANDLE_INST(pseudo_fret, 1, 1, InstTypeFlow, GENX_BDW, ATTR_NONE) 135 HANDLE_INST(pseudo_exit, 0, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 136 // pseudo_fc_call are generated for calls to callable kernels. 137 // Destination of such calls is not available at compile time. 138 // Just before binary encoding these instructions are converted to call 139 // and their dst operand is left for runtime to patch. An .fcpatch file 140 // is emitted with VISA instruction number that needs patching. 141 HANDLE_INST(pseudo_fc_call, 1, 1, InstTypeFlow, GENX_BDW, ATTR_NONE) 142 // pseudo_fc_ret are generated for return statements from callable kernels. 143 // This has to be done because for kernels, we convert VISA ret instruction 144 // to EOT. But for callable kernels, we dont want to emit EOT because they 145 // may have to return to a top-level kernel. Only top-level kernel will 146 // have VISA ret lowered to EOT. 147 HANDLE_INST(pseudo_fc_ret, 1, 0, InstTypeFlow, GENX_BDW, ATTR_NONE) 148 149 // 150 // InstTypeVector 151 // 152 HANDLE_INST(sad2, 2, 1, InstTypeVector, GENX_BDW, ATTR_NONE) 153 HANDLE_INST(sada2, 2, 1, InstTypeVector, GENX_BDW, ATTR_NONE) 154 HANDLE_INST(dp4, 2, 1, InstTypeVector, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 155 HANDLE_INST(dph, 2, 1, InstTypeVector, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 156 HANDLE_INST(dp3, 2, 1, InstTypeVector, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 157 HANDLE_INST(dp2, 2, 1, InstTypeVector, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 158 HANDLE_INST(line, 2, 1, InstTypeVector, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 159 HANDLE_INST(pln, 2, 1, InstTypeVector, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 160 HANDLE_INST(mad, 3, 1, InstTypeVector, GENX_BDW, ATTR_NONE) 161 HANDLE_INST(lrp, 3, 1, InstTypeVector, GENX_BDW, ATTR_FLOAT_SRC_ONLY) 162 // 163 // Following are pseudo instructions 164 // 165 HANDLE_INST(pseudo_mad, 3, 1, InstTypeVector, GENX_BDW, ATTR_NONE) 166 HANDLE_INST(pseudo_sada2, 3, 1, InstTypeVector, GENX_BDW, ATTR_NONE) 167 168 // 169 // InstTypeMisc 170 // 171 HANDLE_INST(wait, 1, 0, InstTypeMisc, GENX_BDW, ATTR_NONE) 172 HANDLE_INST(send, 2, 1, InstTypeMisc, GENX_BDW, ATTR_NONE) 173 HANDLE_INST(sendc, 2, 1, InstTypeMisc, GENX_BDW, ATTR_NONE) 174 HANDLE_INST(sends, 4, 1, InstTypeMisc, GENX_SKL, ATTR_NONE) 175 HANDLE_INST(sendsc, 4, 1, InstTypeMisc, GENX_SKL, ATTR_NONE) 176 HANDLE_INST(nop, 0, 0, InstTypeMisc, GENX_BDW, ATTR_NONE) 177 178 HANDLE_INST(sync_nop, 1, 0, InstTypeMisc, GENX_TGLLP, ATTR_NONE) 179 HANDLE_INST(sync_allrd, 1, 0, InstTypeMisc, GENX_TGLLP, ATTR_NONE) 180 HANDLE_INST(sync_allwr, 1, 0, InstTypeMisc, GENX_TGLLP, ATTR_NONE) 181 HANDLE_INST(sync_fence, 1, 0, InstTypeMisc, GENX_PVC, ATTR_NONE) 182 183 // 184 // Following are pseudo instructions 185 // 186 HANDLE_NAME_INST(label, "", 0, 0, InstTypeMisc, GENX_BDW, ATTR_NONE) 187 HANDLE_INST(intrinsic, 1, 3, InstTypeMisc, GENX_BDW, ATTR_NONE) 188 189 // 190 // InstTypePseudoLogic 191 // 192 HANDLE_INST(pseudo_and, 2, 1, InstTypePseudoLogic, GENX_BDW, ATTR_COMMUTATIVE) 193 HANDLE_INST(pseudo_or, 2, 1, InstTypePseudoLogic, GENX_BDW, ATTR_COMMUTATIVE) 194 HANDLE_INST(pseudo_xor, 2, 1, InstTypePseudoLogic, GENX_BDW, ATTR_COMMUTATIVE) 195 HANDLE_INST(pseudo_not, 1, 1, InstTypePseudoLogic, GENX_BDW, ATTR_NONE) 196 197 #undef HANDLE_INST 198 #undef HANDLE_NAME_INST 199