1/*========================== begin_copyright_notice ============================ 2 3Copyright (C) 2017-2021 Intel Corporation 4 5SPDX-License-Identifier: MIT 6 7============================= end_copyright_notice ===========================*/ 8 9#pragma once 10// HW Capabilities 11// these functions are part of IR_Builder class and included in Build_IR.h 12 13 bool hasMixMode() const 14 { 15 if (getOption(vISA_ForceMixMode)) 16 { 17 return true; 18 } 19 if (getOption(vISA_DisableMixMode)) 20 { 21 return false; 22 } 23 24 return getPlatform() > GENX_BDW && 25 getPlatformGeneration(getPlatform()) != PlatformGen::GEN11; 26 } 27 28 // True if it has bfloat16 mixed mode support. 29 bool hasBFMixMode() const { return hasDPAS();} 30 31 bool forceSamplerHeader() const 32 { 33 return m_options->getOption(vISA_forceSamplerHeader) || 34 (getPlatform() < GENX_ICLLP && m_options->getOption(vISA_enablePreemption)); 35 } 36 37 bool needsNoPreemptR2ForSend() const 38 { 39 return getPlatformGeneration(getPlatform()) == PlatformGen::GEN11; 40 } 41 42 bool noDDAllowedPlatform() const 43 { 44 return getPlatform() >= GENX_SKL; 45 } 46 47 bool noSrcDepSetAllowedPlatform() const 48 { 49 return getPlatform() >= GENX_SKL; 50 } 51 52 bool doPlane() const 53 { 54 return getPlatform() < GENX_ICLLP && !getOption(vISA_expandPlane); 55 } 56 57 bool favorFloatMov() const 58 { 59 return getPlatformGeneration(getPlatform()) == PlatformGen::GEN11 || isXeLP(); 60 } 61 62 bool noScalarJmp() const 63 { 64 return !getOption(vISA_EnableScalarJmp); 65 } 66 67 bool hasAlign1Ternary() const 68 { 69 return getPlatform() >= GENX_CNL && getOption(vISA_doAlign1Ternary); 70 } 71 72 bool encodeUnitStrideTernary() const 73 { 74 return getPlatformGeneration(getPlatform()) >= PlatformGen::XE; 75 } 76 77 bool hasMacl() const 78 { 79 return getPlatform() >= GENX_CNL; 80 } 81 82 bool hasCPS() const 83 { 84 return getPlatform() >= GENX_CNL; 85 } 86 87 bool hasBindlessSampler() const 88 { 89 return getPlatform() >= GENX_CNL; 90 } 91 92 bool noSrc2Regioning() const 93 { 94 return getPlatform() >= GENX_ICLLP; 95 } 96 97 bool noSrc1Byte() const 98 { 99 return getOption(vISA_noSrc1Byte) || getPlatform() >= GENX_ICLLP; 100 } 101 102 bool noDFTypeMac() const 103 { 104 if (getPlatform() == GENX_PVC) 105 return true; 106 return false; 107 } 108 109 bool needsFenceCommitEnable() const 110 { 111 if (m_options->getTarget() == VISA_CM) 112 { 113 return getPlatform() >= GENX_SKL; 114 } 115 else 116 { 117 return getPlatform() >= GENX_CNL; 118 } 119 } 120 121 bool hasIEEEDivSqrt() const 122 { 123 return getPlatform() < GENX_ICLLP; 124 } 125 126 bool gotoJumpOnTrue() const 127 { 128 return getPlatform() >= GENX_CNL; 129 } 130 131 bool needsToReserveR127() const 132 { 133 return getPlatform() < GENX_CNL; 134 } 135 136 bool hasSLMFence() const 137 { 138 return getPlatform() >= GENX_ICLLP; 139 } 140 141 bool GRFAlign() const 142 { 143 return getPlatform() < GENX_SKL; 144 } 145 146 bool twoSourcesCollision() const 147 { 148 return getPlatform() < GENX_CNL; 149 } 150 151 bool lowHighBundle() const 152 { 153 return getPlatformGeneration(getPlatform()) <= PlatformGen::GEN11; 154 } 155 156 bool hasSendShootdown() const 157 { 158 return getPlatform() >= GENX_CNL; 159 } 160 161 bool useNewR0Format() const 162 { 163 return getPlatform() >= GENX_ICLLP; 164 } 165 166 int getPredMaskEnableBit() const 167 { 168 return getPlatform() < GENX_ICLLP ? 30 : 23; 169 } 170 171 int getBarrierIDMask() const 172 { 173 return getPlatform() < GENX_ICLLP ? 0x8F000000 : 0x7F000000; 174 } 175 176 uint32_t getMaxSendMessageLength() const 177 { 178 return getPlatform() < GENX_CNL ? 16 : 32; 179 } 180 181 bool hasPixelNullMask() const 182 { 183 return getPlatform() >= GENX_SKL; 184 } 185 186 bool noSLMMsgHeader() const 187 { 188 return getPlatform() >= GENX_SKL; 189 } 190 191 bool needsA32MsgHeader() const 192 { 193 return getPlatform() < GENX_SKL; 194 } 195 196 int getThreadIDMask() const 197 { 198 return getPlatform() >= GENX_SKL ? 0x7FF : 0x1FF; 199 } 200 201 bool hasFloatAtomics() const 202 { 203 return getPlatform() >= GENX_SKL; 204 } 205 206 bool hasBlockedSLMMessage() const 207 { 208 return false; 209 } 210 211 bool hasHeaderlessMRTWrite() const 212 { 213 return getPlatform() >= GENX_ICLLP; 214 } 215 216 bool hasDotProductInst() const 217 { 218 return getPlatform() < GENX_CNL; 219 } 220 221 bool hasLRP() const 222 { 223 return getPlatform() < GENX_ICLLP; 224 } 225 226 int getBarrierMask(bool enableBarrierInstCounterBits) const 227 { 228 if (getPlatform() < GENX_SKL) 229 { 230 //pre-SKL: and (8) H0.0:ud r0.2:ud 0x0F000000 (r0.2, bit 24-27) 231 return enableBarrierInstCounterBits ? 0x0F00FE00 : 0x0F000000; 232 } 233 else if (getPlatform() < GENX_ICLLP) 234 { 235 //SKL+: and (8) H0.0:ud r0.2:ud 0x8F000000 (r0.2, bit24-27, bit31) 236 return enableBarrierInstCounterBits ? 0x8F00FE00 : 0x8F000000; 237 } 238 else 239 { 240 //else: and (8) H0.0:ud r0.2:ud 0x7F000000 (r0.2, bit24-30) 241 return enableBarrierInstCounterBits ? 0x7F00FF00 : 0x7F000000; 242 } 243 } 244 245 bool canMadHaveAcc() const 246 { 247 return getPlatform() >= GENX_CNL; 248 } 249 250 bool hasFdivPow() const 251 { 252 return getPlatformGeneration(getPlatform()) < PlatformGen::XE; 253 } 254 255 bool hasFdivPowWA() const 256 { 257 return getPlatform() < GENX_ICLLP; 258 } 259 260 bool hasCondModForTernary() const 261 { 262 return getPlatformGeneration(getPlatform()) < PlatformGen::XE; 263 } 264 265 bool hasSWSB() const 266 { 267 return getPlatformGeneration(getPlatform()) >= PlatformGen::XE; 268 } 269 270 bool hasPartialMixMode() const 271 { 272 return getPlatformGeneration(getPlatform()) == PlatformGen::XE; 273 } 274 275 // whether EOT sources need to be assigned r112-r127 276 bool hasEOTGRFBinding() const 277 { 278 return true; 279 } 280 281 bool hasSmov() const 282 { 283 return getPlatformGeneration(getPlatform()) < PlatformGen::XE; 284 } 285 286 bool doAccSub() const 287 { 288 return getPlatformGeneration(getPlatform()) >= PlatformGen::GEN11; 289 } 290 291 bool hasNFType() const 292 { 293 return getPlatform() >= GENX_ICLLP && 294 getPlatformGeneration(getPlatform()) != PlatformGen::XE; 295 } 296 297 void getSSIDBits(uint32_t& width, uint32_t& start) const 298 { 299 if (getPlatform() < GENX_CNL) 300 { 301 width = 2; 302 start = 12; //[12:13] 303 } 304 else if (getPlatform() == GENX_CNL) 305 { 306 width = 2; 307 start = 8; //[8:9] 308 } 309 else 310 { 311 width = 3; 312 start = 8;//[8:10] 313 } 314 } 315 316 bool encodeAccRegSelAsAlign1() const 317 { 318 return getPlatform() >= GENX_ICLLP; 319 } 320 321 bool fuseTypedWrites() const 322 { 323 return getOption(vISA_FuseTypedWrites); 324 } 325 326 bool avoidWAWSubRegHazard() const 327 { 328 return getPlatformGeneration(getPlatform()) < PlatformGen::XE && 329 getOption(vISA_WAWSubregHazardAvoidance); 330 } 331 332 bool newTernaryStride() const 333 { 334 return getPlatformGeneration(getPlatform()) >= PlatformGen::XE; 335 } 336 337 // acc restrictions that are relaxed for Xe 338 // -- dp4a can take acc src/dst 339 // -- the same acc may be used in both src0 and src1 of a three-source inst 340 bool relaxedACCRestrictions2() const 341 { 342 return getPlatformGeneration(getPlatform()) >= PlatformGen::XE; 343 } 344 345 bool fuseURBMessage() const 346 { 347 return isXeLP(); 348 } 349 350 bool supportSrcModforMul() const 351 { 352 return getPlatformGeneration(getPlatform()) != PlatformGen::XE; 353 } 354 355 bool doMultiAccSub() const 356 { 357 return getPlatformGeneration(getPlatform()) >= PlatformGen::XE; 358 } 359 360 bool canMadHaveSrc0Acc() const 361 { 362 return getPlatformGeneration(getPlatform()) >= PlatformGen::XE; 363 } 364 365 bool accDstforIndirectSrc() const 366 { 367 return getPlatformGeneration(getPlatform()) != PlatformGen::XE; 368 } 369 370 bool restrictedACCRestrictions() const 371 { 372 return getPlatform() >= GENX_PVC; 373 } 374 375 bool favorFpMad() const 376 { 377 return getPlatform() < GENX_CNL; 378 } 379 380 bool avoidAccDstWithIndirectSource() const 381 { 382 return getPlatform() >= GENX_TGLLP; 383 } 384 385 bool hasRSForSpecificPlatform() const 386 { 387 if (getPlatform() == GENX_DG2) 388 { 389 return m_options->getOption(vISA_ManualEnableRSWA); 390 } 391 return true; 392 } 393 394 bool hasReadSuppression() const 395 { 396 return getPlatform() >= GENX_TGLLP && hasRSForSpecificPlatform(); 397 } 398 399 bool hasEOTReadSuppressionIssue() const 400 { 401 if(getPlatform() == GENX_DG2 && hasRSForSpecificPlatform()) 402 { 403 return true; 404 } 405 return false; 406 } 407 408 bool hasScalarReadSuppression() const 409 { 410 return getPlatform() > GENX_TGLLP && hasRSForSpecificPlatform(); 411 } 412 413 bool hasFPU0ReadSuppressionIssue() const 414 { 415 return getPlatform() == GENX_PVCXT && hasRSForSpecificPlatform(); 416 } 417 418 bool alignBindlessSampler() const 419 { 420 return getPlatformGeneration(getPlatform()) == PlatformGen::GEN9; 421 } 422 423 bool noL3Flush() const 424 { 425 return getPlatform() == GENX_TGLLP; 426 } 427 428 bool needResetA0forVxHA0() const 429 { 430 return getPlatform() >= GENX_ICLLP; 431 } 432 433 unsigned getCoIssueUints() const 434 { 435#if 0 436 auto GEN = getPlatformGeneration(getPlatform()); 437 return (GEN >= PlatformGen::XE) ? 1 : 2; 438#else 439 return 2; 440#endif 441 } 442 443 bool useMultiThreadLatency() const 444 { 445#if 0 446 auto GEN = getPlatformGeneration(getPlatform()); 447 if (GEN >= PlatformGen::XE) 448 return false; 449#endif 450 451 return getOptions()->getOption(vISA_useMultiThreadedLatencies); 452 } 453 454 bool useIGAEncoder() const 455 { 456 return getOption(vISA_IGAEncoder) || getPlatformGeneration(getPlatform()) >= PlatformGen::XE; 457 } 458 459 bool needReplaceIndirectCallWithJmpi() const 460 { 461 return getPlatform() <= GENX_ICLLP || 462 getOption(vISA_replaceIndirectCallWithJmpi); 463 } 464 465 bool needIPWA() const 466 { 467 return getPlatform() == XeHP_SDV; 468 } 469 470 bool canEncodeFullExtDesc() const 471 { 472 return getPlatform() >= GENX_TGLLP; 473 } 474 475 bool needSwap64ImmLoHi() const 476 { 477 return getPlatform() >= GENX_TGLLP; 478 } 479 480 bool has8ByteA64Gather() const 481 { 482 return getPlatform() != GENX_TGLLP; 483 } 484 485 bool WaDisableSendSrcDstOverlap() const 486 { 487 return getOption(vISA_noSendSrcDstOverlap) || 488 (m_options->getTarget() == VISA_CM && getPlatform() >= GENX_SKL && getPlatform() < GENX_TGLLP) || 489 getPlatform() == GENX_ICLLP; 490 } 491 492 bool isXeLP() const 493 { 494 return getPlatform() == GENX_TGLLP; 495 } 496 497 bool hasEarlyGRFRead() const 498 { 499 return (getPlatform() == GENX_TGLLP) && getOption(vISA_HasEarlyGRFRead); 500 } 501 502 503 bool noInt64() const 504 { 505 return getPlatform() == GENX_ICLLP || isXeLP() || getPlatform() == GENX_DG2; 506 } 507 508 bool noFP64() const 509 { 510 return getPlatform() == GENX_ICLLP || isXeLP() || getPlatform() == GENX_DG2; 511 } 512 513 bool no64bitRegioning() const 514 { 515 return getPlatform() == GENX_CHV || getPlatform() == GENX_BXT || 516 getPlatform() == GENX_ICLLP || isXeLP() || getPlatform() == GENX_DG2; 517 } 518 519 bool hasBankCollision() const 520 { 521 if(getPlatform() == GENX_TGLLP) 522 { 523 return true; 524 } 525 return (getPlatformGeneration(getPlatform()) <= PlatformGen::GEN11) || getOption(vISA_forceBCR) || 526 (getOption(vISA_enableBCR) && !hasEarlyGRFRead()); 527 } 528 529 bool oneGRFBankDivision() const 530 { 531 return getPlatform() != XeHP_SDV && getPlatform() != GENX_DG2 && !(getPlatform() == GENX_PVC && !getOption(vISA_HasPartialInt64)); 532 } 533 534 bool hasMadm() const 535 { 536 return getPlatform() != GENX_ICLLP && !isXeLP() && getPlatform() != GENX_DG2; 537 } 538 539 bool hasSIMD16TypedRW() const 540 { 541 return getPlatform() >= XeHP_SDV; 542 } 543 544 bool hasRegDistDepIssue() const 545 { 546 return getPlatform() == GENX_PVCXT; 547 } 548 549 bool doNotRewriteContiguousRegion() const 550 { 551 return getPlatform() >= XeHP_SDV; 552 } 553 554 // acc restrictions that are relaxed for Xe HP 555 // -- mov can have both acc src and dst simultaneously 556 // -- acc0 and acc1 may both be used simultaneously in one inst 557 // -- acc can be packed HF dst of a mix mode inst 558 bool relaxedACCRestrictions() const 559 { 560 return getPlatform() >= XeHP_SDV; 561 } 562 563 bool relaxedACCRestrictions_1() const 564 { 565 return getPlatform() >= GENX_DG2; 566 } 567 568 bool loadThreadPayload() const 569 { 570 return getPlatform() >= XeHP_SDV; 571 } 572 573 bool needFenceBeforeEOT() const 574 { 575 return getPlatform() == XeHP_SDV; 576 } 577 578 bool hasSrc0ReadSuppression() const 579 { 580 return getPlatform() >= XeHP_SDV && hasRSForSpecificPlatform(); 581 } 582 583 bool needToClearScratchWrites() const 584 { 585 return getPlatform() < XeHP_SDV; 586 } 587 588 bool needsToLoadLocalID() const 589 { 590 return loadThreadPayload() && getPerThreadInputSize() > 0 && !getOption(vISA_autoLoadLocalID); 591 } 592 593 bool noDwDstForDwordMul() const 594 { 595 return noInt64() || getPlatform() >= XeHP_SDV; 596 } 597 598 bool useNewExtDescFormat() const 599 { 600 return getPlatform() >= XeHP_SDV; 601 } 602 603 bool has16OWordSLMBlockRW() const 604 { 605 return getPlatform() >= XeHP_SDV; 606 } 607 608 bool hasVxHFloat64b() const 609 { 610 return getPlatform() < XeHP_SDV; 611 } 612 613 bool supportFloatOr64bRegioning() const 614 { 615 return getPlatform() < XeHP_SDV && !getOption(vISA_forceNoFP64bRegioning); 616 } 617 618 int getFP64MadmExecSize() const 619 { 620 auto plat = getPlatform(); 621 if (plat >= GENX_PVC) 622 { 623 return 16; 624 } 625 else if (plat == XeHP_SDV || plat == GENX_DG2) 626 { 627 return 8; 628 } 629 else 630 { 631 return 4; 632 } 633 } 634 635 bool balanceIntFloatMoves() const 636 { 637 return getPlatform() >= XeHP_SDV; 638 } 639 640 G4_Type getMixModeType() const 641 { 642 return getPlatform() >= XeHP_SDV ? Type_BF : Type_HF; 643 } 644 645 // each flag register is 16-bit 646 uint32_t getNumFlagRegisters(void) 647 { 648 return getPlatform() >= GENX_PVC ? 8 : 4; 649 } 650 651 uint32_t getNumScalarRegisters(void) 652 { 653 if (hasScalarRegister()) 654 { 655 return 1; 656 } 657 return 0; 658 } 659 660 bool encodeAccWrEn() const 661 { 662 return getPlatform() < GENX_PVC; 663 } 664 665 SFID getEOTSFID() const 666 { 667 return getPlatform() >= GENX_DG2 ? SFID::GATEWAY : SFID::SPAWNER; 668 } 669 670 // EU native execution size for 32-bit types 671 G4_ExecSize getNativeExecSize() const 672 { 673 return getPlatform() >= GENX_PVC ? g4::SIMD16 : g4::SIMD8; 674 } 675 676 bool noScalarByteToFloat() const 677 { 678 return getPlatform() >= XeHP_SDV; 679 } 680 681 bool noHFToInteger() const 682 { 683 return getPlatform() == GENX_PVCXT; 684 } 685 686 bool useAccForDF() const 687 { 688 return getPlatform() >= XeHP_SDV; 689 } 690 691 bool useAccForMadm() const 692 { 693 return getPlatform() >= XeHP_SDV; 694 } 695 696 bool hasUnifiedBarrier() const 697 { 698 return getPlatform() >= GENX_DG2; 699 } 700 701 bool predCtrlHasWidth() const 702 { 703 return getPlatform() < GENX_PVC; 704 } 705 706 bool hasNibCtrl() const 707 { 708 return getPlatform() < GENX_PVC; 709 } 710 711 bool hasMaskForScratchMsg() const 712 { 713 return getPlatform() < GENX_PVC; 714 } 715 716 bool avoidDstSrcOverlap() 717 { 718 return getPlatform() >= GENX_ICLLP && getOption(vISA_DstSrcOverlapWA); 719 } 720 721 bool avoidSrc1Src2Overlap() 722 { 723 return getOption(vISA_Src1Src2OverlapWA); 724 } 725 726 bool hasTwoGRFMathMacro() const 727 { 728 return getPlatform() >= GENX_PVC; 729 } 730 731 bool hasFP64Acc() const 732 { 733 return !noFP64(); 734 } 735 736 bool hasMathAcc() const 737 { 738 return getOption(vISA_mathAccSub); 739 } 740 741 //to relax ACC usage restrictions for FP MUL and MAD instructions. 742 //1. Support both sources as ACC for FP MUL 743 //2. Support Src2 as ACC for FP MAD 744 bool relaxedACCRestrictions3() const 745 { 746 return false; 747 } 748 749 bool hasDoubleAcc() const 750 { 751 return getOption(vISA_hasDoubleAcc); 752 } 753 754 bool hasHFMathGRFAlign() const 755 { 756 return getPlatform() == GENX_PVCXT; 757 } 758 759 bool hasFixedCycleMathPipeline() const 760 { 761 return getPlatform() >= GENX_PVC; 762 } 763 764 bool hasByteALU() const 765 { 766 // Avoid byte operands in ALU operations if hasByteALU() returns false. 767 return getPlatform() < GENX_PVC; 768 } 769 770 bool hasSingleALUPipe() const 771 { 772 return getPlatform() == GENX_TGLLP; 773 } 774 775 bool hasMathRSIsuue() const 776 { 777 return getPlatform() == GENX_TGLLP; 778 } 779 780 bool supportsSampler() const 781 { 782 return getPlatform() != GENX_PVC && getPlatform() != GENX_PVCXT; 783 } 784 785 bool has2xDP() const 786 { 787 return getPlatform() >= GENX_PVCXT; 788 } 789 790 int get3SrcDstAlign() const 791 { 792 return getPlatform() >= XeHP_SDV ? 2 : 8; 793 } 794 795 bool supportCallaRegSrc() const 796 { 797 if (getPlatform() >= GENX_DG2) 798 return true; 799 return false; 800 } 801 802 803 bool hasTwoGRFBank16Bundles() const 804 { 805 const TARGET_PLATFORM P = getPlatform(); 806 return P == XeHP_SDV || P == GENX_DG2 || (P == GENX_PVC && !getOption(vISA_HasPartialInt64)); 807 } 808 809 bool hasOneGRFBank16Bundles() const 810 { 811 const TARGET_PLATFORM P = getPlatform(); 812 return P != XeHP_SDV && P != GENX_DG2 && !(P == GENX_PVC && !getOption(vISA_HasPartialInt64)); 813 } 814 815 bool hasDPASSrc0Src1BankConflict() const 816 { 817 return getPlatform() >= XeHP_SDV; 818 } 819 820 bool needsToLoadCrossThreadConstantData() const 821 { 822 return loadThreadPayload() && getOption(vISA_loadCrossThreadConstantData); 823 } 824 825 bool hasDPAS() const 826 { 827 return getPlatform() >= XeHP_SDV; 828 } 829 830 bool hasAMFSFastClear() const 831 { 832 return getPlatform() >= XeHP_SDV; 833 } 834 835 // only valid type combinations during format mov conversion if acc is used: 836 // Src Type UD/D - Dst Type W/UW/UD/D 837 // Src Type UW/W - Dst Type W/UW/UD/D 838 // Src Type F/HF - Dst Type F/HF 839 // Src Type DF - Dst Type DF 840 bool hasFormatConversionACCRestrictions() const 841 { 842 return getPlatform() >= XeHP_SDV; 843 } 844 845 bool hasScratchSurface() const 846 { 847 return getPlatform() >= XeHP_SDV; 848 } 849 850 // Note that this function is intentionally omitted from HWCapsOpen.inc to avoid IP leak 851 bool hasThreeALUPipes() const 852 { 853 const TARGET_PLATFORM P = getPlatform(); 854 return (P == XeHP_SDV || P == GENX_DG2); 855 } 856 857 bool hasFusedEUWA() const 858 { 859 return ((getuint32Option(vISA_noMaskWA) & 0x3) > 0 || 860 getOption(vISA_forceNoMaskWA)) && !getOption(vISA_LinearScan) && hasFusedEU(); 861 } 862 863 bool hasFusedEU() const 864 { 865 return (getPlatform() == GENX_TGLLP || getPlatform() == XeHP_SDV || getPlatform() == GENX_DG2); 866 } 867 868 bool hasSLMWARIssue() const 869 { 870 return getPlatform() == GENX_DG2 || getPlatform() == GENX_PVC || getPlatform() == GENX_PVCXT; 871 } 872 873 bool noSelOnALTMode() const 874 { 875 return getPlatform() == GENX_DG2; 876 } 877 878 bool hasLongOperandTypeDepIssue() const 879 { 880 return getPlatform() == GENX_PVCXT; 881 } 882 883 bool hasFourALUPipes() const 884 { 885 return getPlatform() >= GENX_PVC; 886 } 887 888 bool hasFiveALUPipes() const 889 { 890 return false; 891 } 892 893 bool hasSrc2ReadSupression() const 894 { 895 return getPlatform() >= GENX_PVCXT;; 896 } 897 898 bool hasSrc2ReadSupressionSameRegSameType() const 899 { 900 return getPlatform() == GENX_PVC && !getOption(vISA_HasPartialInt64); 901 } 902 903 bool hasFixedCycleMathPipe() const 904 { 905 return getPlatform() >= GENX_PVC; 906 } 907 908 bool hasBFDstforDPAS() const 909 { 910 return getPlatform() >= GENX_PVC; 911 } 912 913 bool hasHWordBlockLoad() const 914 { 915 return getPlatform() >= GENX_PVC; 916 } 917 918 bool hasFenceControl() const 919 { 920 return false; 921 } 922 923 bool useLSCForPayloadLoad() const 924 { 925 return getPlatform() >= GENX_PVC; 926 } 927 928 bool hasPartialInt64Support() const 929 { 930 return getPlatform() >= GENX_PVCXT || (getPlatform() >= GENX_PVC && getOption(vISA_HasPartialInt64)); 931 } 932 933 bool hasInt64Add() const 934 { 935 return getOption(vISA_HasInt64Add); 936 } 937 938 bool supportsLSC() const 939 { 940 return getPlatform() >= GENX_DG2; 941 } 942 943 bool encodeSendSrc1Length() const 944 { 945 return getPlatform() >= GENX_DG2; 946 } 947 948 bool hasLSCEnableHalfSIMD() const 949 { 950 return getPlatform() >= GENX_PVCXT || getOption(vISA_LSCEnableHalfSIMD); 951 } 952 953 bool isLSCCacheOpt17_19() const 954 { 955 return true; 956 } 957 958 959 bool has64bundleSize() const 960 { 961 return false; 962 } 963 964 965 bool hasDPASSrc2ReadSuppressionIssue() const 966 { 967 return getPlatform() == GENX_PVC; 968 } 969 bool hasDPASSrc2ReadSuppressionDepIssue() const 970 { 971 return getPlatform() == GENX_PVC; 972 } 973 974 bool hasMathDpasConflict() const 975 { 976 return (getPlatform() == GENX_PVC) && getOption(vISA_EnableMathDPASWA); 977 } 978 979 bool waDisableIntMac() const 980 { 981 return getPlatform() == GENX_PVC; 982 } 983 984 bool hasWriteCombine() const 985 { 986 return getPlatform() >= GENX_PVC; 987 } 988 989 bool noMulOrMadwExpandingBeforeScheduler() 990 { 991 return getPlatform() == GENX_PVC || getPlatform() == GENX_PVCXT; 992 } 993 bool hasA0WARHWissue() 994 { 995 return (getPlatform() == XeHP_SDV || getPlatform() == GENX_DG2 || getPlatform() == GENX_PVC); 996 } 997 998 bool hasFtoPackedHFMove() const 999 { 1000 return getPlatform() >= GENX_DG2; 1001 } 1002 1003 bool hasGather4PO() const 1004 { 1005 return getPlatform() <= GENX_TGLLP; 1006 } 1007 1008 bool hasQ2FInIntegerPipe() const 1009 { 1010 return false; 1011 } 1012 1013 bool hasScalarRegister() const 1014 { 1015 return false; 1016 } 1017 1018 unsigned int getMaxPTSS() const 1019 { 1020 if (getPlatform() >= GENX_TGLLP) 1021 { 1022 // Max PTSS supported is 256kb 1023 return 256 * 1024; 1024 } 1025 1026 // Max PTSS supported is 2MB 1027 return 2 * 1024 * 1024; 1028 } 1029 // end HW capabilities 1030