1 //===- llvm/MC/MCInstrAnalysis.h - InstrDesc target hooks -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the MCInstrAnalysis class which the MCTargetDescs can 10 // derive from to give additional information to MC. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_MC_MCINSTRANALYSIS_H 15 #define LLVM_MC_MCINSTRANALYSIS_H 16 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include <cstdint> 21 22 namespace llvm { 23 24 class MCRegisterInfo; 25 class Triple; 26 27 class MCInstrAnalysis { 28 protected: 29 friend class Target; 30 31 const MCInstrInfo *Info; 32 33 public: MCInstrAnalysis(const MCInstrInfo * Info)34 MCInstrAnalysis(const MCInstrInfo *Info) : Info(Info) {} 35 virtual ~MCInstrAnalysis() = default; 36 isBranch(const MCInst & Inst)37 virtual bool isBranch(const MCInst &Inst) const { 38 return Info->get(Inst.getOpcode()).isBranch(); 39 } 40 isConditionalBranch(const MCInst & Inst)41 virtual bool isConditionalBranch(const MCInst &Inst) const { 42 return Info->get(Inst.getOpcode()).isConditionalBranch(); 43 } 44 isUnconditionalBranch(const MCInst & Inst)45 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 46 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 47 } 48 isIndirectBranch(const MCInst & Inst)49 virtual bool isIndirectBranch(const MCInst &Inst) const { 50 return Info->get(Inst.getOpcode()).isIndirectBranch(); 51 } 52 isCall(const MCInst & Inst)53 virtual bool isCall(const MCInst &Inst) const { 54 return Info->get(Inst.getOpcode()).isCall(); 55 } 56 isReturn(const MCInst & Inst)57 virtual bool isReturn(const MCInst &Inst) const { 58 return Info->get(Inst.getOpcode()).isReturn(); 59 } 60 isTerminator(const MCInst & Inst)61 virtual bool isTerminator(const MCInst &Inst) const { 62 return Info->get(Inst.getOpcode()).isTerminator(); 63 } 64 isCapTableLoad(const MCInst & Inst,int64_t & Offset)65 virtual bool isCapTableLoad(const MCInst &Inst, int64_t &Offset) const { 66 return false; 67 } 68 69 /// Returns true if at least one of the register writes performed by 70 /// \param Inst implicitly clears the upper portion of all super-registers. 71 /// 72 /// Example: on X86-64, a write to EAX implicitly clears the upper half of 73 /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit 74 /// instruction implicitly clears the upper portion of the correspondent 75 /// YMM register. 76 /// 77 /// This method also updates an APInt which is used as mask of register 78 /// writes. There is one bit for every explicit/implicit write performed by 79 /// the instruction. If a write implicitly clears its super-registers, then 80 /// the corresponding bit is set (vic. the corresponding bit is cleared). 81 /// 82 /// The first bits in the APint are related to explicit writes. The remaining 83 /// bits are related to implicit writes. The sequence of writes follows the 84 /// machine operand sequence. For implicit writes, the sequence is defined by 85 /// the MCInstrDesc. 86 /// 87 /// The assumption is that the bit-width of the APInt is correctly set by 88 /// the caller. The default implementation conservatively assumes that none of 89 /// the writes clears the upper portion of a super-register. 90 virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI, 91 const MCInst &Inst, 92 APInt &Writes) const; 93 94 /// Returns true if MI is a dependency breaking zero-idiom for the given 95 /// subtarget. 96 /// 97 /// Mask is used to identify input operands that have their dependency 98 /// broken. Each bit of the mask is associated with a specific input operand. 99 /// Bits associated with explicit input operands are laid out first in the 100 /// mask; implicit operands come after explicit operands. 101 /// 102 /// Dependencies are broken only for operands that have their corresponding bit 103 /// set. Operands that have their bit cleared, or that don't have a 104 /// corresponding bit in the mask don't have their dependency broken. Note 105 /// that Mask may not be big enough to describe all operands. The assumption 106 /// for operands that don't have a correspondent bit in the mask is that those 107 /// are still data dependent. 108 /// 109 /// The only exception to the rule is for when Mask has all zeroes. 110 /// A zero mask means: dependencies are broken for all explicit register 111 /// operands. isZeroIdiom(const MCInst & MI,APInt & Mask,unsigned CPUID)112 virtual bool isZeroIdiom(const MCInst &MI, APInt &Mask, 113 unsigned CPUID) const { 114 return false; 115 } 116 117 /// Returns true if MI is a dependency breaking instruction for the 118 /// subtarget associated with CPUID . 119 /// 120 /// The value computed by a dependency breaking instruction is not dependent 121 /// on the inputs. An example of dependency breaking instruction on X86 is 122 /// `XOR %eax, %eax`. 123 /// 124 /// If MI is a dependency breaking instruction for subtarget CPUID, then Mask 125 /// can be inspected to identify independent operands. 126 /// 127 /// Essentially, each bit of the mask corresponds to an input operand. 128 /// Explicit operands are laid out first in the mask; implicit operands follow 129 /// explicit operands. Bits are set for operands that are independent. 130 /// 131 /// Note that the number of bits in Mask may not be equivalent to the sum of 132 /// explicit and implicit operands in MI. Operands that don't have a 133 /// corresponding bit in Mask are assumed "not independente". 134 /// 135 /// The only exception is for when Mask is all zeroes. That means: explicit 136 /// input operands of MI are independent. isDependencyBreaking(const MCInst & MI,APInt & Mask,unsigned CPUID)137 virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask, 138 unsigned CPUID) const { 139 return isZeroIdiom(MI, Mask, CPUID); 140 } 141 142 /// Returns true if MI is a candidate for move elimination. 143 /// 144 /// Different subtargets may apply different constraints to optimizable 145 /// register moves. For example, on most X86 subtargets, a candidate for move 146 /// elimination cannot specify the same register for both source and 147 /// destination. isOptimizableRegisterMove(const MCInst & MI,unsigned CPUID)148 virtual bool isOptimizableRegisterMove(const MCInst &MI, 149 unsigned CPUID) const { 150 return false; 151 } 152 153 /// Given a branch instruction try to get the address the branch 154 /// targets. Return true on success, and the address in Target. 155 virtual bool 156 evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 157 uint64_t &Target) const; 158 159 /// Given an instruction tries to get the address of a memory operand. Returns 160 /// the address on success. 161 virtual Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst, 162 uint64_t Addr, 163 uint64_t Size) const; 164 165 /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries. 166 virtual std::vector<std::pair<uint64_t, uint64_t>> findPltEntries(uint64_t PltSectionVA,ArrayRef<uint8_t> PltContents,uint64_t GotPltSectionVA,const Triple & TargetTriple)167 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 168 uint64_t GotPltSectionVA, const Triple &TargetTriple) const { 169 return {}; 170 } 171 }; 172 173 } // end namespace llvm 174 175 #endif // LLVM_MC_MCINSTRANALYSIS_H 176