1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 81HANDLE_TARGET_OPCODE(DBG_LABEL) 82 83/// REG_SEQUENCE - This variadic instruction is used to form a register that 84/// represents a consecutive sequence of sub-registers. It's used as a 85/// register coalescing / allocation aid and must be eliminated before code 86/// emission. 87// In SDNode form, the first operand encodes the register class created by 88// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 89// pair. Once it has been lowered to a MachineInstr, the regclass operand 90// is no longer present. 91/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 92/// After register coalescing references of v1024 should be replace with 93/// v1027:3, v1025 with v1027:4, etc. 94 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 95 96/// COPY - Target-independent register copy. This instruction can also be 97/// used to copy between subregisters of virtual registers. 98 HANDLE_TARGET_OPCODE(COPY) 99 100/// BUNDLE - This instruction represents an instruction bundle. Instructions 101/// which immediately follow a BUNDLE instruction which are marked with 102/// 'InsideBundle' flag are inside the bundle. 103HANDLE_TARGET_OPCODE(BUNDLE) 104 105/// Lifetime markers. 106HANDLE_TARGET_OPCODE(LIFETIME_START) 107HANDLE_TARGET_OPCODE(LIFETIME_END) 108 109/// A Stackmap instruction captures the location of live variables at its 110/// position in the instruction stream. It is followed by a shadow of bytes 111/// that must lie within the function and not contain another stackmap. 112HANDLE_TARGET_OPCODE(STACKMAP) 113 114/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 115HANDLE_TARGET_OPCODE(FENTRY_CALL) 116 117/// Patchable call instruction - this instruction represents a call to a 118/// constant address, followed by a series of NOPs. It is intended to 119/// support optimizations for dynamic languages (such as javascript) that 120/// rewrite calls to runtimes with more efficient code sequences. 121/// This also implies a stack map. 122HANDLE_TARGET_OPCODE(PATCHPOINT) 123 124/// This pseudo-instruction loads the stack guard value. Targets which need 125/// to prevent the stack guard value or address from being spilled to the 126/// stack should override TargetLowering::emitLoadStackGuardNode and 127/// additionally expand this pseudo after register allocation. 128HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 129 130/// These are used to support call sites that must have the stack adjusted 131/// before the call (e.g. to initialize an argument passed by value). 132/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 133HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 134HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 135 136/// Call instruction with associated vm state for deoptimization and list 137/// of live pointers for relocation by the garbage collector. It is 138/// intended to support garbage collection with fully precise relocating 139/// collectors and deoptimizations in either the callee or caller. 140HANDLE_TARGET_OPCODE(STATEPOINT) 141 142/// Instruction that records the offset of a local stack allocation passed to 143/// llvm.localescape. It has two arguments: the symbol for the label and the 144/// frame index of the local stack allocation. 145HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 146 147/// Wraps a machine instruction which can fault, bundled with associated 148/// information on how to handle such a fault. 149/// For example loading instruction that may page fault, bundled with associated 150/// information on how to handle such a page fault. It is intended to support 151/// "zero cost" null checks in managed languages by allowing LLVM to fold 152/// comparisons into existing memory operations. 153HANDLE_TARGET_OPCODE(FAULTING_OP) 154 155/// Wraps a machine instruction to add patchability constraints. An 156/// instruction wrapped in PATCHABLE_OP has to either have a minimum 157/// size or be preceded with a nop of that size. The first operand is 158/// an immediate denoting the minimum size of the instruction, the 159/// second operand is an immediate denoting the opcode of the original 160/// instruction. The rest of the operands are the operands of the 161/// original instruction. 162HANDLE_TARGET_OPCODE(PATCHABLE_OP) 163 164/// This is a marker instruction which gets translated into a nop sled, useful 165/// for inserting instrumentation instructions at runtime. 166HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 167 168/// Wraps a return instruction and its operands to enable adding nop sleds 169/// either before or after the return. The nop sleds are useful for inserting 170/// instrumentation instructions at runtime. 171/// The patch here replaces the return instruction. 172HANDLE_TARGET_OPCODE(PATCHABLE_RET) 173 174/// This is a marker instruction which gets translated into a nop sled, useful 175/// for inserting instrumentation instructions at runtime. 176/// The patch here prepends the return instruction. 177/// The same thing as in x86_64 is not possible for ARM because it has multiple 178/// return instructions. Furthermore, CPU allows parametrized and even 179/// conditional return instructions. In the current ARM implementation we are 180/// making use of the fact that currently LLVM doesn't seem to generate 181/// conditional return instructions. 182/// On ARM, the same instruction can be used for popping multiple registers 183/// from the stack and returning (it just pops pc register too), and LLVM 184/// generates it sometimes. So we can't insert the sled between this stack 185/// adjustment and the return without splitting the original instruction into 2 186/// instructions. So on ARM, rather than jumping into the exit trampoline, we 187/// call it, it does the tracing, preserves the stack and returns. 188HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 189 190/// Wraps a tail call instruction and its operands to enable adding nop sleds 191/// either before or after the tail exit. We use this as a disambiguation from 192/// PATCHABLE_RET which specifically only works for return instructions. 193HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 194 195/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 196/// be patched to insert instrumentation instructions. 197HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 198 199/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 200/// can be patched to insert instrumentation instructions. 201HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 202 203HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 204 205/// The following generic opcodes are not supposed to appear after ISel. 206/// This is something we might want to relax, but for now, this is convenient 207/// to produce diagnostics. 208 209/// Generic ADD instruction. This is an integer add. 210HANDLE_TARGET_OPCODE(G_ADD) 211HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 212 213/// Generic SUB instruction. This is an integer sub. 214HANDLE_TARGET_OPCODE(G_SUB) 215 216// Generic multiply instruction. 217HANDLE_TARGET_OPCODE(G_MUL) 218 219// Generic signed division instruction. 220HANDLE_TARGET_OPCODE(G_SDIV) 221 222// Generic unsigned division instruction. 223HANDLE_TARGET_OPCODE(G_UDIV) 224 225// Generic signed remainder instruction. 226HANDLE_TARGET_OPCODE(G_SREM) 227 228// Generic unsigned remainder instruction. 229HANDLE_TARGET_OPCODE(G_UREM) 230 231/// Generic bitwise and instruction. 232HANDLE_TARGET_OPCODE(G_AND) 233 234/// Generic bitwise or instruction. 235HANDLE_TARGET_OPCODE(G_OR) 236 237/// Generic bitwise exclusive-or instruction. 238HANDLE_TARGET_OPCODE(G_XOR) 239 240 241HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 242 243/// Generic PHI instruction with types. 244HANDLE_TARGET_OPCODE(G_PHI) 245 246/// Generic instruction to materialize the address of an alloca or other 247/// stack-based object. 248HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 249 250/// Generic reference to global value. 251HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 252 253/// Generic instruction to extract blocks of bits from the register given 254/// (typically a sub-register COPY after instruction selection). 255HANDLE_TARGET_OPCODE(G_EXTRACT) 256 257HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 258 259/// Generic instruction to insert blocks of bits from the registers given into 260/// the source. 261HANDLE_TARGET_OPCODE(G_INSERT) 262 263/// Generic instruction to paste a variable number of components together into a 264/// larger register. 265HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 266 267/// Generic instruction to create a vector value from a number of scalar 268/// components. 269HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 270 271/// Generic instruction to create a vector value from a number of scalar 272/// components, which have types larger than the result vector elt type. 273HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 274 275/// Generic instruction to create a vector by concatenating multiple vectors. 276HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 277 278/// Generic pointer to int conversion. 279HANDLE_TARGET_OPCODE(G_PTRTOINT) 280 281/// Generic int to pointer conversion. 282HANDLE_TARGET_OPCODE(G_INTTOPTR) 283 284/// Generic bitcast. The source and destination types must be different, or a 285/// COPY is the relevant instruction. 286HANDLE_TARGET_OPCODE(G_BITCAST) 287 288/// Generic freeze. 289HANDLE_TARGET_OPCODE(G_FREEZE) 290 291/// INTRINSIC trunc intrinsic. 292HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 293 294/// INTRINSIC round intrinsic. 295HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 296 297/// INTRINSIC readcyclecounter 298HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 299 300/// Generic load (including anyext load) 301HANDLE_TARGET_OPCODE(G_LOAD) 302 303/// Generic signext load 304HANDLE_TARGET_OPCODE(G_SEXTLOAD) 305 306/// Generic zeroext load 307HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 308 309/// Generic indexed load (including anyext load) 310HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 311 312/// Generic indexed signext load 313HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 314 315/// Generic indexed zeroext load 316HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 317 318/// Generic store. 319HANDLE_TARGET_OPCODE(G_STORE) 320 321/// Generic indexed store. 322HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 323 324/// Generic atomic cmpxchg with internal success check. 325HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 326 327/// Generic atomic cmpxchg. 328HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 329 330/// Generic atomicrmw. 331HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 332HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 333HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 334HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 335HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 336HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 337HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 338HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 339HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 340HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 341HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 342HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 343HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 344 345// Generic atomic fence 346HANDLE_TARGET_OPCODE(G_FENCE) 347 348/// Generic conditional branch instruction. 349HANDLE_TARGET_OPCODE(G_BRCOND) 350 351/// Generic indirect branch instruction. 352HANDLE_TARGET_OPCODE(G_BRINDIRECT) 353 354/// Generic intrinsic use (without side effects). 355HANDLE_TARGET_OPCODE(G_INTRINSIC) 356 357/// Generic intrinsic use (with side effects). 358HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 359 360/// Generic extension allowing rubbish in high bits. 361HANDLE_TARGET_OPCODE(G_ANYEXT) 362 363/// Generic instruction to discard the high bits of a register. This differs 364/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 365/// each element individually, G_EXTRACT will typically discard the high 366/// elements of the vector. 367HANDLE_TARGET_OPCODE(G_TRUNC) 368 369/// Generic integer constant. 370HANDLE_TARGET_OPCODE(G_CONSTANT) 371 372/// Generic floating constant. 373HANDLE_TARGET_OPCODE(G_FCONSTANT) 374 375/// Generic va_start instruction. Stores to its one pointer operand. 376HANDLE_TARGET_OPCODE(G_VASTART) 377 378/// Generic va_start instruction. Stores to its one pointer operand. 379HANDLE_TARGET_OPCODE(G_VAARG) 380 381// Generic sign extend 382HANDLE_TARGET_OPCODE(G_SEXT) 383HANDLE_TARGET_OPCODE(G_SEXT_INREG) 384 385// Generic zero extend 386HANDLE_TARGET_OPCODE(G_ZEXT) 387 388// Generic left-shift 389HANDLE_TARGET_OPCODE(G_SHL) 390 391// Generic logical right-shift 392HANDLE_TARGET_OPCODE(G_LSHR) 393 394// Generic arithmetic right-shift 395HANDLE_TARGET_OPCODE(G_ASHR) 396 397// Generic funnel left shift 398HANDLE_TARGET_OPCODE(G_FSHL) 399 400// Generic funnel right shift 401HANDLE_TARGET_OPCODE(G_FSHR) 402 403/// Generic integer-base comparison, also applicable to vectors of integers. 404HANDLE_TARGET_OPCODE(G_ICMP) 405 406/// Generic floating-point comparison, also applicable to vectors. 407HANDLE_TARGET_OPCODE(G_FCMP) 408 409/// Generic select. 410HANDLE_TARGET_OPCODE(G_SELECT) 411 412/// Generic unsigned add instruction, consuming the normal operands and 413/// producing the result and a carry flag. 414HANDLE_TARGET_OPCODE(G_UADDO) 415 416/// Generic unsigned add instruction, consuming the normal operands plus a carry 417/// flag, and similarly producing the result and a carry flag. 418HANDLE_TARGET_OPCODE(G_UADDE) 419 420/// Generic unsigned sub instruction, consuming the normal operands and 421/// producing the result and a carry flag. 422HANDLE_TARGET_OPCODE(G_USUBO) 423 424/// Generic unsigned subtract instruction, consuming the normal operands plus a 425/// carry flag, and similarly producing the result and a carry flag. 426HANDLE_TARGET_OPCODE(G_USUBE) 427 428/// Generic signed add instruction, producing the result and a signed overflow 429/// flag. 430HANDLE_TARGET_OPCODE(G_SADDO) 431 432/// Generic signed add instruction, consuming the normal operands plus a carry 433/// flag, and similarly producing the result and a carry flag. 434HANDLE_TARGET_OPCODE(G_SADDE) 435 436/// Generic signed subtract instruction, producing the result and a signed 437/// overflow flag. 438HANDLE_TARGET_OPCODE(G_SSUBO) 439 440/// Generic signed sub instruction, consuming the normal operands plus a carry 441/// flag, and similarly producing the result and a carry flag. 442HANDLE_TARGET_OPCODE(G_SSUBE) 443 444/// Generic unsigned multiply instruction, producing the result and a signed 445/// overflow flag. 446HANDLE_TARGET_OPCODE(G_UMULO) 447 448/// Generic signed multiply instruction, producing the result and a signed 449/// overflow flag. 450HANDLE_TARGET_OPCODE(G_SMULO) 451 452// Multiply two numbers at twice the incoming bit width (unsigned) and return 453// the high half of the result. 454HANDLE_TARGET_OPCODE(G_UMULH) 455 456// Multiply two numbers at twice the incoming bit width (signed) and return 457// the high half of the result. 458HANDLE_TARGET_OPCODE(G_SMULH) 459 460/// Generic saturating unsigned addition. 461HANDLE_TARGET_OPCODE(G_UADDSAT) 462 463/// Generic saturating signed addition. 464HANDLE_TARGET_OPCODE(G_SADDSAT) 465 466/// Generic saturating unsigned subtraction. 467HANDLE_TARGET_OPCODE(G_USUBSAT) 468 469/// Generic saturating signed subtraction. 470HANDLE_TARGET_OPCODE(G_SSUBSAT) 471 472/// Generic FP addition. 473HANDLE_TARGET_OPCODE(G_FADD) 474 475/// Generic FP subtraction. 476HANDLE_TARGET_OPCODE(G_FSUB) 477 478/// Generic FP multiplication. 479HANDLE_TARGET_OPCODE(G_FMUL) 480 481/// Generic FMA multiplication. Behaves like llvm fma intrinsic 482HANDLE_TARGET_OPCODE(G_FMA) 483 484/// Generic FP multiply and add. Behaves as separate fmul and fadd. 485HANDLE_TARGET_OPCODE(G_FMAD) 486 487/// Generic FP division. 488HANDLE_TARGET_OPCODE(G_FDIV) 489 490/// Generic FP remainder. 491HANDLE_TARGET_OPCODE(G_FREM) 492 493/// Generic FP exponentiation. 494HANDLE_TARGET_OPCODE(G_FPOW) 495 496/// Generic base-e exponential of a value. 497HANDLE_TARGET_OPCODE(G_FEXP) 498 499/// Generic base-2 exponential of a value. 500HANDLE_TARGET_OPCODE(G_FEXP2) 501 502/// Floating point base-e logarithm of a value. 503HANDLE_TARGET_OPCODE(G_FLOG) 504 505/// Floating point base-2 logarithm of a value. 506HANDLE_TARGET_OPCODE(G_FLOG2) 507 508/// Floating point base-10 logarithm of a value. 509HANDLE_TARGET_OPCODE(G_FLOG10) 510 511/// Generic FP negation. 512HANDLE_TARGET_OPCODE(G_FNEG) 513 514/// Generic FP extension. 515HANDLE_TARGET_OPCODE(G_FPEXT) 516 517/// Generic float to signed-int conversion 518HANDLE_TARGET_OPCODE(G_FPTRUNC) 519 520/// Generic float to signed-int conversion 521HANDLE_TARGET_OPCODE(G_FPTOSI) 522 523/// Generic float to unsigned-int conversion 524HANDLE_TARGET_OPCODE(G_FPTOUI) 525 526/// Generic signed-int to float conversion 527HANDLE_TARGET_OPCODE(G_SITOFP) 528 529/// Generic unsigned-int to float conversion 530HANDLE_TARGET_OPCODE(G_UITOFP) 531 532/// Generic FP absolute value. 533HANDLE_TARGET_OPCODE(G_FABS) 534 535/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 536/// not require that X and Y have the same type, just that they are both 537/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 538/// f64) is allowed. 539HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 540 541/// Generic FP canonicalize value. 542HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 543 544/// FP min/max matching libm's fmin/fmax 545HANDLE_TARGET_OPCODE(G_FMINNUM) 546HANDLE_TARGET_OPCODE(G_FMAXNUM) 547 548/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 549HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 550HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 551 552/// FP min/max matching IEEE-754 2018 draft semantics. 553HANDLE_TARGET_OPCODE(G_FMINIMUM) 554HANDLE_TARGET_OPCODE(G_FMAXIMUM) 555 556/// Generic pointer offset 557HANDLE_TARGET_OPCODE(G_PTR_ADD) 558 559/// Clear the specified bits in a pointer. 560HANDLE_TARGET_OPCODE(G_PTRMASK) 561 562/// Generic signed integer minimum. 563HANDLE_TARGET_OPCODE(G_SMIN) 564 565/// Generic signed integer maximum. 566HANDLE_TARGET_OPCODE(G_SMAX) 567 568/// Generic unsigned integer maximum. 569HANDLE_TARGET_OPCODE(G_UMIN) 570 571/// Generic unsigned integer maximum. 572HANDLE_TARGET_OPCODE(G_UMAX) 573 574/// Generic BRANCH instruction. This is an unconditional branch. 575HANDLE_TARGET_OPCODE(G_BR) 576 577/// Generic branch to jump table entry. 578HANDLE_TARGET_OPCODE(G_BRJT) 579 580/// Generic insertelement. 581HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 582 583/// Generic extractelement. 584HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 585 586/// Generic shufflevector. 587HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 588 589/// Generic count trailing zeroes. 590HANDLE_TARGET_OPCODE(G_CTTZ) 591 592/// Same as above, undefined for zero inputs. 593HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 594 595/// Generic count leading zeroes. 596HANDLE_TARGET_OPCODE(G_CTLZ) 597 598/// Same as above, undefined for zero inputs. 599HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 600 601/// Generic count bits. 602HANDLE_TARGET_OPCODE(G_CTPOP) 603 604/// Generic byte swap. 605HANDLE_TARGET_OPCODE(G_BSWAP) 606 607/// Generic bit reverse. 608HANDLE_TARGET_OPCODE(G_BITREVERSE) 609 610/// Floating point ceil. 611HANDLE_TARGET_OPCODE(G_FCEIL) 612 613/// Floating point cosine. 614HANDLE_TARGET_OPCODE(G_FCOS) 615 616/// Floating point sine. 617HANDLE_TARGET_OPCODE(G_FSIN) 618 619/// Floating point square root. 620HANDLE_TARGET_OPCODE(G_FSQRT) 621 622/// Floating point floor. 623HANDLE_TARGET_OPCODE(G_FFLOOR) 624 625/// Floating point round to next integer. 626HANDLE_TARGET_OPCODE(G_FRINT) 627 628/// Floating point round to nearest integer. 629HANDLE_TARGET_OPCODE(G_FNEARBYINT) 630 631/// Generic AddressSpaceCast. 632HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 633 634/// Generic block address 635HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 636 637/// Generic jump table address 638HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 639 640/// Generic dynamic stack allocation. 641HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 642 643/// Strict floating point instructions. 644HANDLE_TARGET_OPCODE(G_STRICT_FADD) 645HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 646HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 647HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 648HANDLE_TARGET_OPCODE(G_STRICT_FREM) 649HANDLE_TARGET_OPCODE(G_STRICT_FMA) 650HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 651 652/// read_register intrinsic 653HANDLE_TARGET_OPCODE(G_READ_REGISTER) 654 655/// write_register intrinsic 656HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 657 658/// Marker for the end of the generic opcode. 659/// This is used to check if an opcode is in the range of the 660/// generic opcodes. 661HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_WRITE_REGISTER) 662 663/// BUILTIN_OP_END - This must be the last enum value in this list. 664/// The target-specific post-isel opcode values start here. 665HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 666