1 //===- PeepholeOptimizer.cpp - Peephole Optimizations ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Perform peephole optimizations on the machine code:
10 //
11 // - Optimize Extensions
12 //
13 // Optimization of sign / zero extension instructions. It may be extended to
14 // handle other instructions with similar properties.
15 //
16 // On some targets, some instructions, e.g. X86 sign / zero extension, may
17 // leave the source value in the lower part of the result. This optimization
18 // will replace some uses of the pre-extension value with uses of the
19 // sub-register of the results.
20 //
21 // - Optimize Comparisons
22 //
23 // Optimization of comparison instructions. For instance, in this code:
24 //
25 // sub r1, 1
26 // cmp r1, 0
27 // bz L1
28 //
29 // If the "sub" instruction all ready sets (or could be modified to set) the
30 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
31 // eliminate the "cmp" instruction.
32 //
33 // Another instance, in this code:
34 //
35 // sub r1, r3 | sub r1, imm
36 // cmp r3, r1 or cmp r1, r3 | cmp r1, imm
37 // bge L1
38 //
39 // If the branch instruction can use flag from "sub", then we can replace
40 // "sub" with "subs" and eliminate the "cmp" instruction.
41 //
42 // - Optimize Loads:
43 //
44 // Loads that can be folded into a later instruction. A load is foldable
45 // if it loads to virtual registers and the virtual register defined has
46 // a single use.
47 //
48 // - Optimize Copies and Bitcast (more generally, target specific copies):
49 //
50 // Rewrite copies and bitcasts to avoid cross register bank copies
51 // when possible.
52 // E.g., Consider the following example, where capital and lower
53 // letters denote different register file:
54 // b = copy A <-- cross-bank copy
55 // C = copy b <-- cross-bank copy
56 // =>
57 // b = copy A <-- cross-bank copy
58 // C = copy A <-- same-bank copy
59 //
60 // E.g., for bitcast:
61 // b = bitcast A <-- cross-bank copy
62 // C = bitcast b <-- cross-bank copy
63 // =>
64 // b = bitcast A <-- cross-bank copy
65 // C = copy A <-- same-bank copy
66 //===----------------------------------------------------------------------===//
67
68 #include "llvm/ADT/DenseMap.h"
69 #include "llvm/ADT/Optional.h"
70 #include "llvm/ADT/SmallPtrSet.h"
71 #include "llvm/ADT/SmallSet.h"
72 #include "llvm/ADT/SmallVector.h"
73 #include "llvm/ADT/Statistic.h"
74 #include "llvm/CodeGen/MachineBasicBlock.h"
75 #include "llvm/CodeGen/MachineDominators.h"
76 #include "llvm/CodeGen/MachineFunction.h"
77 #include "llvm/CodeGen/MachineFunctionPass.h"
78 #include "llvm/CodeGen/MachineInstr.h"
79 #include "llvm/CodeGen/MachineInstrBuilder.h"
80 #include "llvm/CodeGen/MachineLoopInfo.h"
81 #include "llvm/CodeGen/MachineOperand.h"
82 #include "llvm/CodeGen/MachineRegisterInfo.h"
83 #include "llvm/CodeGen/TargetInstrInfo.h"
84 #include "llvm/CodeGen/TargetOpcodes.h"
85 #include "llvm/CodeGen/TargetRegisterInfo.h"
86 #include "llvm/CodeGen/TargetSubtargetInfo.h"
87 #include "llvm/InitializePasses.h"
88 #include "llvm/MC/LaneBitmask.h"
89 #include "llvm/MC/MCInstrDesc.h"
90 #include "llvm/Pass.h"
91 #include "llvm/Support/CommandLine.h"
92 #include "llvm/Support/Debug.h"
93 #include "llvm/Support/ErrorHandling.h"
94 #include "llvm/Support/raw_ostream.h"
95 #include <cassert>
96 #include <cstdint>
97 #include <memory>
98 #include <utility>
99
100 using namespace llvm;
101 using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
102 using RegSubRegPairAndIdx = TargetInstrInfo::RegSubRegPairAndIdx;
103
104 #define DEBUG_TYPE "peephole-opt"
105
106 // Optimize Extensions
107 static cl::opt<bool>
108 Aggressive("aggressive-ext-opt", cl::Hidden,
109 cl::desc("Aggressive extension optimization"));
110
111 static cl::opt<bool>
112 DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
113 cl::desc("Disable the peephole optimizer"));
114
115 /// Specifiy whether or not the value tracking looks through
116 /// complex instructions. When this is true, the value tracker
117 /// bails on everything that is not a copy or a bitcast.
118 static cl::opt<bool>
119 DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
120 cl::desc("Disable advanced copy optimization"));
121
122 static cl::opt<bool> DisableNAPhysCopyOpt(
123 "disable-non-allocatable-phys-copy-opt", cl::Hidden, cl::init(false),
124 cl::desc("Disable non-allocatable physical register copy optimization"));
125
126 // Limit the number of PHI instructions to process
127 // in PeepholeOptimizer::getNextSource.
128 static cl::opt<unsigned> RewritePHILimit(
129 "rewrite-phi-limit", cl::Hidden, cl::init(10),
130 cl::desc("Limit the length of PHI chains to lookup"));
131
132 // Limit the length of recurrence chain when evaluating the benefit of
133 // commuting operands.
134 static cl::opt<unsigned> MaxRecurrenceChain(
135 "recurrence-chain-limit", cl::Hidden, cl::init(3),
136 cl::desc("Maximum length of recurrence chain when evaluating the benefit "
137 "of commuting operands"));
138
139
140 STATISTIC(NumReuse, "Number of extension results reused");
141 STATISTIC(NumCmps, "Number of compares eliminated");
142 STATISTIC(NumImmFold, "Number of move immediate folded");
143 STATISTIC(NumLoadFold, "Number of loads folded");
144 STATISTIC(NumSelects, "Number of selects optimized");
145 STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
146 STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
147 STATISTIC(NumNAPhysCopies, "Number of non-allocatable physical copies removed");
148
149 namespace {
150
151 class ValueTrackerResult;
152 class RecurrenceInstr;
153
154 class PeepholeOptimizer : public MachineFunctionPass {
155 const TargetInstrInfo *TII;
156 const TargetRegisterInfo *TRI;
157 MachineRegisterInfo *MRI;
158 MachineDominatorTree *DT; // Machine dominator tree
159 MachineLoopInfo *MLI;
160
161 public:
162 static char ID; // Pass identification
163
PeepholeOptimizer()164 PeepholeOptimizer() : MachineFunctionPass(ID) {
165 initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
166 }
167
168 bool runOnMachineFunction(MachineFunction &MF) override;
169
getAnalysisUsage(AnalysisUsage & AU) const170 void getAnalysisUsage(AnalysisUsage &AU) const override {
171 AU.setPreservesCFG();
172 MachineFunctionPass::getAnalysisUsage(AU);
173 AU.addRequired<MachineLoopInfo>();
174 AU.addPreserved<MachineLoopInfo>();
175 if (Aggressive) {
176 AU.addRequired<MachineDominatorTree>();
177 AU.addPreserved<MachineDominatorTree>();
178 }
179 }
180
181 /// Track Def -> Use info used for rewriting copies.
182 using RewriteMapTy = SmallDenseMap<RegSubRegPair, ValueTrackerResult>;
183
184 /// Sequence of instructions that formulate recurrence cycle.
185 using RecurrenceCycle = SmallVector<RecurrenceInstr, 4>;
186
187 private:
188 bool optimizeCmpInstr(MachineInstr &MI);
189 bool optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
190 SmallPtrSetImpl<MachineInstr*> &LocalMIs);
191 bool optimizeSelect(MachineInstr &MI,
192 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
193 bool optimizeCondBranch(MachineInstr &MI);
194 bool optimizeCoalescableCopy(MachineInstr &MI);
195 bool optimizeUncoalescableCopy(MachineInstr &MI,
196 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
197 bool optimizeRecurrence(MachineInstr &PHI);
198 bool findNextSource(RegSubRegPair RegSubReg, RewriteMapTy &RewriteMap);
199 bool isMoveImmediate(MachineInstr &MI,
200 SmallSet<unsigned, 4> &ImmDefRegs,
201 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
202 bool foldImmediate(MachineInstr &MI, SmallSet<unsigned, 4> &ImmDefRegs,
203 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
204
205 /// Finds recurrence cycles, but only ones that formulated around
206 /// a def operand and a use operand that are tied. If there is a use
207 /// operand commutable with the tied use operand, find recurrence cycle
208 /// along that operand as well.
209 bool findTargetRecurrence(unsigned Reg,
210 const SmallSet<unsigned, 2> &TargetReg,
211 RecurrenceCycle &RC);
212
213 /// If copy instruction \p MI is a virtual register copy, track it in
214 /// the set \p CopySrcRegs and \p CopyMIs. If this virtual register was
215 /// previously seen as a copy, replace the uses of this copy with the
216 /// previously seen copy's destination register.
217 bool foldRedundantCopy(MachineInstr &MI,
218 SmallSet<unsigned, 4> &CopySrcRegs,
219 DenseMap<unsigned, MachineInstr *> &CopyMIs);
220
221 /// Is the register \p Reg a non-allocatable physical register?
222 bool isNAPhysCopy(unsigned Reg);
223
224 /// If copy instruction \p MI is a non-allocatable virtual<->physical
225 /// register copy, track it in the \p NAPhysToVirtMIs map. If this
226 /// non-allocatable physical register was previously copied to a virtual
227 /// registered and hasn't been clobbered, the virt->phys copy can be
228 /// deleted.
229 bool foldRedundantNAPhysCopy(MachineInstr &MI,
230 DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs);
231
232 bool isLoadFoldable(MachineInstr &MI,
233 SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
234
235 /// Check whether \p MI is understood by the register coalescer
236 /// but may require some rewriting.
isCoalescableCopy(const MachineInstr & MI)237 bool isCoalescableCopy(const MachineInstr &MI) {
238 // SubregToRegs are not interesting, because they are already register
239 // coalescer friendly.
240 return MI.isCopy() || (!DisableAdvCopyOpt &&
241 (MI.isRegSequence() || MI.isInsertSubreg() ||
242 MI.isExtractSubreg()));
243 }
244
245 /// Check whether \p MI is a copy like instruction that is
246 /// not recognized by the register coalescer.
isUncoalescableCopy(const MachineInstr & MI)247 bool isUncoalescableCopy(const MachineInstr &MI) {
248 return MI.isBitcast() ||
249 (!DisableAdvCopyOpt &&
250 (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
251 MI.isExtractSubregLike()));
252 }
253
254 MachineInstr &rewriteSource(MachineInstr &CopyLike,
255 RegSubRegPair Def, RewriteMapTy &RewriteMap);
256 };
257
258 /// Helper class to hold instructions that are inside recurrence cycles.
259 /// The recurrence cycle is formulated around 1) a def operand and its
260 /// tied use operand, or 2) a def operand and a use operand that is commutable
261 /// with another use operand which is tied to the def operand. In the latter
262 /// case, index of the tied use operand and the commutable use operand are
263 /// maintained with CommutePair.
264 class RecurrenceInstr {
265 public:
266 using IndexPair = std::pair<unsigned, unsigned>;
267
RecurrenceInstr(MachineInstr * MI)268 RecurrenceInstr(MachineInstr *MI) : MI(MI) {}
RecurrenceInstr(MachineInstr * MI,unsigned Idx1,unsigned Idx2)269 RecurrenceInstr(MachineInstr *MI, unsigned Idx1, unsigned Idx2)
270 : MI(MI), CommutePair(std::make_pair(Idx1, Idx2)) {}
271
getMI() const272 MachineInstr *getMI() const { return MI; }
getCommutePair() const273 Optional<IndexPair> getCommutePair() const { return CommutePair; }
274
275 private:
276 MachineInstr *MI;
277 Optional<IndexPair> CommutePair;
278 };
279
280 /// Helper class to hold a reply for ValueTracker queries.
281 /// Contains the returned sources for a given search and the instructions
282 /// where the sources were tracked from.
283 class ValueTrackerResult {
284 private:
285 /// Track all sources found by one ValueTracker query.
286 SmallVector<RegSubRegPair, 2> RegSrcs;
287
288 /// Instruction using the sources in 'RegSrcs'.
289 const MachineInstr *Inst = nullptr;
290
291 public:
292 ValueTrackerResult() = default;
293
ValueTrackerResult(unsigned Reg,unsigned SubReg)294 ValueTrackerResult(unsigned Reg, unsigned SubReg) {
295 addSource(Reg, SubReg);
296 }
297
isValid() const298 bool isValid() const { return getNumSources() > 0; }
299
setInst(const MachineInstr * I)300 void setInst(const MachineInstr *I) { Inst = I; }
getInst() const301 const MachineInstr *getInst() const { return Inst; }
302
clear()303 void clear() {
304 RegSrcs.clear();
305 Inst = nullptr;
306 }
307
addSource(unsigned SrcReg,unsigned SrcSubReg)308 void addSource(unsigned SrcReg, unsigned SrcSubReg) {
309 RegSrcs.push_back(RegSubRegPair(SrcReg, SrcSubReg));
310 }
311
setSource(int Idx,unsigned SrcReg,unsigned SrcSubReg)312 void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) {
313 assert(Idx < getNumSources() && "Reg pair source out of index");
314 RegSrcs[Idx] = RegSubRegPair(SrcReg, SrcSubReg);
315 }
316
getNumSources() const317 int getNumSources() const { return RegSrcs.size(); }
318
getSrc(int Idx) const319 RegSubRegPair getSrc(int Idx) const {
320 return RegSrcs[Idx];
321 }
322
getSrcReg(int Idx) const323 unsigned getSrcReg(int Idx) const {
324 assert(Idx < getNumSources() && "Reg source out of index");
325 return RegSrcs[Idx].Reg;
326 }
327
getSrcSubReg(int Idx) const328 unsigned getSrcSubReg(int Idx) const {
329 assert(Idx < getNumSources() && "SubReg source out of index");
330 return RegSrcs[Idx].SubReg;
331 }
332
operator ==(const ValueTrackerResult & Other)333 bool operator==(const ValueTrackerResult &Other) {
334 if (Other.getInst() != getInst())
335 return false;
336
337 if (Other.getNumSources() != getNumSources())
338 return false;
339
340 for (int i = 0, e = Other.getNumSources(); i != e; ++i)
341 if (Other.getSrcReg(i) != getSrcReg(i) ||
342 Other.getSrcSubReg(i) != getSrcSubReg(i))
343 return false;
344 return true;
345 }
346 };
347
348 /// Helper class to track the possible sources of a value defined by
349 /// a (chain of) copy related instructions.
350 /// Given a definition (instruction and definition index), this class
351 /// follows the use-def chain to find successive suitable sources.
352 /// The given source can be used to rewrite the definition into
353 /// def = COPY src.
354 ///
355 /// For instance, let us consider the following snippet:
356 /// v0 =
357 /// v2 = INSERT_SUBREG v1, v0, sub0
358 /// def = COPY v2.sub0
359 ///
360 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
361 /// suitable sources:
362 /// v2.sub0 and v0.
363 /// Then, def can be rewritten into def = COPY v0.
364 class ValueTracker {
365 private:
366 /// The current point into the use-def chain.
367 const MachineInstr *Def = nullptr;
368
369 /// The index of the definition in Def.
370 unsigned DefIdx = 0;
371
372 /// The sub register index of the definition.
373 unsigned DefSubReg;
374
375 /// The register where the value can be found.
376 unsigned Reg;
377
378 /// MachineRegisterInfo used to perform tracking.
379 const MachineRegisterInfo &MRI;
380
381 /// Optional TargetInstrInfo used to perform some complex tracking.
382 const TargetInstrInfo *TII;
383
384 /// Dispatcher to the right underlying implementation of getNextSource.
385 ValueTrackerResult getNextSourceImpl();
386
387 /// Specialized version of getNextSource for Copy instructions.
388 ValueTrackerResult getNextSourceFromCopy();
389
390 /// Specialized version of getNextSource for Bitcast instructions.
391 ValueTrackerResult getNextSourceFromBitcast();
392
393 /// Specialized version of getNextSource for RegSequence instructions.
394 ValueTrackerResult getNextSourceFromRegSequence();
395
396 /// Specialized version of getNextSource for InsertSubreg instructions.
397 ValueTrackerResult getNextSourceFromInsertSubreg();
398
399 /// Specialized version of getNextSource for ExtractSubreg instructions.
400 ValueTrackerResult getNextSourceFromExtractSubreg();
401
402 /// Specialized version of getNextSource for SubregToReg instructions.
403 ValueTrackerResult getNextSourceFromSubregToReg();
404
405 /// Specialized version of getNextSource for PHI instructions.
406 ValueTrackerResult getNextSourceFromPHI();
407
408 public:
409 /// Create a ValueTracker instance for the value defined by \p Reg.
410 /// \p DefSubReg represents the sub register index the value tracker will
411 /// track. It does not need to match the sub register index used in the
412 /// definition of \p Reg.
413 /// If \p Reg is a physical register, a value tracker constructed with
414 /// this constructor will not find any alternative source.
415 /// Indeed, when \p Reg is a physical register that constructor does not
416 /// know which definition of \p Reg it should track.
417 /// Use the next constructor to track a physical register.
ValueTracker(unsigned Reg,unsigned DefSubReg,const MachineRegisterInfo & MRI,const TargetInstrInfo * TII=nullptr)418 ValueTracker(unsigned Reg, unsigned DefSubReg,
419 const MachineRegisterInfo &MRI,
420 const TargetInstrInfo *TII = nullptr)
421 : DefSubReg(DefSubReg), Reg(Reg), MRI(MRI), TII(TII) {
422 if (!Register::isPhysicalRegister(Reg)) {
423 Def = MRI.getVRegDef(Reg);
424 DefIdx = MRI.def_begin(Reg).getOperandNo();
425 }
426 }
427
428 /// Following the use-def chain, get the next available source
429 /// for the tracked value.
430 /// \return A ValueTrackerResult containing a set of registers
431 /// and sub registers with tracked values. A ValueTrackerResult with
432 /// an empty set of registers means no source was found.
433 ValueTrackerResult getNextSource();
434 };
435
436 } // end anonymous namespace
437
438 char PeepholeOptimizer::ID = 0;
439
440 char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
441
442 INITIALIZE_PASS_BEGIN(PeepholeOptimizer, DEBUG_TYPE,
443 "Peephole Optimizations", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)444 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
445 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
446 INITIALIZE_PASS_END(PeepholeOptimizer, DEBUG_TYPE,
447 "Peephole Optimizations", false, false)
448
449 /// If instruction is a copy-like instruction, i.e. it reads a single register
450 /// and writes a single register and it does not modify the source, and if the
451 /// source value is preserved as a sub-register of the result, then replace all
452 /// reachable uses of the source with the subreg of the result.
453 ///
454 /// Do not generate an EXTRACT that is used only in a debug use, as this changes
455 /// the code. Since this code does not currently share EXTRACTs, just ignore all
456 /// debug uses.
457 bool PeepholeOptimizer::
458 optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
459 SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
460 Register SrcReg, DstReg;
461 unsigned SubIdx;
462 if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx))
463 return false;
464
465 if (DstReg.isPhysical() || SrcReg.isPhysical())
466 return false;
467
468 if (MRI->hasOneNonDBGUse(SrcReg))
469 // No other uses.
470 return false;
471
472 // Ensure DstReg can get a register class that actually supports
473 // sub-registers. Don't change the class until we commit.
474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
475 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
476 if (!DstRC)
477 return false;
478
479 // The ext instr may be operating on a sub-register of SrcReg as well.
480 // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
481 // register.
482 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
483 // SrcReg:SubIdx should be replaced.
484 bool UseSrcSubIdx =
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
486
487 // The source has other uses. See if we can replace the other uses with use of
488 // the result of the extension.
489 SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
490 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
491 ReachedBBs.insert(UI.getParent());
492
493 // Uses that are in the same BB of uses of the result of the instruction.
494 SmallVector<MachineOperand*, 8> Uses;
495
496 // Uses that the result of the instruction can reach.
497 SmallVector<MachineOperand*, 8> ExtendedUses;
498
499 bool ExtendLife = true;
500 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
501 MachineInstr *UseMI = UseMO.getParent();
502 if (UseMI == &MI)
503 continue;
504
505 if (UseMI->isPHI()) {
506 ExtendLife = false;
507 continue;
508 }
509
510 // Only accept uses of SrcReg:SubIdx.
511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
512 continue;
513
514 // It's an error to translate this:
515 //
516 // %reg1025 = <sext> %reg1024
517 // ...
518 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
519 //
520 // into this:
521 //
522 // %reg1025 = <sext> %reg1024
523 // ...
524 // %reg1027 = COPY %reg1025:4
525 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
526 //
527 // The problem here is that SUBREG_TO_REG is there to assert that an
528 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
529 // the COPY here, it will give us the value after the <sext>, not the
530 // original value of %reg1024 before <sext>.
531 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
532 continue;
533
534 MachineBasicBlock *UseMBB = UseMI->getParent();
535 if (UseMBB == &MBB) {
536 // Local uses that come after the extension.
537 if (!LocalMIs.count(UseMI))
538 Uses.push_back(&UseMO);
539 } else if (ReachedBBs.count(UseMBB)) {
540 // Non-local uses where the result of the extension is used. Always
541 // replace these unless it's a PHI.
542 Uses.push_back(&UseMO);
543 } else if (Aggressive && DT->dominates(&MBB, UseMBB)) {
544 // We may want to extend the live range of the extension result in order
545 // to replace these uses.
546 ExtendedUses.push_back(&UseMO);
547 } else {
548 // Both will be live out of the def MBB anyway. Don't extend live range of
549 // the extension result.
550 ExtendLife = false;
551 break;
552 }
553 }
554
555 if (ExtendLife && !ExtendedUses.empty())
556 // Extend the liveness of the extension result.
557 Uses.append(ExtendedUses.begin(), ExtendedUses.end());
558
559 // Now replace all uses.
560 bool Changed = false;
561 if (!Uses.empty()) {
562 SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
563
564 // Look for PHI uses of the extended result, we don't want to extend the
565 // liveness of a PHI input. It breaks all kinds of assumptions down
566 // stream. A PHI use is expected to be the kill of its source values.
567 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
568 if (UI.isPHI())
569 PHIBBs.insert(UI.getParent());
570
571 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
572 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
573 MachineOperand *UseMO = Uses[i];
574 MachineInstr *UseMI = UseMO->getParent();
575 MachineBasicBlock *UseMBB = UseMI->getParent();
576 if (PHIBBs.count(UseMBB))
577 continue;
578
579 // About to add uses of DstReg, clear DstReg's kill flags.
580 if (!Changed) {
581 MRI->clearKillFlags(DstReg);
582 MRI->constrainRegClass(DstReg, DstRC);
583 }
584
585 Register NewVR = MRI->createVirtualRegister(RC);
586 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
587 TII->get(TargetOpcode::COPY), NewVR)
588 .addReg(DstReg, 0, SubIdx);
589 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
590 if (UseSrcSubIdx) {
591 Copy->getOperand(0).setSubReg(SubIdx);
592 Copy->getOperand(0).setIsUndef();
593 }
594 UseMO->setReg(NewVR);
595 ++NumReuse;
596 Changed = true;
597 }
598 }
599
600 return Changed;
601 }
602
603 /// If the instruction is a compare and the previous instruction it's comparing
604 /// against already sets (or could be modified to set) the same flag as the
605 /// compare, then we can remove the comparison and use the flag from the
606 /// previous instruction.
optimizeCmpInstr(MachineInstr & MI)607 bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr &MI) {
608 // If this instruction is a comparison against zero and isn't comparing a
609 // physical register, we can try to optimize it.
610 Register SrcReg, SrcReg2;
611 int CmpMask, CmpValue;
612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
613 SrcReg.isPhysical() || SrcReg2.isPhysical())
614 return false;
615
616 // Attempt to optimize the comparison instruction.
617 LLVM_DEBUG(dbgs() << "Attempting to optimize compare: " << MI);
618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
619 LLVM_DEBUG(dbgs() << " -> Successfully optimized compare!\n");
620 ++NumCmps;
621 return true;
622 }
623
624 return false;
625 }
626
627 /// Optimize a select instruction.
optimizeSelect(MachineInstr & MI,SmallPtrSetImpl<MachineInstr * > & LocalMIs)628 bool PeepholeOptimizer::optimizeSelect(MachineInstr &MI,
629 SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
630 unsigned TrueOp = 0;
631 unsigned FalseOp = 0;
632 bool Optimizable = false;
633 SmallVector<MachineOperand, 4> Cond;
634 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
635 return false;
636 if (!Optimizable)
637 return false;
638 if (!TII->optimizeSelect(MI, LocalMIs))
639 return false;
640 LLVM_DEBUG(dbgs() << "Deleting select: " << MI);
641 MI.eraseFromParent();
642 ++NumSelects;
643 return true;
644 }
645
646 /// Check if a simpler conditional branch can be generated.
optimizeCondBranch(MachineInstr & MI)647 bool PeepholeOptimizer::optimizeCondBranch(MachineInstr &MI) {
648 return TII->optimizeCondBranch(MI);
649 }
650
651 /// Try to find the next source that share the same register file
652 /// for the value defined by \p Reg and \p SubReg.
653 /// When true is returned, the \p RewriteMap can be used by the client to
654 /// retrieve all Def -> Use along the way up to the next source. Any found
655 /// Use that is not itself a key for another entry, is the next source to
656 /// use. During the search for the next source, multiple sources can be found
657 /// given multiple incoming sources of a PHI instruction. In this case, we
658 /// look in each PHI source for the next source; all found next sources must
659 /// share the same register file as \p Reg and \p SubReg. The client should
660 /// then be capable to rewrite all intermediate PHIs to get the next source.
661 /// \return False if no alternative sources are available. True otherwise.
findNextSource(RegSubRegPair RegSubReg,RewriteMapTy & RewriteMap)662 bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg,
663 RewriteMapTy &RewriteMap) {
664 // Do not try to find a new source for a physical register.
665 // So far we do not have any motivating example for doing that.
666 // Thus, instead of maintaining untested code, we will revisit that if
667 // that changes at some point.
668 Register Reg = RegSubReg.Reg;
669 if (Reg.isPhysical())
670 return false;
671 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
672
673 SmallVector<RegSubRegPair, 4> SrcToLook;
674 RegSubRegPair CurSrcPair = RegSubReg;
675 SrcToLook.push_back(CurSrcPair);
676
677 unsigned PHICount = 0;
678 do {
679 CurSrcPair = SrcToLook.pop_back_val();
680 // As explained above, do not handle physical registers
681 if (Register::isPhysicalRegister(CurSrcPair.Reg))
682 return false;
683
684 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII);
685
686 // Follow the chain of copies until we find a more suitable source, a phi
687 // or have to abort.
688 while (true) {
689 ValueTrackerResult Res = ValTracker.getNextSource();
690 // Abort at the end of a chain (without finding a suitable source).
691 if (!Res.isValid())
692 return false;
693
694 // Insert the Def -> Use entry for the recently found source.
695 ValueTrackerResult CurSrcRes = RewriteMap.lookup(CurSrcPair);
696 if (CurSrcRes.isValid()) {
697 assert(CurSrcRes == Res && "ValueTrackerResult found must match");
698 // An existent entry with multiple sources is a PHI cycle we must avoid.
699 // Otherwise it's an entry with a valid next source we already found.
700 if (CurSrcRes.getNumSources() > 1) {
701 LLVM_DEBUG(dbgs()
702 << "findNextSource: found PHI cycle, aborting...\n");
703 return false;
704 }
705 break;
706 }
707 RewriteMap.insert(std::make_pair(CurSrcPair, Res));
708
709 // ValueTrackerResult usually have one source unless it's the result from
710 // a PHI instruction. Add the found PHI edges to be looked up further.
711 unsigned NumSrcs = Res.getNumSources();
712 if (NumSrcs > 1) {
713 PHICount++;
714 if (PHICount >= RewritePHILimit) {
715 LLVM_DEBUG(dbgs() << "findNextSource: PHI limit reached\n");
716 return false;
717 }
718
719 for (unsigned i = 0; i < NumSrcs; ++i)
720 SrcToLook.push_back(Res.getSrc(i));
721 break;
722 }
723
724 CurSrcPair = Res.getSrc(0);
725 // Do not extend the live-ranges of physical registers as they add
726 // constraints to the register allocator. Moreover, if we want to extend
727 // the live-range of a physical register, unlike SSA virtual register,
728 // we will have to check that they aren't redefine before the related use.
729 if (Register::isPhysicalRegister(CurSrcPair.Reg))
730 return false;
731
732 // Keep following the chain if the value isn't any better yet.
733 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
734 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC,
735 CurSrcPair.SubReg))
736 continue;
737
738 // We currently cannot deal with subreg operands on PHI instructions
739 // (see insertPHI()).
740 if (PHICount > 0 && CurSrcPair.SubReg != 0)
741 continue;
742
743 // We found a suitable source, and are done with this chain.
744 break;
745 }
746 } while (!SrcToLook.empty());
747
748 // If we did not find a more suitable source, there is nothing to optimize.
749 return CurSrcPair.Reg != Reg;
750 }
751
752 /// Insert a PHI instruction with incoming edges \p SrcRegs that are
753 /// guaranteed to have the same register class. This is necessary whenever we
754 /// successfully traverse a PHI instruction and find suitable sources coming
755 /// from its edges. By inserting a new PHI, we provide a rewritten PHI def
756 /// suitable to be used in a new COPY instruction.
757 static MachineInstr &
insertPHI(MachineRegisterInfo & MRI,const TargetInstrInfo & TII,const SmallVectorImpl<RegSubRegPair> & SrcRegs,MachineInstr & OrigPHI)758 insertPHI(MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
759 const SmallVectorImpl<RegSubRegPair> &SrcRegs,
760 MachineInstr &OrigPHI) {
761 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?");
762
763 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg);
764 // NewRC is only correct if no subregisters are involved. findNextSource()
765 // should have rejected those cases already.
766 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand");
767 Register NewVR = MRI.createVirtualRegister(NewRC);
768 MachineBasicBlock *MBB = OrigPHI.getParent();
769 MachineInstrBuilder MIB = BuildMI(*MBB, &OrigPHI, OrigPHI.getDebugLoc(),
770 TII.get(TargetOpcode::PHI), NewVR);
771
772 unsigned MBBOpIdx = 2;
773 for (const RegSubRegPair &RegPair : SrcRegs) {
774 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
775 MIB.addMBB(OrigPHI.getOperand(MBBOpIdx).getMBB());
776 // Since we're extended the lifetime of RegPair.Reg, clear the
777 // kill flags to account for that and make RegPair.Reg reaches
778 // the new PHI.
779 MRI.clearKillFlags(RegPair.Reg);
780 MBBOpIdx += 2;
781 }
782
783 return *MIB;
784 }
785
786 namespace {
787
788 /// Interface to query instructions amenable to copy rewriting.
789 class Rewriter {
790 protected:
791 MachineInstr &CopyLike;
792 unsigned CurrentSrcIdx = 0; ///< The index of the source being rewritten.
793 public:
Rewriter(MachineInstr & CopyLike)794 Rewriter(MachineInstr &CopyLike) : CopyLike(CopyLike) {}
~Rewriter()795 virtual ~Rewriter() {}
796
797 /// Get the next rewritable source (SrcReg, SrcSubReg) and
798 /// the related value that it affects (DstReg, DstSubReg).
799 /// A source is considered rewritable if its register class and the
800 /// register class of the related DstReg may not be register
801 /// coalescer friendly. In other words, given a copy-like instruction
802 /// not all the arguments may be returned at rewritable source, since
803 /// some arguments are none to be register coalescer friendly.
804 ///
805 /// Each call of this method moves the current source to the next
806 /// rewritable source.
807 /// For instance, let CopyLike be the instruction to rewrite.
808 /// CopyLike has one definition and one source:
809 /// dst.dstSubIdx = CopyLike src.srcSubIdx.
810 ///
811 /// The first call will give the first rewritable source, i.e.,
812 /// the only source this instruction has:
813 /// (SrcReg, SrcSubReg) = (src, srcSubIdx).
814 /// This source defines the whole definition, i.e.,
815 /// (DstReg, DstSubReg) = (dst, dstSubIdx).
816 ///
817 /// The second and subsequent calls will return false, as there is only one
818 /// rewritable source.
819 ///
820 /// \return True if a rewritable source has been found, false otherwise.
821 /// The output arguments are valid if and only if true is returned.
822 virtual bool getNextRewritableSource(RegSubRegPair &Src,
823 RegSubRegPair &Dst) = 0;
824
825 /// Rewrite the current source with \p NewReg and \p NewSubReg if possible.
826 /// \return True if the rewriting was possible, false otherwise.
827 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) = 0;
828 };
829
830 /// Rewriter for COPY instructions.
831 class CopyRewriter : public Rewriter {
832 public:
CopyRewriter(MachineInstr & MI)833 CopyRewriter(MachineInstr &MI) : Rewriter(MI) {
834 assert(MI.isCopy() && "Expected copy instruction");
835 }
836 virtual ~CopyRewriter() = default;
837
getNextRewritableSource(RegSubRegPair & Src,RegSubRegPair & Dst)838 bool getNextRewritableSource(RegSubRegPair &Src,
839 RegSubRegPair &Dst) override {
840 // CurrentSrcIdx > 0 means this function has already been called.
841 if (CurrentSrcIdx > 0)
842 return false;
843 // This is the first call to getNextRewritableSource.
844 // Move the CurrentSrcIdx to remember that we made that call.
845 CurrentSrcIdx = 1;
846 // The rewritable source is the argument.
847 const MachineOperand &MOSrc = CopyLike.getOperand(1);
848 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg());
849 // What we track are the alternative sources of the definition.
850 const MachineOperand &MODef = CopyLike.getOperand(0);
851 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
852 return true;
853 }
854
RewriteCurrentSource(unsigned NewReg,unsigned NewSubReg)855 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
856 if (CurrentSrcIdx != 1)
857 return false;
858 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
859 MOSrc.setReg(NewReg);
860 MOSrc.setSubReg(NewSubReg);
861 return true;
862 }
863 };
864
865 /// Helper class to rewrite uncoalescable copy like instructions
866 /// into new COPY (coalescable friendly) instructions.
867 class UncoalescableRewriter : public Rewriter {
868 unsigned NumDefs; ///< Number of defs in the bitcast.
869
870 public:
UncoalescableRewriter(MachineInstr & MI)871 UncoalescableRewriter(MachineInstr &MI) : Rewriter(MI) {
872 NumDefs = MI.getDesc().getNumDefs();
873 }
874
875 /// \see See Rewriter::getNextRewritableSource()
876 /// All such sources need to be considered rewritable in order to
877 /// rewrite a uncoalescable copy-like instruction. This method return
878 /// each definition that must be checked if rewritable.
getNextRewritableSource(RegSubRegPair & Src,RegSubRegPair & Dst)879 bool getNextRewritableSource(RegSubRegPair &Src,
880 RegSubRegPair &Dst) override {
881 // Find the next non-dead definition and continue from there.
882 if (CurrentSrcIdx == NumDefs)
883 return false;
884
885 while (CopyLike.getOperand(CurrentSrcIdx).isDead()) {
886 ++CurrentSrcIdx;
887 if (CurrentSrcIdx == NumDefs)
888 return false;
889 }
890
891 // What we track are the alternative sources of the definition.
892 Src = RegSubRegPair(0, 0);
893 const MachineOperand &MODef = CopyLike.getOperand(CurrentSrcIdx);
894 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
895
896 CurrentSrcIdx++;
897 return true;
898 }
899
RewriteCurrentSource(unsigned NewReg,unsigned NewSubReg)900 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
901 return false;
902 }
903 };
904
905 /// Specialized rewriter for INSERT_SUBREG instruction.
906 class InsertSubregRewriter : public Rewriter {
907 public:
InsertSubregRewriter(MachineInstr & MI)908 InsertSubregRewriter(MachineInstr &MI) : Rewriter(MI) {
909 assert(MI.isInsertSubreg() && "Invalid instruction");
910 }
911
912 /// \see See Rewriter::getNextRewritableSource()
913 /// Here CopyLike has the following form:
914 /// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
915 /// Src1 has the same register class has dst, hence, there is
916 /// nothing to rewrite.
917 /// Src2.src2SubIdx, may not be register coalescer friendly.
918 /// Therefore, the first call to this method returns:
919 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
920 /// (DstReg, DstSubReg) = (dst, subIdx).
921 ///
922 /// Subsequence calls will return false.
getNextRewritableSource(RegSubRegPair & Src,RegSubRegPair & Dst)923 bool getNextRewritableSource(RegSubRegPair &Src,
924 RegSubRegPair &Dst) override {
925 // If we already get the only source we can rewrite, return false.
926 if (CurrentSrcIdx == 2)
927 return false;
928 // We are looking at v2 = INSERT_SUBREG v0, v1, sub0.
929 CurrentSrcIdx = 2;
930 const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
931 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg());
932 const MachineOperand &MODef = CopyLike.getOperand(0);
933
934 // We want to track something that is compatible with the
935 // partial definition.
936 if (MODef.getSubReg())
937 // Bail if we have to compose sub-register indices.
938 return false;
939 Dst = RegSubRegPair(MODef.getReg(),
940 (unsigned)CopyLike.getOperand(3).getImm());
941 return true;
942 }
943
RewriteCurrentSource(unsigned NewReg,unsigned NewSubReg)944 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
945 if (CurrentSrcIdx != 2)
946 return false;
947 // We are rewriting the inserted reg.
948 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
949 MO.setReg(NewReg);
950 MO.setSubReg(NewSubReg);
951 return true;
952 }
953 };
954
955 /// Specialized rewriter for EXTRACT_SUBREG instruction.
956 class ExtractSubregRewriter : public Rewriter {
957 const TargetInstrInfo &TII;
958
959 public:
ExtractSubregRewriter(MachineInstr & MI,const TargetInstrInfo & TII)960 ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
961 : Rewriter(MI), TII(TII) {
962 assert(MI.isExtractSubreg() && "Invalid instruction");
963 }
964
965 /// \see Rewriter::getNextRewritableSource()
966 /// Here CopyLike has the following form:
967 /// dst.dstSubIdx = EXTRACT_SUBREG Src, subIdx.
968 /// There is only one rewritable source: Src.subIdx,
969 /// which defines dst.dstSubIdx.
getNextRewritableSource(RegSubRegPair & Src,RegSubRegPair & Dst)970 bool getNextRewritableSource(RegSubRegPair &Src,
971 RegSubRegPair &Dst) override {
972 // If we already get the only source we can rewrite, return false.
973 if (CurrentSrcIdx == 1)
974 return false;
975 // We are looking at v1 = EXTRACT_SUBREG v0, sub0.
976 CurrentSrcIdx = 1;
977 const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
978 // If we have to compose sub-register indices, bail out.
979 if (MOExtractedReg.getSubReg())
980 return false;
981
982 Src = RegSubRegPair(MOExtractedReg.getReg(),
983 CopyLike.getOperand(2).getImm());
984
985 // We want to track something that is compatible with the definition.
986 const MachineOperand &MODef = CopyLike.getOperand(0);
987 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
988 return true;
989 }
990
RewriteCurrentSource(unsigned NewReg,unsigned NewSubReg)991 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
992 // The only source we can rewrite is the input register.
993 if (CurrentSrcIdx != 1)
994 return false;
995
996 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
997
998 // If we find a source that does not require to extract something,
999 // rewrite the operation with a copy.
1000 if (!NewSubReg) {
1001 // Move the current index to an invalid position.
1002 // We do not want another call to this method to be able
1003 // to do any change.
1004 CurrentSrcIdx = -1;
1005 // Rewrite the operation as a COPY.
1006 // Get rid of the sub-register index.
1007 CopyLike.RemoveOperand(2);
1008 // Morph the operation into a COPY.
1009 CopyLike.setDesc(TII.get(TargetOpcode::COPY));
1010 return true;
1011 }
1012 CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
1013 return true;
1014 }
1015 };
1016
1017 /// Specialized rewriter for REG_SEQUENCE instruction.
1018 class RegSequenceRewriter : public Rewriter {
1019 public:
RegSequenceRewriter(MachineInstr & MI)1020 RegSequenceRewriter(MachineInstr &MI) : Rewriter(MI) {
1021 assert(MI.isRegSequence() && "Invalid instruction");
1022 }
1023
1024 /// \see Rewriter::getNextRewritableSource()
1025 /// Here CopyLike has the following form:
1026 /// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
1027 /// Each call will return a different source, walking all the available
1028 /// source.
1029 ///
1030 /// The first call returns:
1031 /// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
1032 /// (DstReg, DstSubReg) = (dst, subIdx1).
1033 ///
1034 /// The second call returns:
1035 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
1036 /// (DstReg, DstSubReg) = (dst, subIdx2).
1037 ///
1038 /// And so on, until all the sources have been traversed, then
1039 /// it returns false.
getNextRewritableSource(RegSubRegPair & Src,RegSubRegPair & Dst)1040 bool getNextRewritableSource(RegSubRegPair &Src,
1041 RegSubRegPair &Dst) override {
1042 // We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
1043
1044 // If this is the first call, move to the first argument.
1045 if (CurrentSrcIdx == 0) {
1046 CurrentSrcIdx = 1;
1047 } else {
1048 // Otherwise, move to the next argument and check that it is valid.
1049 CurrentSrcIdx += 2;
1050 if (CurrentSrcIdx >= CopyLike.getNumOperands())
1051 return false;
1052 }
1053 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
1054 Src.Reg = MOInsertedReg.getReg();
1055 // If we have to compose sub-register indices, bail out.
1056 if ((Src.SubReg = MOInsertedReg.getSubReg()))
1057 return false;
1058
1059 // We want to track something that is compatible with the related
1060 // partial definition.
1061 Dst.SubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
1062
1063 const MachineOperand &MODef = CopyLike.getOperand(0);
1064 Dst.Reg = MODef.getReg();
1065 // If we have to compose sub-registers, bail.
1066 return MODef.getSubReg() == 0;
1067 }
1068
RewriteCurrentSource(unsigned NewReg,unsigned NewSubReg)1069 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1070 // We cannot rewrite out of bound operands.
1071 // Moreover, rewritable sources are at odd positions.
1072 if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
1073 return false;
1074
1075 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1076 MO.setReg(NewReg);
1077 MO.setSubReg(NewSubReg);
1078 return true;
1079 }
1080 };
1081
1082 } // end anonymous namespace
1083
1084 /// Get the appropriated Rewriter for \p MI.
1085 /// \return A pointer to a dynamically allocated Rewriter or nullptr if no
1086 /// rewriter works for \p MI.
getCopyRewriter(MachineInstr & MI,const TargetInstrInfo & TII)1087 static Rewriter *getCopyRewriter(MachineInstr &MI, const TargetInstrInfo &TII) {
1088 // Handle uncoalescable copy-like instructions.
1089 if (MI.isBitcast() || MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
1090 MI.isExtractSubregLike())
1091 return new UncoalescableRewriter(MI);
1092
1093 switch (MI.getOpcode()) {
1094 default:
1095 return nullptr;
1096 case TargetOpcode::COPY:
1097 return new CopyRewriter(MI);
1098 case TargetOpcode::INSERT_SUBREG:
1099 return new InsertSubregRewriter(MI);
1100 case TargetOpcode::EXTRACT_SUBREG:
1101 return new ExtractSubregRewriter(MI, TII);
1102 case TargetOpcode::REG_SEQUENCE:
1103 return new RegSequenceRewriter(MI);
1104 }
1105 }
1106
1107 /// Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
1108 /// the new source to use for rewrite. If \p HandleMultipleSources is true and
1109 /// multiple sources for a given \p Def are found along the way, we found a
1110 /// PHI instructions that needs to be rewritten.
1111 /// TODO: HandleMultipleSources should be removed once we test PHI handling
1112 /// with coalescable copies.
1113 static RegSubRegPair
getNewSource(MachineRegisterInfo * MRI,const TargetInstrInfo * TII,RegSubRegPair Def,const PeepholeOptimizer::RewriteMapTy & RewriteMap,bool HandleMultipleSources=true)1114 getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
1115 RegSubRegPair Def,
1116 const PeepholeOptimizer::RewriteMapTy &RewriteMap,
1117 bool HandleMultipleSources = true) {
1118 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
1119 while (true) {
1120 ValueTrackerResult Res = RewriteMap.lookup(LookupSrc);
1121 // If there are no entries on the map, LookupSrc is the new source.
1122 if (!Res.isValid())
1123 return LookupSrc;
1124
1125 // There's only one source for this definition, keep searching...
1126 unsigned NumSrcs = Res.getNumSources();
1127 if (NumSrcs == 1) {
1128 LookupSrc.Reg = Res.getSrcReg(0);
1129 LookupSrc.SubReg = Res.getSrcSubReg(0);
1130 continue;
1131 }
1132
1133 // TODO: Remove once multiple srcs w/ coalescable copies are supported.
1134 if (!HandleMultipleSources)
1135 break;
1136
1137 // Multiple sources, recurse into each source to find a new source
1138 // for it. Then, rewrite the PHI accordingly to its new edges.
1139 SmallVector<RegSubRegPair, 4> NewPHISrcs;
1140 for (unsigned i = 0; i < NumSrcs; ++i) {
1141 RegSubRegPair PHISrc(Res.getSrcReg(i), Res.getSrcSubReg(i));
1142 NewPHISrcs.push_back(
1143 getNewSource(MRI, TII, PHISrc, RewriteMap, HandleMultipleSources));
1144 }
1145
1146 // Build the new PHI node and return its def register as the new source.
1147 MachineInstr &OrigPHI = const_cast<MachineInstr &>(*Res.getInst());
1148 MachineInstr &NewPHI = insertPHI(*MRI, *TII, NewPHISrcs, OrigPHI);
1149 LLVM_DEBUG(dbgs() << "-- getNewSource\n");
1150 LLVM_DEBUG(dbgs() << " Replacing: " << OrigPHI);
1151 LLVM_DEBUG(dbgs() << " With: " << NewPHI);
1152 const MachineOperand &MODef = NewPHI.getOperand(0);
1153 return RegSubRegPair(MODef.getReg(), MODef.getSubReg());
1154 }
1155
1156 return RegSubRegPair(0, 0);
1157 }
1158
1159 /// Optimize generic copy instructions to avoid cross register bank copy.
1160 /// The optimization looks through a chain of copies and tries to find a source
1161 /// that has a compatible register class.
1162 /// Two register classes are considered to be compatible if they share the same
1163 /// register bank.
1164 /// New copies issued by this optimization are register allocator
1165 /// friendly. This optimization does not remove any copy as it may
1166 /// overconstrain the register allocator, but replaces some operands
1167 /// when possible.
1168 /// \pre isCoalescableCopy(*MI) is true.
1169 /// \return True, when \p MI has been rewritten. False otherwise.
optimizeCoalescableCopy(MachineInstr & MI)1170 bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr &MI) {
1171 assert(isCoalescableCopy(MI) && "Invalid argument");
1172 assert(MI.getDesc().getNumDefs() == 1 &&
1173 "Coalescer can understand multiple defs?!");
1174 const MachineOperand &MODef = MI.getOperand(0);
1175 // Do not rewrite physical definitions.
1176 if (Register::isPhysicalRegister(MODef.getReg()))
1177 return false;
1178
1179 bool Changed = false;
1180 // Get the right rewriter for the current copy.
1181 std::unique_ptr<Rewriter> CpyRewriter(getCopyRewriter(MI, *TII));
1182 // If none exists, bail out.
1183 if (!CpyRewriter)
1184 return false;
1185 // Rewrite each rewritable source.
1186 RegSubRegPair Src;
1187 RegSubRegPair TrackPair;
1188 while (CpyRewriter->getNextRewritableSource(Src, TrackPair)) {
1189 // Keep track of PHI nodes and its incoming edges when looking for sources.
1190 RewriteMapTy RewriteMap;
1191 // Try to find a more suitable source. If we failed to do so, or get the
1192 // actual source, move to the next source.
1193 if (!findNextSource(TrackPair, RewriteMap))
1194 continue;
1195
1196 // Get the new source to rewrite. TODO: Only enable handling of multiple
1197 // sources (PHIs) once we have a motivating example and testcases for it.
1198 RegSubRegPair NewSrc = getNewSource(MRI, TII, TrackPair, RewriteMap,
1199 /*HandleMultipleSources=*/false);
1200 if (Src.Reg == NewSrc.Reg || NewSrc.Reg == 0)
1201 continue;
1202
1203 // Rewrite source.
1204 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) {
1205 // We may have extended the live-range of NewSrc, account for that.
1206 MRI->clearKillFlags(NewSrc.Reg);
1207 Changed = true;
1208 }
1209 }
1210 // TODO: We could have a clean-up method to tidy the instruction.
1211 // E.g., v0 = INSERT_SUBREG v1, v1.sub0, sub0
1212 // => v0 = COPY v1
1213 // Currently we haven't seen motivating example for that and we
1214 // want to avoid untested code.
1215 NumRewrittenCopies += Changed;
1216 return Changed;
1217 }
1218
1219 /// Rewrite the source found through \p Def, by using the \p RewriteMap
1220 /// and create a new COPY instruction. More info about RewriteMap in
1221 /// PeepholeOptimizer::findNextSource. Right now this is only used to handle
1222 /// Uncoalescable copies, since they are copy like instructions that aren't
1223 /// recognized by the register allocator.
1224 MachineInstr &
rewriteSource(MachineInstr & CopyLike,RegSubRegPair Def,RewriteMapTy & RewriteMap)1225 PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike,
1226 RegSubRegPair Def, RewriteMapTy &RewriteMap) {
1227 assert(!Register::isPhysicalRegister(Def.Reg) &&
1228 "We do not rewrite physical registers");
1229
1230 // Find the new source to use in the COPY rewrite.
1231 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap);
1232
1233 // Insert the COPY.
1234 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
1235 Register NewVReg = MRI->createVirtualRegister(DefRC);
1236
1237 MachineInstr *NewCopy =
1238 BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
1239 TII->get(TargetOpcode::COPY), NewVReg)
1240 .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
1241
1242 if (Def.SubReg) {
1243 NewCopy->getOperand(0).setSubReg(Def.SubReg);
1244 NewCopy->getOperand(0).setIsUndef();
1245 }
1246
1247 LLVM_DEBUG(dbgs() << "-- RewriteSource\n");
1248 LLVM_DEBUG(dbgs() << " Replacing: " << CopyLike);
1249 LLVM_DEBUG(dbgs() << " With: " << *NewCopy);
1250 MRI->replaceRegWith(Def.Reg, NewVReg);
1251 MRI->clearKillFlags(NewVReg);
1252
1253 // We extended the lifetime of NewSrc.Reg, clear the kill flags to
1254 // account for that.
1255 MRI->clearKillFlags(NewSrc.Reg);
1256
1257 return *NewCopy;
1258 }
1259
1260 /// Optimize copy-like instructions to create
1261 /// register coalescer friendly instruction.
1262 /// The optimization tries to kill-off the \p MI by looking
1263 /// through a chain of copies to find a source that has a compatible
1264 /// register class.
1265 /// If such a source is found, it replace \p MI by a generic COPY
1266 /// operation.
1267 /// \pre isUncoalescableCopy(*MI) is true.
1268 /// \return True, when \p MI has been optimized. In that case, \p MI has
1269 /// been removed from its parent.
1270 /// All COPY instructions created, are inserted in \p LocalMIs.
optimizeUncoalescableCopy(MachineInstr & MI,SmallPtrSetImpl<MachineInstr * > & LocalMIs)1271 bool PeepholeOptimizer::optimizeUncoalescableCopy(
1272 MachineInstr &MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
1273 assert(isUncoalescableCopy(MI) && "Invalid argument");
1274 UncoalescableRewriter CpyRewriter(MI);
1275
1276 // Rewrite each rewritable source by generating new COPYs. This works
1277 // differently from optimizeCoalescableCopy since it first makes sure that all
1278 // definitions can be rewritten.
1279 RewriteMapTy RewriteMap;
1280 RegSubRegPair Src;
1281 RegSubRegPair Def;
1282 SmallVector<RegSubRegPair, 4> RewritePairs;
1283 while (CpyRewriter.getNextRewritableSource(Src, Def)) {
1284 // If a physical register is here, this is probably for a good reason.
1285 // Do not rewrite that.
1286 if (Register::isPhysicalRegister(Def.Reg))
1287 return false;
1288
1289 // If we do not know how to rewrite this definition, there is no point
1290 // in trying to kill this instruction.
1291 if (!findNextSource(Def, RewriteMap))
1292 return false;
1293
1294 RewritePairs.push_back(Def);
1295 }
1296
1297 // The change is possible for all defs, do it.
1298 for (const RegSubRegPair &Def : RewritePairs) {
1299 // Rewrite the "copy" in a way the register coalescer understands.
1300 MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap);
1301 LocalMIs.insert(&NewCopy);
1302 }
1303
1304 // MI is now dead.
1305 LLVM_DEBUG(dbgs() << "Deleting uncoalescable copy: " << MI);
1306 MI.eraseFromParent();
1307 ++NumUncoalescableCopies;
1308 return true;
1309 }
1310
1311 /// Check whether MI is a candidate for folding into a later instruction.
1312 /// We only fold loads to virtual registers and the virtual register defined
1313 /// has a single user.
isLoadFoldable(MachineInstr & MI,SmallSet<unsigned,16> & FoldAsLoadDefCandidates)1314 bool PeepholeOptimizer::isLoadFoldable(
1315 MachineInstr &MI, SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
1316 if (!MI.canFoldAsLoad() || !MI.mayLoad())
1317 return false;
1318 const MCInstrDesc &MCID = MI.getDesc();
1319 if (MCID.getNumDefs() != 1)
1320 return false;
1321
1322 Register Reg = MI.getOperand(0).getReg();
1323 // To reduce compilation time, we check MRI->hasOneNonDBGUser when inserting
1324 // loads. It should be checked when processing uses of the load, since
1325 // uses can be removed during peephole.
1326 if (!MI.getOperand(0).getSubReg() && Register::isVirtualRegister(Reg) &&
1327 MRI->hasOneNonDBGUser(Reg)) {
1328 FoldAsLoadDefCandidates.insert(Reg);
1329 return true;
1330 }
1331 return false;
1332 }
1333
isMoveImmediate(MachineInstr & MI,SmallSet<unsigned,4> & ImmDefRegs,DenseMap<unsigned,MachineInstr * > & ImmDefMIs)1334 bool PeepholeOptimizer::isMoveImmediate(
1335 MachineInstr &MI, SmallSet<unsigned, 4> &ImmDefRegs,
1336 DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
1337 const MCInstrDesc &MCID = MI.getDesc();
1338 if (!MI.isMoveImmediate())
1339 return false;
1340 if (MCID.getNumDefs() != 1)
1341 return false;
1342 Register Reg = MI.getOperand(0).getReg();
1343 if (Register::isVirtualRegister(Reg)) {
1344 ImmDefMIs.insert(std::make_pair(Reg, &MI));
1345 ImmDefRegs.insert(Reg);
1346 return true;
1347 }
1348
1349 return false;
1350 }
1351
1352 /// Try folding register operands that are defined by move immediate
1353 /// instructions, i.e. a trivial constant folding optimization, if
1354 /// and only if the def and use are in the same BB.
foldImmediate(MachineInstr & MI,SmallSet<unsigned,4> & ImmDefRegs,DenseMap<unsigned,MachineInstr * > & ImmDefMIs)1355 bool PeepholeOptimizer::foldImmediate(MachineInstr &MI,
1356 SmallSet<unsigned, 4> &ImmDefRegs,
1357 DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
1358 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1359 MachineOperand &MO = MI.getOperand(i);
1360 if (!MO.isReg() || MO.isDef())
1361 continue;
1362 // Ignore dead implicit defs.
1363 if (MO.isImplicit() && MO.isDead())
1364 continue;
1365 Register Reg = MO.getReg();
1366 if (!Register::isVirtualRegister(Reg))
1367 continue;
1368 if (ImmDefRegs.count(Reg) == 0)
1369 continue;
1370 DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
1371 assert(II != ImmDefMIs.end() && "couldn't find immediate definition");
1372 if (TII->FoldImmediate(MI, *II->second, Reg, MRI)) {
1373 ++NumImmFold;
1374 return true;
1375 }
1376 }
1377 return false;
1378 }
1379
1380 // FIXME: This is very simple and misses some cases which should be handled when
1381 // motivating examples are found.
1382 //
1383 // The copy rewriting logic should look at uses as well as defs and be able to
1384 // eliminate copies across blocks.
1385 //
1386 // Later copies that are subregister extracts will also not be eliminated since
1387 // only the first copy is considered.
1388 //
1389 // e.g.
1390 // %1 = COPY %0
1391 // %2 = COPY %0:sub1
1392 //
1393 // Should replace %2 uses with %1:sub1
foldRedundantCopy(MachineInstr & MI,SmallSet<unsigned,4> & CopySrcRegs,DenseMap<unsigned,MachineInstr * > & CopyMIs)1394 bool PeepholeOptimizer::foldRedundantCopy(MachineInstr &MI,
1395 SmallSet<unsigned, 4> &CopySrcRegs,
1396 DenseMap<unsigned, MachineInstr *> &CopyMIs) {
1397 assert(MI.isCopy() && "expected a COPY machine instruction");
1398
1399 Register SrcReg = MI.getOperand(1).getReg();
1400 if (!Register::isVirtualRegister(SrcReg))
1401 return false;
1402
1403 Register DstReg = MI.getOperand(0).getReg();
1404 if (!Register::isVirtualRegister(DstReg))
1405 return false;
1406
1407 if (CopySrcRegs.insert(SrcReg).second) {
1408 // First copy of this reg seen.
1409 CopyMIs.insert(std::make_pair(SrcReg, &MI));
1410 return false;
1411 }
1412
1413 MachineInstr *PrevCopy = CopyMIs.find(SrcReg)->second;
1414
1415 unsigned SrcSubReg = MI.getOperand(1).getSubReg();
1416 unsigned PrevSrcSubReg = PrevCopy->getOperand(1).getSubReg();
1417
1418 // Can't replace different subregister extracts.
1419 if (SrcSubReg != PrevSrcSubReg)
1420 return false;
1421
1422 Register PrevDstReg = PrevCopy->getOperand(0).getReg();
1423
1424 // Only replace if the copy register class is the same.
1425 //
1426 // TODO: If we have multiple copies to different register classes, we may want
1427 // to track multiple copies of the same source register.
1428 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg))
1429 return false;
1430
1431 MRI->replaceRegWith(DstReg, PrevDstReg);
1432
1433 // Lifetime of the previous copy has been extended.
1434 MRI->clearKillFlags(PrevDstReg);
1435 return true;
1436 }
1437
isNAPhysCopy(unsigned Reg)1438 bool PeepholeOptimizer::isNAPhysCopy(unsigned Reg) {
1439 return Register::isPhysicalRegister(Reg) && !MRI->isAllocatable(Reg);
1440 }
1441
foldRedundantNAPhysCopy(MachineInstr & MI,DenseMap<unsigned,MachineInstr * > & NAPhysToVirtMIs)1442 bool PeepholeOptimizer::foldRedundantNAPhysCopy(
1443 MachineInstr &MI, DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs) {
1444 assert(MI.isCopy() && "expected a COPY machine instruction");
1445
1446 if (DisableNAPhysCopyOpt)
1447 return false;
1448
1449 Register DstReg = MI.getOperand(0).getReg();
1450 Register SrcReg = MI.getOperand(1).getReg();
1451 if (isNAPhysCopy(SrcReg) && Register::isVirtualRegister(DstReg)) {
1452 // %vreg = COPY %physreg
1453 // Avoid using a datastructure which can track multiple live non-allocatable
1454 // phys->virt copies since LLVM doesn't seem to do this.
1455 NAPhysToVirtMIs.insert({SrcReg, &MI});
1456 return false;
1457 }
1458
1459 if (!(Register::isVirtualRegister(SrcReg) && isNAPhysCopy(DstReg)))
1460 return false;
1461
1462 // %physreg = COPY %vreg
1463 auto PrevCopy = NAPhysToVirtMIs.find(DstReg);
1464 if (PrevCopy == NAPhysToVirtMIs.end()) {
1465 // We can't remove the copy: there was an intervening clobber of the
1466 // non-allocatable physical register after the copy to virtual.
1467 LLVM_DEBUG(dbgs() << "NAPhysCopy: intervening clobber forbids erasing "
1468 << MI);
1469 return false;
1470 }
1471
1472 Register PrevDstReg = PrevCopy->second->getOperand(0).getReg();
1473 if (PrevDstReg == SrcReg) {
1474 // Remove the virt->phys copy: we saw the virtual register definition, and
1475 // the non-allocatable physical register's state hasn't changed since then.
1476 LLVM_DEBUG(dbgs() << "NAPhysCopy: erasing " << MI);
1477 ++NumNAPhysCopies;
1478 return true;
1479 }
1480
1481 // Potential missed optimization opportunity: we saw a different virtual
1482 // register get a copy of the non-allocatable physical register, and we only
1483 // track one such copy. Avoid getting confused by this new non-allocatable
1484 // physical register definition, and remove it from the tracked copies.
1485 LLVM_DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << MI);
1486 NAPhysToVirtMIs.erase(PrevCopy);
1487 return false;
1488 }
1489
1490 /// \bried Returns true if \p MO is a virtual register operand.
isVirtualRegisterOperand(MachineOperand & MO)1491 static bool isVirtualRegisterOperand(MachineOperand &MO) {
1492 if (!MO.isReg())
1493 return false;
1494 return Register::isVirtualRegister(MO.getReg());
1495 }
1496
findTargetRecurrence(unsigned Reg,const SmallSet<unsigned,2> & TargetRegs,RecurrenceCycle & RC)1497 bool PeepholeOptimizer::findTargetRecurrence(
1498 unsigned Reg, const SmallSet<unsigned, 2> &TargetRegs,
1499 RecurrenceCycle &RC) {
1500 // Recurrence found if Reg is in TargetRegs.
1501 if (TargetRegs.count(Reg))
1502 return true;
1503
1504 // TODO: Curerntly, we only allow the last instruction of the recurrence
1505 // cycle (the instruction that feeds the PHI instruction) to have more than
1506 // one uses to guarantee that commuting operands does not tie registers
1507 // with overlapping live range. Once we have actual live range info of
1508 // each register, this constraint can be relaxed.
1509 if (!MRI->hasOneNonDBGUse(Reg))
1510 return false;
1511
1512 // Give up if the reccurrence chain length is longer than the limit.
1513 if (RC.size() >= MaxRecurrenceChain)
1514 return false;
1515
1516 MachineInstr &MI = *(MRI->use_instr_nodbg_begin(Reg));
1517 unsigned Idx = MI.findRegisterUseOperandIdx(Reg);
1518
1519 // Only interested in recurrences whose instructions have only one def, which
1520 // is a virtual register.
1521 if (MI.getDesc().getNumDefs() != 1)
1522 return false;
1523
1524 MachineOperand &DefOp = MI.getOperand(0);
1525 if (!isVirtualRegisterOperand(DefOp))
1526 return false;
1527
1528 // Check if def operand of MI is tied to any use operand. We are only
1529 // interested in the case that all the instructions in the recurrence chain
1530 // have there def operand tied with one of the use operand.
1531 unsigned TiedUseIdx;
1532 if (!MI.isRegTiedToUseOperand(0, &TiedUseIdx))
1533 return false;
1534
1535 if (Idx == TiedUseIdx) {
1536 RC.push_back(RecurrenceInstr(&MI));
1537 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC);
1538 } else {
1539 // If Idx is not TiedUseIdx, check if Idx is commutable with TiedUseIdx.
1540 unsigned CommIdx = TargetInstrInfo::CommuteAnyOperandIndex;
1541 if (TII->findCommutedOpIndices(MI, Idx, CommIdx) && CommIdx == TiedUseIdx) {
1542 RC.push_back(RecurrenceInstr(&MI, Idx, CommIdx));
1543 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC);
1544 }
1545 }
1546
1547 return false;
1548 }
1549
1550 /// Phi instructions will eventually be lowered to copy instructions.
1551 /// If phi is in a loop header, a recurrence may formulated around the source
1552 /// and destination of the phi. For such case commuting operands of the
1553 /// instructions in the recurrence may enable coalescing of the copy instruction
1554 /// generated from the phi. For example, if there is a recurrence of
1555 ///
1556 /// LoopHeader:
1557 /// %1 = phi(%0, %100)
1558 /// LoopLatch:
1559 /// %0<def, tied1> = ADD %2<def, tied0>, %1
1560 ///
1561 /// , the fact that %0 and %2 are in the same tied operands set makes
1562 /// the coalescing of copy instruction generated from the phi in
1563 /// LoopHeader(i.e. %1 = COPY %0) impossible, because %1 and
1564 /// %2 have overlapping live range. This introduces additional move
1565 /// instruction to the final assembly. However, if we commute %2 and
1566 /// %1 of ADD instruction, the redundant move instruction can be
1567 /// avoided.
optimizeRecurrence(MachineInstr & PHI)1568 bool PeepholeOptimizer::optimizeRecurrence(MachineInstr &PHI) {
1569 SmallSet<unsigned, 2> TargetRegs;
1570 for (unsigned Idx = 1; Idx < PHI.getNumOperands(); Idx += 2) {
1571 MachineOperand &MO = PHI.getOperand(Idx);
1572 assert(isVirtualRegisterOperand(MO) && "Invalid PHI instruction");
1573 TargetRegs.insert(MO.getReg());
1574 }
1575
1576 bool Changed = false;
1577 RecurrenceCycle RC;
1578 if (findTargetRecurrence(PHI.getOperand(0).getReg(), TargetRegs, RC)) {
1579 // Commutes operands of instructions in RC if necessary so that the copy to
1580 // be generated from PHI can be coalesced.
1581 LLVM_DEBUG(dbgs() << "Optimize recurrence chain from " << PHI);
1582 for (auto &RI : RC) {
1583 LLVM_DEBUG(dbgs() << "\tInst: " << *(RI.getMI()));
1584 auto CP = RI.getCommutePair();
1585 if (CP) {
1586 Changed = true;
1587 TII->commuteInstruction(*(RI.getMI()), false, (*CP).first,
1588 (*CP).second);
1589 LLVM_DEBUG(dbgs() << "\t\tCommuted: " << *(RI.getMI()));
1590 }
1591 }
1592 }
1593
1594 return Changed;
1595 }
1596
runOnMachineFunction(MachineFunction & MF)1597 bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
1598 if (skipFunction(MF.getFunction()))
1599 return false;
1600
1601 LLVM_DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
1602 LLVM_DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
1603
1604 if (DisablePeephole)
1605 return false;
1606
1607 TII = MF.getSubtarget().getInstrInfo();
1608 TRI = MF.getSubtarget().getRegisterInfo();
1609 MRI = &MF.getRegInfo();
1610 DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
1611 MLI = &getAnalysis<MachineLoopInfo>();
1612
1613 bool Changed = false;
1614
1615 for (MachineBasicBlock &MBB : MF) {
1616 bool SeenMoveImm = false;
1617
1618 // During this forward scan, at some point it needs to answer the question
1619 // "given a pointer to an MI in the current BB, is it located before or
1620 // after the current instruction".
1621 // To perform this, the following set keeps track of the MIs already seen
1622 // during the scan, if a MI is not in the set, it is assumed to be located
1623 // after. Newly created MIs have to be inserted in the set as well.
1624 SmallPtrSet<MachineInstr*, 16> LocalMIs;
1625 SmallSet<unsigned, 4> ImmDefRegs;
1626 DenseMap<unsigned, MachineInstr*> ImmDefMIs;
1627 SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
1628
1629 // Track when a non-allocatable physical register is copied to a virtual
1630 // register so that useless moves can be removed.
1631 //
1632 // %physreg is the map index; MI is the last valid `%vreg = COPY %physreg`
1633 // without any intervening re-definition of %physreg.
1634 DenseMap<unsigned, MachineInstr *> NAPhysToVirtMIs;
1635
1636 // Set of virtual registers that are copied from.
1637 SmallSet<unsigned, 4> CopySrcRegs;
1638 DenseMap<unsigned, MachineInstr *> CopySrcMIs;
1639
1640 bool IsLoopHeader = MLI->isLoopHeader(&MBB);
1641
1642 for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
1643 MII != MIE; ) {
1644 MachineInstr *MI = &*MII;
1645 // We may be erasing MI below, increment MII now.
1646 ++MII;
1647 LocalMIs.insert(MI);
1648
1649 // Skip debug instructions. They should not affect this peephole optimization.
1650 if (MI->isDebugInstr())
1651 continue;
1652
1653 if (MI->isPosition())
1654 continue;
1655
1656 if (IsLoopHeader && MI->isPHI()) {
1657 if (optimizeRecurrence(*MI)) {
1658 Changed = true;
1659 continue;
1660 }
1661 }
1662
1663 if (!MI->isCopy()) {
1664 for (const MachineOperand &MO : MI->operands()) {
1665 // Visit all operands: definitions can be implicit or explicit.
1666 if (MO.isReg()) {
1667 Register Reg = MO.getReg();
1668 if (MO.isDef() && isNAPhysCopy(Reg)) {
1669 const auto &Def = NAPhysToVirtMIs.find(Reg);
1670 if (Def != NAPhysToVirtMIs.end()) {
1671 // A new definition of the non-allocatable physical register
1672 // invalidates previous copies.
1673 LLVM_DEBUG(dbgs()
1674 << "NAPhysCopy: invalidating because of " << *MI);
1675 NAPhysToVirtMIs.erase(Def);
1676 }
1677 }
1678 } else if (MO.isRegMask()) {
1679 const uint32_t *RegMask = MO.getRegMask();
1680 for (auto &RegMI : NAPhysToVirtMIs) {
1681 unsigned Def = RegMI.first;
1682 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1683 LLVM_DEBUG(dbgs()
1684 << "NAPhysCopy: invalidating because of " << *MI);
1685 NAPhysToVirtMIs.erase(Def);
1686 }
1687 }
1688 }
1689 }
1690 }
1691
1692 if (MI->isImplicitDef() || MI->isKill())
1693 continue;
1694
1695 if (MI->isInlineAsm() || MI->hasUnmodeledSideEffects()) {
1696 // Blow away all non-allocatable physical registers knowledge since we
1697 // don't know what's correct anymore.
1698 //
1699 // FIXME: handle explicit asm clobbers.
1700 LLVM_DEBUG(dbgs() << "NAPhysCopy: blowing away all info due to "
1701 << *MI);
1702 NAPhysToVirtMIs.clear();
1703 }
1704
1705 if ((isUncoalescableCopy(*MI) &&
1706 optimizeUncoalescableCopy(*MI, LocalMIs)) ||
1707 (MI->isCompare() && optimizeCmpInstr(*MI)) ||
1708 (MI->isSelect() && optimizeSelect(*MI, LocalMIs))) {
1709 // MI is deleted.
1710 LocalMIs.erase(MI);
1711 Changed = true;
1712 continue;
1713 }
1714
1715 if (MI->isConditionalBranch() && optimizeCondBranch(*MI)) {
1716 Changed = true;
1717 continue;
1718 }
1719
1720 if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(*MI)) {
1721 // MI is just rewritten.
1722 Changed = true;
1723 continue;
1724 }
1725
1726 if (MI->isCopy() &&
1727 (foldRedundantCopy(*MI, CopySrcRegs, CopySrcMIs) ||
1728 foldRedundantNAPhysCopy(*MI, NAPhysToVirtMIs))) {
1729 LocalMIs.erase(MI);
1730 LLVM_DEBUG(dbgs() << "Deleting redundant copy: " << *MI << "\n");
1731 MI->eraseFromParent();
1732 Changed = true;
1733 continue;
1734 }
1735
1736 if (isMoveImmediate(*MI, ImmDefRegs, ImmDefMIs)) {
1737 SeenMoveImm = true;
1738 } else {
1739 Changed |= optimizeExtInstr(*MI, MBB, LocalMIs);
1740 // optimizeExtInstr might have created new instructions after MI
1741 // and before the already incremented MII. Adjust MII so that the
1742 // next iteration sees the new instructions.
1743 MII = MI;
1744 ++MII;
1745 if (SeenMoveImm)
1746 Changed |= foldImmediate(*MI, ImmDefRegs, ImmDefMIs);
1747 }
1748
1749 // Check whether MI is a load candidate for folding into a later
1750 // instruction. If MI is not a candidate, check whether we can fold an
1751 // earlier load into MI.
1752 if (!isLoadFoldable(*MI, FoldAsLoadDefCandidates) &&
1753 !FoldAsLoadDefCandidates.empty()) {
1754
1755 // We visit each operand even after successfully folding a previous
1756 // one. This allows us to fold multiple loads into a single
1757 // instruction. We do assume that optimizeLoadInstr doesn't insert
1758 // foldable uses earlier in the argument list. Since we don't restart
1759 // iteration, we'd miss such cases.
1760 const MCInstrDesc &MIDesc = MI->getDesc();
1761 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands();
1762 ++i) {
1763 const MachineOperand &MOp = MI->getOperand(i);
1764 if (!MOp.isReg())
1765 continue;
1766 unsigned FoldAsLoadDefReg = MOp.getReg();
1767 if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
1768 // We need to fold load after optimizeCmpInstr, since
1769 // optimizeCmpInstr can enable folding by converting SUB to CMP.
1770 // Save FoldAsLoadDefReg because optimizeLoadInstr() resets it and
1771 // we need it for markUsesInDebugValueAsUndef().
1772 unsigned FoldedReg = FoldAsLoadDefReg;
1773 MachineInstr *DefMI = nullptr;
1774 if (MachineInstr *FoldMI =
1775 TII->optimizeLoadInstr(*MI, MRI, FoldAsLoadDefReg, DefMI)) {
1776 // Update LocalMIs since we replaced MI with FoldMI and deleted
1777 // DefMI.
1778 LLVM_DEBUG(dbgs() << "Replacing: " << *MI);
1779 LLVM_DEBUG(dbgs() << " With: " << *FoldMI);
1780 LocalMIs.erase(MI);
1781 LocalMIs.erase(DefMI);
1782 LocalMIs.insert(FoldMI);
1783 // Update the call site info.
1784 if (MI->shouldUpdateCallSiteInfo())
1785 MI->getMF()->moveCallSiteInfo(MI, FoldMI);
1786 MI->eraseFromParent();
1787 DefMI->eraseFromParent();
1788 MRI->markUsesInDebugValueAsUndef(FoldedReg);
1789 FoldAsLoadDefCandidates.erase(FoldedReg);
1790 ++NumLoadFold;
1791
1792 // MI is replaced with FoldMI so we can continue trying to fold
1793 Changed = true;
1794 MI = FoldMI;
1795 }
1796 }
1797 }
1798 }
1799
1800 // If we run into an instruction we can't fold across, discard
1801 // the load candidates. Note: We might be able to fold *into* this
1802 // instruction, so this needs to be after the folding logic.
1803 if (MI->isLoadFoldBarrier()) {
1804 LLVM_DEBUG(dbgs() << "Encountered load fold barrier on " << *MI);
1805 FoldAsLoadDefCandidates.clear();
1806 }
1807 }
1808 }
1809
1810 return Changed;
1811 }
1812
getNextSourceFromCopy()1813 ValueTrackerResult ValueTracker::getNextSourceFromCopy() {
1814 assert(Def->isCopy() && "Invalid definition");
1815 // Copy instruction are supposed to be: Def = Src.
1816 // If someone breaks this assumption, bad things will happen everywhere.
1817 // There may be implicit uses preventing the copy to be moved across
1818 // some target specific register definitions
1819 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 &&
1820 "Invalid number of operands");
1821 assert(!Def->hasImplicitDef() && "Only implicit uses are allowed");
1822
1823 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1824 // If we look for a different subreg, it means we want a subreg of src.
1825 // Bails as we do not support composing subregs yet.
1826 return ValueTrackerResult();
1827 // Otherwise, we want the whole source.
1828 const MachineOperand &Src = Def->getOperand(1);
1829 if (Src.isUndef())
1830 return ValueTrackerResult();
1831 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1832 }
1833
getNextSourceFromBitcast()1834 ValueTrackerResult ValueTracker::getNextSourceFromBitcast() {
1835 assert(Def->isBitcast() && "Invalid definition");
1836
1837 // Bail if there are effects that a plain copy will not expose.
1838 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects())
1839 return ValueTrackerResult();
1840
1841 // Bitcasts with more than one def are not supported.
1842 if (Def->getDesc().getNumDefs() != 1)
1843 return ValueTrackerResult();
1844 const MachineOperand DefOp = Def->getOperand(DefIdx);
1845 if (DefOp.getSubReg() != DefSubReg)
1846 // If we look for a different subreg, it means we want a subreg of the src.
1847 // Bails as we do not support composing subregs yet.
1848 return ValueTrackerResult();
1849
1850 unsigned SrcIdx = Def->getNumOperands();
1851 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
1852 ++OpIdx) {
1853 const MachineOperand &MO = Def->getOperand(OpIdx);
1854 if (!MO.isReg() || !MO.getReg())
1855 continue;
1856 // Ignore dead implicit defs.
1857 if (MO.isImplicit() && MO.isDead())
1858 continue;
1859 assert(!MO.isDef() && "We should have skipped all the definitions by now");
1860 if (SrcIdx != EndOpIdx)
1861 // Multiple sources?
1862 return ValueTrackerResult();
1863 SrcIdx = OpIdx;
1864 }
1865
1866 // In some rare case, Def has no input, SrcIdx is out of bound,
1867 // getOperand(SrcIdx) will fail below.
1868 if (SrcIdx >= Def->getNumOperands())
1869 return ValueTrackerResult();
1870
1871 // Stop when any user of the bitcast is a SUBREG_TO_REG, replacing with a COPY
1872 // will break the assumed guarantees for the upper bits.
1873 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {
1874 if (UseMI.isSubregToReg())
1875 return ValueTrackerResult();
1876 }
1877
1878 const MachineOperand &Src = Def->getOperand(SrcIdx);
1879 if (Src.isUndef())
1880 return ValueTrackerResult();
1881 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1882 }
1883
getNextSourceFromRegSequence()1884 ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
1885 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1886 "Invalid definition");
1887
1888 if (Def->getOperand(DefIdx).getSubReg())
1889 // If we are composing subregs, bail out.
1890 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1891 // This should almost never happen as the SSA property is tracked at
1892 // the register level (as opposed to the subreg level).
1893 // I.e.,
1894 // Def.sub0 =
1895 // Def.sub1 =
1896 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1897 // Def. Thus, it must not be generated.
1898 // However, some code could theoretically generates a single
1899 // Def.sub0 (i.e, not defining the other subregs) and we would
1900 // have this case.
1901 // If we can ascertain (or force) that this never happens, we could
1902 // turn that into an assertion.
1903 return ValueTrackerResult();
1904
1905 if (!TII)
1906 // We could handle the REG_SEQUENCE here, but we do not want to
1907 // duplicate the code from the generic TII.
1908 return ValueTrackerResult();
1909
1910 SmallVector<RegSubRegPairAndIdx, 8> RegSeqInputRegs;
1911 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1912 return ValueTrackerResult();
1913
1914 // We are looking at:
1915 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1916 // Check if one of the operand defines the subreg we are interested in.
1917 for (const RegSubRegPairAndIdx &RegSeqInput : RegSeqInputRegs) {
1918 if (RegSeqInput.SubIdx == DefSubReg)
1919 return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg);
1920 }
1921
1922 // If the subreg we are tracking is super-defined by another subreg,
1923 // we could follow this value. However, this would require to compose
1924 // the subreg and we do not do that for now.
1925 return ValueTrackerResult();
1926 }
1927
getNextSourceFromInsertSubreg()1928 ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
1929 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
1930 "Invalid definition");
1931
1932 if (Def->getOperand(DefIdx).getSubReg())
1933 // If we are composing subreg, bail out.
1934 // Same remark as getNextSourceFromRegSequence.
1935 // I.e., this may be turned into an assert.
1936 return ValueTrackerResult();
1937
1938 if (!TII)
1939 // We could handle the REG_SEQUENCE here, but we do not want to
1940 // duplicate the code from the generic TII.
1941 return ValueTrackerResult();
1942
1943 RegSubRegPair BaseReg;
1944 RegSubRegPairAndIdx InsertedReg;
1945 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1946 return ValueTrackerResult();
1947
1948 // We are looking at:
1949 // Def = INSERT_SUBREG v0, v1, sub1
1950 // There are two cases:
1951 // 1. DefSubReg == sub1, get v1.
1952 // 2. DefSubReg != sub1, the value may be available through v0.
1953
1954 // #1 Check if the inserted register matches the required sub index.
1955 if (InsertedReg.SubIdx == DefSubReg) {
1956 return ValueTrackerResult(InsertedReg.Reg, InsertedReg.SubReg);
1957 }
1958 // #2 Otherwise, if the sub register we are looking for is not partial
1959 // defined by the inserted element, we can look through the main
1960 // register (v0).
1961 const MachineOperand &MODef = Def->getOperand(DefIdx);
1962 // If the result register (Def) and the base register (v0) do not
1963 // have the same register class or if we have to compose
1964 // subregisters, bail out.
1965 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
1966 BaseReg.SubReg)
1967 return ValueTrackerResult();
1968
1969 // Get the TRI and check if the inserted sub-register overlaps with the
1970 // sub-register we are tracking.
1971 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
1972 if (!TRI ||
1973 !(TRI->getSubRegIndexLaneMask(DefSubReg) &
1974 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none())
1975 return ValueTrackerResult();
1976 // At this point, the value is available in v0 via the same subreg
1977 // we used for Def.
1978 return ValueTrackerResult(BaseReg.Reg, DefSubReg);
1979 }
1980
getNextSourceFromExtractSubreg()1981 ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() {
1982 assert((Def->isExtractSubreg() ||
1983 Def->isExtractSubregLike()) && "Invalid definition");
1984 // We are looking at:
1985 // Def = EXTRACT_SUBREG v0, sub0
1986
1987 // Bail if we have to compose sub registers.
1988 // Indeed, if DefSubReg != 0, we would have to compose it with sub0.
1989 if (DefSubReg)
1990 return ValueTrackerResult();
1991
1992 if (!TII)
1993 // We could handle the EXTRACT_SUBREG here, but we do not want to
1994 // duplicate the code from the generic TII.
1995 return ValueTrackerResult();
1996
1997 RegSubRegPairAndIdx ExtractSubregInputReg;
1998 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
1999 return ValueTrackerResult();
2000
2001 // Bail if we have to compose sub registers.
2002 // Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
2003 if (ExtractSubregInputReg.SubReg)
2004 return ValueTrackerResult();
2005 // Otherwise, the value is available in the v0.sub0.
2006 return ValueTrackerResult(ExtractSubregInputReg.Reg,
2007 ExtractSubregInputReg.SubIdx);
2008 }
2009
getNextSourceFromSubregToReg()2010 ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() {
2011 assert(Def->isSubregToReg() && "Invalid definition");
2012 // We are looking at:
2013 // Def = SUBREG_TO_REG Imm, v0, sub0
2014
2015 // Bail if we have to compose sub registers.
2016 // If DefSubReg != sub0, we would have to check that all the bits
2017 // we track are included in sub0 and if yes, we would have to
2018 // determine the right subreg in v0.
2019 if (DefSubReg != Def->getOperand(3).getImm())
2020 return ValueTrackerResult();
2021 // Bail if we have to compose sub registers.
2022 // Likewise, if v0.subreg != 0, we would have to compose it with sub0.
2023 if (Def->getOperand(2).getSubReg())
2024 return ValueTrackerResult();
2025
2026 return ValueTrackerResult(Def->getOperand(2).getReg(),
2027 Def->getOperand(3).getImm());
2028 }
2029
2030 /// Explore each PHI incoming operand and return its sources.
getNextSourceFromPHI()2031 ValueTrackerResult ValueTracker::getNextSourceFromPHI() {
2032 assert(Def->isPHI() && "Invalid definition");
2033 ValueTrackerResult Res;
2034
2035 // If we look for a different subreg, bail as we do not support composing
2036 // subregs yet.
2037 if (Def->getOperand(0).getSubReg() != DefSubReg)
2038 return ValueTrackerResult();
2039
2040 // Return all register sources for PHI instructions.
2041 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
2042 const MachineOperand &MO = Def->getOperand(i);
2043 assert(MO.isReg() && "Invalid PHI instruction");
2044 // We have no code to deal with undef operands. They shouldn't happen in
2045 // normal programs anyway.
2046 if (MO.isUndef())
2047 return ValueTrackerResult();
2048 Res.addSource(MO.getReg(), MO.getSubReg());
2049 }
2050
2051 return Res;
2052 }
2053
getNextSourceImpl()2054 ValueTrackerResult ValueTracker::getNextSourceImpl() {
2055 assert(Def && "This method needs a valid definition");
2056
2057 assert(((Def->getOperand(DefIdx).isDef() &&
2058 (DefIdx < Def->getDesc().getNumDefs() ||
2059 Def->getDesc().isVariadic())) ||
2060 Def->getOperand(DefIdx).isImplicit()) &&
2061 "Invalid DefIdx");
2062 if (Def->isCopy())
2063 return getNextSourceFromCopy();
2064 if (Def->isBitcast())
2065 return getNextSourceFromBitcast();
2066 // All the remaining cases involve "complex" instructions.
2067 // Bail if we did not ask for the advanced tracking.
2068 if (DisableAdvCopyOpt)
2069 return ValueTrackerResult();
2070 if (Def->isRegSequence() || Def->isRegSequenceLike())
2071 return getNextSourceFromRegSequence();
2072 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
2073 return getNextSourceFromInsertSubreg();
2074 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
2075 return getNextSourceFromExtractSubreg();
2076 if (Def->isSubregToReg())
2077 return getNextSourceFromSubregToReg();
2078 if (Def->isPHI())
2079 return getNextSourceFromPHI();
2080 return ValueTrackerResult();
2081 }
2082
getNextSource()2083 ValueTrackerResult ValueTracker::getNextSource() {
2084 // If we reach a point where we cannot move up in the use-def chain,
2085 // there is nothing we can get.
2086 if (!Def)
2087 return ValueTrackerResult();
2088
2089 ValueTrackerResult Res = getNextSourceImpl();
2090 if (Res.isValid()) {
2091 // Update definition, definition index, and subregister for the
2092 // next call of getNextSource.
2093 // Update the current register.
2094 bool OneRegSrc = Res.getNumSources() == 1;
2095 if (OneRegSrc)
2096 Reg = Res.getSrcReg(0);
2097 // Update the result before moving up in the use-def chain
2098 // with the instruction containing the last found sources.
2099 Res.setInst(Def);
2100
2101 // If we can still move up in the use-def chain, move to the next
2102 // definition.
2103 if (!Register::isPhysicalRegister(Reg) && OneRegSrc) {
2104 MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg);
2105 if (DI != MRI.def_end()) {
2106 Def = DI->getParent();
2107 DefIdx = DI.getOperandNo();
2108 DefSubReg = Res.getSrcSubReg(0);
2109 } else {
2110 Def = nullptr;
2111 }
2112 return Res;
2113 }
2114 }
2115 // If we end up here, this means we will not be able to find another source
2116 // for the next iteration. Make sure any new call to getNextSource bails out
2117 // early by cutting the use-def chain.
2118 Def = nullptr;
2119 return Res;
2120 }
2121