1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "AArch64Disassembler.h"
13 #include "AArch64ExternalSymbolizer.h"
14 #include "MCTargetDesc/AArch64AddressingModes.h"
15 #include "MCTargetDesc/AArch64MCTargetDesc.h"
16 #include "TargetInfo/AArch64TargetInfo.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm-c/Disassembler.h"
19 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
20 #include "llvm/MC/MCFixedLenDisassembler.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include <algorithm>
29 #include <memory>
30
31 using namespace llvm;
32
33 #define DEBUG_TYPE "aarch64-disassembler"
34
35 // Pull DecodeStatus and its enum values into the global namespace.
36 using DecodeStatus = MCDisassembler::DecodeStatus;
37
38 // Forward declare these because the autogenerated code will reference them.
39 // Definitions are further down.
40 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
41 unsigned RegNo, uint64_t Address,
42 const void *Decoder);
43 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
44 unsigned RegNo,
45 uint64_t Address,
46 const void *Decoder);
47 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
48 uint64_t Address,
49 const void *Decoder);
50 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
51 uint64_t Address,
52 const void *Decoder);
53 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
54 uint64_t Address,
55 const void *Decoder);
56 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
57 uint64_t Address,
58 const void *Decoder);
59 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
60 uint64_t Address,
61 const void *Decoder);
62 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
63 uint64_t Address,
64 const void *Decoder);
65 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
66 unsigned RegNo, uint64_t Address,
67 const void *Decoder);
68 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
69 uint64_t Address,
70 const void *Decoder);
71 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
72 unsigned RegNo, uint64_t Address,
73 const void *Decoder);
74 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
75 uint64_t Address,
76 const void *Decoder);
77 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
78 uint64_t Address,
79 const void *Decoder);
80 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
81 uint64_t Address,
82 const void *Decoder);
83 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
84 uint64_t Address,
85 const void *Decoder);
86 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
87 uint64_t Address,
88 const void *Decoder);
89 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
90 uint64_t Address,
91 const void *Decoder);
92 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
93 uint64_t Address,
94 const void *Decoder);
95 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
96 uint64_t Address,
97 const void *Decoder);
98 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
99 uint64_t Address,
100 const void *Decoder);
101 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
102 uint64_t Address,
103 const void *Decoder);
104 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
105 uint64_t Address,
106 const void *Decoder);
107 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
108 uint64_t Address,
109 const void *Decoder);
110 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
112 const void *Decoder);
113 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
114 uint64_t Address,
115 const void *Decoder);
116
117 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
118 uint64_t Address,
119 const void *Decoder);
120 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
121 uint64_t Address,
122 const void *Decoder);
123 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
124 uint64_t Address, const void *Decoder);
125 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
126 uint64_t Address, const void *Decoder);
127 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
128 uint64_t Address, const void *Decoder);
129 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
130 uint64_t Address, const void *Decoder);
131 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
132 uint64_t Address,
133 const void *Decoder);
134 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
135 uint64_t Address,
136 const void *Decoder);
137 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
138 uint64_t Address,
139 const void *Decoder);
140 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
141 uint64_t Address,
142 const void *Decoder);
143 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
144 uint64_t Address,
145 const void *Decoder);
146 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
147 uint64_t Address,
148 const void *Decoder);
149 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
150 uint64_t Address,
151 const void *Decoder);
152 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
153 uint64_t Address,
154 const void *Decoder);
155 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
156 uint64_t Address,
157 const void *Decoder);
158 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
159 uint64_t Address,
160 const void *Decoder);
161 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
162 uint64_t Address,
163 const void *Decoder);
164 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
169 uint64_t Address,
170 const void *Decoder);
171 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
172 uint64_t Address,
173 const void *Decoder);
174 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
175 uint64_t Address, const void *Decoder);
176
177 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
178 uint64_t Address,
179 const void *Decoder);
180 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
181 uint64_t Addr, const void *Decoder);
182 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
183 uint64_t Addr,
184 const void *Decoder);
185 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
186 uint64_t Addr, const void *Decoder);
187 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
188 uint64_t Addr,
189 const void *Decoder);
190 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
191 uint64_t Addr, const void *Decoder);
192 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
193 uint64_t Addr,
194 const void *Decoder);
195 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
196 uint64_t Addr, const void *Decoder);
197 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
198 uint64_t Addr, const void *Decoder);
199 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
200 uint64_t Addr, const void *Decoder);
201 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
202 uint64_t Addr, const void *Decoder);
203 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
204 uint64_t Addr, const void *Decoder);
205 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
206 unsigned RegNo,
207 uint64_t Addr,
208 const void *Decoder);
209 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
210 unsigned RegNo,
211 uint64_t Addr,
212 const void *Decoder);
213 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
214 uint32_t insn,
215 uint64_t Address,
216 const void *Decoder);
217 template<int Bits>
218 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
219 uint64_t Address, const void *Decoder);
220 template <int ElementWidth>
221 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
222 uint64_t Addr, const void *Decoder);
223 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
224 uint64_t Addr, const void *Decoder);
225
Check(DecodeStatus & Out,DecodeStatus In)226 static bool Check(DecodeStatus &Out, DecodeStatus In) {
227 switch (In) {
228 case MCDisassembler::Success:
229 // Out stays the same.
230 return true;
231 case MCDisassembler::SoftFail:
232 Out = In;
233 return true;
234 case MCDisassembler::Fail:
235 Out = In;
236 return false;
237 }
238 llvm_unreachable("Invalid DecodeStatus!");
239 }
240
241 #include "AArch64GenDisassemblerTables.inc"
242 #include "AArch64GenInstrInfo.inc"
243
244 #define Success MCDisassembler::Success
245 #define Fail MCDisassembler::Fail
246 #define SoftFail MCDisassembler::SoftFail
247
createAArch64Disassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)248 static MCDisassembler *createAArch64Disassembler(const Target &T,
249 const MCSubtargetInfo &STI,
250 MCContext &Ctx) {
251 return new AArch64Disassembler(STI, Ctx);
252 }
253
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const254 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
255 ArrayRef<uint8_t> Bytes,
256 uint64_t Address,
257 raw_ostream &CS) const {
258 CommentStream = &CS;
259
260 Size = 0;
261 // We want to read exactly 4 bytes of data.
262 if (Bytes.size() < 4)
263 return Fail;
264 Size = 4;
265
266 // Encoded as a small-endian 32-bit word in the stream.
267 uint32_t Insn =
268 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
269
270 // Calling the auto-generated decoder function.
271 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
272 }
273
274 static MCSymbolizer *
createAArch64ExternalSymbolizer(const Triple & TT,LLVMOpInfoCallback GetOpInfo,LLVMSymbolLookupCallback SymbolLookUp,void * DisInfo,MCContext * Ctx,std::unique_ptr<MCRelocationInfo> && RelInfo)275 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
276 LLVMSymbolLookupCallback SymbolLookUp,
277 void *DisInfo, MCContext *Ctx,
278 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
279 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
280 SymbolLookUp, DisInfo);
281 }
282
LLVMInitializeAArch64Disassembler()283 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
284 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
285 createAArch64Disassembler);
286 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
287 createAArch64Disassembler);
288 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
289 createAArch64ExternalSymbolizer);
290 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
291 createAArch64ExternalSymbolizer);
292 TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
293 createAArch64Disassembler);
294 TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
295 createAArch64ExternalSymbolizer);
296
297 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
298 createAArch64Disassembler);
299 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
300 createAArch64ExternalSymbolizer);
301 TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
302 createAArch64Disassembler);
303 TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
304 createAArch64ExternalSymbolizer);
305 }
306
307 static const unsigned FPR128DecoderTable[] = {
308 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
309 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
310 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
311 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
312 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
313 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
314 AArch64::Q30, AArch64::Q31
315 };
316
DecodeFPR128RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)317 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
318 uint64_t Addr,
319 const void *Decoder) {
320 if (RegNo > 31)
321 return Fail;
322
323 unsigned Register = FPR128DecoderTable[RegNo];
324 Inst.addOperand(MCOperand::createReg(Register));
325 return Success;
326 }
327
DecodeFPR128_loRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)328 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
329 uint64_t Addr,
330 const void *Decoder) {
331 if (RegNo > 15)
332 return Fail;
333 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
334 }
335
336 static const unsigned FPR64DecoderTable[] = {
337 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
338 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
339 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
340 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
341 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
342 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
343 AArch64::D30, AArch64::D31
344 };
345
DecodeFPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)346 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
347 uint64_t Addr,
348 const void *Decoder) {
349 if (RegNo > 31)
350 return Fail;
351
352 unsigned Register = FPR64DecoderTable[RegNo];
353 Inst.addOperand(MCOperand::createReg(Register));
354 return Success;
355 }
356
357 static const unsigned FPR32DecoderTable[] = {
358 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
359 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
360 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
361 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
362 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
363 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
364 AArch64::S30, AArch64::S31
365 };
366
DecodeFPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)367 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
368 uint64_t Addr,
369 const void *Decoder) {
370 if (RegNo > 31)
371 return Fail;
372
373 unsigned Register = FPR32DecoderTable[RegNo];
374 Inst.addOperand(MCOperand::createReg(Register));
375 return Success;
376 }
377
378 static const unsigned FPR16DecoderTable[] = {
379 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
380 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
381 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
382 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
383 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
384 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
385 AArch64::H30, AArch64::H31
386 };
387
DecodeFPR16RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)388 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
389 uint64_t Addr,
390 const void *Decoder) {
391 if (RegNo > 31)
392 return Fail;
393
394 unsigned Register = FPR16DecoderTable[RegNo];
395 Inst.addOperand(MCOperand::createReg(Register));
396 return Success;
397 }
398
399 static const unsigned FPR8DecoderTable[] = {
400 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
401 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
402 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
403 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
404 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
405 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
406 AArch64::B30, AArch64::B31
407 };
408
DecodeFPR8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)409 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
410 uint64_t Addr,
411 const void *Decoder) {
412 if (RegNo > 31)
413 return Fail;
414
415 unsigned Register = FPR8DecoderTable[RegNo];
416 Inst.addOperand(MCOperand::createReg(Register));
417 return Success;
418 }
419
420 static const unsigned GPR64DecoderTable[] = {
421 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
422 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
423 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
424 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
425 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
426 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
427 AArch64::LR, AArch64::XZR
428 };
429
DecodeGPR64commonRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)430 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
431 uint64_t Addr,
432 const void *Decoder) {
433 if (RegNo > 30)
434 return Fail;
435
436 unsigned Register = GPR64DecoderTable[RegNo];
437 Inst.addOperand(MCOperand::createReg(Register));
438 return Success;
439 }
440
DecodeGPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)441 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
442 uint64_t Addr,
443 const void *Decoder) {
444 if (RegNo > 31)
445 return Fail;
446
447 unsigned Register = GPR64DecoderTable[RegNo];
448 Inst.addOperand(MCOperand::createReg(Register));
449 return Success;
450 }
451
DecodeGPR64spRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)452 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
453 uint64_t Addr,
454 const void *Decoder) {
455 if (RegNo > 31)
456 return Fail;
457 unsigned Register = GPR64DecoderTable[RegNo];
458 if (Register == AArch64::XZR)
459 Register = AArch64::SP;
460 Inst.addOperand(MCOperand::createReg(Register));
461 return Success;
462 }
463
464 static const unsigned GPR32DecoderTable[] = {
465 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
466 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
467 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
468 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
469 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
470 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
471 AArch64::W30, AArch64::WZR
472 };
473
DecodeGPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)474 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
475 uint64_t Addr,
476 const void *Decoder) {
477 if (RegNo > 31)
478 return Fail;
479
480 unsigned Register = GPR32DecoderTable[RegNo];
481 Inst.addOperand(MCOperand::createReg(Register));
482 return Success;
483 }
484
DecodeGPR32spRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)485 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
486 uint64_t Addr,
487 const void *Decoder) {
488 if (RegNo > 31)
489 return Fail;
490
491 unsigned Register = GPR32DecoderTable[RegNo];
492 if (Register == AArch64::WZR)
493 Register = AArch64::WSP;
494 Inst.addOperand(MCOperand::createReg(Register));
495 return Success;
496 }
497 static const unsigned ZPRDecoderTable[] = {
498 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
499 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
500 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11,
501 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
502 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19,
503 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23,
504 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27,
505 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31
506 };
507
DecodeZPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)508 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
509 uint64_t Address,
510 const void* Decoder) {
511 if (RegNo > 31)
512 return Fail;
513
514 unsigned Register = ZPRDecoderTable[RegNo];
515 Inst.addOperand(MCOperand::createReg(Register));
516 return Success;
517 }
518
DecodeZPR_4bRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)519 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
520 uint64_t Address,
521 const void *Decoder) {
522 if (RegNo > 15)
523 return Fail;
524 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
525 }
526
DecodeZPR_3bRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)527 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
528 uint64_t Address,
529 const void *Decoder) {
530 if (RegNo > 7)
531 return Fail;
532 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
533 }
534
535 static const unsigned ZZDecoderTable[] = {
536 AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4,
537 AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
538 AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12,
539 AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
540 AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20,
541 AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24,
542 AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28,
543 AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0
544 };
545
DecodeZPR2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)546 static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
547 uint64_t Address,
548 const void* Decoder) {
549 if (RegNo > 31)
550 return Fail;
551 unsigned Register = ZZDecoderTable[RegNo];
552 Inst.addOperand(MCOperand::createReg(Register));
553 return Success;
554 }
555
556 static const unsigned ZZZDecoderTable[] = {
557 AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4,
558 AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
559 AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10,
560 AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13,
561 AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
562 AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19,
563 AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22,
564 AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25,
565 AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28,
566 AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31,
567 AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1
568 };
569
DecodeZPR3RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)570 static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
571 uint64_t Address,
572 const void* Decoder) {
573 if (RegNo > 31)
574 return Fail;
575 unsigned Register = ZZZDecoderTable[RegNo];
576 Inst.addOperand(MCOperand::createReg(Register));
577 return Success;
578 }
579
580 static const unsigned ZZZZDecoderTable[] = {
581 AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5,
582 AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
583 AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11,
584 AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14,
585 AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
586 AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20,
587 AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23,
588 AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26,
589 AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29,
590 AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0,
591 AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2
592 };
593
DecodeZPR4RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)594 static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
595 uint64_t Address,
596 const void* Decoder) {
597 if (RegNo > 31)
598 return Fail;
599 unsigned Register = ZZZZDecoderTable[RegNo];
600 Inst.addOperand(MCOperand::createReg(Register));
601 return Success;
602 }
603
604 static const unsigned PPRDecoderTable[] = {
605 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3,
606 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
607 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11,
608 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15
609 };
610
DecodePPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)611 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
612 uint64_t Addr, const void *Decoder) {
613 if (RegNo > 15)
614 return Fail;
615
616 unsigned Register = PPRDecoderTable[RegNo];
617 Inst.addOperand(MCOperand::createReg(Register));
618 return Success;
619 }
620
DecodePPR_3bRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)621 static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
622 uint64_t Addr,
623 const void* Decoder) {
624 if (RegNo > 7)
625 return Fail;
626
627 // Just reuse the PPR decode table
628 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
629 }
630
631 static const unsigned VectorDecoderTable[] = {
632 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
633 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
634 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
635 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
636 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
637 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
638 AArch64::Q30, AArch64::Q31
639 };
640
DecodeVectorRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)641 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
642 uint64_t Addr,
643 const void *Decoder) {
644 if (RegNo > 31)
645 return Fail;
646
647 unsigned Register = VectorDecoderTable[RegNo];
648 Inst.addOperand(MCOperand::createReg(Register));
649 return Success;
650 }
651
652 static const unsigned QQDecoderTable[] = {
653 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
654 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
655 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
656 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
657 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
658 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
659 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
660 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
661 };
662
DecodeQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)663 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
664 uint64_t Addr, const void *Decoder) {
665 if (RegNo > 31)
666 return Fail;
667 unsigned Register = QQDecoderTable[RegNo];
668 Inst.addOperand(MCOperand::createReg(Register));
669 return Success;
670 }
671
672 static const unsigned QQQDecoderTable[] = {
673 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
674 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
675 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
676 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
677 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
678 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
679 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
680 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
681 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
682 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
683 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
684 };
685
DecodeQQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)686 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
687 uint64_t Addr, const void *Decoder) {
688 if (RegNo > 31)
689 return Fail;
690 unsigned Register = QQQDecoderTable[RegNo];
691 Inst.addOperand(MCOperand::createReg(Register));
692 return Success;
693 }
694
695 static const unsigned QQQQDecoderTable[] = {
696 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
697 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
698 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
699 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
700 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
701 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
702 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
703 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
704 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
705 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
706 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
707 };
708
DecodeQQQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)709 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
710 uint64_t Addr,
711 const void *Decoder) {
712 if (RegNo > 31)
713 return Fail;
714 unsigned Register = QQQQDecoderTable[RegNo];
715 Inst.addOperand(MCOperand::createReg(Register));
716 return Success;
717 }
718
719 static const unsigned DDDecoderTable[] = {
720 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
721 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
722 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
723 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
724 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
725 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
726 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
727 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
728 };
729
DecodeDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)730 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
731 uint64_t Addr, const void *Decoder) {
732 if (RegNo > 31)
733 return Fail;
734 unsigned Register = DDDecoderTable[RegNo];
735 Inst.addOperand(MCOperand::createReg(Register));
736 return Success;
737 }
738
739 static const unsigned DDDDecoderTable[] = {
740 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
741 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
742 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
743 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
744 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
745 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
746 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
747 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
748 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
749 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
750 AArch64::D30_D31_D0, AArch64::D31_D0_D1
751 };
752
DecodeDDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)753 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
754 uint64_t Addr, const void *Decoder) {
755 if (RegNo > 31)
756 return Fail;
757 unsigned Register = DDDDecoderTable[RegNo];
758 Inst.addOperand(MCOperand::createReg(Register));
759 return Success;
760 }
761
762 static const unsigned DDDDDecoderTable[] = {
763 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
764 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
765 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
766 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
767 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
768 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
769 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
770 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
771 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
772 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
773 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
774 };
775
DecodeDDDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)776 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
777 uint64_t Addr,
778 const void *Decoder) {
779 if (RegNo > 31)
780 return Fail;
781 unsigned Register = DDDDDecoderTable[RegNo];
782 Inst.addOperand(MCOperand::createReg(Register));
783 return Success;
784 }
785
DecodeFixedPointScaleImm32(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)786 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
787 uint64_t Addr,
788 const void *Decoder) {
789 // scale{5} is asserted as 1 in tblgen.
790 Imm |= 0x20;
791 Inst.addOperand(MCOperand::createImm(64 - Imm));
792 return Success;
793 }
794
DecodeFixedPointScaleImm64(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)795 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
796 uint64_t Addr,
797 const void *Decoder) {
798 Inst.addOperand(MCOperand::createImm(64 - Imm));
799 return Success;
800 }
801
DecodePCRelLabel19(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)802 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
803 uint64_t Addr, const void *Decoder) {
804 int64_t ImmVal = Imm;
805 const AArch64Disassembler *Dis =
806 static_cast<const AArch64Disassembler *>(Decoder);
807
808 // Sign-extend 19-bit immediate.
809 if (ImmVal & (1 << (19 - 1)))
810 ImmVal |= ~((1LL << 19) - 1);
811
812 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
813 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
814 Inst.addOperand(MCOperand::createImm(ImmVal));
815 return Success;
816 }
817
DecodeMemExtend(MCInst & Inst,unsigned Imm,uint64_t Address,const void * Decoder)818 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
819 uint64_t Address, const void *Decoder) {
820 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
821 Inst.addOperand(MCOperand::createImm(Imm & 1));
822 return Success;
823 }
824
DecodeMRSSystemRegister(MCInst & Inst,unsigned Imm,uint64_t Address,const void * Decoder)825 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
826 uint64_t Address,
827 const void *Decoder) {
828 Inst.addOperand(MCOperand::createImm(Imm));
829
830 // Every system register in the encoding space is valid with the syntax
831 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
832 return Success;
833 }
834
DecodeMSRSystemRegister(MCInst & Inst,unsigned Imm,uint64_t Address,const void * Decoder)835 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
836 uint64_t Address,
837 const void *Decoder) {
838 Inst.addOperand(MCOperand::createImm(Imm));
839
840 return Success;
841 }
842
DecodeFMOVLaneInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)843 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
844 uint64_t Address,
845 const void *Decoder) {
846 // This decoder exists to add the dummy Lane operand to the MCInst, which must
847 // be 1 in assembly but has no other real manifestation.
848 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
849 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
850 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
851
852 if (IsToVec) {
853 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
854 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
855 } else {
856 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
857 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
858 }
859
860 // Add the lane
861 Inst.addOperand(MCOperand::createImm(1));
862
863 return Success;
864 }
865
DecodeVecShiftRImm(MCInst & Inst,unsigned Imm,unsigned Add)866 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
867 unsigned Add) {
868 Inst.addOperand(MCOperand::createImm(Add - Imm));
869 return Success;
870 }
871
DecodeVecShiftLImm(MCInst & Inst,unsigned Imm,unsigned Add)872 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
873 unsigned Add) {
874 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
875 return Success;
876 }
877
DecodeVecShiftR64Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)878 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
879 uint64_t Addr, const void *Decoder) {
880 return DecodeVecShiftRImm(Inst, Imm, 64);
881 }
882
DecodeVecShiftR64ImmNarrow(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)883 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
884 uint64_t Addr,
885 const void *Decoder) {
886 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
887 }
888
DecodeVecShiftR32Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)889 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
890 uint64_t Addr, const void *Decoder) {
891 return DecodeVecShiftRImm(Inst, Imm, 32);
892 }
893
DecodeVecShiftR32ImmNarrow(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)894 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
895 uint64_t Addr,
896 const void *Decoder) {
897 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
898 }
899
DecodeVecShiftR16Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)900 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
901 uint64_t Addr, const void *Decoder) {
902 return DecodeVecShiftRImm(Inst, Imm, 16);
903 }
904
DecodeVecShiftR16ImmNarrow(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)905 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
906 uint64_t Addr,
907 const void *Decoder) {
908 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
909 }
910
DecodeVecShiftR8Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)911 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
912 uint64_t Addr, const void *Decoder) {
913 return DecodeVecShiftRImm(Inst, Imm, 8);
914 }
915
DecodeVecShiftL64Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)916 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
917 uint64_t Addr, const void *Decoder) {
918 return DecodeVecShiftLImm(Inst, Imm, 64);
919 }
920
DecodeVecShiftL32Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)921 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
922 uint64_t Addr, const void *Decoder) {
923 return DecodeVecShiftLImm(Inst, Imm, 32);
924 }
925
DecodeVecShiftL16Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)926 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
927 uint64_t Addr, const void *Decoder) {
928 return DecodeVecShiftLImm(Inst, Imm, 16);
929 }
930
DecodeVecShiftL8Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)931 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
932 uint64_t Addr, const void *Decoder) {
933 return DecodeVecShiftLImm(Inst, Imm, 8);
934 }
935
DecodeThreeAddrSRegInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)936 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
937 uint64_t Addr,
938 const void *Decoder) {
939 unsigned Rd = fieldFromInstruction(insn, 0, 5);
940 unsigned Rn = fieldFromInstruction(insn, 5, 5);
941 unsigned Rm = fieldFromInstruction(insn, 16, 5);
942 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
943 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
944 unsigned shift = (shiftHi << 6) | shiftLo;
945 switch (Inst.getOpcode()) {
946 default:
947 return Fail;
948 case AArch64::ADDWrs:
949 case AArch64::ADDSWrs:
950 case AArch64::SUBWrs:
951 case AArch64::SUBSWrs:
952 // if shift == '11' then ReservedValue()
953 if (shiftHi == 0x3)
954 return Fail;
955 LLVM_FALLTHROUGH;
956 case AArch64::ANDWrs:
957 case AArch64::ANDSWrs:
958 case AArch64::BICWrs:
959 case AArch64::BICSWrs:
960 case AArch64::ORRWrs:
961 case AArch64::ORNWrs:
962 case AArch64::EORWrs:
963 case AArch64::EONWrs: {
964 // if sf == '0' and imm6<5> == '1' then ReservedValue()
965 if (shiftLo >> 5 == 1)
966 return Fail;
967 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
968 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
969 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
970 break;
971 }
972 case AArch64::ADDXrs:
973 case AArch64::ADDSXrs:
974 case AArch64::SUBXrs:
975 case AArch64::SUBSXrs:
976 // if shift == '11' then ReservedValue()
977 if (shiftHi == 0x3)
978 return Fail;
979 LLVM_FALLTHROUGH;
980 case AArch64::ANDXrs:
981 case AArch64::ANDSXrs:
982 case AArch64::BICXrs:
983 case AArch64::BICSXrs:
984 case AArch64::ORRXrs:
985 case AArch64::ORNXrs:
986 case AArch64::EORXrs:
987 case AArch64::EONXrs:
988 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
989 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
990 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
991 break;
992 }
993
994 Inst.addOperand(MCOperand::createImm(shift));
995 return Success;
996 }
997
DecodeMoveImmInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)998 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
999 uint64_t Addr,
1000 const void *Decoder) {
1001 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1002 unsigned imm = fieldFromInstruction(insn, 5, 16);
1003 unsigned shift = fieldFromInstruction(insn, 21, 2);
1004 shift <<= 4;
1005 switch (Inst.getOpcode()) {
1006 default:
1007 return Fail;
1008 case AArch64::MOVZWi:
1009 case AArch64::MOVNWi:
1010 case AArch64::MOVKWi:
1011 if (shift & (1U << 5))
1012 return Fail;
1013 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1014 break;
1015 case AArch64::MOVZXi:
1016 case AArch64::MOVNXi:
1017 case AArch64::MOVKXi:
1018 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1019 break;
1020 }
1021
1022 if (Inst.getOpcode() == AArch64::MOVKWi ||
1023 Inst.getOpcode() == AArch64::MOVKXi)
1024 Inst.addOperand(Inst.getOperand(0));
1025
1026 Inst.addOperand(MCOperand::createImm(imm));
1027 Inst.addOperand(MCOperand::createImm(shift));
1028 return Success;
1029 }
1030
DecodeUnsignedLdStInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1031 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
1032 uint64_t Addr,
1033 const void *Decoder) {
1034 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1035 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1036 unsigned offset = fieldFromInstruction(insn, 10, 12);
1037 const AArch64Disassembler *Dis =
1038 static_cast<const AArch64Disassembler *>(Decoder);
1039
1040 switch (Inst.getOpcode()) {
1041 default:
1042 return Fail;
1043 case AArch64::PRFMui:
1044 // Rt is an immediate in prefetch.
1045 Inst.addOperand(MCOperand::createImm(Rt));
1046 break;
1047 case AArch64::STRBBui:
1048 case AArch64::LDRBBui:
1049 case AArch64::LDRSBWui:
1050 case AArch64::STRHHui:
1051 case AArch64::LDRHHui:
1052 case AArch64::LDRSHWui:
1053 case AArch64::STRWui:
1054 case AArch64::LDRWui:
1055 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1056 break;
1057 case AArch64::LDRSBXui:
1058 case AArch64::LDRSHXui:
1059 case AArch64::LDRSWui:
1060 case AArch64::STRXui:
1061 case AArch64::LDRXui:
1062 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1063 break;
1064 case AArch64::LDRQui:
1065 case AArch64::STRQui:
1066 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1067 break;
1068 case AArch64::LDRDui:
1069 case AArch64::STRDui:
1070 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1071 break;
1072 case AArch64::LDRSui:
1073 case AArch64::STRSui:
1074 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1075 break;
1076 case AArch64::LDRHui:
1077 case AArch64::STRHui:
1078 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1079 break;
1080 case AArch64::LDRBui:
1081 case AArch64::STRBui:
1082 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1083 break;
1084 }
1085
1086 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1087 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
1088 Inst.addOperand(MCOperand::createImm(offset));
1089 return Success;
1090 }
1091
DecodeSignedLdStInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1092 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1093 uint64_t Addr,
1094 const void *Decoder) {
1095 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1096 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1097 int64_t offset = fieldFromInstruction(insn, 12, 9);
1098
1099 // offset is a 9-bit signed immediate, so sign extend it to
1100 // fill the unsigned.
1101 if (offset & (1 << (9 - 1)))
1102 offset |= ~((1LL << 9) - 1);
1103
1104 // First operand is always the writeback to the address register, if needed.
1105 switch (Inst.getOpcode()) {
1106 default:
1107 break;
1108 case AArch64::LDRSBWpre:
1109 case AArch64::LDRSHWpre:
1110 case AArch64::STRBBpre:
1111 case AArch64::LDRBBpre:
1112 case AArch64::STRHHpre:
1113 case AArch64::LDRHHpre:
1114 case AArch64::STRWpre:
1115 case AArch64::LDRWpre:
1116 case AArch64::LDRSBWpost:
1117 case AArch64::LDRSHWpost:
1118 case AArch64::STRBBpost:
1119 case AArch64::LDRBBpost:
1120 case AArch64::STRHHpost:
1121 case AArch64::LDRHHpost:
1122 case AArch64::STRWpost:
1123 case AArch64::LDRWpost:
1124 case AArch64::LDRSBXpre:
1125 case AArch64::LDRSHXpre:
1126 case AArch64::STRXpre:
1127 case AArch64::LDRSWpre:
1128 case AArch64::LDRXpre:
1129 case AArch64::LDRSBXpost:
1130 case AArch64::LDRSHXpost:
1131 case AArch64::STRXpost:
1132 case AArch64::LDRSWpost:
1133 case AArch64::LDRXpost:
1134 case AArch64::LDRQpre:
1135 case AArch64::STRQpre:
1136 case AArch64::LDRQpost:
1137 case AArch64::STRQpost:
1138 case AArch64::LDRDpre:
1139 case AArch64::STRDpre:
1140 case AArch64::LDRDpost:
1141 case AArch64::STRDpost:
1142 case AArch64::LDRSpre:
1143 case AArch64::STRSpre:
1144 case AArch64::LDRSpost:
1145 case AArch64::STRSpost:
1146 case AArch64::LDRHpre:
1147 case AArch64::STRHpre:
1148 case AArch64::LDRHpost:
1149 case AArch64::STRHpost:
1150 case AArch64::LDRBpre:
1151 case AArch64::STRBpre:
1152 case AArch64::LDRBpost:
1153 case AArch64::STRBpost:
1154 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1155 break;
1156 }
1157
1158 switch (Inst.getOpcode()) {
1159 default:
1160 return Fail;
1161 case AArch64::PRFUMi:
1162 // Rt is an immediate in prefetch.
1163 Inst.addOperand(MCOperand::createImm(Rt));
1164 break;
1165 case AArch64::STURBBi:
1166 case AArch64::LDURBBi:
1167 case AArch64::LDURSBWi:
1168 case AArch64::STURHHi:
1169 case AArch64::LDURHHi:
1170 case AArch64::LDURSHWi:
1171 case AArch64::STURWi:
1172 case AArch64::LDURWi:
1173 case AArch64::LDTRSBWi:
1174 case AArch64::LDTRSHWi:
1175 case AArch64::STTRWi:
1176 case AArch64::LDTRWi:
1177 case AArch64::STTRHi:
1178 case AArch64::LDTRHi:
1179 case AArch64::LDTRBi:
1180 case AArch64::STTRBi:
1181 case AArch64::LDRSBWpre:
1182 case AArch64::LDRSHWpre:
1183 case AArch64::STRBBpre:
1184 case AArch64::LDRBBpre:
1185 case AArch64::STRHHpre:
1186 case AArch64::LDRHHpre:
1187 case AArch64::STRWpre:
1188 case AArch64::LDRWpre:
1189 case AArch64::LDRSBWpost:
1190 case AArch64::LDRSHWpost:
1191 case AArch64::STRBBpost:
1192 case AArch64::LDRBBpost:
1193 case AArch64::STRHHpost:
1194 case AArch64::LDRHHpost:
1195 case AArch64::STRWpost:
1196 case AArch64::LDRWpost:
1197 case AArch64::STLURBi:
1198 case AArch64::STLURHi:
1199 case AArch64::STLURWi:
1200 case AArch64::LDAPURBi:
1201 case AArch64::LDAPURSBWi:
1202 case AArch64::LDAPURHi:
1203 case AArch64::LDAPURSHWi:
1204 case AArch64::LDAPURi:
1205 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1206 break;
1207 case AArch64::LDURSBXi:
1208 case AArch64::LDURSHXi:
1209 case AArch64::LDURSWi:
1210 case AArch64::STURXi:
1211 case AArch64::LDURXi:
1212 case AArch64::LDTRSBXi:
1213 case AArch64::LDTRSHXi:
1214 case AArch64::LDTRSWi:
1215 case AArch64::STTRXi:
1216 case AArch64::LDTRXi:
1217 case AArch64::LDRSBXpre:
1218 case AArch64::LDRSHXpre:
1219 case AArch64::STRXpre:
1220 case AArch64::LDRSWpre:
1221 case AArch64::LDRXpre:
1222 case AArch64::LDRSBXpost:
1223 case AArch64::LDRSHXpost:
1224 case AArch64::STRXpost:
1225 case AArch64::LDRSWpost:
1226 case AArch64::LDRXpost:
1227 case AArch64::LDAPURSWi:
1228 case AArch64::LDAPURSHXi:
1229 case AArch64::LDAPURSBXi:
1230 case AArch64::STLURXi:
1231 case AArch64::LDAPURXi:
1232 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1233 break;
1234 case AArch64::LDURQi:
1235 case AArch64::STURQi:
1236 case AArch64::LDRQpre:
1237 case AArch64::STRQpre:
1238 case AArch64::LDRQpost:
1239 case AArch64::STRQpost:
1240 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1241 break;
1242 case AArch64::LDURDi:
1243 case AArch64::STURDi:
1244 case AArch64::LDRDpre:
1245 case AArch64::STRDpre:
1246 case AArch64::LDRDpost:
1247 case AArch64::STRDpost:
1248 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1249 break;
1250 case AArch64::LDURSi:
1251 case AArch64::STURSi:
1252 case AArch64::LDRSpre:
1253 case AArch64::STRSpre:
1254 case AArch64::LDRSpost:
1255 case AArch64::STRSpost:
1256 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1257 break;
1258 case AArch64::LDURHi:
1259 case AArch64::STURHi:
1260 case AArch64::LDRHpre:
1261 case AArch64::STRHpre:
1262 case AArch64::LDRHpost:
1263 case AArch64::STRHpost:
1264 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1265 break;
1266 case AArch64::LDURBi:
1267 case AArch64::STURBi:
1268 case AArch64::LDRBpre:
1269 case AArch64::STRBpre:
1270 case AArch64::LDRBpost:
1271 case AArch64::STRBpost:
1272 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1273 break;
1274 }
1275
1276 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1277 Inst.addOperand(MCOperand::createImm(offset));
1278
1279 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1280 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1281 bool IsFP = fieldFromInstruction(insn, 26, 1);
1282
1283 // Cannot write back to a transfer register (but xzr != sp).
1284 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1285 return SoftFail;
1286
1287 return Success;
1288 }
1289
DecodeExclusiveLdStInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1290 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1291 uint64_t Addr,
1292 const void *Decoder) {
1293 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1294 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1295 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1296 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1297
1298 unsigned Opcode = Inst.getOpcode();
1299 switch (Opcode) {
1300 default:
1301 return Fail;
1302 case AArch64::STLXRW:
1303 case AArch64::STLXRB:
1304 case AArch64::STLXRH:
1305 case AArch64::STXRW:
1306 case AArch64::STXRB:
1307 case AArch64::STXRH:
1308 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1309 LLVM_FALLTHROUGH;
1310 case AArch64::LDARW:
1311 case AArch64::LDARB:
1312 case AArch64::LDARH:
1313 case AArch64::LDAXRW:
1314 case AArch64::LDAXRB:
1315 case AArch64::LDAXRH:
1316 case AArch64::LDXRW:
1317 case AArch64::LDXRB:
1318 case AArch64::LDXRH:
1319 case AArch64::STLRW:
1320 case AArch64::STLRB:
1321 case AArch64::STLRH:
1322 case AArch64::STLLRW:
1323 case AArch64::STLLRB:
1324 case AArch64::STLLRH:
1325 case AArch64::LDLARW:
1326 case AArch64::LDLARB:
1327 case AArch64::LDLARH:
1328 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1329 break;
1330 case AArch64::STLXRX:
1331 case AArch64::STXRX:
1332 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1333 LLVM_FALLTHROUGH;
1334 case AArch64::LDARX:
1335 case AArch64::LDAXRX:
1336 case AArch64::LDXRX:
1337 case AArch64::STLRX:
1338 case AArch64::LDLARX:
1339 case AArch64::STLLRX:
1340 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1341 break;
1342 case AArch64::STLXPW:
1343 case AArch64::STXPW:
1344 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1345 LLVM_FALLTHROUGH;
1346 case AArch64::LDAXPW:
1347 case AArch64::LDXPW:
1348 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1349 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1350 break;
1351 case AArch64::STLXPX:
1352 case AArch64::STXPX:
1353 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1354 LLVM_FALLTHROUGH;
1355 case AArch64::LDAXPX:
1356 case AArch64::LDXPX:
1357 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1358 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1359 break;
1360 }
1361
1362 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1363
1364 // You shouldn't load to the same register twice in an instruction...
1365 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1366 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1367 Rt == Rt2)
1368 return SoftFail;
1369
1370 return Success;
1371 }
1372
DecodePairLdStInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1373 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1374 uint64_t Addr,
1375 const void *Decoder) {
1376 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1377 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1378 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1379 int64_t offset = fieldFromInstruction(insn, 15, 7);
1380 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1381
1382 // offset is a 7-bit signed immediate, so sign extend it to
1383 // fill the unsigned.
1384 if (offset & (1 << (7 - 1)))
1385 offset |= ~((1LL << 7) - 1);
1386
1387 unsigned Opcode = Inst.getOpcode();
1388 bool NeedsDisjointWritebackTransfer = false;
1389
1390 // First operand is always writeback of base register.
1391 switch (Opcode) {
1392 default:
1393 break;
1394 case AArch64::LDPXpost:
1395 case AArch64::STPXpost:
1396 case AArch64::LDPSWpost:
1397 case AArch64::LDPXpre:
1398 case AArch64::STPXpre:
1399 case AArch64::LDPSWpre:
1400 case AArch64::LDPWpost:
1401 case AArch64::STPWpost:
1402 case AArch64::LDPWpre:
1403 case AArch64::STPWpre:
1404 case AArch64::LDPQpost:
1405 case AArch64::STPQpost:
1406 case AArch64::LDPQpre:
1407 case AArch64::STPQpre:
1408 case AArch64::LDPDpost:
1409 case AArch64::STPDpost:
1410 case AArch64::LDPDpre:
1411 case AArch64::STPDpre:
1412 case AArch64::LDPSpost:
1413 case AArch64::STPSpost:
1414 case AArch64::LDPSpre:
1415 case AArch64::STPSpre:
1416 case AArch64::STGPpre:
1417 case AArch64::STGPpost:
1418 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1419 break;
1420 }
1421
1422 switch (Opcode) {
1423 default:
1424 return Fail;
1425 case AArch64::LDPXpost:
1426 case AArch64::STPXpost:
1427 case AArch64::LDPSWpost:
1428 case AArch64::LDPXpre:
1429 case AArch64::STPXpre:
1430 case AArch64::LDPSWpre:
1431 case AArch64::STGPpre:
1432 case AArch64::STGPpost:
1433 NeedsDisjointWritebackTransfer = true;
1434 LLVM_FALLTHROUGH;
1435 case AArch64::LDNPXi:
1436 case AArch64::STNPXi:
1437 case AArch64::LDPXi:
1438 case AArch64::STPXi:
1439 case AArch64::LDPSWi:
1440 case AArch64::STGPi:
1441 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1442 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1443 break;
1444 case AArch64::LDPWpost:
1445 case AArch64::STPWpost:
1446 case AArch64::LDPWpre:
1447 case AArch64::STPWpre:
1448 NeedsDisjointWritebackTransfer = true;
1449 LLVM_FALLTHROUGH;
1450 case AArch64::LDNPWi:
1451 case AArch64::STNPWi:
1452 case AArch64::LDPWi:
1453 case AArch64::STPWi:
1454 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1455 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1456 break;
1457 case AArch64::LDNPQi:
1458 case AArch64::STNPQi:
1459 case AArch64::LDPQpost:
1460 case AArch64::STPQpost:
1461 case AArch64::LDPQi:
1462 case AArch64::STPQi:
1463 case AArch64::LDPQpre:
1464 case AArch64::STPQpre:
1465 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1466 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1467 break;
1468 case AArch64::LDNPDi:
1469 case AArch64::STNPDi:
1470 case AArch64::LDPDpost:
1471 case AArch64::STPDpost:
1472 case AArch64::LDPDi:
1473 case AArch64::STPDi:
1474 case AArch64::LDPDpre:
1475 case AArch64::STPDpre:
1476 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1477 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1478 break;
1479 case AArch64::LDNPSi:
1480 case AArch64::STNPSi:
1481 case AArch64::LDPSpost:
1482 case AArch64::STPSpost:
1483 case AArch64::LDPSi:
1484 case AArch64::STPSi:
1485 case AArch64::LDPSpre:
1486 case AArch64::STPSpre:
1487 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1488 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1489 break;
1490 }
1491
1492 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1493 Inst.addOperand(MCOperand::createImm(offset));
1494
1495 // You shouldn't load to the same register twice in an instruction...
1496 if (IsLoad && Rt == Rt2)
1497 return SoftFail;
1498
1499 // ... or do any operation that writes-back to a transfer register. But note
1500 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1501 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1502 return SoftFail;
1503
1504 return Success;
1505 }
1506
DecodeAuthLoadInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1507 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1508 uint64_t Addr,
1509 const void *Decoder) {
1510 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1511 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1512 uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1513 fieldFromInstruction(insn, 12, 9);
1514 unsigned writeback = fieldFromInstruction(insn, 11, 1);
1515
1516 switch (Inst.getOpcode()) {
1517 default:
1518 return Fail;
1519 case AArch64::LDRAAwriteback:
1520 case AArch64::LDRABwriteback:
1521 DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1522 Decoder);
1523 break;
1524 case AArch64::LDRAAindexed:
1525 case AArch64::LDRABindexed:
1526 break;
1527 }
1528
1529 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1530 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1531 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1532
1533 if (writeback && Rt == Rn && Rn != 31) {
1534 return SoftFail;
1535 }
1536
1537 return Success;
1538 }
1539
DecodeAddSubERegInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1540 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1541 uint64_t Addr,
1542 const void *Decoder) {
1543 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1544 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1545 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1546 unsigned extend = fieldFromInstruction(insn, 10, 6);
1547
1548 unsigned shift = extend & 0x7;
1549 if (shift > 4)
1550 return Fail;
1551
1552 switch (Inst.getOpcode()) {
1553 default:
1554 return Fail;
1555 case AArch64::ADDWrx:
1556 case AArch64::SUBWrx:
1557 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1558 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1559 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1560 break;
1561 case AArch64::ADDSWrx:
1562 case AArch64::SUBSWrx:
1563 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1564 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1565 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1566 break;
1567 case AArch64::ADDXrx:
1568 case AArch64::SUBXrx:
1569 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1570 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1571 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1572 break;
1573 case AArch64::ADDSXrx:
1574 case AArch64::SUBSXrx:
1575 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1576 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1577 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1578 break;
1579 case AArch64::ADDXrx64:
1580 case AArch64::SUBXrx64:
1581 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1582 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1583 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1584 break;
1585 case AArch64::SUBSXrx64:
1586 case AArch64::ADDSXrx64:
1587 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1588 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1589 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1590 break;
1591 }
1592
1593 Inst.addOperand(MCOperand::createImm(extend));
1594 return Success;
1595 }
1596
DecodeLogicalImmInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1597 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1598 uint64_t Addr,
1599 const void *Decoder) {
1600 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1601 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1602 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1603 unsigned imm;
1604
1605 if (Datasize) {
1606 if (Inst.getOpcode() == AArch64::ANDSXri)
1607 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1608 else
1609 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1610 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1611 imm = fieldFromInstruction(insn, 10, 13);
1612 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1613 return Fail;
1614 } else {
1615 if (Inst.getOpcode() == AArch64::ANDSWri)
1616 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1617 else
1618 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1619 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1620 imm = fieldFromInstruction(insn, 10, 12);
1621 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1622 return Fail;
1623 }
1624 Inst.addOperand(MCOperand::createImm(imm));
1625 return Success;
1626 }
1627
DecodeModImmInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1628 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1629 uint64_t Addr,
1630 const void *Decoder) {
1631 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1632 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1633 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1634 imm |= fieldFromInstruction(insn, 5, 5);
1635
1636 if (Inst.getOpcode() == AArch64::MOVID)
1637 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1638 else
1639 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1640
1641 Inst.addOperand(MCOperand::createImm(imm));
1642
1643 switch (Inst.getOpcode()) {
1644 default:
1645 break;
1646 case AArch64::MOVIv4i16:
1647 case AArch64::MOVIv8i16:
1648 case AArch64::MVNIv4i16:
1649 case AArch64::MVNIv8i16:
1650 case AArch64::MOVIv2i32:
1651 case AArch64::MOVIv4i32:
1652 case AArch64::MVNIv2i32:
1653 case AArch64::MVNIv4i32:
1654 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1655 break;
1656 case AArch64::MOVIv2s_msl:
1657 case AArch64::MOVIv4s_msl:
1658 case AArch64::MVNIv2s_msl:
1659 case AArch64::MVNIv4s_msl:
1660 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1661 break;
1662 }
1663
1664 return Success;
1665 }
1666
DecodeModImmTiedInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1667 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1668 uint64_t Addr,
1669 const void *Decoder) {
1670 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1671 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1672 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1673 imm |= fieldFromInstruction(insn, 5, 5);
1674
1675 // Tied operands added twice.
1676 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1677 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1678
1679 Inst.addOperand(MCOperand::createImm(imm));
1680 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1681
1682 return Success;
1683 }
1684
DecodeAdrInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1685 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1686 uint64_t Addr, const void *Decoder) {
1687 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1688 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1689 imm |= fieldFromInstruction(insn, 29, 2);
1690 const AArch64Disassembler *Dis =
1691 static_cast<const AArch64Disassembler *>(Decoder);
1692
1693 // Sign-extend the 21-bit immediate.
1694 if (imm & (1 << (21 - 1)))
1695 imm |= ~((1LL << 21) - 1);
1696
1697 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1698 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1699 Inst.addOperand(MCOperand::createImm(imm));
1700
1701 return Success;
1702 }
1703
DecodeAddSubImmShift(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1704 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1705 uint64_t Addr, const void *Decoder) {
1706 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1707 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1708 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1709 unsigned S = fieldFromInstruction(insn, 29, 1);
1710 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1711
1712 unsigned ShifterVal = (Imm >> 12) & 3;
1713 unsigned ImmVal = Imm & 0xFFF;
1714 const AArch64Disassembler *Dis =
1715 static_cast<const AArch64Disassembler *>(Decoder);
1716
1717 if (ShifterVal != 0 && ShifterVal != 1)
1718 return Fail;
1719
1720 if (Datasize) {
1721 if (Rd == 31 && !S)
1722 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1723 else
1724 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1725 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1726 } else {
1727 if (Rd == 31 && !S)
1728 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1729 else
1730 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1731 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1732 }
1733
1734 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1735 Inst.addOperand(MCOperand::createImm(ImmVal));
1736 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1737 return Success;
1738 }
1739
DecodeUnconditionalBranch(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1740 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1741 uint64_t Addr,
1742 const void *Decoder) {
1743 int64_t imm = fieldFromInstruction(insn, 0, 26);
1744 const AArch64Disassembler *Dis =
1745 static_cast<const AArch64Disassembler *>(Decoder);
1746
1747 // Sign-extend the 26-bit immediate.
1748 if (imm & (1 << (26 - 1)))
1749 imm |= ~((1LL << 26) - 1);
1750
1751 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1752 Inst.addOperand(MCOperand::createImm(imm));
1753
1754 return Success;
1755 }
1756
DecodeSystemPStateInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1757 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1758 uint64_t Addr,
1759 const void *Decoder) {
1760 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1761 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1762 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1763 uint64_t pstate_field = (op1 << 3) | op2;
1764
1765 switch (pstate_field) {
1766 case 0x01: // XAFlag
1767 case 0x02: // AXFlag
1768 return Fail;
1769 }
1770
1771 if ((pstate_field == AArch64PState::PAN ||
1772 pstate_field == AArch64PState::UAO ||
1773 pstate_field == AArch64PState::SSBS) && crm > 1)
1774 return Fail;
1775
1776 Inst.addOperand(MCOperand::createImm(pstate_field));
1777 Inst.addOperand(MCOperand::createImm(crm));
1778
1779 const AArch64Disassembler *Dis =
1780 static_cast<const AArch64Disassembler *>(Decoder);
1781 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1782 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1783 return Success;
1784 return Fail;
1785 }
1786
DecodeTestAndBranch(MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1787 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1788 uint64_t Addr, const void *Decoder) {
1789 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1790 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1791 bit |= fieldFromInstruction(insn, 19, 5);
1792 int64_t dst = fieldFromInstruction(insn, 5, 14);
1793 const AArch64Disassembler *Dis =
1794 static_cast<const AArch64Disassembler *>(Decoder);
1795
1796 // Sign-extend 14-bit immediate.
1797 if (dst & (1 << (14 - 1)))
1798 dst |= ~((1LL << 14) - 1);
1799
1800 if (fieldFromInstruction(insn, 31, 1) == 0)
1801 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1802 else
1803 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1804 Inst.addOperand(MCOperand::createImm(bit));
1805 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1806 Inst.addOperand(MCOperand::createImm(dst));
1807
1808 return Success;
1809 }
1810
DecodeGPRSeqPairsClassRegisterClass(MCInst & Inst,unsigned RegClassID,unsigned RegNo,uint64_t Addr,const void * Decoder)1811 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1812 unsigned RegClassID,
1813 unsigned RegNo,
1814 uint64_t Addr,
1815 const void *Decoder) {
1816 // Register number must be even (see CASP instruction)
1817 if (RegNo & 0x1)
1818 return Fail;
1819
1820 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1821 Inst.addOperand(MCOperand::createReg(Reg));
1822 return Success;
1823 }
1824
DecodeWSeqPairsClassRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)1825 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1826 unsigned RegNo,
1827 uint64_t Addr,
1828 const void *Decoder) {
1829 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1830 AArch64::WSeqPairsClassRegClassID,
1831 RegNo, Addr, Decoder);
1832 }
1833
DecodeXSeqPairsClassRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)1834 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1835 unsigned RegNo,
1836 uint64_t Addr,
1837 const void *Decoder) {
1838 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1839 AArch64::XSeqPairsClassRegClassID,
1840 RegNo, Addr, Decoder);
1841 }
1842
DecodeSVELogicalImmInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1843 static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst,
1844 uint32_t insn,
1845 uint64_t Addr,
1846 const void *Decoder) {
1847 unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1848 unsigned imm = fieldFromInstruction(insn, 5, 13);
1849 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1850 return Fail;
1851
1852 // The same (tied) operand is added twice to the instruction.
1853 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1854 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1855 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1856 Inst.addOperand(MCOperand::createImm(imm));
1857 return Success;
1858 }
1859
1860 template<int Bits>
DecodeSImm(llvm::MCInst & Inst,uint64_t Imm,uint64_t Address,const void * Decoder)1861 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1862 uint64_t Address, const void *Decoder) {
1863 if (Imm & ~((1LL << Bits) - 1))
1864 return Fail;
1865
1866 // Imm is a signed immediate, so sign extend it.
1867 if (Imm & (1 << (Bits - 1)))
1868 Imm |= ~((1LL << Bits) - 1);
1869
1870 Inst.addOperand(MCOperand::createImm(Imm));
1871 return Success;
1872 }
1873
1874 // Decode 8-bit signed/unsigned immediate for a given element width.
1875 template <int ElementWidth>
DecodeImm8OptLsl(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)1876 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
1877 uint64_t Addr, const void *Decoder) {
1878 unsigned Val = (uint8_t)Imm;
1879 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1880 if (ElementWidth == 8 && Shift)
1881 return Fail;
1882 Inst.addOperand(MCOperand::createImm(Val));
1883 Inst.addOperand(MCOperand::createImm(Shift));
1884 return Success;
1885 }
1886
1887 // Decode uimm4 ranged from 1-16.
DecodeSVEIncDecImm(MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)1888 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1889 uint64_t Addr, const void *Decoder) {
1890 Inst.addOperand(MCOperand::createImm(Imm + 1));
1891 return Success;
1892 }
1893