1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
16 #include "HexagonHazardRecognizer.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/CodeGen/DFAPacketizer.h"
24 #include "llvm/CodeGen/LivePhysRegs.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetOpcodes.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstrDesc.h"
44 #include "llvm/MC/MCInstrItineraries.h"
45 #include "llvm/MC/MCRegisterInfo.h"
46 #include "llvm/Support/BranchProbability.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MachineValueType.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include <cassert>
55 #include <cctype>
56 #include <cstdint>
57 #include <cstring>
58 #include <iterator>
59 #include <string>
60 #include <utility>
61
62 using namespace llvm;
63
64 #define DEBUG_TYPE "hexagon-instrinfo"
65
66 #define GET_INSTRINFO_CTOR_DTOR
67 #define GET_INSTRMAP_INFO
68 #include "HexagonDepTimingClasses.h"
69 #include "HexagonGenDFAPacketizer.inc"
70 #include "HexagonGenInstrInfo.inc"
71
72 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
73 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
74 "packetization boundary."));
75
76 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
77 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
78
79 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
80 cl::Hidden, cl::ZeroOrMore, cl::init(false),
81 cl::desc("Disable schedule adjustment for new value stores."));
82
83 static cl::opt<bool> EnableTimingClassLatency(
84 "enable-timing-class-latency", cl::Hidden, cl::init(false),
85 cl::desc("Enable timing class latency"));
86
87 static cl::opt<bool> EnableALUForwarding(
88 "enable-alu-forwarding", cl::Hidden, cl::init(true),
89 cl::desc("Enable vec alu forwarding"));
90
91 static cl::opt<bool> EnableACCForwarding(
92 "enable-acc-forwarding", cl::Hidden, cl::init(true),
93 cl::desc("Enable vec acc forwarding"));
94
95 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
96 cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
97
98 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
99 cl::init(true), cl::Hidden, cl::ZeroOrMore,
100 cl::desc("Use the DFA based hazard recognizer."));
101
102 /// Constants for Hexagon instructions.
103 const int Hexagon_MEMW_OFFSET_MAX = 4095;
104 const int Hexagon_MEMW_OFFSET_MIN = -4096;
105 const int Hexagon_MEMD_OFFSET_MAX = 8191;
106 const int Hexagon_MEMD_OFFSET_MIN = -8192;
107 const int Hexagon_MEMH_OFFSET_MAX = 2047;
108 const int Hexagon_MEMH_OFFSET_MIN = -2048;
109 const int Hexagon_MEMB_OFFSET_MAX = 1023;
110 const int Hexagon_MEMB_OFFSET_MIN = -1024;
111 const int Hexagon_ADDI_OFFSET_MAX = 32767;
112 const int Hexagon_ADDI_OFFSET_MIN = -32768;
113
114 // Pin the vtable to this file.
anchor()115 void HexagonInstrInfo::anchor() {}
116
HexagonInstrInfo(HexagonSubtarget & ST)117 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
118 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
119 Subtarget(ST) {}
120
121 namespace llvm {
122 namespace HexagonFUnits {
123 bool isSlot0Only(unsigned units);
124 }
125 }
126
isIntRegForSubInst(unsigned Reg)127 static bool isIntRegForSubInst(unsigned Reg) {
128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
130 }
131
isDblRegForSubInst(unsigned Reg,const HexagonRegisterInfo & HRI)132 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
133 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
134 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
135 }
136
137 /// Calculate number of instructions excluding the debug instructions.
nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,MachineBasicBlock::const_instr_iterator MIE)138 static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
139 MachineBasicBlock::const_instr_iterator MIE) {
140 unsigned Count = 0;
141 for (; MIB != MIE; ++MIB) {
142 if (!MIB->isDebugInstr())
143 ++Count;
144 }
145 return Count;
146 }
147
148 /// Find the hardware loop instruction used to set-up the specified loop.
149 /// On Hexagon, we have two instructions used to set-up the hardware loop
150 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
151 /// to indicate the end of a loop.
findLoopInstr(MachineBasicBlock * BB,unsigned EndLoopOp,MachineBasicBlock * TargetBB,SmallPtrSet<MachineBasicBlock *,8> & Visited) const152 MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,
153 unsigned EndLoopOp, MachineBasicBlock *TargetBB,
154 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
155 unsigned LOOPi;
156 unsigned LOOPr;
157 if (EndLoopOp == Hexagon::ENDLOOP0) {
158 LOOPi = Hexagon::J2_loop0i;
159 LOOPr = Hexagon::J2_loop0r;
160 } else { // EndLoopOp == Hexagon::EndLOOP1
161 LOOPi = Hexagon::J2_loop1i;
162 LOOPr = Hexagon::J2_loop1r;
163 }
164
165 // The loop set-up instruction will be in a predecessor block
166 for (MachineBasicBlock *PB : BB->predecessors()) {
167 // If this has been visited, already skip it.
168 if (!Visited.insert(PB).second)
169 continue;
170 if (PB == BB)
171 continue;
172 for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
173 unsigned Opc = I->getOpcode();
174 if (Opc == LOOPi || Opc == LOOPr)
175 return &*I;
176 // We've reached a different loop, which means the loop01 has been
177 // removed.
178 if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
179 return nullptr;
180 }
181 // Check the predecessors for the LOOP instruction.
182 if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
183 return Loop;
184 }
185 return nullptr;
186 }
187
188 /// Gather register def/uses from MI.
189 /// This treats possible (predicated) defs as actually happening ones
190 /// (conservatively).
parseOperands(const MachineInstr & MI,SmallVector<unsigned,4> & Defs,SmallVector<unsigned,8> & Uses)191 static inline void parseOperands(const MachineInstr &MI,
192 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
193 Defs.clear();
194 Uses.clear();
195
196 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
197 const MachineOperand &MO = MI.getOperand(i);
198
199 if (!MO.isReg())
200 continue;
201
202 Register Reg = MO.getReg();
203 if (!Reg)
204 continue;
205
206 if (MO.isUse())
207 Uses.push_back(MO.getReg());
208
209 if (MO.isDef())
210 Defs.push_back(MO.getReg());
211 }
212 }
213
214 // Position dependent, so check twice for swap.
isDuplexPairMatch(unsigned Ga,unsigned Gb)215 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
216 switch (Ga) {
217 case HexagonII::HSIG_None:
218 default:
219 return false;
220 case HexagonII::HSIG_L1:
221 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
222 case HexagonII::HSIG_L2:
223 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224 Gb == HexagonII::HSIG_A);
225 case HexagonII::HSIG_S1:
226 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
227 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
228 case HexagonII::HSIG_S2:
229 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
230 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
231 Gb == HexagonII::HSIG_A);
232 case HexagonII::HSIG_A:
233 return (Gb == HexagonII::HSIG_A);
234 case HexagonII::HSIG_Compound:
235 return (Gb == HexagonII::HSIG_Compound);
236 }
237 return false;
238 }
239
240 /// isLoadFromStackSlot - If the specified machine instruction is a direct
241 /// load from a stack slot, return the virtual or physical register number of
242 /// the destination along with the FrameIndex of the loaded stack slot. If
243 /// not, return 0. This predicate must return 0 if the instruction has
244 /// any side effects other than loading from the stack slot.
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const245 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
246 int &FrameIndex) const {
247 switch (MI.getOpcode()) {
248 default:
249 break;
250 case Hexagon::L2_loadri_io:
251 case Hexagon::L2_loadrd_io:
252 case Hexagon::V6_vL32b_ai:
253 case Hexagon::V6_vL32b_nt_ai:
254 case Hexagon::V6_vL32Ub_ai:
255 case Hexagon::LDriw_pred:
256 case Hexagon::LDriw_ctr:
257 case Hexagon::PS_vloadrq_ai:
258 case Hexagon::PS_vloadrw_ai:
259 case Hexagon::PS_vloadrw_nt_ai: {
260 const MachineOperand OpFI = MI.getOperand(1);
261 if (!OpFI.isFI())
262 return 0;
263 const MachineOperand OpOff = MI.getOperand(2);
264 if (!OpOff.isImm() || OpOff.getImm() != 0)
265 return 0;
266 FrameIndex = OpFI.getIndex();
267 return MI.getOperand(0).getReg();
268 }
269
270 case Hexagon::L2_ploadrit_io:
271 case Hexagon::L2_ploadrif_io:
272 case Hexagon::L2_ploadrdt_io:
273 case Hexagon::L2_ploadrdf_io: {
274 const MachineOperand OpFI = MI.getOperand(2);
275 if (!OpFI.isFI())
276 return 0;
277 const MachineOperand OpOff = MI.getOperand(3);
278 if (!OpOff.isImm() || OpOff.getImm() != 0)
279 return 0;
280 FrameIndex = OpFI.getIndex();
281 return MI.getOperand(0).getReg();
282 }
283 }
284
285 return 0;
286 }
287
288 /// isStoreToStackSlot - If the specified machine instruction is a direct
289 /// store to a stack slot, return the virtual or physical register number of
290 /// the source reg along with the FrameIndex of the loaded stack slot. If
291 /// not, return 0. This predicate must return 0 if the instruction has
292 /// any side effects other than storing to the stack slot.
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const293 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
294 int &FrameIndex) const {
295 switch (MI.getOpcode()) {
296 default:
297 break;
298 case Hexagon::S2_storerb_io:
299 case Hexagon::S2_storerh_io:
300 case Hexagon::S2_storeri_io:
301 case Hexagon::S2_storerd_io:
302 case Hexagon::V6_vS32b_ai:
303 case Hexagon::V6_vS32Ub_ai:
304 case Hexagon::STriw_pred:
305 case Hexagon::STriw_ctr:
306 case Hexagon::PS_vstorerq_ai:
307 case Hexagon::PS_vstorerw_ai: {
308 const MachineOperand &OpFI = MI.getOperand(0);
309 if (!OpFI.isFI())
310 return 0;
311 const MachineOperand &OpOff = MI.getOperand(1);
312 if (!OpOff.isImm() || OpOff.getImm() != 0)
313 return 0;
314 FrameIndex = OpFI.getIndex();
315 return MI.getOperand(2).getReg();
316 }
317
318 case Hexagon::S2_pstorerbt_io:
319 case Hexagon::S2_pstorerbf_io:
320 case Hexagon::S2_pstorerht_io:
321 case Hexagon::S2_pstorerhf_io:
322 case Hexagon::S2_pstorerit_io:
323 case Hexagon::S2_pstorerif_io:
324 case Hexagon::S2_pstorerdt_io:
325 case Hexagon::S2_pstorerdf_io: {
326 const MachineOperand &OpFI = MI.getOperand(1);
327 if (!OpFI.isFI())
328 return 0;
329 const MachineOperand &OpOff = MI.getOperand(2);
330 if (!OpOff.isImm() || OpOff.getImm() != 0)
331 return 0;
332 FrameIndex = OpFI.getIndex();
333 return MI.getOperand(3).getReg();
334 }
335 }
336
337 return 0;
338 }
339
340 /// This function checks if the instruction or bundle of instructions
341 /// has load from stack slot and returns frameindex and machine memory
342 /// operand of that instruction if true.
hasLoadFromStackSlot(const MachineInstr & MI,SmallVectorImpl<const MachineMemOperand * > & Accesses) const343 bool HexagonInstrInfo::hasLoadFromStackSlot(
344 const MachineInstr &MI,
345 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
346 if (MI.isBundle()) {
347 const MachineBasicBlock *MBB = MI.getParent();
348 MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
349 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
350 if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
351 return true;
352 return false;
353 }
354
355 return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
356 }
357
358 /// This function checks if the instruction or bundle of instructions
359 /// has store to stack slot and returns frameindex and machine memory
360 /// operand of that instruction if true.
hasStoreToStackSlot(const MachineInstr & MI,SmallVectorImpl<const MachineMemOperand * > & Accesses) const361 bool HexagonInstrInfo::hasStoreToStackSlot(
362 const MachineInstr &MI,
363 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
364 if (MI.isBundle()) {
365 const MachineBasicBlock *MBB = MI.getParent();
366 MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
367 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
368 if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
369 return true;
370 return false;
371 }
372
373 return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
374 }
375
376 /// This function can analyze one/two way branching only and should (mostly) be
377 /// called by target independent side.
378 /// First entry is always the opcode of the branching instruction, except when
379 /// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
380 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
381 /// e.g. Jump_c p will have
382 /// Cond[0] = Jump_c
383 /// Cond[1] = p
384 /// HW-loop ENDLOOP:
385 /// Cond[0] = ENDLOOP
386 /// Cond[1] = MBB
387 /// New value jump:
388 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
389 /// Cond[1] = R
390 /// Cond[2] = Imm
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const391 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
392 MachineBasicBlock *&TBB,
393 MachineBasicBlock *&FBB,
394 SmallVectorImpl<MachineOperand> &Cond,
395 bool AllowModify) const {
396 TBB = nullptr;
397 FBB = nullptr;
398 Cond.clear();
399
400 // If the block has no terminators, it just falls into the block after it.
401 MachineBasicBlock::instr_iterator I = MBB.instr_end();
402 if (I == MBB.instr_begin())
403 return false;
404
405 // A basic block may looks like this:
406 //
407 // [ insn
408 // EH_LABEL
409 // insn
410 // insn
411 // insn
412 // EH_LABEL
413 // insn ]
414 //
415 // It has two succs but does not have a terminator
416 // Don't know how to handle it.
417 do {
418 --I;
419 if (I->isEHLabel())
420 // Don't analyze EH branches.
421 return true;
422 } while (I != MBB.instr_begin());
423
424 I = MBB.instr_end();
425 --I;
426
427 while (I->isDebugInstr()) {
428 if (I == MBB.instr_begin())
429 return false;
430 --I;
431 }
432
433 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
434 I->getOperand(0).isMBB();
435 // Delete the J2_jump if it's equivalent to a fall-through.
436 if (AllowModify && JumpToBlock &&
437 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
438 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
439 I->eraseFromParent();
440 I = MBB.instr_end();
441 if (I == MBB.instr_begin())
442 return false;
443 --I;
444 }
445 if (!isUnpredicatedTerminator(*I))
446 return false;
447
448 // Get the last instruction in the block.
449 MachineInstr *LastInst = &*I;
450 MachineInstr *SecondLastInst = nullptr;
451 // Find one more terminator if present.
452 while (true) {
453 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
454 if (!SecondLastInst)
455 SecondLastInst = &*I;
456 else
457 // This is a third branch.
458 return true;
459 }
460 if (I == MBB.instr_begin())
461 break;
462 --I;
463 }
464
465 int LastOpcode = LastInst->getOpcode();
466 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
467 // If the branch target is not a basic block, it could be a tail call.
468 // (It is, if the target is a function.)
469 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
470 return true;
471 if (SecLastOpcode == Hexagon::J2_jump &&
472 !SecondLastInst->getOperand(0).isMBB())
473 return true;
474
475 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
476 bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
477
478 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
479 return true;
480
481 // If there is only one terminator instruction, process it.
482 if (LastInst && !SecondLastInst) {
483 if (LastOpcode == Hexagon::J2_jump) {
484 TBB = LastInst->getOperand(0).getMBB();
485 return false;
486 }
487 if (isEndLoopN(LastOpcode)) {
488 TBB = LastInst->getOperand(0).getMBB();
489 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
490 Cond.push_back(LastInst->getOperand(0));
491 return false;
492 }
493 if (LastOpcodeHasJMP_c) {
494 TBB = LastInst->getOperand(1).getMBB();
495 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
496 Cond.push_back(LastInst->getOperand(0));
497 return false;
498 }
499 // Only supporting rr/ri versions of new-value jumps.
500 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
501 TBB = LastInst->getOperand(2).getMBB();
502 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
503 Cond.push_back(LastInst->getOperand(0));
504 Cond.push_back(LastInst->getOperand(1));
505 return false;
506 }
507 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
508 << " with one jump\n";);
509 // Otherwise, don't know what this is.
510 return true;
511 }
512
513 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
514 bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
515 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
516 if (!SecondLastInst->getOperand(1).isMBB())
517 return true;
518 TBB = SecondLastInst->getOperand(1).getMBB();
519 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
520 Cond.push_back(SecondLastInst->getOperand(0));
521 FBB = LastInst->getOperand(0).getMBB();
522 return false;
523 }
524
525 // Only supporting rr/ri versions of new-value jumps.
526 if (SecLastOpcodeHasNVJump &&
527 (SecondLastInst->getNumExplicitOperands() == 3) &&
528 (LastOpcode == Hexagon::J2_jump)) {
529 TBB = SecondLastInst->getOperand(2).getMBB();
530 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
531 Cond.push_back(SecondLastInst->getOperand(0));
532 Cond.push_back(SecondLastInst->getOperand(1));
533 FBB = LastInst->getOperand(0).getMBB();
534 return false;
535 }
536
537 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
538 // executed, so remove it.
539 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
540 TBB = SecondLastInst->getOperand(0).getMBB();
541 I = LastInst->getIterator();
542 if (AllowModify)
543 I->eraseFromParent();
544 return false;
545 }
546
547 // If the block ends with an ENDLOOP, and J2_jump, handle it.
548 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
549 TBB = SecondLastInst->getOperand(0).getMBB();
550 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
551 Cond.push_back(SecondLastInst->getOperand(0));
552 FBB = LastInst->getOperand(0).getMBB();
553 return false;
554 }
555 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
556 << " with two jumps";);
557 // Otherwise, can't handle this.
558 return true;
559 }
560
removeBranch(MachineBasicBlock & MBB,int * BytesRemoved) const561 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
562 int *BytesRemoved) const {
563 assert(!BytesRemoved && "code size not handled");
564
565 LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
566 MachineBasicBlock::iterator I = MBB.end();
567 unsigned Count = 0;
568 while (I != MBB.begin()) {
569 --I;
570 if (I->isDebugInstr())
571 continue;
572 // Only removing branches from end of MBB.
573 if (!I->isBranch())
574 return Count;
575 if (Count && (I->getOpcode() == Hexagon::J2_jump))
576 llvm_unreachable("Malformed basic block: unconditional branch not last");
577 MBB.erase(&MBB.back());
578 I = MBB.end();
579 ++Count;
580 }
581 return Count;
582 }
583
insertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL,int * BytesAdded) const584 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
585 MachineBasicBlock *TBB,
586 MachineBasicBlock *FBB,
587 ArrayRef<MachineOperand> Cond,
588 const DebugLoc &DL,
589 int *BytesAdded) const {
590 unsigned BOpc = Hexagon::J2_jump;
591 unsigned BccOpc = Hexagon::J2_jumpt;
592 assert(validateBranchCond(Cond) && "Invalid branching condition");
593 assert(TBB && "insertBranch must not be told to insert a fallthrough");
594 assert(!BytesAdded && "code size not handled");
595
596 // Check if reverseBranchCondition has asked to reverse this branch
597 // If we want to reverse the branch an odd number of times, we want
598 // J2_jumpf.
599 if (!Cond.empty() && Cond[0].isImm())
600 BccOpc = Cond[0].getImm();
601
602 if (!FBB) {
603 if (Cond.empty()) {
604 // Due to a bug in TailMerging/CFG Optimization, we need to add a
605 // special case handling of a predicated jump followed by an
606 // unconditional jump. If not, Tail Merging and CFG Optimization go
607 // into an infinite loop.
608 MachineBasicBlock *NewTBB, *NewFBB;
609 SmallVector<MachineOperand, 4> Cond;
610 auto Term = MBB.getFirstTerminator();
611 if (Term != MBB.end() && isPredicated(*Term) &&
612 !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
613 MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
614 reverseBranchCondition(Cond);
615 removeBranch(MBB);
616 return insertBranch(MBB, TBB, nullptr, Cond, DL);
617 }
618 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
619 } else if (isEndLoopN(Cond[0].getImm())) {
620 int EndLoopOp = Cond[0].getImm();
621 assert(Cond[1].isMBB());
622 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
623 // Check for it, and change the BB target if needed.
624 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
625 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
626 VisitedBBs);
627 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
628 Loop->getOperand(0).setMBB(TBB);
629 // Add the ENDLOOP after the finding the LOOP0.
630 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
631 } else if (isNewValueJump(Cond[0].getImm())) {
632 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
633 // New value jump
634 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
635 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
636 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
637 LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
638 << printMBBReference(MBB););
639 if (Cond[2].isReg()) {
640 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
641 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
642 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
643 } else if(Cond[2].isImm()) {
644 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
645 addImm(Cond[2].getImm()).addMBB(TBB);
646 } else
647 llvm_unreachable("Invalid condition for branching");
648 } else {
649 assert((Cond.size() == 2) && "Malformed cond vector");
650 const MachineOperand &RO = Cond[1];
651 unsigned Flags = getUndefRegState(RO.isUndef());
652 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
653 }
654 return 1;
655 }
656 assert((!Cond.empty()) &&
657 "Cond. cannot be empty when multiple branchings are required");
658 assert((!isNewValueJump(Cond[0].getImm())) &&
659 "NV-jump cannot be inserted with another branch");
660 // Special case for hardware loops. The condition is a basic block.
661 if (isEndLoopN(Cond[0].getImm())) {
662 int EndLoopOp = Cond[0].getImm();
663 assert(Cond[1].isMBB());
664 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
665 // Check for it, and change the BB target if needed.
666 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
667 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
668 VisitedBBs);
669 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
670 Loop->getOperand(0).setMBB(TBB);
671 // Add the ENDLOOP after the finding the LOOP0.
672 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
673 } else {
674 const MachineOperand &RO = Cond[1];
675 unsigned Flags = getUndefRegState(RO.isUndef());
676 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
677 }
678 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
679
680 return 2;
681 }
682
683 namespace {
684 class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
685 MachineInstr *Loop, *EndLoop;
686 MachineFunction *MF;
687 const HexagonInstrInfo *TII;
688 int64_t TripCount;
689 Register LoopCount;
690 DebugLoc DL;
691
692 public:
HexagonPipelinerLoopInfo(MachineInstr * Loop,MachineInstr * EndLoop)693 HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
694 : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
695 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
696 DL(Loop->getDebugLoc()) {
697 // Inspect the Loop instruction up-front, as it may be deleted when we call
698 // createTripCountGreaterCondition.
699 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
700 ? -1
701 : Loop->getOperand(1).getImm();
702 if (TripCount == -1)
703 LoopCount = Loop->getOperand(1).getReg();
704 }
705
shouldIgnoreForPipelining(const MachineInstr * MI) const706 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
707 // Only ignore the terminator.
708 return MI == EndLoop;
709 }
710
711 Optional<bool>
createTripCountGreaterCondition(int TC,MachineBasicBlock & MBB,SmallVectorImpl<MachineOperand> & Cond)712 createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
713 SmallVectorImpl<MachineOperand> &Cond) override {
714 if (TripCount == -1) {
715 // Check if we're done with the loop.
716 unsigned Done = TII->createVR(MF, MVT::i1);
717 MachineInstr *NewCmp = BuildMI(&MBB, DL,
718 TII->get(Hexagon::C2_cmpgtui), Done)
719 .addReg(LoopCount)
720 .addImm(TC);
721 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
722 Cond.push_back(NewCmp->getOperand(0));
723 return {};
724 }
725
726 return TripCount > TC;
727 }
728
setPreheader(MachineBasicBlock * NewPreheader)729 void setPreheader(MachineBasicBlock *NewPreheader) override {
730 NewPreheader->splice(NewPreheader->getFirstTerminator(), Loop->getParent(),
731 Loop);
732 }
733
adjustTripCount(int TripCountAdjust)734 void adjustTripCount(int TripCountAdjust) override {
735 // If the loop trip count is a compile-time value, then just change the
736 // value.
737 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
738 Loop->getOpcode() == Hexagon::J2_loop1i) {
739 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
740 assert(TripCount > 0 && "Can't create an empty or negative loop!");
741 Loop->getOperand(1).setImm(TripCount);
742 return;
743 }
744
745 // The loop trip count is a run-time value. We generate code to subtract
746 // one from the trip count, and update the loop instruction.
747 Register LoopCount = Loop->getOperand(1).getReg();
748 Register NewLoopCount = TII->createVR(MF, MVT::i32);
749 BuildMI(*Loop->getParent(), Loop, Loop->getDebugLoc(),
750 TII->get(Hexagon::A2_addi), NewLoopCount)
751 .addReg(LoopCount)
752 .addImm(TripCountAdjust);
753 Loop->getOperand(1).setReg(NewLoopCount);
754 }
755
disposed()756 void disposed() override { Loop->eraseFromParent(); }
757 };
758 } // namespace
759
760 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
analyzeLoopForPipelining(MachineBasicBlock * LoopBB) const761 HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
762 // We really "analyze" only hardware loops right now.
763 MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
764
765 if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
766 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
767 MachineInstr *LoopInst = findLoopInstr(
768 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
769 if (LoopInst)
770 return std::make_unique<HexagonPipelinerLoopInfo>(LoopInst, &*I);
771 }
772 return nullptr;
773 }
774
isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,BranchProbability Probability) const775 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
776 unsigned NumCycles, unsigned ExtraPredCycles,
777 BranchProbability Probability) const {
778 return nonDbgBBSize(&MBB) <= 3;
779 }
780
isProfitableToIfCvt(MachineBasicBlock & TMBB,unsigned NumTCycles,unsigned ExtraTCycles,MachineBasicBlock & FMBB,unsigned NumFCycles,unsigned ExtraFCycles,BranchProbability Probability) const781 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
782 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
783 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
784 const {
785 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
786 }
787
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumInstrs,BranchProbability Probability) const788 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
789 unsigned NumInstrs, BranchProbability Probability) const {
790 return NumInstrs <= 4;
791 }
792
getLiveInRegsAt(LivePhysRegs & Regs,const MachineInstr & MI)793 static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
794 SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;
795 const MachineBasicBlock &B = *MI.getParent();
796 Regs.addLiveIns(B);
797 auto E = MachineBasicBlock::const_iterator(MI.getIterator());
798 for (auto I = B.begin(); I != E; ++I) {
799 Clobbers.clear();
800 Regs.stepForward(*I, Clobbers);
801 }
802 }
803
getLiveOutRegsAt(LivePhysRegs & Regs,const MachineInstr & MI)804 static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
805 const MachineBasicBlock &B = *MI.getParent();
806 Regs.addLiveOuts(B);
807 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
808 for (auto I = B.rbegin(); I != E; ++I)
809 Regs.stepBackward(*I);
810 }
811
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const812 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
813 MachineBasicBlock::iterator I,
814 const DebugLoc &DL, MCRegister DestReg,
815 MCRegister SrcReg, bool KillSrc) const {
816 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
817 unsigned KillFlag = getKillRegState(KillSrc);
818
819 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
820 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
821 .addReg(SrcReg, KillFlag);
822 return;
823 }
824 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
825 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
826 .addReg(SrcReg, KillFlag);
827 return;
828 }
829 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
830 // Map Pd = Ps to Pd = or(Ps, Ps).
831 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
832 .addReg(SrcReg).addReg(SrcReg, KillFlag);
833 return;
834 }
835 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
836 Hexagon::IntRegsRegClass.contains(SrcReg)) {
837 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
838 .addReg(SrcReg, KillFlag);
839 return;
840 }
841 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
842 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
843 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
844 .addReg(SrcReg, KillFlag);
845 return;
846 }
847 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
848 Hexagon::IntRegsRegClass.contains(SrcReg)) {
849 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
850 .addReg(SrcReg, KillFlag);
851 return;
852 }
853 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
854 Hexagon::IntRegsRegClass.contains(DestReg)) {
855 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
856 .addReg(SrcReg, KillFlag);
857 return;
858 }
859 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
860 Hexagon::PredRegsRegClass.contains(DestReg)) {
861 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
862 .addReg(SrcReg, KillFlag);
863 return;
864 }
865 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
866 Hexagon::IntRegsRegClass.contains(DestReg)) {
867 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
868 .addReg(SrcReg, KillFlag);
869 return;
870 }
871 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
872 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
873 addReg(SrcReg, KillFlag);
874 return;
875 }
876 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
877 LivePhysRegs LiveAtMI(HRI);
878 getLiveInRegsAt(LiveAtMI, *I);
879 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
880 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
881 unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
882 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
883 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
884 .addReg(SrcHi, KillFlag | UndefHi)
885 .addReg(SrcLo, KillFlag | UndefLo);
886 return;
887 }
888 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
889 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
890 .addReg(SrcReg)
891 .addReg(SrcReg, KillFlag);
892 return;
893 }
894 if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
895 Hexagon::HvxVRRegClass.contains(DestReg)) {
896 llvm_unreachable("Unimplemented pred to vec");
897 return;
898 }
899 if (Hexagon::HvxQRRegClass.contains(DestReg) &&
900 Hexagon::HvxVRRegClass.contains(SrcReg)) {
901 llvm_unreachable("Unimplemented vec to pred");
902 return;
903 }
904
905 #ifndef NDEBUG
906 // Show the invalid registers to ease debugging.
907 dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
908 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
909 #endif
910 llvm_unreachable("Unimplemented");
911 }
912
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const913 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
914 MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI,
915 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
916 DebugLoc DL = MBB.findDebugLoc(I);
917 MachineFunction &MF = *MBB.getParent();
918 MachineFrameInfo &MFI = MF.getFrameInfo();
919 unsigned KillFlag = getKillRegState(isKill);
920
921 MachineMemOperand *MMO = MF.getMachineMemOperand(
922 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
923 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
924
925 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
926 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
927 .addFrameIndex(FI).addImm(0)
928 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
929 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
930 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
931 .addFrameIndex(FI).addImm(0)
932 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
933 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
934 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
935 .addFrameIndex(FI).addImm(0)
936 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
937 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
938 BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
939 .addFrameIndex(FI).addImm(0)
940 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
941 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
942 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
943 .addFrameIndex(FI).addImm(0)
944 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
945 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
946 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai))
947 .addFrameIndex(FI).addImm(0)
948 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
949 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
950 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai))
951 .addFrameIndex(FI).addImm(0)
952 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
953 } else {
954 llvm_unreachable("Unimplemented");
955 }
956 }
957
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const958 void HexagonInstrInfo::loadRegFromStackSlot(
959 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
960 int FI, const TargetRegisterClass *RC,
961 const TargetRegisterInfo *TRI) const {
962 DebugLoc DL = MBB.findDebugLoc(I);
963 MachineFunction &MF = *MBB.getParent();
964 MachineFrameInfo &MFI = MF.getFrameInfo();
965
966 MachineMemOperand *MMO = MF.getMachineMemOperand(
967 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
968 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
969
970 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
971 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
972 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
973 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
974 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
975 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
976 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
977 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
978 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
979 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
980 BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
981 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
982 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
983 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
984 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
985 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
986 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg)
987 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
988 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
989 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg)
990 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
991 } else {
992 llvm_unreachable("Can't store this register to stack slot");
993 }
994 }
995
996 /// expandPostRAPseudo - This function is called for all pseudo instructions
997 /// that remain after register allocation. Many pseudo instructions are
998 /// created to help register allocation. This is the place to convert them
999 /// into real instructions. The target can edit MI in place, or it can insert
1000 /// new instructions and erase MI. The function should return true if
1001 /// anything was changed.
expandPostRAPseudo(MachineInstr & MI) const1002 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1003 MachineBasicBlock &MBB = *MI.getParent();
1004 MachineFunction &MF = *MBB.getParent();
1005 MachineRegisterInfo &MRI = MF.getRegInfo();
1006 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1007 LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1008 DebugLoc DL = MI.getDebugLoc();
1009 unsigned Opc = MI.getOpcode();
1010
1011 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1012 Register Mx = MI.getOperand(MxOp).getReg();
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1014 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1015 .add(MI.getOperand((HasImm ? 5 : 4)));
1016 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1017 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1018 if (HasImm)
1019 MIB.add(MI.getOperand(4));
1020 MIB.addReg(CSx, RegState::Implicit);
1021 MBB.erase(MI);
1022 return true;
1023 };
1024
1025 auto UseAligned = [&] (const MachineInstr &MI, unsigned NeedAlign) {
1026 if (MI.memoperands().empty())
1027 return false;
1028 return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
1029 return MMO->getAlign() >= NeedAlign;
1030 });
1031 };
1032
1033 switch (Opc) {
1034 case TargetOpcode::COPY: {
1035 MachineOperand &MD = MI.getOperand(0);
1036 MachineOperand &MS = MI.getOperand(1);
1037 MachineBasicBlock::iterator MBBI = MI.getIterator();
1038 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1039 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1040 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1041 }
1042 MBB.erase(MBBI);
1043 return true;
1044 }
1045 case Hexagon::PS_aligna:
1046 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1047 .addReg(HRI.getFrameRegister())
1048 .addImm(-MI.getOperand(1).getImm());
1049 MBB.erase(MI);
1050 return true;
1051 case Hexagon::V6_vassignp: {
1052 Register SrcReg = MI.getOperand(1).getReg();
1053 Register DstReg = MI.getOperand(0).getReg();
1054 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1055 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1056 getLiveInRegsAt(LiveIn, MI);
1057 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1058 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
1059 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1060 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1061 .addReg(SrcHi, UndefHi)
1062 .addReg(SrcLo, Kill | UndefLo);
1063 MBB.erase(MI);
1064 return true;
1065 }
1066 case Hexagon::V6_lo: {
1067 Register SrcReg = MI.getOperand(1).getReg();
1068 Register DstReg = MI.getOperand(0).getReg();
1069 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1070 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1071 MBB.erase(MI);
1072 MRI.clearKillFlags(SrcSubLo);
1073 return true;
1074 }
1075 case Hexagon::V6_hi: {
1076 Register SrcReg = MI.getOperand(1).getReg();
1077 Register DstReg = MI.getOperand(0).getReg();
1078 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1079 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1080 MBB.erase(MI);
1081 MRI.clearKillFlags(SrcSubHi);
1082 return true;
1083 }
1084 case Hexagon::PS_vloadrv_ai: {
1085 Register DstReg = MI.getOperand(0).getReg();
1086 const MachineOperand &BaseOp = MI.getOperand(1);
1087 assert(BaseOp.getSubReg() == 0);
1088 int Offset = MI.getOperand(2).getImm();
1089 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1090 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1091 : Hexagon::V6_vL32Ub_ai;
1092 BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1093 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1094 .addImm(Offset)
1095 .cloneMemRefs(MI);
1096 MBB.erase(MI);
1097 return true;
1098 }
1099 case Hexagon::PS_vloadrw_ai: {
1100 Register DstReg = MI.getOperand(0).getReg();
1101 const MachineOperand &BaseOp = MI.getOperand(1);
1102 assert(BaseOp.getSubReg() == 0);
1103 int Offset = MI.getOperand(2).getImm();
1104 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1105 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1106 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1107 : Hexagon::V6_vL32Ub_ai;
1108 BuildMI(MBB, MI, DL, get(NewOpc),
1109 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1110 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1111 .addImm(Offset)
1112 .cloneMemRefs(MI);
1113 BuildMI(MBB, MI, DL, get(NewOpc),
1114 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1115 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1116 .addImm(Offset + VecOffset)
1117 .cloneMemRefs(MI);
1118 MBB.erase(MI);
1119 return true;
1120 }
1121 case Hexagon::PS_vstorerv_ai: {
1122 const MachineOperand &SrcOp = MI.getOperand(2);
1123 assert(SrcOp.getSubReg() == 0);
1124 const MachineOperand &BaseOp = MI.getOperand(0);
1125 assert(BaseOp.getSubReg() == 0);
1126 int Offset = MI.getOperand(1).getImm();
1127 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1128 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1129 : Hexagon::V6_vS32Ub_ai;
1130 BuildMI(MBB, MI, DL, get(NewOpc))
1131 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1132 .addImm(Offset)
1133 .addReg(SrcOp.getReg(), getRegState(SrcOp))
1134 .cloneMemRefs(MI);
1135 MBB.erase(MI);
1136 return true;
1137 }
1138 case Hexagon::PS_vstorerw_ai: {
1139 Register SrcReg = MI.getOperand(2).getReg();
1140 const MachineOperand &BaseOp = MI.getOperand(0);
1141 assert(BaseOp.getSubReg() == 0);
1142 int Offset = MI.getOperand(1).getImm();
1143 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1144 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
1145 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1146 : Hexagon::V6_vS32Ub_ai;
1147 BuildMI(MBB, MI, DL, get(NewOpc))
1148 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1149 .addImm(Offset)
1150 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo))
1151 .cloneMemRefs(MI);
1152 BuildMI(MBB, MI, DL, get(NewOpc))
1153 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1154 .addImm(Offset + VecOffset)
1155 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi))
1156 .cloneMemRefs(MI);
1157 MBB.erase(MI);
1158 return true;
1159 }
1160 case Hexagon::PS_true: {
1161 Register Reg = MI.getOperand(0).getReg();
1162 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1163 .addReg(Reg, RegState::Undef)
1164 .addReg(Reg, RegState::Undef);
1165 MBB.erase(MI);
1166 return true;
1167 }
1168 case Hexagon::PS_false: {
1169 Register Reg = MI.getOperand(0).getReg();
1170 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1171 .addReg(Reg, RegState::Undef)
1172 .addReg(Reg, RegState::Undef);
1173 MBB.erase(MI);
1174 return true;
1175 }
1176 case Hexagon::PS_qtrue: {
1177 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1178 .addReg(Hexagon::V0, RegState::Undef)
1179 .addReg(Hexagon::V0, RegState::Undef);
1180 MBB.erase(MI);
1181 return true;
1182 }
1183 case Hexagon::PS_qfalse: {
1184 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1185 .addReg(Hexagon::V0, RegState::Undef)
1186 .addReg(Hexagon::V0, RegState::Undef);
1187 MBB.erase(MI);
1188 return true;
1189 }
1190 case Hexagon::PS_vdd0: {
1191 Register Vd = MI.getOperand(0).getReg();
1192 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1193 .addReg(Vd, RegState::Undef)
1194 .addReg(Vd, RegState::Undef);
1195 MBB.erase(MI);
1196 return true;
1197 }
1198 case Hexagon::PS_vmulw: {
1199 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1200 Register DstReg = MI.getOperand(0).getReg();
1201 Register Src1Reg = MI.getOperand(1).getReg();
1202 Register Src2Reg = MI.getOperand(2).getReg();
1203 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1204 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1205 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1206 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1207 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1208 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1209 .addReg(Src1SubHi)
1210 .addReg(Src2SubHi);
1211 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1212 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1213 .addReg(Src1SubLo)
1214 .addReg(Src2SubLo);
1215 MBB.erase(MI);
1216 MRI.clearKillFlags(Src1SubHi);
1217 MRI.clearKillFlags(Src1SubLo);
1218 MRI.clearKillFlags(Src2SubHi);
1219 MRI.clearKillFlags(Src2SubLo);
1220 return true;
1221 }
1222 case Hexagon::PS_vmulw_acc: {
1223 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1224 Register DstReg = MI.getOperand(0).getReg();
1225 Register Src1Reg = MI.getOperand(1).getReg();
1226 Register Src2Reg = MI.getOperand(2).getReg();
1227 Register Src3Reg = MI.getOperand(3).getReg();
1228 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1229 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1230 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1231 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1232 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1233 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1234 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1235 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1236 .addReg(Src1SubHi)
1237 .addReg(Src2SubHi)
1238 .addReg(Src3SubHi);
1239 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1240 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1241 .addReg(Src1SubLo)
1242 .addReg(Src2SubLo)
1243 .addReg(Src3SubLo);
1244 MBB.erase(MI);
1245 MRI.clearKillFlags(Src1SubHi);
1246 MRI.clearKillFlags(Src1SubLo);
1247 MRI.clearKillFlags(Src2SubHi);
1248 MRI.clearKillFlags(Src2SubLo);
1249 MRI.clearKillFlags(Src3SubHi);
1250 MRI.clearKillFlags(Src3SubLo);
1251 return true;
1252 }
1253 case Hexagon::PS_pselect: {
1254 const MachineOperand &Op0 = MI.getOperand(0);
1255 const MachineOperand &Op1 = MI.getOperand(1);
1256 const MachineOperand &Op2 = MI.getOperand(2);
1257 const MachineOperand &Op3 = MI.getOperand(3);
1258 Register Rd = Op0.getReg();
1259 Register Pu = Op1.getReg();
1260 Register Rs = Op2.getReg();
1261 Register Rt = Op3.getReg();
1262 DebugLoc DL = MI.getDebugLoc();
1263 unsigned K1 = getKillRegState(Op1.isKill());
1264 unsigned K2 = getKillRegState(Op2.isKill());
1265 unsigned K3 = getKillRegState(Op3.isKill());
1266 if (Rd != Rs)
1267 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1268 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1269 .addReg(Rs, K2);
1270 if (Rd != Rt)
1271 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1272 .addReg(Pu, K1)
1273 .addReg(Rt, K3);
1274 MBB.erase(MI);
1275 return true;
1276 }
1277 case Hexagon::PS_vselect: {
1278 const MachineOperand &Op0 = MI.getOperand(0);
1279 const MachineOperand &Op1 = MI.getOperand(1);
1280 const MachineOperand &Op2 = MI.getOperand(2);
1281 const MachineOperand &Op3 = MI.getOperand(3);
1282 getLiveOutRegsAt(LiveOut, MI);
1283 bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1284 Register PReg = Op1.getReg();
1285 assert(Op1.getSubReg() == 0);
1286 unsigned PState = getRegState(Op1);
1287
1288 if (Op0.getReg() != Op2.getReg()) {
1289 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1290 : PState;
1291 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1292 .add(Op0)
1293 .addReg(PReg, S)
1294 .add(Op2);
1295 if (IsDestLive)
1296 T.addReg(Op0.getReg(), RegState::Implicit);
1297 IsDestLive = true;
1298 }
1299 if (Op0.getReg() != Op3.getReg()) {
1300 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1301 .add(Op0)
1302 .addReg(PReg, PState)
1303 .add(Op3);
1304 if (IsDestLive)
1305 T.addReg(Op0.getReg(), RegState::Implicit);
1306 }
1307 MBB.erase(MI);
1308 return true;
1309 }
1310 case Hexagon::PS_wselect: {
1311 MachineOperand &Op0 = MI.getOperand(0);
1312 MachineOperand &Op1 = MI.getOperand(1);
1313 MachineOperand &Op2 = MI.getOperand(2);
1314 MachineOperand &Op3 = MI.getOperand(3);
1315 getLiveOutRegsAt(LiveOut, MI);
1316 bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
1317 Register PReg = Op1.getReg();
1318 assert(Op1.getSubReg() == 0);
1319 unsigned PState = getRegState(Op1);
1320
1321 if (Op0.getReg() != Op2.getReg()) {
1322 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1323 : PState;
1324 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1325 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1326 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1327 .add(Op0)
1328 .addReg(PReg, S)
1329 .addReg(SrcHi)
1330 .addReg(SrcLo);
1331 if (IsDestLive)
1332 T.addReg(Op0.getReg(), RegState::Implicit);
1333 IsDestLive = true;
1334 }
1335 if (Op0.getReg() != Op3.getReg()) {
1336 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1337 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1338 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1339 .add(Op0)
1340 .addReg(PReg, PState)
1341 .addReg(SrcHi)
1342 .addReg(SrcLo);
1343 if (IsDestLive)
1344 T.addReg(Op0.getReg(), RegState::Implicit);
1345 }
1346 MBB.erase(MI);
1347 return true;
1348 }
1349
1350 case Hexagon::PS_crash: {
1351 // Generate a misaligned load that is guaranteed to cause a crash.
1352 class CrashPseudoSourceValue : public PseudoSourceValue {
1353 public:
1354 CrashPseudoSourceValue(const TargetInstrInfo &TII)
1355 : PseudoSourceValue(TargetCustom, TII) {}
1356
1357 bool isConstant(const MachineFrameInfo *) const override {
1358 return false;
1359 }
1360 bool isAliased(const MachineFrameInfo *) const override {
1361 return false;
1362 }
1363 bool mayAlias(const MachineFrameInfo *) const override {
1364 return false;
1365 }
1366 void printCustom(raw_ostream &OS) const override {
1367 OS << "MisalignedCrash";
1368 }
1369 };
1370
1371 static const CrashPseudoSourceValue CrashPSV(*this);
1372 MachineMemOperand *MMO = MF.getMachineMemOperand(
1373 MachinePointerInfo(&CrashPSV),
1374 MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8,
1375 Align(1));
1376 BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1377 .addImm(0xBADC0FEE) // Misaligned load.
1378 .addMemOperand(MMO);
1379 MBB.erase(MI);
1380 return true;
1381 }
1382
1383 case Hexagon::PS_tailcall_i:
1384 MI.setDesc(get(Hexagon::J2_jump));
1385 return true;
1386 case Hexagon::PS_tailcall_r:
1387 case Hexagon::PS_jmpret:
1388 MI.setDesc(get(Hexagon::J2_jumpr));
1389 return true;
1390 case Hexagon::PS_jmprett:
1391 MI.setDesc(get(Hexagon::J2_jumprt));
1392 return true;
1393 case Hexagon::PS_jmpretf:
1394 MI.setDesc(get(Hexagon::J2_jumprf));
1395 return true;
1396 case Hexagon::PS_jmprettnewpt:
1397 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1398 return true;
1399 case Hexagon::PS_jmpretfnewpt:
1400 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1401 return true;
1402 case Hexagon::PS_jmprettnew:
1403 MI.setDesc(get(Hexagon::J2_jumprtnew));
1404 return true;
1405 case Hexagon::PS_jmpretfnew:
1406 MI.setDesc(get(Hexagon::J2_jumprfnew));
1407 return true;
1408
1409 case Hexagon::PS_loadrub_pci:
1410 return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1411 case Hexagon::PS_loadrb_pci:
1412 return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1413 case Hexagon::PS_loadruh_pci:
1414 return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1415 case Hexagon::PS_loadrh_pci:
1416 return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1417 case Hexagon::PS_loadri_pci:
1418 return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1419 case Hexagon::PS_loadrd_pci:
1420 return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1421 case Hexagon::PS_loadrub_pcr:
1422 return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1423 case Hexagon::PS_loadrb_pcr:
1424 return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1425 case Hexagon::PS_loadruh_pcr:
1426 return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1427 case Hexagon::PS_loadrh_pcr:
1428 return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1429 case Hexagon::PS_loadri_pcr:
1430 return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1431 case Hexagon::PS_loadrd_pcr:
1432 return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1433 case Hexagon::PS_storerb_pci:
1434 return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1435 case Hexagon::PS_storerh_pci:
1436 return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1437 case Hexagon::PS_storerf_pci:
1438 return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1439 case Hexagon::PS_storeri_pci:
1440 return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1441 case Hexagon::PS_storerd_pci:
1442 return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1443 case Hexagon::PS_storerb_pcr:
1444 return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1445 case Hexagon::PS_storerh_pcr:
1446 return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1447 case Hexagon::PS_storerf_pcr:
1448 return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1449 case Hexagon::PS_storeri_pcr:
1450 return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1451 case Hexagon::PS_storerd_pcr:
1452 return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1453 }
1454
1455 return false;
1456 }
1457
1458 MachineBasicBlock::instr_iterator
expandVGatherPseudo(MachineInstr & MI) const1459 HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {
1460 MachineBasicBlock &MBB = *MI.getParent();
1461 const DebugLoc &DL = MI.getDebugLoc();
1462 unsigned Opc = MI.getOpcode();
1463 MachineBasicBlock::iterator First;
1464
1465 switch (Opc) {
1466 case Hexagon::V6_vgathermh_pseudo:
1467 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1468 .add(MI.getOperand(1))
1469 .add(MI.getOperand(2))
1470 .add(MI.getOperand(3));
1471 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1472 .add(MI.getOperand(0))
1473 .addImm(0)
1474 .addReg(Hexagon::VTMP);
1475 MBB.erase(MI);
1476 return First.getInstrIterator();
1477
1478 case Hexagon::V6_vgathermw_pseudo:
1479 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1480 .add(MI.getOperand(1))
1481 .add(MI.getOperand(2))
1482 .add(MI.getOperand(3));
1483 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1484 .add(MI.getOperand(0))
1485 .addImm(0)
1486 .addReg(Hexagon::VTMP);
1487 MBB.erase(MI);
1488 return First.getInstrIterator();
1489
1490 case Hexagon::V6_vgathermhw_pseudo:
1491 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1492 .add(MI.getOperand(1))
1493 .add(MI.getOperand(2))
1494 .add(MI.getOperand(3));
1495 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1496 .add(MI.getOperand(0))
1497 .addImm(0)
1498 .addReg(Hexagon::VTMP);
1499 MBB.erase(MI);
1500 return First.getInstrIterator();
1501
1502 case Hexagon::V6_vgathermhq_pseudo:
1503 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1504 .add(MI.getOperand(1))
1505 .add(MI.getOperand(2))
1506 .add(MI.getOperand(3))
1507 .add(MI.getOperand(4));
1508 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1509 .add(MI.getOperand(0))
1510 .addImm(0)
1511 .addReg(Hexagon::VTMP);
1512 MBB.erase(MI);
1513 return First.getInstrIterator();
1514
1515 case Hexagon::V6_vgathermwq_pseudo:
1516 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1517 .add(MI.getOperand(1))
1518 .add(MI.getOperand(2))
1519 .add(MI.getOperand(3))
1520 .add(MI.getOperand(4));
1521 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1522 .add(MI.getOperand(0))
1523 .addImm(0)
1524 .addReg(Hexagon::VTMP);
1525 MBB.erase(MI);
1526 return First.getInstrIterator();
1527
1528 case Hexagon::V6_vgathermhwq_pseudo:
1529 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1530 .add(MI.getOperand(1))
1531 .add(MI.getOperand(2))
1532 .add(MI.getOperand(3))
1533 .add(MI.getOperand(4));
1534 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1535 .add(MI.getOperand(0))
1536 .addImm(0)
1537 .addReg(Hexagon::VTMP);
1538 MBB.erase(MI);
1539 return First.getInstrIterator();
1540 }
1541
1542 return MI.getIterator();
1543 }
1544
1545 // We indicate that we want to reverse the branch by
1546 // inserting the reversed branching opcode.
reverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const1547 bool HexagonInstrInfo::reverseBranchCondition(
1548 SmallVectorImpl<MachineOperand> &Cond) const {
1549 if (Cond.empty())
1550 return true;
1551 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1552 unsigned opcode = Cond[0].getImm();
1553 //unsigned temp;
1554 assert(get(opcode).isBranch() && "Should be a branching condition.");
1555 if (isEndLoopN(opcode))
1556 return true;
1557 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1558 Cond[0].setImm(NewOpcode);
1559 return false;
1560 }
1561
insertNoop(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI) const1562 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1563 MachineBasicBlock::iterator MI) const {
1564 DebugLoc DL;
1565 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1566 }
1567
isPostIncrement(const MachineInstr & MI) const1568 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1569 return getAddrMode(MI) == HexagonII::PostInc;
1570 }
1571
1572 // Returns true if an instruction is predicated irrespective of the predicate
1573 // sense. For example, all of the following will return true.
1574 // if (p0) R1 = add(R2, R3)
1575 // if (!p0) R1 = add(R2, R3)
1576 // if (p0.new) R1 = add(R2, R3)
1577 // if (!p0.new) R1 = add(R2, R3)
1578 // Note: New-value stores are not included here as in the current
1579 // implementation, we don't need to check their predicate sense.
isPredicated(const MachineInstr & MI) const1580 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1581 const uint64_t F = MI.getDesc().TSFlags;
1582 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1583 }
1584
PredicateInstruction(MachineInstr & MI,ArrayRef<MachineOperand> Cond) const1585 bool HexagonInstrInfo::PredicateInstruction(
1586 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1587 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1588 isEndLoopN(Cond[0].getImm())) {
1589 LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1590 return false;
1591 }
1592 int Opc = MI.getOpcode();
1593 assert (isPredicable(MI) && "Expected predicable instruction");
1594 bool invertJump = predOpcodeHasNot(Cond);
1595
1596 // We have to predicate MI "in place", i.e. after this function returns,
1597 // MI will need to be transformed into a predicated form. To avoid com-
1598 // plicated manipulations with the operands (handling tied operands,
1599 // etc.), build a new temporary instruction, then overwrite MI with it.
1600
1601 MachineBasicBlock &B = *MI.getParent();
1602 DebugLoc DL = MI.getDebugLoc();
1603 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1604 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1605 unsigned NOp = 0, NumOps = MI.getNumOperands();
1606 while (NOp < NumOps) {
1607 MachineOperand &Op = MI.getOperand(NOp);
1608 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1609 break;
1610 T.add(Op);
1611 NOp++;
1612 }
1613
1614 unsigned PredReg, PredRegPos, PredRegFlags;
1615 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1616 (void)GotPredReg;
1617 assert(GotPredReg);
1618 T.addReg(PredReg, PredRegFlags);
1619 while (NOp < NumOps)
1620 T.add(MI.getOperand(NOp++));
1621
1622 MI.setDesc(get(PredOpc));
1623 while (unsigned n = MI.getNumOperands())
1624 MI.RemoveOperand(n-1);
1625 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1626 MI.addOperand(T->getOperand(i));
1627
1628 MachineBasicBlock::instr_iterator TI = T->getIterator();
1629 B.erase(TI);
1630
1631 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1632 MRI.clearKillFlags(PredReg);
1633 return true;
1634 }
1635
SubsumesPredicate(ArrayRef<MachineOperand> Pred1,ArrayRef<MachineOperand> Pred2) const1636 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1637 ArrayRef<MachineOperand> Pred2) const {
1638 // TODO: Fix this
1639 return false;
1640 }
1641
DefinesPredicate(MachineInstr & MI,std::vector<MachineOperand> & Pred) const1642 bool HexagonInstrInfo::DefinesPredicate(MachineInstr &MI,
1643 std::vector<MachineOperand> &Pred) const {
1644 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1645
1646 for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1647 MachineOperand MO = MI.getOperand(oper);
1648 if (MO.isReg()) {
1649 if (!MO.isDef())
1650 continue;
1651 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1652 if (RC == &Hexagon::PredRegsRegClass) {
1653 Pred.push_back(MO);
1654 return true;
1655 }
1656 continue;
1657 } else if (MO.isRegMask()) {
1658 for (unsigned PR : Hexagon::PredRegsRegClass) {
1659 if (!MI.modifiesRegister(PR, &HRI))
1660 continue;
1661 Pred.push_back(MO);
1662 return true;
1663 }
1664 }
1665 }
1666 return false;
1667 }
1668
isPredicable(const MachineInstr & MI) const1669 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1670 if (!MI.getDesc().isPredicable())
1671 return false;
1672
1673 if (MI.isCall() || isTailCall(MI)) {
1674 if (!Subtarget.usePredicatedCalls())
1675 return false;
1676 }
1677
1678 // HVX loads are not predicable on v60, but are on v62.
1679 if (!Subtarget.hasV62Ops()) {
1680 switch (MI.getOpcode()) {
1681 case Hexagon::V6_vL32b_ai:
1682 case Hexagon::V6_vL32b_pi:
1683 case Hexagon::V6_vL32b_ppu:
1684 case Hexagon::V6_vL32b_cur_ai:
1685 case Hexagon::V6_vL32b_cur_pi:
1686 case Hexagon::V6_vL32b_cur_ppu:
1687 case Hexagon::V6_vL32b_nt_ai:
1688 case Hexagon::V6_vL32b_nt_pi:
1689 case Hexagon::V6_vL32b_nt_ppu:
1690 case Hexagon::V6_vL32b_tmp_ai:
1691 case Hexagon::V6_vL32b_tmp_pi:
1692 case Hexagon::V6_vL32b_tmp_ppu:
1693 case Hexagon::V6_vL32b_nt_cur_ai:
1694 case Hexagon::V6_vL32b_nt_cur_pi:
1695 case Hexagon::V6_vL32b_nt_cur_ppu:
1696 case Hexagon::V6_vL32b_nt_tmp_ai:
1697 case Hexagon::V6_vL32b_nt_tmp_pi:
1698 case Hexagon::V6_vL32b_nt_tmp_ppu:
1699 return false;
1700 }
1701 }
1702 return true;
1703 }
1704
isSchedulingBoundary(const MachineInstr & MI,const MachineBasicBlock * MBB,const MachineFunction & MF) const1705 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1706 const MachineBasicBlock *MBB,
1707 const MachineFunction &MF) const {
1708 // Debug info is never a scheduling boundary. It's necessary to be explicit
1709 // due to the special treatment of IT instructions below, otherwise a
1710 // dbg_value followed by an IT will result in the IT instruction being
1711 // considered a scheduling hazard, which is wrong. It should be the actual
1712 // instruction preceding the dbg_value instruction(s), just like it is
1713 // when debug info is not present.
1714 if (MI.isDebugInstr())
1715 return false;
1716
1717 // Throwing call is a boundary.
1718 if (MI.isCall()) {
1719 // Don't mess around with no return calls.
1720 if (doesNotReturn(MI))
1721 return true;
1722 // If any of the block's successors is a landing pad, this could be a
1723 // throwing call.
1724 for (auto I : MBB->successors())
1725 if (I->isEHPad())
1726 return true;
1727 }
1728
1729 // Terminators and labels can't be scheduled around.
1730 if (MI.getDesc().isTerminator() || MI.isPosition())
1731 return true;
1732
1733 // INLINEASM_BR can jump to another block
1734 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1735 return true;
1736
1737 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1738 return true;
1739
1740 return false;
1741 }
1742
1743 /// Measure the specified inline asm to determine an approximation of its
1744 /// length.
1745 /// Comments (which run till the next SeparatorString or newline) do not
1746 /// count as an instruction.
1747 /// Any other non-whitespace text is considered an instruction, with
1748 /// multiple instructions separated by SeparatorString or newlines.
1749 /// Variable-length instructions are not handled here; this function
1750 /// may be overloaded in the target code to do that.
1751 /// Hexagon counts the number of ##'s and adjust for that many
1752 /// constant exenders.
getInlineAsmLength(const char * Str,const MCAsmInfo & MAI,const TargetSubtargetInfo * STI) const1753 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1754 const MCAsmInfo &MAI,
1755 const TargetSubtargetInfo *STI) const {
1756 StringRef AStr(Str);
1757 // Count the number of instructions in the asm.
1758 bool atInsnStart = true;
1759 unsigned Length = 0;
1760 const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1761 for (; *Str; ++Str) {
1762 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1763 strlen(MAI.getSeparatorString())) == 0)
1764 atInsnStart = true;
1765 if (atInsnStart && !isSpace(static_cast<unsigned char>(*Str))) {
1766 Length += MaxInstLength;
1767 atInsnStart = false;
1768 }
1769 if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1770 MAI.getCommentString().size()) == 0)
1771 atInsnStart = false;
1772 }
1773
1774 // Add to size number of constant extenders seen * 4.
1775 StringRef Occ("##");
1776 Length += AStr.count(Occ)*4;
1777 return Length;
1778 }
1779
1780 ScheduleHazardRecognizer*
CreateTargetPostRAHazardRecognizer(const InstrItineraryData * II,const ScheduleDAG * DAG) const1781 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1782 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1783 if (UseDFAHazardRec)
1784 return new HexagonHazardRecognizer(II, this, Subtarget);
1785 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1786 }
1787
1788 /// For a comparison instruction, return the source registers in
1789 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1790 /// compares against in CmpValue. Return true if the comparison instruction
1791 /// can be analyzed.
analyzeCompare(const MachineInstr & MI,Register & SrcReg,Register & SrcReg2,int & Mask,int & Value) const1792 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1793 Register &SrcReg2, int &Mask,
1794 int &Value) const {
1795 unsigned Opc = MI.getOpcode();
1796
1797 // Set mask and the first source register.
1798 switch (Opc) {
1799 case Hexagon::C2_cmpeq:
1800 case Hexagon::C2_cmpeqp:
1801 case Hexagon::C2_cmpgt:
1802 case Hexagon::C2_cmpgtp:
1803 case Hexagon::C2_cmpgtu:
1804 case Hexagon::C2_cmpgtup:
1805 case Hexagon::C4_cmpneq:
1806 case Hexagon::C4_cmplte:
1807 case Hexagon::C4_cmplteu:
1808 case Hexagon::C2_cmpeqi:
1809 case Hexagon::C2_cmpgti:
1810 case Hexagon::C2_cmpgtui:
1811 case Hexagon::C4_cmpneqi:
1812 case Hexagon::C4_cmplteui:
1813 case Hexagon::C4_cmpltei:
1814 SrcReg = MI.getOperand(1).getReg();
1815 Mask = ~0;
1816 break;
1817 case Hexagon::A4_cmpbeq:
1818 case Hexagon::A4_cmpbgt:
1819 case Hexagon::A4_cmpbgtu:
1820 case Hexagon::A4_cmpbeqi:
1821 case Hexagon::A4_cmpbgti:
1822 case Hexagon::A4_cmpbgtui:
1823 SrcReg = MI.getOperand(1).getReg();
1824 Mask = 0xFF;
1825 break;
1826 case Hexagon::A4_cmpheq:
1827 case Hexagon::A4_cmphgt:
1828 case Hexagon::A4_cmphgtu:
1829 case Hexagon::A4_cmpheqi:
1830 case Hexagon::A4_cmphgti:
1831 case Hexagon::A4_cmphgtui:
1832 SrcReg = MI.getOperand(1).getReg();
1833 Mask = 0xFFFF;
1834 break;
1835 }
1836
1837 // Set the value/second source register.
1838 switch (Opc) {
1839 case Hexagon::C2_cmpeq:
1840 case Hexagon::C2_cmpeqp:
1841 case Hexagon::C2_cmpgt:
1842 case Hexagon::C2_cmpgtp:
1843 case Hexagon::C2_cmpgtu:
1844 case Hexagon::C2_cmpgtup:
1845 case Hexagon::A4_cmpbeq:
1846 case Hexagon::A4_cmpbgt:
1847 case Hexagon::A4_cmpbgtu:
1848 case Hexagon::A4_cmpheq:
1849 case Hexagon::A4_cmphgt:
1850 case Hexagon::A4_cmphgtu:
1851 case Hexagon::C4_cmpneq:
1852 case Hexagon::C4_cmplte:
1853 case Hexagon::C4_cmplteu:
1854 SrcReg2 = MI.getOperand(2).getReg();
1855 return true;
1856
1857 case Hexagon::C2_cmpeqi:
1858 case Hexagon::C2_cmpgtui:
1859 case Hexagon::C2_cmpgti:
1860 case Hexagon::C4_cmpneqi:
1861 case Hexagon::C4_cmplteui:
1862 case Hexagon::C4_cmpltei:
1863 case Hexagon::A4_cmpbeqi:
1864 case Hexagon::A4_cmpbgti:
1865 case Hexagon::A4_cmpbgtui:
1866 case Hexagon::A4_cmpheqi:
1867 case Hexagon::A4_cmphgti:
1868 case Hexagon::A4_cmphgtui: {
1869 SrcReg2 = 0;
1870 const MachineOperand &Op2 = MI.getOperand(2);
1871 if (!Op2.isImm())
1872 return false;
1873 Value = MI.getOperand(2).getImm();
1874 return true;
1875 }
1876 }
1877
1878 return false;
1879 }
1880
getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const1881 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1882 const MachineInstr &MI,
1883 unsigned *PredCost) const {
1884 return getInstrTimingClassLatency(ItinData, MI);
1885 }
1886
CreateTargetScheduleState(const TargetSubtargetInfo & STI) const1887 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1888 const TargetSubtargetInfo &STI) const {
1889 const InstrItineraryData *II = STI.getInstrItineraryData();
1890 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1891 }
1892
1893 // Inspired by this pair:
1894 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1895 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1896 // Currently AA considers the addresses in these instructions to be aliasing.
areMemAccessesTriviallyDisjoint(const MachineInstr & MIa,const MachineInstr & MIb) const1897 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
1898 const MachineInstr &MIa, const MachineInstr &MIb) const {
1899 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1900 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
1901 return false;
1902
1903 // Instructions that are pure loads, not loads and stores like memops are not
1904 // dependent.
1905 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1906 return true;
1907
1908 // Get the base register in MIa.
1909 unsigned BasePosA, OffsetPosA;
1910 if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1911 return false;
1912 const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1913 Register BaseRegA = BaseA.getReg();
1914 unsigned BaseSubA = BaseA.getSubReg();
1915
1916 // Get the base register in MIb.
1917 unsigned BasePosB, OffsetPosB;
1918 if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1919 return false;
1920 const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1921 Register BaseRegB = BaseB.getReg();
1922 unsigned BaseSubB = BaseB.getSubReg();
1923
1924 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1925 return false;
1926
1927 // Get the access sizes.
1928 unsigned SizeA = getMemAccessSize(MIa);
1929 unsigned SizeB = getMemAccessSize(MIb);
1930
1931 // Get the offsets. Handle immediates only for now.
1932 const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1933 const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1934 if (!MIa.getOperand(OffsetPosA).isImm() ||
1935 !MIb.getOperand(OffsetPosB).isImm())
1936 return false;
1937 int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1938 int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1939
1940 // This is a mem access with the same base register and known offsets from it.
1941 // Reason about it.
1942 if (OffsetA > OffsetB) {
1943 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1944 return SizeB <= OffDiff;
1945 }
1946 if (OffsetA < OffsetB) {
1947 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1948 return SizeA <= OffDiff;
1949 }
1950
1951 return false;
1952 }
1953
1954 /// If the instruction is an increment of a constant value, return the amount.
getIncrementValue(const MachineInstr & MI,int & Value) const1955 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
1956 int &Value) const {
1957 if (isPostIncrement(MI)) {
1958 unsigned BasePos = 0, OffsetPos = 0;
1959 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1960 return false;
1961 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1962 if (OffsetOp.isImm()) {
1963 Value = OffsetOp.getImm();
1964 return true;
1965 }
1966 } else if (MI.getOpcode() == Hexagon::A2_addi) {
1967 const MachineOperand &AddOp = MI.getOperand(2);
1968 if (AddOp.isImm()) {
1969 Value = AddOp.getImm();
1970 return true;
1971 }
1972 }
1973
1974 return false;
1975 }
1976
1977 std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const1978 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1979 return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1980 TF & HexagonII::MO_Bitmasks);
1981 }
1982
1983 ArrayRef<std::pair<unsigned, const char*>>
getSerializableDirectMachineOperandTargetFlags() const1984 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1985 using namespace HexagonII;
1986
1987 static const std::pair<unsigned, const char*> Flags[] = {
1988 {MO_PCREL, "hexagon-pcrel"},
1989 {MO_GOT, "hexagon-got"},
1990 {MO_LO16, "hexagon-lo16"},
1991 {MO_HI16, "hexagon-hi16"},
1992 {MO_GPREL, "hexagon-gprel"},
1993 {MO_GDGOT, "hexagon-gdgot"},
1994 {MO_GDPLT, "hexagon-gdplt"},
1995 {MO_IE, "hexagon-ie"},
1996 {MO_IEGOT, "hexagon-iegot"},
1997 {MO_TPREL, "hexagon-tprel"}
1998 };
1999 return makeArrayRef(Flags);
2000 }
2001
2002 ArrayRef<std::pair<unsigned, const char*>>
getSerializableBitmaskMachineOperandTargetFlags() const2003 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2004 using namespace HexagonII;
2005
2006 static const std::pair<unsigned, const char*> Flags[] = {
2007 {HMOTF_ConstExtended, "hexagon-ext"}
2008 };
2009 return makeArrayRef(Flags);
2010 }
2011
createVR(MachineFunction * MF,MVT VT) const2012 unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
2013 MachineRegisterInfo &MRI = MF->getRegInfo();
2014 const TargetRegisterClass *TRC;
2015 if (VT == MVT::i1) {
2016 TRC = &Hexagon::PredRegsRegClass;
2017 } else if (VT == MVT::i32 || VT == MVT::f32) {
2018 TRC = &Hexagon::IntRegsRegClass;
2019 } else if (VT == MVT::i64 || VT == MVT::f64) {
2020 TRC = &Hexagon::DoubleRegsRegClass;
2021 } else {
2022 llvm_unreachable("Cannot handle this register class");
2023 }
2024
2025 Register NewReg = MRI.createVirtualRegister(TRC);
2026 return NewReg;
2027 }
2028
isAbsoluteSet(const MachineInstr & MI) const2029 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
2030 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2031 }
2032
isAccumulator(const MachineInstr & MI) const2033 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
2034 const uint64_t F = MI.getDesc().TSFlags;
2035 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
2036 }
2037
isBaseImmOffset(const MachineInstr & MI) const2038 bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {
2039 return getAddrMode(MI) == HexagonII::BaseImmOffset;
2040 }
2041
isComplex(const MachineInstr & MI) const2042 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
2043 return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2044 !MI.getDesc().mayStore() &&
2045 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2046 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2047 !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2048 }
2049
2050 // Return true if the instruction is a compund branch instruction.
isCompoundBranchInstr(const MachineInstr & MI) const2051 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
2052 return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2053 }
2054
2055 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2056 // isFPImm and later getFPImm as well.
isConstExtended(const MachineInstr & MI) const2057 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
2058 const uint64_t F = MI.getDesc().TSFlags;
2059 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
2060 if (isExtended) // Instruction must be extended.
2061 return true;
2062
2063 unsigned isExtendable =
2064 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
2065 if (!isExtendable)
2066 return false;
2067
2068 if (MI.isCall())
2069 return false;
2070
2071 short ExtOpNum = getCExtOpNum(MI);
2072 const MachineOperand &MO = MI.getOperand(ExtOpNum);
2073 // Use MO operand flags to determine if MO
2074 // has the HMOTF_ConstExtended flag set.
2075 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2076 return true;
2077 // If this is a Machine BB address we are talking about, and it is
2078 // not marked as extended, say so.
2079 if (MO.isMBB())
2080 return false;
2081
2082 // We could be using an instruction with an extendable immediate and shoehorn
2083 // a global address into it. If it is a global address it will be constant
2084 // extended. We do this for COMBINE.
2085 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2086 MO.isJTI() || MO.isCPI() || MO.isFPImm())
2087 return true;
2088
2089 // If the extendable operand is not 'Immediate' type, the instruction should
2090 // have 'isExtended' flag set.
2091 assert(MO.isImm() && "Extendable operand must be Immediate type");
2092
2093 int MinValue = getMinValue(MI);
2094 int MaxValue = getMaxValue(MI);
2095 int ImmValue = MO.getImm();
2096
2097 return (ImmValue < MinValue || ImmValue > MaxValue);
2098 }
2099
isDeallocRet(const MachineInstr & MI) const2100 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
2101 switch (MI.getOpcode()) {
2102 case Hexagon::L4_return:
2103 case Hexagon::L4_return_t:
2104 case Hexagon::L4_return_f:
2105 case Hexagon::L4_return_tnew_pnt:
2106 case Hexagon::L4_return_fnew_pnt:
2107 case Hexagon::L4_return_tnew_pt:
2108 case Hexagon::L4_return_fnew_pt:
2109 return true;
2110 }
2111 return false;
2112 }
2113
2114 // Return true when ConsMI uses a register defined by ProdMI.
isDependent(const MachineInstr & ProdMI,const MachineInstr & ConsMI) const2115 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
2116 const MachineInstr &ConsMI) const {
2117 if (!ProdMI.getDesc().getNumDefs())
2118 return false;
2119 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2120
2121 SmallVector<unsigned, 4> DefsA;
2122 SmallVector<unsigned, 4> DefsB;
2123 SmallVector<unsigned, 8> UsesA;
2124 SmallVector<unsigned, 8> UsesB;
2125
2126 parseOperands(ProdMI, DefsA, UsesA);
2127 parseOperands(ConsMI, DefsB, UsesB);
2128
2129 for (auto &RegA : DefsA)
2130 for (auto &RegB : UsesB) {
2131 // True data dependency.
2132 if (RegA == RegB)
2133 return true;
2134
2135 if (Register::isPhysicalRegister(RegA))
2136 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2137 if (RegB == *SubRegs)
2138 return true;
2139
2140 if (Register::isPhysicalRegister(RegB))
2141 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2142 if (RegA == *SubRegs)
2143 return true;
2144 }
2145
2146 return false;
2147 }
2148
2149 // Returns true if the instruction is alread a .cur.
isDotCurInst(const MachineInstr & MI) const2150 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
2151 switch (MI.getOpcode()) {
2152 case Hexagon::V6_vL32b_cur_pi:
2153 case Hexagon::V6_vL32b_cur_ai:
2154 return true;
2155 }
2156 return false;
2157 }
2158
2159 // Returns true, if any one of the operands is a dot new
2160 // insn, whether it is predicated dot new or register dot new.
isDotNewInst(const MachineInstr & MI) const2161 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
2162 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2163 return true;
2164
2165 return false;
2166 }
2167
2168 /// Symmetrical. See if these two instructions are fit for duplex pair.
isDuplexPair(const MachineInstr & MIa,const MachineInstr & MIb) const2169 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2170 const MachineInstr &MIb) const {
2171 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
2172 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
2173 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2174 }
2175
isEarlySourceInstr(const MachineInstr & MI) const2176 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr &MI) const {
2177 if (MI.mayLoadOrStore() || MI.isCompare())
2178 return true;
2179
2180 // Multiply
2181 unsigned SchedClass = MI.getDesc().getSchedClass();
2182 return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2183 }
2184
isEndLoopN(unsigned Opcode) const2185 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2186 return (Opcode == Hexagon::ENDLOOP0 ||
2187 Opcode == Hexagon::ENDLOOP1);
2188 }
2189
isExpr(unsigned OpType) const2190 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2191 switch(OpType) {
2192 case MachineOperand::MO_MachineBasicBlock:
2193 case MachineOperand::MO_GlobalAddress:
2194 case MachineOperand::MO_ExternalSymbol:
2195 case MachineOperand::MO_JumpTableIndex:
2196 case MachineOperand::MO_ConstantPoolIndex:
2197 case MachineOperand::MO_BlockAddress:
2198 return true;
2199 default:
2200 return false;
2201 }
2202 }
2203
isExtendable(const MachineInstr & MI) const2204 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2205 const MCInstrDesc &MID = MI.getDesc();
2206 const uint64_t F = MID.TSFlags;
2207 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
2208 return true;
2209
2210 // TODO: This is largely obsolete now. Will need to be removed
2211 // in consecutive patches.
2212 switch (MI.getOpcode()) {
2213 // PS_fi and PS_fia remain special cases.
2214 case Hexagon::PS_fi:
2215 case Hexagon::PS_fia:
2216 return true;
2217 default:
2218 return false;
2219 }
2220 return false;
2221 }
2222
2223 // This returns true in two cases:
2224 // - The OP code itself indicates that this is an extended instruction.
2225 // - One of MOs has been marked with HMOTF_ConstExtended flag.
isExtended(const MachineInstr & MI) const2226 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2227 // First check if this is permanently extended op code.
2228 const uint64_t F = MI.getDesc().TSFlags;
2229 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
2230 return true;
2231 // Use MO operand flags to determine if one of MI's operands
2232 // has HMOTF_ConstExtended flag set.
2233 for (const MachineOperand &MO : MI.operands())
2234 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2235 return true;
2236 return false;
2237 }
2238
isFloat(const MachineInstr & MI) const2239 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2240 unsigned Opcode = MI.getOpcode();
2241 const uint64_t F = get(Opcode).TSFlags;
2242 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2243 }
2244
2245 // No V60 HVX VMEM with A_INDIRECT.
isHVXMemWithAIndirect(const MachineInstr & I,const MachineInstr & J) const2246 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2247 const MachineInstr &J) const {
2248 if (!isHVXVec(I))
2249 return false;
2250 if (!I.mayLoad() && !I.mayStore())
2251 return false;
2252 return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2253 }
2254
isIndirectCall(const MachineInstr & MI) const2255 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2256 switch (MI.getOpcode()) {
2257 case Hexagon::J2_callr:
2258 case Hexagon::J2_callrf:
2259 case Hexagon::J2_callrt:
2260 case Hexagon::PS_call_nr:
2261 return true;
2262 }
2263 return false;
2264 }
2265
isIndirectL4Return(const MachineInstr & MI) const2266 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2267 switch (MI.getOpcode()) {
2268 case Hexagon::L4_return:
2269 case Hexagon::L4_return_t:
2270 case Hexagon::L4_return_f:
2271 case Hexagon::L4_return_fnew_pnt:
2272 case Hexagon::L4_return_fnew_pt:
2273 case Hexagon::L4_return_tnew_pnt:
2274 case Hexagon::L4_return_tnew_pt:
2275 return true;
2276 }
2277 return false;
2278 }
2279
isJumpR(const MachineInstr & MI) const2280 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2281 switch (MI.getOpcode()) {
2282 case Hexagon::J2_jumpr:
2283 case Hexagon::J2_jumprt:
2284 case Hexagon::J2_jumprf:
2285 case Hexagon::J2_jumprtnewpt:
2286 case Hexagon::J2_jumprfnewpt:
2287 case Hexagon::J2_jumprtnew:
2288 case Hexagon::J2_jumprfnew:
2289 return true;
2290 }
2291 return false;
2292 }
2293
2294 // Return true if a given MI can accommodate given offset.
2295 // Use abs estimate as oppose to the exact number.
2296 // TODO: This will need to be changed to use MC level
2297 // definition of instruction extendable field size.
isJumpWithinBranchRange(const MachineInstr & MI,unsigned offset) const2298 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2299 unsigned offset) const {
2300 // This selection of jump instructions matches to that what
2301 // analyzeBranch can parse, plus NVJ.
2302 if (isNewValueJump(MI)) // r9:2
2303 return isInt<11>(offset);
2304
2305 switch (MI.getOpcode()) {
2306 // Still missing Jump to address condition on register value.
2307 default:
2308 return false;
2309 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2310 case Hexagon::J2_call:
2311 case Hexagon::PS_call_nr:
2312 return isInt<24>(offset);
2313 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2314 case Hexagon::J2_jumpf:
2315 case Hexagon::J2_jumptnew:
2316 case Hexagon::J2_jumptnewpt:
2317 case Hexagon::J2_jumpfnew:
2318 case Hexagon::J2_jumpfnewpt:
2319 case Hexagon::J2_callt:
2320 case Hexagon::J2_callf:
2321 return isInt<17>(offset);
2322 case Hexagon::J2_loop0i:
2323 case Hexagon::J2_loop0iext:
2324 case Hexagon::J2_loop0r:
2325 case Hexagon::J2_loop0rext:
2326 case Hexagon::J2_loop1i:
2327 case Hexagon::J2_loop1iext:
2328 case Hexagon::J2_loop1r:
2329 case Hexagon::J2_loop1rext:
2330 return isInt<9>(offset);
2331 // TODO: Add all the compound branches here. Can we do this in Relation model?
2332 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2333 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2334 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2335 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2336 return isInt<11>(offset);
2337 }
2338 }
2339
isLateInstrFeedsEarlyInstr(const MachineInstr & LRMI,const MachineInstr & ESMI) const2340 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
2341 const MachineInstr &ESMI) const {
2342 bool isLate = isLateResultInstr(LRMI);
2343 bool isEarly = isEarlySourceInstr(ESMI);
2344
2345 LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2346 LLVM_DEBUG(LRMI.dump());
2347 LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2348 LLVM_DEBUG(ESMI.dump());
2349
2350 if (isLate && isEarly) {
2351 LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2352 return true;
2353 }
2354
2355 return false;
2356 }
2357
isLateResultInstr(const MachineInstr & MI) const2358 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr &MI) const {
2359 switch (MI.getOpcode()) {
2360 case TargetOpcode::EXTRACT_SUBREG:
2361 case TargetOpcode::INSERT_SUBREG:
2362 case TargetOpcode::SUBREG_TO_REG:
2363 case TargetOpcode::REG_SEQUENCE:
2364 case TargetOpcode::IMPLICIT_DEF:
2365 case TargetOpcode::COPY:
2366 case TargetOpcode::INLINEASM:
2367 case TargetOpcode::PHI:
2368 return false;
2369 default:
2370 break;
2371 }
2372
2373 unsigned SchedClass = MI.getDesc().getSchedClass();
2374 return !is_TC1(SchedClass);
2375 }
2376
isLateSourceInstr(const MachineInstr & MI) const2377 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2378 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2379 // resource, but all operands can be received late like an ALU instruction.
2380 return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2381 }
2382
isLoopN(const MachineInstr & MI) const2383 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2384 unsigned Opcode = MI.getOpcode();
2385 return Opcode == Hexagon::J2_loop0i ||
2386 Opcode == Hexagon::J2_loop0r ||
2387 Opcode == Hexagon::J2_loop0iext ||
2388 Opcode == Hexagon::J2_loop0rext ||
2389 Opcode == Hexagon::J2_loop1i ||
2390 Opcode == Hexagon::J2_loop1r ||
2391 Opcode == Hexagon::J2_loop1iext ||
2392 Opcode == Hexagon::J2_loop1rext;
2393 }
2394
isMemOp(const MachineInstr & MI) const2395 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2396 switch (MI.getOpcode()) {
2397 default: return false;
2398 case Hexagon::L4_iadd_memopw_io:
2399 case Hexagon::L4_isub_memopw_io:
2400 case Hexagon::L4_add_memopw_io:
2401 case Hexagon::L4_sub_memopw_io:
2402 case Hexagon::L4_and_memopw_io:
2403 case Hexagon::L4_or_memopw_io:
2404 case Hexagon::L4_iadd_memoph_io:
2405 case Hexagon::L4_isub_memoph_io:
2406 case Hexagon::L4_add_memoph_io:
2407 case Hexagon::L4_sub_memoph_io:
2408 case Hexagon::L4_and_memoph_io:
2409 case Hexagon::L4_or_memoph_io:
2410 case Hexagon::L4_iadd_memopb_io:
2411 case Hexagon::L4_isub_memopb_io:
2412 case Hexagon::L4_add_memopb_io:
2413 case Hexagon::L4_sub_memopb_io:
2414 case Hexagon::L4_and_memopb_io:
2415 case Hexagon::L4_or_memopb_io:
2416 case Hexagon::L4_ior_memopb_io:
2417 case Hexagon::L4_ior_memoph_io:
2418 case Hexagon::L4_ior_memopw_io:
2419 case Hexagon::L4_iand_memopb_io:
2420 case Hexagon::L4_iand_memoph_io:
2421 case Hexagon::L4_iand_memopw_io:
2422 return true;
2423 }
2424 return false;
2425 }
2426
isNewValue(const MachineInstr & MI) const2427 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2428 const uint64_t F = MI.getDesc().TSFlags;
2429 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2430 }
2431
isNewValue(unsigned Opcode) const2432 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2433 const uint64_t F = get(Opcode).TSFlags;
2434 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2435 }
2436
isNewValueInst(const MachineInstr & MI) const2437 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2438 return isNewValueJump(MI) || isNewValueStore(MI);
2439 }
2440
isNewValueJump(const MachineInstr & MI) const2441 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2442 return isNewValue(MI) && MI.isBranch();
2443 }
2444
isNewValueJump(unsigned Opcode) const2445 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2446 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2447 }
2448
isNewValueStore(const MachineInstr & MI) const2449 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2450 const uint64_t F = MI.getDesc().TSFlags;
2451 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2452 }
2453
isNewValueStore(unsigned Opcode) const2454 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2455 const uint64_t F = get(Opcode).TSFlags;
2456 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2457 }
2458
2459 // Returns true if a particular operand is extendable for an instruction.
isOperandExtended(const MachineInstr & MI,unsigned OperandNum) const2460 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2461 unsigned OperandNum) const {
2462 const uint64_t F = MI.getDesc().TSFlags;
2463 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2464 == OperandNum;
2465 }
2466
isPredicatedNew(const MachineInstr & MI) const2467 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2468 const uint64_t F = MI.getDesc().TSFlags;
2469 assert(isPredicated(MI));
2470 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2471 }
2472
isPredicatedNew(unsigned Opcode) const2473 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2474 const uint64_t F = get(Opcode).TSFlags;
2475 assert(isPredicated(Opcode));
2476 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2477 }
2478
isPredicatedTrue(const MachineInstr & MI) const2479 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2480 const uint64_t F = MI.getDesc().TSFlags;
2481 return !((F >> HexagonII::PredicatedFalsePos) &
2482 HexagonII::PredicatedFalseMask);
2483 }
2484
isPredicatedTrue(unsigned Opcode) const2485 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2486 const uint64_t F = get(Opcode).TSFlags;
2487 // Make sure that the instruction is predicated.
2488 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2489 return !((F >> HexagonII::PredicatedFalsePos) &
2490 HexagonII::PredicatedFalseMask);
2491 }
2492
isPredicated(unsigned Opcode) const2493 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2494 const uint64_t F = get(Opcode).TSFlags;
2495 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2496 }
2497
isPredicateLate(unsigned Opcode) const2498 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2499 const uint64_t F = get(Opcode).TSFlags;
2500 return (F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2501 }
2502
isPredictedTaken(unsigned Opcode) const2503 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2504 const uint64_t F = get(Opcode).TSFlags;
2505 assert(get(Opcode).isBranch() &&
2506 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2507 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2508 }
2509
isSaveCalleeSavedRegsCall(const MachineInstr & MI) const2510 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2511 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2512 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2513 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2514 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2515 }
2516
isSignExtendingLoad(const MachineInstr & MI) const2517 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2518 switch (MI.getOpcode()) {
2519 // Byte
2520 case Hexagon::L2_loadrb_io:
2521 case Hexagon::L4_loadrb_ur:
2522 case Hexagon::L4_loadrb_ap:
2523 case Hexagon::L2_loadrb_pr:
2524 case Hexagon::L2_loadrb_pbr:
2525 case Hexagon::L2_loadrb_pi:
2526 case Hexagon::L2_loadrb_pci:
2527 case Hexagon::L2_loadrb_pcr:
2528 case Hexagon::L2_loadbsw2_io:
2529 case Hexagon::L4_loadbsw2_ur:
2530 case Hexagon::L4_loadbsw2_ap:
2531 case Hexagon::L2_loadbsw2_pr:
2532 case Hexagon::L2_loadbsw2_pbr:
2533 case Hexagon::L2_loadbsw2_pi:
2534 case Hexagon::L2_loadbsw2_pci:
2535 case Hexagon::L2_loadbsw2_pcr:
2536 case Hexagon::L2_loadbsw4_io:
2537 case Hexagon::L4_loadbsw4_ur:
2538 case Hexagon::L4_loadbsw4_ap:
2539 case Hexagon::L2_loadbsw4_pr:
2540 case Hexagon::L2_loadbsw4_pbr:
2541 case Hexagon::L2_loadbsw4_pi:
2542 case Hexagon::L2_loadbsw4_pci:
2543 case Hexagon::L2_loadbsw4_pcr:
2544 case Hexagon::L4_loadrb_rr:
2545 case Hexagon::L2_ploadrbt_io:
2546 case Hexagon::L2_ploadrbt_pi:
2547 case Hexagon::L2_ploadrbf_io:
2548 case Hexagon::L2_ploadrbf_pi:
2549 case Hexagon::L2_ploadrbtnew_io:
2550 case Hexagon::L2_ploadrbfnew_io:
2551 case Hexagon::L4_ploadrbt_rr:
2552 case Hexagon::L4_ploadrbf_rr:
2553 case Hexagon::L4_ploadrbtnew_rr:
2554 case Hexagon::L4_ploadrbfnew_rr:
2555 case Hexagon::L2_ploadrbtnew_pi:
2556 case Hexagon::L2_ploadrbfnew_pi:
2557 case Hexagon::L4_ploadrbt_abs:
2558 case Hexagon::L4_ploadrbf_abs:
2559 case Hexagon::L4_ploadrbtnew_abs:
2560 case Hexagon::L4_ploadrbfnew_abs:
2561 case Hexagon::L2_loadrbgp:
2562 // Half
2563 case Hexagon::L2_loadrh_io:
2564 case Hexagon::L4_loadrh_ur:
2565 case Hexagon::L4_loadrh_ap:
2566 case Hexagon::L2_loadrh_pr:
2567 case Hexagon::L2_loadrh_pbr:
2568 case Hexagon::L2_loadrh_pi:
2569 case Hexagon::L2_loadrh_pci:
2570 case Hexagon::L2_loadrh_pcr:
2571 case Hexagon::L4_loadrh_rr:
2572 case Hexagon::L2_ploadrht_io:
2573 case Hexagon::L2_ploadrht_pi:
2574 case Hexagon::L2_ploadrhf_io:
2575 case Hexagon::L2_ploadrhf_pi:
2576 case Hexagon::L2_ploadrhtnew_io:
2577 case Hexagon::L2_ploadrhfnew_io:
2578 case Hexagon::L4_ploadrht_rr:
2579 case Hexagon::L4_ploadrhf_rr:
2580 case Hexagon::L4_ploadrhtnew_rr:
2581 case Hexagon::L4_ploadrhfnew_rr:
2582 case Hexagon::L2_ploadrhtnew_pi:
2583 case Hexagon::L2_ploadrhfnew_pi:
2584 case Hexagon::L4_ploadrht_abs:
2585 case Hexagon::L4_ploadrhf_abs:
2586 case Hexagon::L4_ploadrhtnew_abs:
2587 case Hexagon::L4_ploadrhfnew_abs:
2588 case Hexagon::L2_loadrhgp:
2589 return true;
2590 default:
2591 return false;
2592 }
2593 }
2594
isSolo(const MachineInstr & MI) const2595 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2596 const uint64_t F = MI.getDesc().TSFlags;
2597 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2598 }
2599
isSpillPredRegOp(const MachineInstr & MI) const2600 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2601 switch (MI.getOpcode()) {
2602 case Hexagon::STriw_pred:
2603 case Hexagon::LDriw_pred:
2604 return true;
2605 default:
2606 return false;
2607 }
2608 }
2609
isTailCall(const MachineInstr & MI) const2610 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2611 if (!MI.isBranch())
2612 return false;
2613
2614 for (auto &Op : MI.operands())
2615 if (Op.isGlobal() || Op.isSymbol())
2616 return true;
2617 return false;
2618 }
2619
2620 // Returns true when SU has a timing class TC1.
isTC1(const MachineInstr & MI) const2621 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2622 unsigned SchedClass = MI.getDesc().getSchedClass();
2623 return is_TC1(SchedClass);
2624 }
2625
isTC2(const MachineInstr & MI) const2626 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2627 unsigned SchedClass = MI.getDesc().getSchedClass();
2628 return is_TC2(SchedClass);
2629 }
2630
isTC2Early(const MachineInstr & MI) const2631 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2632 unsigned SchedClass = MI.getDesc().getSchedClass();
2633 return is_TC2early(SchedClass);
2634 }
2635
isTC4x(const MachineInstr & MI) const2636 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2637 unsigned SchedClass = MI.getDesc().getSchedClass();
2638 return is_TC4x(SchedClass);
2639 }
2640
2641 // Schedule this ASAP.
isToBeScheduledASAP(const MachineInstr & MI1,const MachineInstr & MI2) const2642 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2643 const MachineInstr &MI2) const {
2644 if (mayBeCurLoad(MI1)) {
2645 // if (result of SU is used in Next) return true;
2646 Register DstReg = MI1.getOperand(0).getReg();
2647 int N = MI2.getNumOperands();
2648 for (int I = 0; I < N; I++)
2649 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2650 return true;
2651 }
2652 if (mayBeNewStore(MI2))
2653 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2654 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2655 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2656 return true;
2657 return false;
2658 }
2659
isHVXVec(const MachineInstr & MI) const2660 bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
2661 const uint64_t V = getType(MI);
2662 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2663 }
2664
2665 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
isValidAutoIncImm(const EVT VT,int Offset) const2666 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2667 int Size = VT.getSizeInBits() / 8;
2668 if (Offset % Size != 0)
2669 return false;
2670 int Count = Offset / Size;
2671
2672 switch (VT.getSimpleVT().SimpleTy) {
2673 // For scalars the auto-inc is s4
2674 case MVT::i8:
2675 case MVT::i16:
2676 case MVT::i32:
2677 case MVT::i64:
2678 case MVT::f32:
2679 case MVT::f64:
2680 case MVT::v2i16:
2681 case MVT::v2i32:
2682 case MVT::v4i8:
2683 case MVT::v4i16:
2684 case MVT::v8i8:
2685 return isInt<4>(Count);
2686 // For HVX vectors the auto-inc is s3
2687 case MVT::v64i8:
2688 case MVT::v32i16:
2689 case MVT::v16i32:
2690 case MVT::v8i64:
2691 case MVT::v128i8:
2692 case MVT::v64i16:
2693 case MVT::v32i32:
2694 case MVT::v16i64:
2695 return isInt<3>(Count);
2696 default:
2697 break;
2698 }
2699
2700 llvm_unreachable("Not an valid type!");
2701 }
2702
isValidOffset(unsigned Opcode,int Offset,const TargetRegisterInfo * TRI,bool Extend) const2703 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2704 const TargetRegisterInfo *TRI, bool Extend) const {
2705 // This function is to check whether the "Offset" is in the correct range of
2706 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2707 // inserted to calculate the final address. Due to this reason, the function
2708 // assumes that the "Offset" has correct alignment.
2709 // We used to assert if the offset was not properly aligned, however,
2710 // there are cases where a misaligned pointer recast can cause this
2711 // problem, and we need to allow for it. The front end warns of such
2712 // misaligns with respect to load size.
2713 switch (Opcode) {
2714 case Hexagon::PS_vstorerq_ai:
2715 case Hexagon::PS_vstorerv_ai:
2716 case Hexagon::PS_vstorerw_ai:
2717 case Hexagon::PS_vstorerw_nt_ai:
2718 case Hexagon::PS_vloadrq_ai:
2719 case Hexagon::PS_vloadrv_ai:
2720 case Hexagon::PS_vloadrw_ai:
2721 case Hexagon::PS_vloadrw_nt_ai:
2722 case Hexagon::V6_vL32b_ai:
2723 case Hexagon::V6_vS32b_ai:
2724 case Hexagon::V6_vL32b_nt_ai:
2725 case Hexagon::V6_vS32b_nt_ai:
2726 case Hexagon::V6_vL32Ub_ai:
2727 case Hexagon::V6_vS32Ub_ai: {
2728 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2729 assert(isPowerOf2_32(VectorSize));
2730 if (Offset & (VectorSize-1))
2731 return false;
2732 return isInt<4>(Offset >> Log2_32(VectorSize));
2733 }
2734
2735 case Hexagon::J2_loop0i:
2736 case Hexagon::J2_loop1i:
2737 return isUInt<10>(Offset);
2738
2739 case Hexagon::S4_storeirb_io:
2740 case Hexagon::S4_storeirbt_io:
2741 case Hexagon::S4_storeirbf_io:
2742 return isUInt<6>(Offset);
2743
2744 case Hexagon::S4_storeirh_io:
2745 case Hexagon::S4_storeirht_io:
2746 case Hexagon::S4_storeirhf_io:
2747 return isShiftedUInt<6,1>(Offset);
2748
2749 case Hexagon::S4_storeiri_io:
2750 case Hexagon::S4_storeirit_io:
2751 case Hexagon::S4_storeirif_io:
2752 return isShiftedUInt<6,2>(Offset);
2753 }
2754
2755 if (Extend)
2756 return true;
2757
2758 switch (Opcode) {
2759 case Hexagon::L2_loadri_io:
2760 case Hexagon::S2_storeri_io:
2761 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2762 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2763
2764 case Hexagon::L2_loadrd_io:
2765 case Hexagon::S2_storerd_io:
2766 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2767 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2768
2769 case Hexagon::L2_loadrh_io:
2770 case Hexagon::L2_loadruh_io:
2771 case Hexagon::S2_storerh_io:
2772 case Hexagon::S2_storerf_io:
2773 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2774 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2775
2776 case Hexagon::L2_loadrb_io:
2777 case Hexagon::L2_loadrub_io:
2778 case Hexagon::S2_storerb_io:
2779 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2780 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2781
2782 case Hexagon::A2_addi:
2783 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2784 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2785
2786 case Hexagon::L4_iadd_memopw_io:
2787 case Hexagon::L4_isub_memopw_io:
2788 case Hexagon::L4_add_memopw_io:
2789 case Hexagon::L4_sub_memopw_io:
2790 case Hexagon::L4_and_memopw_io:
2791 case Hexagon::L4_or_memopw_io:
2792 return (0 <= Offset && Offset <= 255);
2793
2794 case Hexagon::L4_iadd_memoph_io:
2795 case Hexagon::L4_isub_memoph_io:
2796 case Hexagon::L4_add_memoph_io:
2797 case Hexagon::L4_sub_memoph_io:
2798 case Hexagon::L4_and_memoph_io:
2799 case Hexagon::L4_or_memoph_io:
2800 return (0 <= Offset && Offset <= 127);
2801
2802 case Hexagon::L4_iadd_memopb_io:
2803 case Hexagon::L4_isub_memopb_io:
2804 case Hexagon::L4_add_memopb_io:
2805 case Hexagon::L4_sub_memopb_io:
2806 case Hexagon::L4_and_memopb_io:
2807 case Hexagon::L4_or_memopb_io:
2808 return (0 <= Offset && Offset <= 63);
2809
2810 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2811 // any size. Later pass knows how to handle it.
2812 case Hexagon::STriw_pred:
2813 case Hexagon::LDriw_pred:
2814 case Hexagon::STriw_ctr:
2815 case Hexagon::LDriw_ctr:
2816 return true;
2817
2818 case Hexagon::PS_fi:
2819 case Hexagon::PS_fia:
2820 case Hexagon::INLINEASM:
2821 return true;
2822
2823 case Hexagon::L2_ploadrbt_io:
2824 case Hexagon::L2_ploadrbf_io:
2825 case Hexagon::L2_ploadrubt_io:
2826 case Hexagon::L2_ploadrubf_io:
2827 case Hexagon::S2_pstorerbt_io:
2828 case Hexagon::S2_pstorerbf_io:
2829 return isUInt<6>(Offset);
2830
2831 case Hexagon::L2_ploadrht_io:
2832 case Hexagon::L2_ploadrhf_io:
2833 case Hexagon::L2_ploadruht_io:
2834 case Hexagon::L2_ploadruhf_io:
2835 case Hexagon::S2_pstorerht_io:
2836 case Hexagon::S2_pstorerhf_io:
2837 return isShiftedUInt<6,1>(Offset);
2838
2839 case Hexagon::L2_ploadrit_io:
2840 case Hexagon::L2_ploadrif_io:
2841 case Hexagon::S2_pstorerit_io:
2842 case Hexagon::S2_pstorerif_io:
2843 return isShiftedUInt<6,2>(Offset);
2844
2845 case Hexagon::L2_ploadrdt_io:
2846 case Hexagon::L2_ploadrdf_io:
2847 case Hexagon::S2_pstorerdt_io:
2848 case Hexagon::S2_pstorerdf_io:
2849 return isShiftedUInt<6,3>(Offset);
2850 } // switch
2851
2852 llvm_unreachable("No offset range is defined for this opcode. "
2853 "Please define it in the above switch statement!");
2854 }
2855
isVecAcc(const MachineInstr & MI) const2856 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2857 return isHVXVec(MI) && isAccumulator(MI);
2858 }
2859
isVecALU(const MachineInstr & MI) const2860 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
2861 const uint64_t F = get(MI.getOpcode()).TSFlags;
2862 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2863 return
2864 V == HexagonII::TypeCVI_VA ||
2865 V == HexagonII::TypeCVI_VA_DV;
2866 }
2867
isVecUsableNextPacket(const MachineInstr & ProdMI,const MachineInstr & ConsMI) const2868 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
2869 const MachineInstr &ConsMI) const {
2870 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2871 return true;
2872
2873 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2874 return true;
2875
2876 if (mayBeNewStore(ConsMI))
2877 return true;
2878
2879 return false;
2880 }
2881
isZeroExtendingLoad(const MachineInstr & MI) const2882 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
2883 switch (MI.getOpcode()) {
2884 // Byte
2885 case Hexagon::L2_loadrub_io:
2886 case Hexagon::L4_loadrub_ur:
2887 case Hexagon::L4_loadrub_ap:
2888 case Hexagon::L2_loadrub_pr:
2889 case Hexagon::L2_loadrub_pbr:
2890 case Hexagon::L2_loadrub_pi:
2891 case Hexagon::L2_loadrub_pci:
2892 case Hexagon::L2_loadrub_pcr:
2893 case Hexagon::L2_loadbzw2_io:
2894 case Hexagon::L4_loadbzw2_ur:
2895 case Hexagon::L4_loadbzw2_ap:
2896 case Hexagon::L2_loadbzw2_pr:
2897 case Hexagon::L2_loadbzw2_pbr:
2898 case Hexagon::L2_loadbzw2_pi:
2899 case Hexagon::L2_loadbzw2_pci:
2900 case Hexagon::L2_loadbzw2_pcr:
2901 case Hexagon::L2_loadbzw4_io:
2902 case Hexagon::L4_loadbzw4_ur:
2903 case Hexagon::L4_loadbzw4_ap:
2904 case Hexagon::L2_loadbzw4_pr:
2905 case Hexagon::L2_loadbzw4_pbr:
2906 case Hexagon::L2_loadbzw4_pi:
2907 case Hexagon::L2_loadbzw4_pci:
2908 case Hexagon::L2_loadbzw4_pcr:
2909 case Hexagon::L4_loadrub_rr:
2910 case Hexagon::L2_ploadrubt_io:
2911 case Hexagon::L2_ploadrubt_pi:
2912 case Hexagon::L2_ploadrubf_io:
2913 case Hexagon::L2_ploadrubf_pi:
2914 case Hexagon::L2_ploadrubtnew_io:
2915 case Hexagon::L2_ploadrubfnew_io:
2916 case Hexagon::L4_ploadrubt_rr:
2917 case Hexagon::L4_ploadrubf_rr:
2918 case Hexagon::L4_ploadrubtnew_rr:
2919 case Hexagon::L4_ploadrubfnew_rr:
2920 case Hexagon::L2_ploadrubtnew_pi:
2921 case Hexagon::L2_ploadrubfnew_pi:
2922 case Hexagon::L4_ploadrubt_abs:
2923 case Hexagon::L4_ploadrubf_abs:
2924 case Hexagon::L4_ploadrubtnew_abs:
2925 case Hexagon::L4_ploadrubfnew_abs:
2926 case Hexagon::L2_loadrubgp:
2927 // Half
2928 case Hexagon::L2_loadruh_io:
2929 case Hexagon::L4_loadruh_ur:
2930 case Hexagon::L4_loadruh_ap:
2931 case Hexagon::L2_loadruh_pr:
2932 case Hexagon::L2_loadruh_pbr:
2933 case Hexagon::L2_loadruh_pi:
2934 case Hexagon::L2_loadruh_pci:
2935 case Hexagon::L2_loadruh_pcr:
2936 case Hexagon::L4_loadruh_rr:
2937 case Hexagon::L2_ploadruht_io:
2938 case Hexagon::L2_ploadruht_pi:
2939 case Hexagon::L2_ploadruhf_io:
2940 case Hexagon::L2_ploadruhf_pi:
2941 case Hexagon::L2_ploadruhtnew_io:
2942 case Hexagon::L2_ploadruhfnew_io:
2943 case Hexagon::L4_ploadruht_rr:
2944 case Hexagon::L4_ploadruhf_rr:
2945 case Hexagon::L4_ploadruhtnew_rr:
2946 case Hexagon::L4_ploadruhfnew_rr:
2947 case Hexagon::L2_ploadruhtnew_pi:
2948 case Hexagon::L2_ploadruhfnew_pi:
2949 case Hexagon::L4_ploadruht_abs:
2950 case Hexagon::L4_ploadruhf_abs:
2951 case Hexagon::L4_ploadruhtnew_abs:
2952 case Hexagon::L4_ploadruhfnew_abs:
2953 case Hexagon::L2_loadruhgp:
2954 return true;
2955 default:
2956 return false;
2957 }
2958 }
2959
2960 // Add latency to instruction.
addLatencyToSchedule(const MachineInstr & MI1,const MachineInstr & MI2) const2961 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
2962 const MachineInstr &MI2) const {
2963 if (isHVXVec(MI1) && isHVXVec(MI2))
2964 if (!isVecUsableNextPacket(MI1, MI2))
2965 return true;
2966 return false;
2967 }
2968
2969 /// Get the base register and byte offset of a load/store instr.
getMemOperandsWithOffsetWidth(const MachineInstr & LdSt,SmallVectorImpl<const MachineOperand * > & BaseOps,int64_t & Offset,bool & OffsetIsScalable,unsigned & Width,const TargetRegisterInfo * TRI) const2970 bool HexagonInstrInfo::getMemOperandsWithOffsetWidth(
2971 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
2972 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
2973 const TargetRegisterInfo *TRI) const {
2974 OffsetIsScalable = false;
2975 const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
2976 if (!BaseOp || !BaseOp->isReg())
2977 return false;
2978 BaseOps.push_back(BaseOp);
2979 return true;
2980 }
2981
2982 /// Can these instructions execute at the same time in a bundle.
canExecuteInBundle(const MachineInstr & First,const MachineInstr & Second) const2983 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
2984 const MachineInstr &Second) const {
2985 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2986 const MachineOperand &Op = Second.getOperand(0);
2987 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2988 return true;
2989 }
2990 if (DisableNVSchedule)
2991 return false;
2992 if (mayBeNewStore(Second)) {
2993 // Make sure the definition of the first instruction is the value being
2994 // stored.
2995 const MachineOperand &Stored =
2996 Second.getOperand(Second.getNumOperands() - 1);
2997 if (!Stored.isReg())
2998 return false;
2999 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3000 const MachineOperand &Op = First.getOperand(i);
3001 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3002 return true;
3003 }
3004 }
3005 return false;
3006 }
3007
doesNotReturn(const MachineInstr & CallMI) const3008 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
3009 unsigned Opc = CallMI.getOpcode();
3010 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3011 }
3012
hasEHLabel(const MachineBasicBlock * B) const3013 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
3014 for (auto &I : *B)
3015 if (I.isEHLabel())
3016 return true;
3017 return false;
3018 }
3019
3020 // Returns true if an instruction can be converted into a non-extended
3021 // equivalent instruction.
hasNonExtEquivalent(const MachineInstr & MI) const3022 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
3023 short NonExtOpcode;
3024 // Check if the instruction has a register form that uses register in place
3025 // of the extended operand, if so return that as the non-extended form.
3026 if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
3027 return true;
3028
3029 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3030 // Check addressing mode and retrieve non-ext equivalent instruction.
3031
3032 switch (getAddrMode(MI)) {
3033 case HexagonII::Absolute:
3034 // Load/store with absolute addressing mode can be converted into
3035 // base+offset mode.
3036 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
3037 break;
3038 case HexagonII::BaseImmOffset:
3039 // Load/store with base+offset addressing mode can be converted into
3040 // base+register offset addressing mode. However left shift operand should
3041 // be set to 0.
3042 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3043 break;
3044 case HexagonII::BaseLongOffset:
3045 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3046 break;
3047 default:
3048 return false;
3049 }
3050 if (NonExtOpcode < 0)
3051 return false;
3052 return true;
3053 }
3054 return false;
3055 }
3056
hasPseudoInstrPair(const MachineInstr & MI) const3057 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
3058 return Hexagon::getRealHWInstr(MI.getOpcode(),
3059 Hexagon::InstrType_Pseudo) >= 0;
3060 }
3061
hasUncondBranch(const MachineBasicBlock * B) const3062 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3063 const {
3064 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3065 while (I != E) {
3066 if (I->isBarrier())
3067 return true;
3068 ++I;
3069 }
3070 return false;
3071 }
3072
3073 // Returns true, if a LD insn can be promoted to a cur load.
mayBeCurLoad(const MachineInstr & MI) const3074 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
3075 const uint64_t F = MI.getDesc().TSFlags;
3076 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
3077 Subtarget.hasV60Ops();
3078 }
3079
3080 // Returns true, if a ST insn can be promoted to a new-value store.
mayBeNewStore(const MachineInstr & MI) const3081 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
3082 if (MI.mayStore() && !Subtarget.useNewValueStores())
3083 return false;
3084
3085 const uint64_t F = MI.getDesc().TSFlags;
3086 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
3087 }
3088
producesStall(const MachineInstr & ProdMI,const MachineInstr & ConsMI) const3089 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
3090 const MachineInstr &ConsMI) const {
3091 // There is no stall when ProdMI is not a V60 vector.
3092 if (!isHVXVec(ProdMI))
3093 return false;
3094
3095 // There is no stall when ProdMI and ConsMI are not dependent.
3096 if (!isDependent(ProdMI, ConsMI))
3097 return false;
3098
3099 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3100 // are scheduled in consecutive packets.
3101 if (isVecUsableNextPacket(ProdMI, ConsMI))
3102 return false;
3103
3104 return true;
3105 }
3106
producesStall(const MachineInstr & MI,MachineBasicBlock::const_instr_iterator BII) const3107 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
3108 MachineBasicBlock::const_instr_iterator BII) const {
3109 // There is no stall when I is not a V60 vector.
3110 if (!isHVXVec(MI))
3111 return false;
3112
3113 MachineBasicBlock::const_instr_iterator MII = BII;
3114 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3115
3116 if (!MII->isBundle())
3117 return producesStall(*MII, MI);
3118
3119 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3120 const MachineInstr &J = *MII;
3121 if (producesStall(J, MI))
3122 return true;
3123 }
3124 return false;
3125 }
3126
predCanBeUsedAsDotNew(const MachineInstr & MI,unsigned PredReg) const3127 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3128 unsigned PredReg) const {
3129 for (const MachineOperand &MO : MI.operands()) {
3130 // Predicate register must be explicitly defined.
3131 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3132 return false;
3133 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3134 return false;
3135 }
3136
3137 // Instruction that produce late predicate cannot be used as sources of
3138 // dot-new.
3139 switch (MI.getOpcode()) {
3140 case Hexagon::A4_addp_c:
3141 case Hexagon::A4_subp_c:
3142 case Hexagon::A4_tlbmatch:
3143 case Hexagon::A5_ACS:
3144 case Hexagon::F2_sfinvsqrta:
3145 case Hexagon::F2_sfrecipa:
3146 case Hexagon::J2_endloop0:
3147 case Hexagon::J2_endloop01:
3148 case Hexagon::J2_ploop1si:
3149 case Hexagon::J2_ploop1sr:
3150 case Hexagon::J2_ploop2si:
3151 case Hexagon::J2_ploop2sr:
3152 case Hexagon::J2_ploop3si:
3153 case Hexagon::J2_ploop3sr:
3154 case Hexagon::S2_cabacdecbin:
3155 case Hexagon::S2_storew_locked:
3156 case Hexagon::S4_stored_locked:
3157 return false;
3158 }
3159 return true;
3160 }
3161
PredOpcodeHasJMP_c(unsigned Opcode) const3162 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3163 return Opcode == Hexagon::J2_jumpt ||
3164 Opcode == Hexagon::J2_jumptpt ||
3165 Opcode == Hexagon::J2_jumpf ||
3166 Opcode == Hexagon::J2_jumpfpt ||
3167 Opcode == Hexagon::J2_jumptnew ||
3168 Opcode == Hexagon::J2_jumpfnew ||
3169 Opcode == Hexagon::J2_jumptnewpt ||
3170 Opcode == Hexagon::J2_jumpfnewpt;
3171 }
3172
predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const3173 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3174 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3175 return false;
3176 return !isPredicatedTrue(Cond[0].getImm());
3177 }
3178
getAddrMode(const MachineInstr & MI) const3179 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3180 const uint64_t F = MI.getDesc().TSFlags;
3181 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
3182 }
3183
3184 // Returns the base register in a memory access (load/store). The offset is
3185 // returned in Offset and the access size is returned in AccessSize.
3186 // If the base operand has a subregister or the offset field does not contain
3187 // an immediate value, return nullptr.
getBaseAndOffset(const MachineInstr & MI,int64_t & Offset,unsigned & AccessSize) const3188 MachineOperand *HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
3189 int64_t &Offset,
3190 unsigned &AccessSize) const {
3191 // Return if it is not a base+offset type instruction or a MemOp.
3192 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
3193 getAddrMode(MI) != HexagonII::BaseLongOffset &&
3194 !isMemOp(MI) && !isPostIncrement(MI))
3195 return nullptr;
3196
3197 AccessSize = getMemAccessSize(MI);
3198
3199 unsigned BasePos = 0, OffsetPos = 0;
3200 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3201 return nullptr;
3202
3203 // Post increment updates its EA after the mem access,
3204 // so we need to treat its offset as zero.
3205 if (isPostIncrement(MI)) {
3206 Offset = 0;
3207 } else {
3208 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3209 if (!OffsetOp.isImm())
3210 return nullptr;
3211 Offset = OffsetOp.getImm();
3212 }
3213
3214 const MachineOperand &BaseOp = MI.getOperand(BasePos);
3215 if (BaseOp.getSubReg() != 0)
3216 return nullptr;
3217 return &const_cast<MachineOperand&>(BaseOp);
3218 }
3219
3220 /// Return the position of the base and offset operands for this instruction.
getBaseAndOffsetPosition(const MachineInstr & MI,unsigned & BasePos,unsigned & OffsetPos) const3221 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3222 unsigned &BasePos, unsigned &OffsetPos) const {
3223 if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3224 return false;
3225
3226 // Deal with memops first.
3227 if (isMemOp(MI)) {
3228 BasePos = 0;
3229 OffsetPos = 1;
3230 } else if (MI.mayStore()) {
3231 BasePos = 0;
3232 OffsetPos = 1;
3233 } else if (MI.mayLoad()) {
3234 BasePos = 1;
3235 OffsetPos = 2;
3236 } else
3237 return false;
3238
3239 if (isPredicated(MI)) {
3240 BasePos++;
3241 OffsetPos++;
3242 }
3243 if (isPostIncrement(MI)) {
3244 BasePos++;
3245 OffsetPos++;
3246 }
3247
3248 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3249 return false;
3250
3251 return true;
3252 }
3253
3254 // Inserts branching instructions in reverse order of their occurrence.
3255 // e.g. jump_t t1 (i1)
3256 // jump t2 (i2)
3257 // Jumpers = {i2, i1}
getBranchingInstrs(MachineBasicBlock & MBB) const3258 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3259 MachineBasicBlock& MBB) const {
3260 SmallVector<MachineInstr*, 2> Jumpers;
3261 // If the block has no terminators, it just falls into the block after it.
3262 MachineBasicBlock::instr_iterator I = MBB.instr_end();
3263 if (I == MBB.instr_begin())
3264 return Jumpers;
3265
3266 // A basic block may looks like this:
3267 //
3268 // [ insn
3269 // EH_LABEL
3270 // insn
3271 // insn
3272 // insn
3273 // EH_LABEL
3274 // insn ]
3275 //
3276 // It has two succs but does not have a terminator
3277 // Don't know how to handle it.
3278 do {
3279 --I;
3280 if (I->isEHLabel())
3281 return Jumpers;
3282 } while (I != MBB.instr_begin());
3283
3284 I = MBB.instr_end();
3285 --I;
3286
3287 while (I->isDebugInstr()) {
3288 if (I == MBB.instr_begin())
3289 return Jumpers;
3290 --I;
3291 }
3292 if (!isUnpredicatedTerminator(*I))
3293 return Jumpers;
3294
3295 // Get the last instruction in the block.
3296 MachineInstr *LastInst = &*I;
3297 Jumpers.push_back(LastInst);
3298 MachineInstr *SecondLastInst = nullptr;
3299 // Find one more terminator if present.
3300 do {
3301 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3302 if (!SecondLastInst) {
3303 SecondLastInst = &*I;
3304 Jumpers.push_back(SecondLastInst);
3305 } else // This is a third branch.
3306 return Jumpers;
3307 }
3308 if (I == MBB.instr_begin())
3309 break;
3310 --I;
3311 } while (true);
3312 return Jumpers;
3313 }
3314
3315 // Returns Operand Index for the constant extended instruction.
getCExtOpNum(const MachineInstr & MI) const3316 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3317 const uint64_t F = MI.getDesc().TSFlags;
3318 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
3319 }
3320
3321 // See if instruction could potentially be a duplex candidate.
3322 // If so, return its group. Zero otherwise.
getCompoundCandidateGroup(const MachineInstr & MI) const3323 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3324 const MachineInstr &MI) const {
3325 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3326
3327 switch (MI.getOpcode()) {
3328 default:
3329 return HexagonII::HCG_None;
3330 //
3331 // Compound pairs.
3332 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3333 // "Rd16=#U6 ; jump #r9:2"
3334 // "Rd16=Rs16 ; jump #r9:2"
3335 //
3336 case Hexagon::C2_cmpeq:
3337 case Hexagon::C2_cmpgt:
3338 case Hexagon::C2_cmpgtu:
3339 DstReg = MI.getOperand(0).getReg();
3340 Src1Reg = MI.getOperand(1).getReg();
3341 Src2Reg = MI.getOperand(2).getReg();
3342 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3343 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3344 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3345 return HexagonII::HCG_A;
3346 break;
3347 case Hexagon::C2_cmpeqi:
3348 case Hexagon::C2_cmpgti:
3349 case Hexagon::C2_cmpgtui:
3350 // P0 = cmp.eq(Rs,#u2)
3351 DstReg = MI.getOperand(0).getReg();
3352 SrcReg = MI.getOperand(1).getReg();
3353 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3354 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3355 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3356 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3357 (MI.getOperand(2).getImm() == -1)))
3358 return HexagonII::HCG_A;
3359 break;
3360 case Hexagon::A2_tfr:
3361 // Rd = Rs
3362 DstReg = MI.getOperand(0).getReg();
3363 SrcReg = MI.getOperand(1).getReg();
3364 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3365 return HexagonII::HCG_A;
3366 break;
3367 case Hexagon::A2_tfrsi:
3368 // Rd = #u6
3369 // Do not test for #u6 size since the const is getting extended
3370 // regardless and compound could be formed.
3371 DstReg = MI.getOperand(0).getReg();
3372 if (isIntRegForSubInst(DstReg))
3373 return HexagonII::HCG_A;
3374 break;
3375 case Hexagon::S2_tstbit_i:
3376 DstReg = MI.getOperand(0).getReg();
3377 Src1Reg = MI.getOperand(1).getReg();
3378 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3379 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3380 MI.getOperand(2).isImm() &&
3381 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3382 return HexagonII::HCG_A;
3383 break;
3384 // The fact that .new form is used pretty much guarantees
3385 // that predicate register will match. Nevertheless,
3386 // there could be some false positives without additional
3387 // checking.
3388 case Hexagon::J2_jumptnew:
3389 case Hexagon::J2_jumpfnew:
3390 case Hexagon::J2_jumptnewpt:
3391 case Hexagon::J2_jumpfnewpt:
3392 Src1Reg = MI.getOperand(0).getReg();
3393 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3394 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3395 return HexagonII::HCG_B;
3396 break;
3397 // Transfer and jump:
3398 // Rd=#U6 ; jump #r9:2
3399 // Rd=Rs ; jump #r9:2
3400 // Do not test for jump range here.
3401 case Hexagon::J2_jump:
3402 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3403 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3404 return HexagonII::HCG_C;
3405 }
3406
3407 return HexagonII::HCG_None;
3408 }
3409
3410 // Returns -1 when there is no opcode found.
getCompoundOpcode(const MachineInstr & GA,const MachineInstr & GB) const3411 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3412 const MachineInstr &GB) const {
3413 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
3414 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
3415 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3416 (GB.getOpcode() != Hexagon::J2_jumptnew))
3417 return -1u;
3418 Register DestReg = GA.getOperand(0).getReg();
3419 if (!GB.readsRegister(DestReg))
3420 return -1u;
3421 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3422 return -1u;
3423 // The value compared against must be either u5 or -1.
3424 const MachineOperand &CmpOp = GA.getOperand(2);
3425 if (!CmpOp.isImm())
3426 return -1u;
3427 int V = CmpOp.getImm();
3428 if (V == -1)
3429 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3430 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3431 if (!isUInt<5>(V))
3432 return -1u;
3433 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3434 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3435 }
3436
3437 // Returns -1 if there is no opcode found.
getDuplexOpcode(const MachineInstr & MI,bool ForBigCore) const3438 int HexagonInstrInfo::getDuplexOpcode(const MachineInstr &MI,
3439 bool ForBigCore) const {
3440 // Static table to switch the opcodes across Tiny Core and Big Core.
3441 // dup_ opcodes are Big core opcodes.
3442 // NOTE: There are special instructions that need to handled later.
3443 // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3444 // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3445 // The compiler need to base the root instruction to L6_return_map_to_raw
3446 // which can go any slot.
3447 static const std::map<unsigned, unsigned> DupMap = {
3448 {Hexagon::A2_add, Hexagon::dup_A2_add},
3449 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3450 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3451 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3452 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3453 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3454 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3455 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3456 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3457 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3458 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3459 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3460 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3461 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3462 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3463 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3464 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3465 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3466 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3467 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3468 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3469 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3470 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3471 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3472 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3473 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3474 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3475 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3476 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3477 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3478 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3479 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3480 };
3481 unsigned OpNum = MI.getOpcode();
3482 // Conversion to Big core.
3483 if (ForBigCore) {
3484 auto Iter = DupMap.find(OpNum);
3485 if (Iter != DupMap.end())
3486 return Iter->second;
3487 } else { // Conversion to Tiny core.
3488 for (auto Iter = DupMap.begin(), End = DupMap.end(); Iter != End; ++Iter)
3489 if (Iter->second == OpNum)
3490 return Iter->first;
3491 }
3492 return -1;
3493 }
3494
getCondOpcode(int Opc,bool invertPredicate) const3495 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3496 enum Hexagon::PredSense inPredSense;
3497 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3498 Hexagon::PredSense_true;
3499 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3500 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3501 return CondOpcode;
3502
3503 llvm_unreachable("Unexpected predicable instruction");
3504 }
3505
3506 // Return the cur value instruction for a given store.
getDotCurOp(const MachineInstr & MI) const3507 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3508 switch (MI.getOpcode()) {
3509 default: llvm_unreachable("Unknown .cur type");
3510 case Hexagon::V6_vL32b_pi:
3511 return Hexagon::V6_vL32b_cur_pi;
3512 case Hexagon::V6_vL32b_ai:
3513 return Hexagon::V6_vL32b_cur_ai;
3514 case Hexagon::V6_vL32b_nt_pi:
3515 return Hexagon::V6_vL32b_nt_cur_pi;
3516 case Hexagon::V6_vL32b_nt_ai:
3517 return Hexagon::V6_vL32b_nt_cur_ai;
3518 }
3519 return 0;
3520 }
3521
3522 // Return the regular version of the .cur instruction.
getNonDotCurOp(const MachineInstr & MI) const3523 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
3524 switch (MI.getOpcode()) {
3525 default: llvm_unreachable("Unknown .cur type");
3526 case Hexagon::V6_vL32b_cur_pi:
3527 return Hexagon::V6_vL32b_pi;
3528 case Hexagon::V6_vL32b_cur_ai:
3529 return Hexagon::V6_vL32b_ai;
3530 case Hexagon::V6_vL32b_nt_cur_pi:
3531 return Hexagon::V6_vL32b_nt_pi;
3532 case Hexagon::V6_vL32b_nt_cur_ai:
3533 return Hexagon::V6_vL32b_nt_ai;
3534 }
3535 return 0;
3536 }
3537
3538 // The diagram below shows the steps involved in the conversion of a predicated
3539 // store instruction to its .new predicated new-value form.
3540 //
3541 // Note: It doesn't include conditional new-value stores as they can't be
3542 // converted to .new predicate.
3543 //
3544 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3545 // ^ ^
3546 // / \ (not OK. it will cause new-value store to be
3547 // / X conditional on p0.new while R2 producer is
3548 // / \ on p0)
3549 // / \.
3550 // p.new store p.old NV store
3551 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3552 // ^ ^
3553 // \ /
3554 // \ /
3555 // \ /
3556 // p.old store
3557 // [if (p0)memw(R0+#0)=R2]
3558 //
3559 // The following set of instructions further explains the scenario where
3560 // conditional new-value store becomes invalid when promoted to .new predicate
3561 // form.
3562 //
3563 // { 1) if (p0) r0 = add(r1, r2)
3564 // 2) p0 = cmp.eq(r3, #0) }
3565 //
3566 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3567 // the first two instructions because in instr 1, r0 is conditional on old value
3568 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3569 // is not valid for new-value stores.
3570 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3571 // from the "Conditional Store" list. Because a predicated new value store
3572 // would NOT be promoted to a double dot new store. See diagram below:
3573 // This function returns yes for those stores that are predicated but not
3574 // yet promoted to predicate dot new instructions.
3575 //
3576 // +---------------------+
3577 // /-----| if (p0) memw(..)=r0 |---------\~
3578 // || +---------------------+ ||
3579 // promote || /\ /\ || promote
3580 // || /||\ /||\ ||
3581 // \||/ demote || \||/
3582 // \/ || || \/
3583 // +-------------------------+ || +-------------------------+
3584 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3585 // +-------------------------+ || +-------------------------+
3586 // || || ||
3587 // || demote \||/
3588 // promote || \/ NOT possible
3589 // || || /\~
3590 // \||/ || /||\~
3591 // \/ || ||
3592 // +-----------------------------+
3593 // | if (p0.new) memw(..)=r0.new |
3594 // +-----------------------------+
3595 // Double Dot New Store
3596 //
3597 // Returns the most basic instruction for the .new predicated instructions and
3598 // new-value stores.
3599 // For example, all of the following instructions will be converted back to the
3600 // same instruction:
3601 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3602 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3603 // 3) if (p0.new) memw(R0+#0) = R1 --->
3604 //
3605 // To understand the translation of instruction 1 to its original form, consider
3606 // a packet with 3 instructions.
3607 // { p0 = cmp.eq(R0,R1)
3608 // if (p0.new) R2 = add(R3, R4)
3609 // R5 = add (R3, R1)
3610 // }
3611 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3612 //
3613 // This instruction can be part of the previous packet only if both p0 and R2
3614 // are promoted to .new values. This promotion happens in steps, first
3615 // predicate register is promoted to .new and in the next iteration R2 is
3616 // promoted. Therefore, in case of dependence check failure (due to R5) during
3617 // next iteration, it should be converted back to its most basic form.
3618
3619 // Return the new value instruction for a given store.
getDotNewOp(const MachineInstr & MI) const3620 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3621 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3622 if (NVOpcode >= 0) // Valid new-value store instruction.
3623 return NVOpcode;
3624
3625 switch (MI.getOpcode()) {
3626 default:
3627 report_fatal_error(std::string("Unknown .new type: ") +
3628 std::to_string(MI.getOpcode()));
3629 case Hexagon::S4_storerb_ur:
3630 return Hexagon::S4_storerbnew_ur;
3631
3632 case Hexagon::S2_storerb_pci:
3633 return Hexagon::S2_storerb_pci;
3634
3635 case Hexagon::S2_storeri_pci:
3636 return Hexagon::S2_storeri_pci;
3637
3638 case Hexagon::S2_storerh_pci:
3639 return Hexagon::S2_storerh_pci;
3640
3641 case Hexagon::S2_storerd_pci:
3642 return Hexagon::S2_storerd_pci;
3643
3644 case Hexagon::S2_storerf_pci:
3645 return Hexagon::S2_storerf_pci;
3646
3647 case Hexagon::V6_vS32b_ai:
3648 return Hexagon::V6_vS32b_new_ai;
3649
3650 case Hexagon::V6_vS32b_pi:
3651 return Hexagon::V6_vS32b_new_pi;
3652 }
3653 return 0;
3654 }
3655
3656 // Returns the opcode to use when converting MI, which is a conditional jump,
3657 // into a conditional instruction which uses the .new value of the predicate.
3658 // We also use branch probabilities to add a hint to the jump.
3659 // If MBPI is null, all edges will be treated as equally likely for the
3660 // purposes of establishing a predication hint.
getDotNewPredJumpOp(const MachineInstr & MI,const MachineBranchProbabilityInfo * MBPI) const3661 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3662 const MachineBranchProbabilityInfo *MBPI) const {
3663 // We assume that block can have at most two successors.
3664 const MachineBasicBlock *Src = MI.getParent();
3665 const MachineOperand &BrTarget = MI.getOperand(1);
3666 bool Taken = false;
3667 const BranchProbability OneHalf(1, 2);
3668
3669 auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3670 const MachineBasicBlock *Dst) {
3671 if (MBPI)
3672 return MBPI->getEdgeProbability(Src, Dst);
3673 return BranchProbability(1, Src->succ_size());
3674 };
3675
3676 if (BrTarget.isMBB()) {
3677 const MachineBasicBlock *Dst = BrTarget.getMBB();
3678 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3679 } else {
3680 // The branch target is not a basic block (most likely a function).
3681 // Since BPI only gives probabilities for targets that are basic blocks,
3682 // try to identify another target of this branch (potentially a fall-
3683 // -through) and check the probability of that target.
3684 //
3685 // The only handled branch combinations are:
3686 // - one conditional branch,
3687 // - one conditional branch followed by one unconditional branch.
3688 // Otherwise, assume not-taken.
3689 assert(MI.isConditionalBranch());
3690 const MachineBasicBlock &B = *MI.getParent();
3691 bool SawCond = false, Bad = false;
3692 for (const MachineInstr &I : B) {
3693 if (!I.isBranch())
3694 continue;
3695 if (I.isConditionalBranch()) {
3696 SawCond = true;
3697 if (&I != &MI) {
3698 Bad = true;
3699 break;
3700 }
3701 }
3702 if (I.isUnconditionalBranch() && !SawCond) {
3703 Bad = true;
3704 break;
3705 }
3706 }
3707 if (!Bad) {
3708 MachineBasicBlock::const_instr_iterator It(MI);
3709 MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3710 if (NextIt == B.instr_end()) {
3711 // If this branch is the last, look for the fall-through block.
3712 for (const MachineBasicBlock *SB : B.successors()) {
3713 if (!B.isLayoutSuccessor(SB))
3714 continue;
3715 Taken = getEdgeProbability(Src, SB) < OneHalf;
3716 break;
3717 }
3718 } else {
3719 assert(NextIt->isUnconditionalBranch());
3720 // Find the first MBB operand and assume it's the target.
3721 const MachineBasicBlock *BT = nullptr;
3722 for (const MachineOperand &Op : NextIt->operands()) {
3723 if (!Op.isMBB())
3724 continue;
3725 BT = Op.getMBB();
3726 break;
3727 }
3728 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3729 }
3730 } // if (!Bad)
3731 }
3732
3733 // The Taken flag should be set to something reasonable by this point.
3734
3735 switch (MI.getOpcode()) {
3736 case Hexagon::J2_jumpt:
3737 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3738 case Hexagon::J2_jumpf:
3739 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3740
3741 default:
3742 llvm_unreachable("Unexpected jump instruction.");
3743 }
3744 }
3745
3746 // Return .new predicate version for an instruction.
getDotNewPredOp(const MachineInstr & MI,const MachineBranchProbabilityInfo * MBPI) const3747 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3748 const MachineBranchProbabilityInfo *MBPI) const {
3749 switch (MI.getOpcode()) {
3750 // Condtional Jumps
3751 case Hexagon::J2_jumpt:
3752 case Hexagon::J2_jumpf:
3753 return getDotNewPredJumpOp(MI, MBPI);
3754 }
3755
3756 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3757 if (NewOpcode >= 0)
3758 return NewOpcode;
3759 return 0;
3760 }
3761
getDotOldOp(const MachineInstr & MI) const3762 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3763 int NewOp = MI.getOpcode();
3764 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3765 NewOp = Hexagon::getPredOldOpcode(NewOp);
3766 // All Hexagon architectures have prediction bits on dot-new branches,
3767 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3768 // to pick the right opcode when converting back to dot-old.
3769 if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3770 switch (NewOp) {
3771 case Hexagon::J2_jumptpt:
3772 NewOp = Hexagon::J2_jumpt;
3773 break;
3774 case Hexagon::J2_jumpfpt:
3775 NewOp = Hexagon::J2_jumpf;
3776 break;
3777 case Hexagon::J2_jumprtpt:
3778 NewOp = Hexagon::J2_jumprt;
3779 break;
3780 case Hexagon::J2_jumprfpt:
3781 NewOp = Hexagon::J2_jumprf;
3782 break;
3783 }
3784 }
3785 assert(NewOp >= 0 &&
3786 "Couldn't change predicate new instruction to its old form.");
3787 }
3788
3789 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3790 NewOp = Hexagon::getNonNVStore(NewOp);
3791 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3792 }
3793
3794 if (Subtarget.hasV60Ops())
3795 return NewOp;
3796
3797 // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3798 switch (NewOp) {
3799 case Hexagon::J2_jumpfpt:
3800 return Hexagon::J2_jumpf;
3801 case Hexagon::J2_jumptpt:
3802 return Hexagon::J2_jumpt;
3803 case Hexagon::J2_jumprfpt:
3804 return Hexagon::J2_jumprf;
3805 case Hexagon::J2_jumprtpt:
3806 return Hexagon::J2_jumprt;
3807 }
3808 return NewOp;
3809 }
3810
3811 // See if instruction could potentially be a duplex candidate.
3812 // If so, return its group. Zero otherwise.
getDuplexCandidateGroup(const MachineInstr & MI) const3813 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3814 const MachineInstr &MI) const {
3815 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3816 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3817
3818 switch (MI.getOpcode()) {
3819 default:
3820 return HexagonII::HSIG_None;
3821 //
3822 // Group L1:
3823 //
3824 // Rd = memw(Rs+#u4:2)
3825 // Rd = memub(Rs+#u4:0)
3826 case Hexagon::L2_loadri_io:
3827 case Hexagon::dup_L2_loadri_io:
3828 DstReg = MI.getOperand(0).getReg();
3829 SrcReg = MI.getOperand(1).getReg();
3830 // Special case this one from Group L2.
3831 // Rd = memw(r29+#u5:2)
3832 if (isIntRegForSubInst(DstReg)) {
3833 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3834 HRI.getStackRegister() == SrcReg &&
3835 MI.getOperand(2).isImm() &&
3836 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3837 return HexagonII::HSIG_L2;
3838 // Rd = memw(Rs+#u4:2)
3839 if (isIntRegForSubInst(SrcReg) &&
3840 (MI.getOperand(2).isImm() &&
3841 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3842 return HexagonII::HSIG_L1;
3843 }
3844 break;
3845 case Hexagon::L2_loadrub_io:
3846 case Hexagon::dup_L2_loadrub_io:
3847 // Rd = memub(Rs+#u4:0)
3848 DstReg = MI.getOperand(0).getReg();
3849 SrcReg = MI.getOperand(1).getReg();
3850 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3851 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3852 return HexagonII::HSIG_L1;
3853 break;
3854 //
3855 // Group L2:
3856 //
3857 // Rd = memh/memuh(Rs+#u3:1)
3858 // Rd = memb(Rs+#u3:0)
3859 // Rd = memw(r29+#u5:2) - Handled above.
3860 // Rdd = memd(r29+#u5:3)
3861 // deallocframe
3862 // [if ([!]p0[.new])] dealloc_return
3863 // [if ([!]p0[.new])] jumpr r31
3864 case Hexagon::L2_loadrh_io:
3865 case Hexagon::L2_loadruh_io:
3866 case Hexagon::dup_L2_loadrh_io:
3867 case Hexagon::dup_L2_loadruh_io:
3868 // Rd = memh/memuh(Rs+#u3:1)
3869 DstReg = MI.getOperand(0).getReg();
3870 SrcReg = MI.getOperand(1).getReg();
3871 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3872 MI.getOperand(2).isImm() &&
3873 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3874 return HexagonII::HSIG_L2;
3875 break;
3876 case Hexagon::L2_loadrb_io:
3877 case Hexagon::dup_L2_loadrb_io:
3878 // Rd = memb(Rs+#u3:0)
3879 DstReg = MI.getOperand(0).getReg();
3880 SrcReg = MI.getOperand(1).getReg();
3881 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3882 MI.getOperand(2).isImm() &&
3883 isUInt<3>(MI.getOperand(2).getImm()))
3884 return HexagonII::HSIG_L2;
3885 break;
3886 case Hexagon::L2_loadrd_io:
3887 case Hexagon::dup_L2_loadrd_io:
3888 // Rdd = memd(r29+#u5:3)
3889 DstReg = MI.getOperand(0).getReg();
3890 SrcReg = MI.getOperand(1).getReg();
3891 if (isDblRegForSubInst(DstReg, HRI) &&
3892 Hexagon::IntRegsRegClass.contains(SrcReg) &&
3893 HRI.getStackRegister() == SrcReg &&
3894 MI.getOperand(2).isImm() &&
3895 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3896 return HexagonII::HSIG_L2;
3897 break;
3898 // dealloc_return is not documented in Hexagon Manual, but marked
3899 // with A_SUBINSN attribute in iset_v4classic.py.
3900 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3901 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3902 case Hexagon::L4_return:
3903 case Hexagon::L2_deallocframe:
3904 case Hexagon::dup_L2_deallocframe:
3905 return HexagonII::HSIG_L2;
3906 case Hexagon::EH_RETURN_JMPR:
3907 case Hexagon::PS_jmpret:
3908 case Hexagon::SL2_jumpr31:
3909 // jumpr r31
3910 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3911 DstReg = MI.getOperand(0).getReg();
3912 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3913 return HexagonII::HSIG_L2;
3914 break;
3915 case Hexagon::PS_jmprett:
3916 case Hexagon::PS_jmpretf:
3917 case Hexagon::PS_jmprettnewpt:
3918 case Hexagon::PS_jmpretfnewpt:
3919 case Hexagon::PS_jmprettnew:
3920 case Hexagon::PS_jmpretfnew:
3921 case Hexagon::SL2_jumpr31_t:
3922 case Hexagon::SL2_jumpr31_f:
3923 case Hexagon::SL2_jumpr31_tnew:
3924 case Hexagon::SL2_jumpr31_fnew:
3925 DstReg = MI.getOperand(1).getReg();
3926 SrcReg = MI.getOperand(0).getReg();
3927 // [if ([!]p0[.new])] jumpr r31
3928 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3929 (Hexagon::P0 == SrcReg)) &&
3930 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3931 return HexagonII::HSIG_L2;
3932 break;
3933 case Hexagon::L4_return_t:
3934 case Hexagon::L4_return_f:
3935 case Hexagon::L4_return_tnew_pnt:
3936 case Hexagon::L4_return_fnew_pnt:
3937 case Hexagon::L4_return_tnew_pt:
3938 case Hexagon::L4_return_fnew_pt:
3939 // [if ([!]p0[.new])] dealloc_return
3940 SrcReg = MI.getOperand(0).getReg();
3941 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3942 return HexagonII::HSIG_L2;
3943 break;
3944 //
3945 // Group S1:
3946 //
3947 // memw(Rs+#u4:2) = Rt
3948 // memb(Rs+#u4:0) = Rt
3949 case Hexagon::S2_storeri_io:
3950 case Hexagon::dup_S2_storeri_io:
3951 // Special case this one from Group S2.
3952 // memw(r29+#u5:2) = Rt
3953 Src1Reg = MI.getOperand(0).getReg();
3954 Src2Reg = MI.getOperand(2).getReg();
3955 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3956 isIntRegForSubInst(Src2Reg) &&
3957 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3958 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3959 return HexagonII::HSIG_S2;
3960 // memw(Rs+#u4:2) = Rt
3961 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3962 MI.getOperand(1).isImm() &&
3963 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3964 return HexagonII::HSIG_S1;
3965 break;
3966 case Hexagon::S2_storerb_io:
3967 case Hexagon::dup_S2_storerb_io:
3968 // memb(Rs+#u4:0) = Rt
3969 Src1Reg = MI.getOperand(0).getReg();
3970 Src2Reg = MI.getOperand(2).getReg();
3971 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3972 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3973 return HexagonII::HSIG_S1;
3974 break;
3975 //
3976 // Group S2:
3977 //
3978 // memh(Rs+#u3:1) = Rt
3979 // memw(r29+#u5:2) = Rt
3980 // memd(r29+#s6:3) = Rtt
3981 // memw(Rs+#u4:2) = #U1
3982 // memb(Rs+#u4) = #U1
3983 // allocframe(#u5:3)
3984 case Hexagon::S2_storerh_io:
3985 case Hexagon::dup_S2_storerh_io:
3986 // memh(Rs+#u3:1) = Rt
3987 Src1Reg = MI.getOperand(0).getReg();
3988 Src2Reg = MI.getOperand(2).getReg();
3989 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3990 MI.getOperand(1).isImm() &&
3991 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3992 return HexagonII::HSIG_S1;
3993 break;
3994 case Hexagon::S2_storerd_io:
3995 case Hexagon::dup_S2_storerd_io:
3996 // memd(r29+#s6:3) = Rtt
3997 Src1Reg = MI.getOperand(0).getReg();
3998 Src2Reg = MI.getOperand(2).getReg();
3999 if (isDblRegForSubInst(Src2Reg, HRI) &&
4000 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
4001 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
4002 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
4003 return HexagonII::HSIG_S2;
4004 break;
4005 case Hexagon::S4_storeiri_io:
4006 case Hexagon::dup_S4_storeiri_io:
4007 // memw(Rs+#u4:2) = #U1
4008 Src1Reg = MI.getOperand(0).getReg();
4009 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
4010 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
4011 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4012 return HexagonII::HSIG_S2;
4013 break;
4014 case Hexagon::S4_storeirb_io:
4015 case Hexagon::dup_S4_storeirb_io:
4016 // memb(Rs+#u4) = #U1
4017 Src1Reg = MI.getOperand(0).getReg();
4018 if (isIntRegForSubInst(Src1Reg) &&
4019 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
4020 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
4021 return HexagonII::HSIG_S2;
4022 break;
4023 case Hexagon::S2_allocframe:
4024 case Hexagon::dup_S2_allocframe:
4025 if (MI.getOperand(2).isImm() &&
4026 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
4027 return HexagonII::HSIG_S1;
4028 break;
4029 //
4030 // Group A:
4031 //
4032 // Rx = add(Rx,#s7)
4033 // Rd = Rs
4034 // Rd = #u6
4035 // Rd = #-1
4036 // if ([!]P0[.new]) Rd = #0
4037 // Rd = add(r29,#u6:2)
4038 // Rx = add(Rx,Rs)
4039 // P0 = cmp.eq(Rs,#u2)
4040 // Rdd = combine(#0,Rs)
4041 // Rdd = combine(Rs,#0)
4042 // Rdd = combine(#u2,#U2)
4043 // Rd = add(Rs,#1)
4044 // Rd = add(Rs,#-1)
4045 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4046 // Rd = and(Rs,#1)
4047 case Hexagon::A2_addi:
4048 case Hexagon::dup_A2_addi:
4049 DstReg = MI.getOperand(0).getReg();
4050 SrcReg = MI.getOperand(1).getReg();
4051 if (isIntRegForSubInst(DstReg)) {
4052 // Rd = add(r29,#u6:2)
4053 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4054 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
4055 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
4056 return HexagonII::HSIG_A;
4057 // Rx = add(Rx,#s7)
4058 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
4059 isInt<7>(MI.getOperand(2).getImm()))
4060 return HexagonII::HSIG_A;
4061 // Rd = add(Rs,#1)
4062 // Rd = add(Rs,#-1)
4063 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
4064 ((MI.getOperand(2).getImm() == 1) ||
4065 (MI.getOperand(2).getImm() == -1)))
4066 return HexagonII::HSIG_A;
4067 }
4068 break;
4069 case Hexagon::A2_add:
4070 case Hexagon::dup_A2_add:
4071 // Rx = add(Rx,Rs)
4072 DstReg = MI.getOperand(0).getReg();
4073 Src1Reg = MI.getOperand(1).getReg();
4074 Src2Reg = MI.getOperand(2).getReg();
4075 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
4076 isIntRegForSubInst(Src2Reg))
4077 return HexagonII::HSIG_A;
4078 break;
4079 case Hexagon::A2_andir:
4080 case Hexagon::dup_A2_andir:
4081 // Same as zxtb.
4082 // Rd16=and(Rs16,#255)
4083 // Rd16=and(Rs16,#1)
4084 DstReg = MI.getOperand(0).getReg();
4085 SrcReg = MI.getOperand(1).getReg();
4086 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
4087 MI.getOperand(2).isImm() &&
4088 ((MI.getOperand(2).getImm() == 1) ||
4089 (MI.getOperand(2).getImm() == 255)))
4090 return HexagonII::HSIG_A;
4091 break;
4092 case Hexagon::A2_tfr:
4093 case Hexagon::dup_A2_tfr:
4094 // Rd = Rs
4095 DstReg = MI.getOperand(0).getReg();
4096 SrcReg = MI.getOperand(1).getReg();
4097 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4098 return HexagonII::HSIG_A;
4099 break;
4100 case Hexagon::A2_tfrsi:
4101 case Hexagon::dup_A2_tfrsi:
4102 // Rd = #u6
4103 // Do not test for #u6 size since the const is getting extended
4104 // regardless and compound could be formed.
4105 // Rd = #-1
4106 DstReg = MI.getOperand(0).getReg();
4107 if (isIntRegForSubInst(DstReg))
4108 return HexagonII::HSIG_A;
4109 break;
4110 case Hexagon::C2_cmoveit:
4111 case Hexagon::C2_cmovenewit:
4112 case Hexagon::C2_cmoveif:
4113 case Hexagon::C2_cmovenewif:
4114 case Hexagon::dup_C2_cmoveit:
4115 case Hexagon::dup_C2_cmovenewit:
4116 case Hexagon::dup_C2_cmoveif:
4117 case Hexagon::dup_C2_cmovenewif:
4118 // if ([!]P0[.new]) Rd = #0
4119 // Actual form:
4120 // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4121 DstReg = MI.getOperand(0).getReg();
4122 SrcReg = MI.getOperand(1).getReg();
4123 if (isIntRegForSubInst(DstReg) &&
4124 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4125 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4126 return HexagonII::HSIG_A;
4127 break;
4128 case Hexagon::C2_cmpeqi:
4129 case Hexagon::dup_C2_cmpeqi:
4130 // P0 = cmp.eq(Rs,#u2)
4131 DstReg = MI.getOperand(0).getReg();
4132 SrcReg = MI.getOperand(1).getReg();
4133 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4134 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4135 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4136 return HexagonII::HSIG_A;
4137 break;
4138 case Hexagon::A2_combineii:
4139 case Hexagon::A4_combineii:
4140 case Hexagon::dup_A2_combineii:
4141 case Hexagon::dup_A4_combineii:
4142 // Rdd = combine(#u2,#U2)
4143 DstReg = MI.getOperand(0).getReg();
4144 if (isDblRegForSubInst(DstReg, HRI) &&
4145 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4146 (MI.getOperand(1).isGlobal() &&
4147 isUInt<2>(MI.getOperand(1).getOffset()))) &&
4148 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4149 (MI.getOperand(2).isGlobal() &&
4150 isUInt<2>(MI.getOperand(2).getOffset()))))
4151 return HexagonII::HSIG_A;
4152 break;
4153 case Hexagon::A4_combineri:
4154 case Hexagon::dup_A4_combineri:
4155 // Rdd = combine(Rs,#0)
4156 // Rdd = combine(Rs,#0)
4157 DstReg = MI.getOperand(0).getReg();
4158 SrcReg = MI.getOperand(1).getReg();
4159 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4160 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4161 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4162 return HexagonII::HSIG_A;
4163 break;
4164 case Hexagon::A4_combineir:
4165 case Hexagon::dup_A4_combineir:
4166 // Rdd = combine(#0,Rs)
4167 DstReg = MI.getOperand(0).getReg();
4168 SrcReg = MI.getOperand(2).getReg();
4169 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4170 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4171 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4172 return HexagonII::HSIG_A;
4173 break;
4174 case Hexagon::A2_sxtb:
4175 case Hexagon::A2_sxth:
4176 case Hexagon::A2_zxtb:
4177 case Hexagon::A2_zxth:
4178 case Hexagon::dup_A2_sxtb:
4179 case Hexagon::dup_A2_sxth:
4180 case Hexagon::dup_A2_zxtb:
4181 case Hexagon::dup_A2_zxth:
4182 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4183 DstReg = MI.getOperand(0).getReg();
4184 SrcReg = MI.getOperand(1).getReg();
4185 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4186 return HexagonII::HSIG_A;
4187 break;
4188 }
4189
4190 return HexagonII::HSIG_None;
4191 }
4192
getEquivalentHWInstr(const MachineInstr & MI) const4193 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
4194 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4195 }
4196
getInstrTimingClassLatency(const InstrItineraryData * ItinData,const MachineInstr & MI) const4197 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
4198 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4199 // Default to one cycle for no itinerary. However, an "empty" itinerary may
4200 // still have a MinLatency property, which getStageLatency checks.
4201 if (!ItinData)
4202 return getInstrLatency(ItinData, MI);
4203
4204 if (MI.isTransient())
4205 return 0;
4206 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4207 }
4208
4209 /// getOperandLatency - Compute and return the use operand latency of a given
4210 /// pair of def and use.
4211 /// In most cases, the static scheduling itinerary was enough to determine the
4212 /// operand latency. But it may not be possible for instructions with variable
4213 /// number of defs / uses.
4214 ///
4215 /// This is a raw interface to the itinerary that may be directly overriden by
4216 /// a target. Use computeOperandLatency to get the best estimate of latency.
getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const4217 int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4218 const MachineInstr &DefMI,
4219 unsigned DefIdx,
4220 const MachineInstr &UseMI,
4221 unsigned UseIdx) const {
4222 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4223
4224 // Get DefIdx and UseIdx for super registers.
4225 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4226
4227 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4228 if (DefMO.isImplicit()) {
4229 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4230 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4231 if (Idx != -1) {
4232 DefIdx = Idx;
4233 break;
4234 }
4235 }
4236 }
4237
4238 const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4239 if (UseMO.isImplicit()) {
4240 for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4241 int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4242 if (Idx != -1) {
4243 UseIdx = Idx;
4244 break;
4245 }
4246 }
4247 }
4248 }
4249
4250 int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4251 UseMI, UseIdx);
4252 if (!Latency)
4253 // We should never have 0 cycle latency between two instructions unless
4254 // they can be packetized together. However, this decision can't be made
4255 // here.
4256 Latency = 1;
4257 return Latency;
4258 }
4259
4260 // inverts the predication logic.
4261 // p -> NotP
4262 // NotP -> P
getInvertedPredSense(SmallVectorImpl<MachineOperand> & Cond) const4263 bool HexagonInstrInfo::getInvertedPredSense(
4264 SmallVectorImpl<MachineOperand> &Cond) const {
4265 if (Cond.empty())
4266 return false;
4267 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4268 Cond[0].setImm(Opc);
4269 return true;
4270 }
4271
getInvertedPredicatedOpcode(const int Opc) const4272 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4273 int InvPredOpcode;
4274 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4275 : Hexagon::getTruePredOpcode(Opc);
4276 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4277 return InvPredOpcode;
4278
4279 llvm_unreachable("Unexpected predicated instruction");
4280 }
4281
4282 // Returns the max value that doesn't need to be extended.
getMaxValue(const MachineInstr & MI) const4283 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4284 const uint64_t F = MI.getDesc().TSFlags;
4285 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4286 & HexagonII::ExtentSignedMask;
4287 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4288 & HexagonII::ExtentBitsMask;
4289
4290 if (isSigned) // if value is signed
4291 return ~(-1U << (bits - 1));
4292 else
4293 return ~(-1U << bits);
4294 }
4295
4296
isAddrModeWithOffset(const MachineInstr & MI) const4297 bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {
4298 switch (MI.getOpcode()) {
4299 case Hexagon::L2_loadrbgp:
4300 case Hexagon::L2_loadrdgp:
4301 case Hexagon::L2_loadrhgp:
4302 case Hexagon::L2_loadrigp:
4303 case Hexagon::L2_loadrubgp:
4304 case Hexagon::L2_loadruhgp:
4305 case Hexagon::S2_storerbgp:
4306 case Hexagon::S2_storerbnewgp:
4307 case Hexagon::S2_storerhgp:
4308 case Hexagon::S2_storerhnewgp:
4309 case Hexagon::S2_storerigp:
4310 case Hexagon::S2_storerinewgp:
4311 case Hexagon::S2_storerdgp:
4312 case Hexagon::S2_storerfgp:
4313 return true;
4314 }
4315 const uint64_t F = MI.getDesc().TSFlags;
4316 unsigned addrMode =
4317 ((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
4318 // Disallow any base+offset instruction. The assembler does not yet reorder
4319 // based up any zero offset instruction.
4320 return (addrMode == HexagonII::BaseRegOffset ||
4321 addrMode == HexagonII::BaseImmOffset ||
4322 addrMode == HexagonII::BaseLongOffset);
4323 }
4324
isPureSlot0(const MachineInstr & MI) const4325 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const {
4326 // Workaround for the Global Scheduler. Sometimes, it creates
4327 // A4_ext as a Pseudo instruction and calls this function to see if
4328 // it can be added to an existing bundle. Since the instruction doesn't
4329 // belong to any BB yet, we can't use getUnits API.
4330 if (MI.getOpcode() == Hexagon::A4_ext)
4331 return false;
4332
4333 unsigned FuncUnits = getUnits(MI);
4334 return HexagonFUnits::isSlot0Only(FuncUnits);
4335 }
4336
isRestrictNoSlot1Store(const MachineInstr & MI) const4337 bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const {
4338 const uint64_t F = MI.getDesc().TSFlags;
4339 return ((F >> HexagonII::RestrictNoSlot1StorePos) &
4340 HexagonII::RestrictNoSlot1StoreMask);
4341 }
4342
changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,bool ToBigInstrs) const4343 void HexagonInstrInfo::changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,
4344 bool ToBigInstrs) const {
4345 int Opcode = -1;
4346 if (ToBigInstrs) { // To BigCore Instr.
4347 // Check if the instruction can form a Duplex.
4348 if (getDuplexCandidateGroup(*MII))
4349 // Get the opcode marked "dup_*" tag.
4350 Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4351 } else // To TinyCore Instr.
4352 Opcode = getDuplexOpcode(*MII, ToBigInstrs);
4353
4354 // Change the opcode of the instruction.
4355 if (Opcode >= 0)
4356 MII->setDesc(get(Opcode));
4357 }
4358
4359 // This function is used to translate instructions to facilitate generating
4360 // Duplexes on TinyCore.
translateInstrsForDup(MachineFunction & MF,bool ToBigInstrs) const4361 void HexagonInstrInfo::translateInstrsForDup(MachineFunction &MF,
4362 bool ToBigInstrs) const {
4363 for (auto &MB : MF)
4364 for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4365 End = MB.instr_end();
4366 Instr != End; ++Instr)
4367 changeDuplexOpcode(Instr, ToBigInstrs);
4368 }
4369
4370 // This is a specialized form of above function.
translateInstrsForDup(MachineBasicBlock::instr_iterator MII,bool ToBigInstrs) const4371 void HexagonInstrInfo::translateInstrsForDup(
4372 MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4373 MachineBasicBlock *MBB = MII->getParent();
4374 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4375 changeDuplexOpcode(MII, ToBigInstrs);
4376 ++MII;
4377 }
4378 }
4379
getMemAccessSize(const MachineInstr & MI) const4380 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4381 using namespace HexagonII;
4382
4383 const uint64_t F = MI.getDesc().TSFlags;
4384 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4385 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S));
4386 if (Size != 0)
4387 return Size;
4388
4389 // Handle vector access sizes.
4390 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4391 switch (S) {
4392 case HexagonII::HVXVectorAccess:
4393 return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4394 default:
4395 llvm_unreachable("Unexpected instruction");
4396 }
4397 }
4398
4399 // Returns the min value that doesn't need to be extended.
getMinValue(const MachineInstr & MI) const4400 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4401 const uint64_t F = MI.getDesc().TSFlags;
4402 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4403 & HexagonII::ExtentSignedMask;
4404 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4405 & HexagonII::ExtentBitsMask;
4406
4407 if (isSigned) // if value is signed
4408 return -1U << (bits - 1);
4409 else
4410 return 0;
4411 }
4412
4413 // Returns opcode of the non-extended equivalent instruction.
getNonExtOpcode(const MachineInstr & MI) const4414 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4415 // Check if the instruction has a register form that uses register in place
4416 // of the extended operand, if so return that as the non-extended form.
4417 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4418 if (NonExtOpcode >= 0)
4419 return NonExtOpcode;
4420
4421 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4422 // Check addressing mode and retrieve non-ext equivalent instruction.
4423 switch (getAddrMode(MI)) {
4424 case HexagonII::Absolute:
4425 return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4426 case HexagonII::BaseImmOffset:
4427 return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4428 case HexagonII::BaseLongOffset:
4429 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4430
4431 default:
4432 return -1;
4433 }
4434 }
4435 return -1;
4436 }
4437
getPredReg(ArrayRef<MachineOperand> Cond,unsigned & PredReg,unsigned & PredRegPos,unsigned & PredRegFlags) const4438 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4439 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4440 if (Cond.empty())
4441 return false;
4442 assert(Cond.size() == 2);
4443 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4444 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4445 return false;
4446 }
4447 PredReg = Cond[1].getReg();
4448 PredRegPos = 1;
4449 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4450 PredRegFlags = 0;
4451 if (Cond[1].isImplicit())
4452 PredRegFlags = RegState::Implicit;
4453 if (Cond[1].isUndef())
4454 PredRegFlags |= RegState::Undef;
4455 return true;
4456 }
4457
getPseudoInstrPair(const MachineInstr & MI) const4458 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4459 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4460 }
4461
getRegForm(const MachineInstr & MI) const4462 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4463 return Hexagon::getRegForm(MI.getOpcode());
4464 }
4465
4466 // Return the number of bytes required to encode the instruction.
4467 // Hexagon instructions are fixed length, 4 bytes, unless they
4468 // use a constant extender, which requires another 4 bytes.
4469 // For debug instructions and prolog labels, return 0.
getSize(const MachineInstr & MI) const4470 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4471 if (MI.isDebugInstr() || MI.isPosition())
4472 return 0;
4473
4474 unsigned Size = MI.getDesc().getSize();
4475 if (!Size)
4476 // Assume the default insn size in case it cannot be determined
4477 // for whatever reason.
4478 Size = HEXAGON_INSTR_SIZE;
4479
4480 if (isConstExtended(MI) || isExtended(MI))
4481 Size += HEXAGON_INSTR_SIZE;
4482
4483 // Try and compute number of instructions in asm.
4484 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4485 const MachineBasicBlock &MBB = *MI.getParent();
4486 const MachineFunction *MF = MBB.getParent();
4487 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4488
4489 // Count the number of register definitions to find the asm string.
4490 unsigned NumDefs = 0;
4491 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4492 ++NumDefs)
4493 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4494
4495 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4496 // Disassemble the AsmStr and approximate number of instructions.
4497 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4498 Size = getInlineAsmLength(AsmStr, *MAI);
4499 }
4500
4501 return Size;
4502 }
4503
getType(const MachineInstr & MI) const4504 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4505 const uint64_t F = MI.getDesc().TSFlags;
4506 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4507 }
4508
getUnits(const MachineInstr & MI) const4509 InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4510 const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4511 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4512
4513 return IS.getUnits();
4514 }
4515
4516 // Calculate size of the basic block without debug instructions.
nonDbgBBSize(const MachineBasicBlock * BB) const4517 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4518 return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4519 }
4520
nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const4521 unsigned HexagonInstrInfo::nonDbgBundleSize(
4522 MachineBasicBlock::const_iterator BundleHead) const {
4523 assert(BundleHead->isBundle() && "Not a bundle header");
4524 auto MII = BundleHead.getInstrIterator();
4525 // Skip the bundle header.
4526 return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4527 }
4528
4529 /// immediateExtend - Changes the instruction in place to one using an immediate
4530 /// extender.
immediateExtend(MachineInstr & MI) const4531 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4532 assert((isExtendable(MI)||isConstExtended(MI)) &&
4533 "Instruction must be extendable");
4534 // Find which operand is extendable.
4535 short ExtOpNum = getCExtOpNum(MI);
4536 MachineOperand &MO = MI.getOperand(ExtOpNum);
4537 // This needs to be something we understand.
4538 assert((MO.isMBB() || MO.isImm()) &&
4539 "Branch with unknown extendable field type");
4540 // Mark given operand as extended.
4541 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
4542 }
4543
invertAndChangeJumpTarget(MachineInstr & MI,MachineBasicBlock * NewTarget) const4544 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4545 MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4546 LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4547 << printMBBReference(*NewTarget);
4548 MI.dump(););
4549 assert(MI.isBranch());
4550 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4551 int TargetPos = MI.getNumOperands() - 1;
4552 // In general branch target is the last operand,
4553 // but some implicit defs added at the end might change it.
4554 while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4555 --TargetPos;
4556 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4557 MI.getOperand(TargetPos).setMBB(NewTarget);
4558 if (EnableBranchPrediction && isPredicatedNew(MI)) {
4559 NewOpcode = reversePrediction(NewOpcode);
4560 }
4561 MI.setDesc(get(NewOpcode));
4562 return true;
4563 }
4564
genAllInsnTimingClasses(MachineFunction & MF) const4565 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4566 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4567 MachineFunction::iterator A = MF.begin();
4568 MachineBasicBlock &B = *A;
4569 MachineBasicBlock::iterator I = B.begin();
4570 DebugLoc DL = I->getDebugLoc();
4571 MachineInstr *NewMI;
4572
4573 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4574 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4575 NewMI = BuildMI(B, I, DL, get(insn));
4576 LLVM_DEBUG(dbgs() << "\n"
4577 << getName(NewMI->getOpcode())
4578 << " Class: " << NewMI->getDesc().getSchedClass());
4579 NewMI->eraseFromParent();
4580 }
4581 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4582 }
4583
4584 // inverts the predication logic.
4585 // p -> NotP
4586 // NotP -> P
reversePredSense(MachineInstr & MI) const4587 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4588 LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4589 MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
4590 return true;
4591 }
4592
4593 // Reverse the branch prediction.
reversePrediction(unsigned Opcode) const4594 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4595 int PredRevOpcode = -1;
4596 if (isPredictedTaken(Opcode))
4597 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4598 else
4599 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4600 assert(PredRevOpcode > 0);
4601 return PredRevOpcode;
4602 }
4603
4604 // TODO: Add more rigorous validation.
validateBranchCond(const ArrayRef<MachineOperand> & Cond) const4605 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4606 const {
4607 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4608 }
4609
4610 void HexagonInstrInfo::
setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const4611 setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const {
4612 assert(MIB->isBundle());
4613 MachineOperand &Operand = MIB->getOperand(0);
4614 if (Operand.isImm())
4615 Operand.setImm(Operand.getImm() | memShufDisabledMask);
4616 else
4617 MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4618 }
4619
getBundleNoShuf(const MachineInstr & MIB) const4620 bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
4621 assert(MIB.isBundle());
4622 const MachineOperand &Operand = MIB.getOperand(0);
4623 return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4624 }
4625
4626 // Addressing mode relations.
changeAddrMode_abs_io(short Opc) const4627 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
4628 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4629 }
4630
changeAddrMode_io_abs(short Opc) const4631 short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {
4632 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4633 }
4634
changeAddrMode_io_pi(short Opc) const4635 short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {
4636 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4637 }
4638
changeAddrMode_io_rr(short Opc) const4639 short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {
4640 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4641 }
4642
changeAddrMode_pi_io(short Opc) const4643 short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {
4644 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4645 }
4646
changeAddrMode_rr_io(short Opc) const4647 short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {
4648 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4649 }
4650
changeAddrMode_rr_ur(short Opc) const4651 short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {
4652 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4653 }
4654
changeAddrMode_ur_rr(short Opc) const4655 short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {
4656 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4657 }
4658