1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Sparc implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SparcFrameLowering.h"
14 #include "SparcInstrInfo.h"
15 #include "SparcMachineFunctionInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Target/TargetOptions.h"
26
27 using namespace llvm;
28
29 static cl::opt<bool>
30 DisableLeafProc("disable-sparc-leaf-proc",
31 cl::init(false),
32 cl::desc("Disable Sparc leaf procedure optimization."),
33 cl::Hidden);
34
SparcFrameLowering(const SparcSubtarget & ST)35 SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
36 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
37 ST.is64Bit() ? Align(16) : Align(8), 0,
38 ST.is64Bit() ? Align(16) : Align(8)) {}
39
emitSPAdjustment(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,int NumBytes,unsigned ADDrr,unsigned ADDri) const40 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
41 MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MBBI,
43 int NumBytes,
44 unsigned ADDrr,
45 unsigned ADDri) const {
46
47 DebugLoc dl;
48 const SparcInstrInfo &TII =
49 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
50
51 if (NumBytes >= -4096 && NumBytes < 4096) {
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
53 .addReg(SP::O6).addImm(NumBytes);
54 return;
55 }
56
57 // Emit this the hard way. This clobbers G1 which we always know is
58 // available here.
59 if (NumBytes >= 0) {
60 // Emit nonnegative numbers with sethi + or.
61 // sethi %hi(NumBytes), %g1
62 // or %g1, %lo(NumBytes), %g1
63 // add %sp, %g1, %sp
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
65 .addImm(HI22(NumBytes));
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
67 .addReg(SP::G1).addImm(LO10(NumBytes));
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
69 .addReg(SP::O6).addReg(SP::G1);
70 return ;
71 }
72
73 // Emit negative numbers with sethi + xor.
74 // sethi %hix(NumBytes), %g1
75 // xor %g1, %lox(NumBytes), %g1
76 // add %sp, %g1, %sp
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
78 .addImm(HIX22(NumBytes));
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
80 .addReg(SP::G1).addImm(LOX10(NumBytes));
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
82 .addReg(SP::O6).addReg(SP::G1);
83 }
84
emitPrologue(MachineFunction & MF,MachineBasicBlock & MBB) const85 void SparcFrameLowering::emitPrologue(MachineFunction &MF,
86 MachineBasicBlock &MBB) const {
87 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
88
89 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
90 MachineFrameInfo &MFI = MF.getFrameInfo();
91 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
92 const SparcInstrInfo &TII =
93 *static_cast<const SparcInstrInfo *>(Subtarget.getInstrInfo());
94 const SparcRegisterInfo &RegInfo =
95 *static_cast<const SparcRegisterInfo *>(Subtarget.getRegisterInfo());
96 MachineBasicBlock::iterator MBBI = MBB.begin();
97 // Debug location must be unknown since the first debug location is used
98 // to determine the end of the prologue.
99 DebugLoc dl;
100 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
101
102 // FIXME: unfortunately, returning false from canRealignStack
103 // actually just causes needsStackRealignment to return false,
104 // rather than reporting an error, as would be sensible. This is
105 // poor, but fixing that bogosity is going to be a large project.
106 // For now, just see if it's lied, and report an error here.
107 if (!NeedsStackRealignment && MFI.getMaxAlign() > getStackAlign())
108 report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
109 "stack re-alignment, but LLVM couldn't handle it "
110 "(probably because it has a dynamic alloca).");
111
112 // Get the number of bytes to allocate from the FrameInfo
113 int NumBytes = (int) MFI.getStackSize();
114
115 unsigned SAVEri = SP::SAVEri;
116 unsigned SAVErr = SP::SAVErr;
117 if (FuncInfo->isLeafProc()) {
118 if (NumBytes == 0)
119 return;
120 SAVEri = SP::ADDri;
121 SAVErr = SP::ADDrr;
122 }
123
124 // The SPARC ABI is a bit odd in that it requires a reserved 92-byte
125 // (128 in v9) area in the user's stack, starting at %sp. Thus, the
126 // first part of the stack that can actually be used is located at
127 // %sp + 92.
128 //
129 // We therefore need to add that offset to the total stack size
130 // after all the stack objects are placed by
131 // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
132 // aligned *after* the extra size is added, we need to disable
133 // calculateFrameObjectOffsets's built-in stack alignment, by having
134 // targetHandlesStackFrameRounding return true.
135
136
137 // Add the extra call frame stack size, if needed. (This is the same
138 // code as in PrologEpilogInserter, but also gets disabled by
139 // targetHandlesStackFrameRounding)
140 if (MFI.adjustsStack() && hasReservedCallFrame(MF))
141 NumBytes += MFI.getMaxCallFrameSize();
142
143 // Adds the SPARC subtarget-specific spill area to the stack
144 // size. Also ensures target-required alignment.
145 NumBytes = Subtarget.getAdjustedFrameSize(NumBytes);
146
147 // Finally, ensure that the size is sufficiently aligned for the
148 // data on the stack.
149 NumBytes = alignTo(NumBytes, MFI.getMaxAlign());
150
151 // Update stack size with corrected value.
152 MFI.setStackSize(NumBytes);
153
154 emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
155
156 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
157
158 // Emit ".cfi_def_cfa_register 30".
159 unsigned CFIIndex =
160 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
161 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
162 .addCFIIndex(CFIIndex);
163
164 // Emit ".cfi_window_save".
165 CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
166 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
167 .addCFIIndex(CFIIndex);
168
169 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
170 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
171 // Emit ".cfi_register 15, 31".
172 CFIIndex = MF.addFrameInst(
173 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
174 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
175 .addCFIIndex(CFIIndex);
176
177 if (NeedsStackRealignment) {
178 int64_t Bias = Subtarget.getStackPointerBias();
179 unsigned regUnbiased;
180 if (Bias) {
181 // This clobbers G1 which we always know is available here.
182 regUnbiased = SP::G1;
183 // add %o6, BIAS, %g1
184 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
185 .addReg(SP::O6).addImm(Bias);
186 } else
187 regUnbiased = SP::O6;
188
189 // andn %regUnbiased, MaxAlign-1, %regUnbiased
190 Align MaxAlign = MFI.getMaxAlign();
191 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
192 .addReg(regUnbiased)
193 .addImm(MaxAlign.value() - 1U);
194
195 if (Bias) {
196 // add %g1, -BIAS, %o6
197 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
198 .addReg(regUnbiased).addImm(-Bias);
199 }
200 }
201 }
202
203 MachineBasicBlock::iterator SparcFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const204 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
205 MachineBasicBlock::iterator I) const {
206 if (!hasReservedCallFrame(MF)) {
207 MachineInstr &MI = *I;
208 int Size = MI.getOperand(0).getImm();
209 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
210 Size = -Size;
211
212 if (Size)
213 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
214 }
215 return MBB.erase(I);
216 }
217
218
emitEpilogue(MachineFunction & MF,MachineBasicBlock & MBB) const219 void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
220 MachineBasicBlock &MBB) const {
221 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
222 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
223 const SparcInstrInfo &TII =
224 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
225 DebugLoc dl = MBBI->getDebugLoc();
226 assert(MBBI->getOpcode() == SP::RETL &&
227 "Can only put epilog before 'retl' instruction!");
228 if (!FuncInfo->isLeafProc()) {
229 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
230 .addReg(SP::G0);
231 return;
232 }
233 MachineFrameInfo &MFI = MF.getFrameInfo();
234
235 int NumBytes = (int) MFI.getStackSize();
236 if (NumBytes == 0)
237 return;
238
239 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
240 }
241
hasReservedCallFrame(const MachineFunction & MF) const242 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
243 // Reserve call frame if there are no variable sized objects on the stack.
244 return !MF.getFrameInfo().hasVarSizedObjects();
245 }
246
247 // hasFP - Return true if the specified function should have a dedicated frame
248 // pointer register. This is true if the function has variable sized allocas or
249 // if frame pointer elimination is disabled.
hasFP(const MachineFunction & MF) const250 bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
251 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
252
253 const MachineFrameInfo &MFI = MF.getFrameInfo();
254 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
255 RegInfo->needsStackRealignment(MF) ||
256 MFI.hasVarSizedObjects() ||
257 MFI.isFrameAddressTaken();
258 }
259
getFrameIndexReference(const MachineFunction & MF,int FI,Register & FrameReg) const260 int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF,
261 int FI,
262 Register &FrameReg) const {
263 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
264 const MachineFrameInfo &MFI = MF.getFrameInfo();
265 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
266 const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
267 bool isFixed = MFI.isFixedObjectIndex(FI);
268
269 // Addressable stack objects are accessed using neg. offsets from
270 // %fp, or positive offsets from %sp.
271 bool UseFP;
272
273 // Sparc uses FP-based references in general, even when "hasFP" is
274 // false. That function is rather a misnomer, because %fp is
275 // actually always available, unless isLeafProc.
276 if (FuncInfo->isLeafProc()) {
277 // If there's a leaf proc, all offsets need to be %sp-based,
278 // because we haven't caused %fp to actually point to our frame.
279 UseFP = false;
280 } else if (isFixed) {
281 // Otherwise, argument access should always use %fp.
282 UseFP = true;
283 } else if (RegInfo->needsStackRealignment(MF)) {
284 // If there is dynamic stack realignment, all local object
285 // references need to be via %sp, to take account of the
286 // re-alignment.
287 UseFP = false;
288 } else {
289 // Finally, default to using %fp.
290 UseFP = true;
291 }
292
293 int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI) +
294 Subtarget.getStackPointerBias();
295
296 if (UseFP) {
297 FrameReg = RegInfo->getFrameRegister(MF);
298 return FrameOffset;
299 } else {
300 FrameReg = SP::O6; // %sp
301 return FrameOffset + MF.getFrameInfo().getStackSize();
302 }
303 }
304
verifyLeafProcRegUse(MachineRegisterInfo * MRI)305 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
306 {
307
308 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
309 if (MRI->isPhysRegUsed(reg))
310 return false;
311
312 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
313 if (MRI->isPhysRegUsed(reg))
314 return false;
315
316 return true;
317 }
318
isLeafProc(MachineFunction & MF) const319 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
320 {
321
322 MachineRegisterInfo &MRI = MF.getRegInfo();
323 MachineFrameInfo &MFI = MF.getFrameInfo();
324
325 return !(MFI.hasCalls() // has calls
326 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
327 || MRI.isPhysRegUsed(SP::O6) // %sp is used
328 || hasFP(MF)); // need %fp
329 }
330
remapRegsForLeafProc(MachineFunction & MF) const331 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
332 MachineRegisterInfo &MRI = MF.getRegInfo();
333 // Remap %i[0-7] to %o[0-7].
334 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
335 if (!MRI.isPhysRegUsed(reg))
336 continue;
337
338 unsigned mapped_reg = reg - SP::I0 + SP::O0;
339
340 // Replace I register with O register.
341 MRI.replaceRegWith(reg, mapped_reg);
342
343 // Also replace register pair super-registers.
344 if ((reg - SP::I0) % 2 == 0) {
345 unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
346 unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
347 MRI.replaceRegWith(preg, mapped_preg);
348 }
349 }
350
351 // Rewrite MBB's Live-ins.
352 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
353 MBB != E; ++MBB) {
354 for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
355 if (!MBB->isLiveIn(reg))
356 continue;
357 MBB->removeLiveIn(reg);
358 MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
359 }
360 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
361 if (!MBB->isLiveIn(reg))
362 continue;
363 MBB->removeLiveIn(reg);
364 MBB->addLiveIn(reg - SP::I0 + SP::O0);
365 }
366 }
367
368 assert(verifyLeafProcRegUse(&MRI));
369 #ifdef EXPENSIVE_CHECKS
370 MF.verify(0, "After LeafProc Remapping");
371 #endif
372 }
373
determineCalleeSaves(MachineFunction & MF,BitVector & SavedRegs,RegScavenger * RS) const374 void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
375 BitVector &SavedRegs,
376 RegScavenger *RS) const {
377 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
378 if (!DisableLeafProc && isLeafProc(MF)) {
379 SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
380 MFI->setLeafProc(true);
381
382 remapRegsForLeafProc(MF);
383 }
384
385 }
386